CA1227456A - Method for making submicron mask openings using sidewall and lift-off techniques - Google Patents

Method for making submicron mask openings using sidewall and lift-off techniques

Info

Publication number
CA1227456A
CA1227456A CA000509770A CA509770A CA1227456A CA 1227456 A CA1227456 A CA 1227456A CA 000509770 A CA000509770 A CA 000509770A CA 509770 A CA509770 A CA 509770A CA 1227456 A CA1227456 A CA 1227456A
Authority
CA
Canada
Prior art keywords
film
substrate
mesa
method described
sidewall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000509770A
Other languages
English (en)
French (fr)
Inventor
Robert K. Cook
Joseph F. Shepard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1227456A publication Critical patent/CA1227456A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0331Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers for lift-off processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/945Special, e.g. metal
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/947Subphotolithographic processing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/948Radiation resist
    • Y10S438/951Lift-off

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Drying Of Semiconductors (AREA)
CA000509770A 1985-11-18 1986-05-22 Method for making submicron mask openings using sidewall and lift-off techniques Expired CA1227456A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/799,053 US4654119A (en) 1985-11-18 1985-11-18 Method for making submicron mask openings using sidewall and lift-off techniques
US799,053 1985-11-18

Publications (1)

Publication Number Publication Date
CA1227456A true CA1227456A (en) 1987-09-29

Family

ID=25174932

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000509770A Expired CA1227456A (en) 1985-11-18 1986-05-22 Method for making submicron mask openings using sidewall and lift-off techniques

Country Status (8)

Country Link
US (1) US4654119A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0223032A3 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS62126637A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CN (1) CN86107855B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
AU (1) AU576086B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
BR (1) BR8605249A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA1227456A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
IN (1) IN168426B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4842633A (en) * 1987-08-25 1989-06-27 Matsushita Electric Industrial Co., Ltd. Method of manufacturing molds for molding optical glass elements and diffraction gratings
EP0369053B1 (de) * 1988-11-17 1994-03-02 International Business Machines Corporation Verfahren zur Herstellung von Masken mit Strukturen im Submikrometerbereich
US5858256A (en) * 1996-07-11 1999-01-12 The Board Of Trustees Of The Leland Stanford, Jr. University Method of forming small aperture
US5956583A (en) * 1997-06-30 1999-09-21 Fuller; Robert T. Method for forming complementary wells and self-aligned trench with a single mask
US20060191863A1 (en) * 2005-02-25 2006-08-31 Benjamin Szu-Min Lin Method for fabricating etch mask and patterning process using the same
KR101291766B1 (ko) * 2007-06-07 2013-08-01 도쿄엘렉트론가부시키가이샤 패터닝 방법
JP2009094125A (ja) * 2007-10-04 2009-04-30 Elpida Memory Inc 半導体装置の製造方法
JP2013004669A (ja) * 2011-06-15 2013-01-07 Toshiba Corp パターン形成方法、電子デバイスの製造方法及び電子デバイス
CN105226002B (zh) * 2014-07-04 2019-05-21 北大方正集团有限公司 自对准沟槽型功率器件及其制造方法
US11056722B2 (en) 2018-02-08 2021-07-06 International Business Machines Corporation Tool and method of fabricating a self-aligned solid state thin film battery
US10720670B2 (en) 2018-02-08 2020-07-21 International Business Machines Corporation Self-aligned 3D solid state thin film battery
US10679853B2 (en) * 2018-02-08 2020-06-09 International Business Machines Corporation Self-aligned, over etched hard mask fabrication method and structure
JP2024119252A (ja) * 2023-02-22 2024-09-03 東京エレクトロン株式会社 基板処理方法、基板処理システム及び保護膜

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3982943A (en) * 1974-03-05 1976-09-28 Ibm Corporation Lift-off method of fabricating thin films and a structure utilizable as a lift-off mask
US4209349A (en) * 1978-11-03 1980-06-24 International Business Machines Corporation Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching
US4274909A (en) * 1980-03-17 1981-06-23 International Business Machines Corporation Method for forming ultra fine deep dielectric isolation
JPS57130431A (en) * 1981-02-06 1982-08-12 Fujitsu Ltd Manufacture of semiconductor device
US4387145A (en) * 1981-09-28 1983-06-07 Fairchild Camera & Instrument Corp. Lift-off shadow mask
US4430791A (en) * 1981-12-30 1984-02-14 International Business Machines Corporation Sub-micrometer channel length field effect transistor process
JPS5870534A (ja) * 1982-09-27 1983-04-27 フエアチアイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン リフトオフ・シヤドウマスクの形成方法
DE3242113A1 (de) * 1982-11-13 1984-05-24 Ibm Deutschland Gmbh, 7000 Stuttgart Verfahren zur herstellung einer duennen dielektrischen isolation in einem siliciumhalbleiterkoerper
US4572765A (en) * 1983-05-02 1986-02-25 Fairchild Camera & Instrument Corporation Method of fabricating integrated circuit structures using replica patterning
KR890003903B1 (ko) * 1983-06-29 1989-10-10 가부시끼가이샤 히다찌세이사꾸쇼 패턴 형성 방법
US4575924A (en) * 1984-07-02 1986-03-18 Texas Instruments Incorporated Process for fabricating quantum-well devices utilizing etch and refill techniques

Also Published As

Publication number Publication date
BR8605249A (pt) 1987-07-28
CN86107855A (zh) 1987-08-19
EP0223032A2 (en) 1987-05-27
EP0223032A3 (en) 1990-06-27
JPS62126637A (ja) 1987-06-08
CN86107855B (zh) 1988-06-29
IN168426B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1991-03-30
AU5884686A (en) 1987-05-21
JPH0543287B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-07-01
US4654119A (en) 1987-03-31
AU576086B2 (en) 1988-08-11

Similar Documents

Publication Publication Date Title
US4549927A (en) Method of selectively exposing the sidewalls of a trench and its use to the forming of a metal silicide substrate contact for dielectric filled deep trench isolated devices
CA1227456A (en) Method for making submicron mask openings using sidewall and lift-off techniques
US4252582A (en) Self aligned method for making bipolar transistor having minimum base to emitter contact spacing
US4801350A (en) Method for obtaining submicron features from optical lithography technology
EP0395330B1 (en) Method of forming an oxide liner and active area mask for selective epitaxial growth in an isolation trench
JPS62279677A (ja) 半導体装置の製造方法
EP0564191A2 (en) Structure and method for fabricating integrated circuits
KR100264502B1 (ko) 이중 포토레지스트층을 사용한 자기정렬 헤테로접합 바이폴라 트랜지스터의 제조방법 및 장치
US4612701A (en) Method to reduce the height of the bird's head in oxide isolated processes
JPH03129818A (ja) 半導体装置の製造方法
US4775644A (en) Zero bird-beak oxide isolation scheme for integrated circuits
EP1237185A2 (en) A method for manufacturing isolating structures
KR910000020B1 (ko) 반도체장치의 제조방법
US4772569A (en) Method for forming oxide isolation films on french sidewalls
KR100228765B1 (ko) 셀 어퍼처 마스크 제조방법
JPH08335543A (ja) アライメントパターンの形成方法
KR0152951B1 (ko) 반도체 소자 제조방법
JPH0257701B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPS59191333A (ja) 半導体装置の製造方法
JPS6213047A (ja) 半導体装置の製造方法
JPH02283029A (ja) 半導体装置の製造方法
KR0134859B1 (ko) 반도체 소자의 콘택홀 형성방법
KR100203911B1 (ko) 반도체 소자의 소자분리막 형성방법
KR100480231B1 (ko) 반도체장치의 필드 산화막 형성방법
KR100400329B1 (ko) 반도체소자의소자분리산화막형성방법

Legal Events

Date Code Title Description
MKEX Expiry