CA1131796A - Method for fabricating mos device with self-aligned contacts - Google Patents

Method for fabricating mos device with self-aligned contacts

Info

Publication number
CA1131796A
CA1131796A CA339,798A CA339798A CA1131796A CA 1131796 A CA1131796 A CA 1131796A CA 339798 A CA339798 A CA 339798A CA 1131796 A CA1131796 A CA 1131796A
Authority
CA
Canada
Prior art keywords
layer
source
drain regions
gate
areas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA339,798A
Other languages
English (en)
French (fr)
Inventor
Tarsaim L. Batra
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
American Microsystems Holding Corp
Original Assignee
American Microsystems Holding Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Microsystems Holding Corp filed Critical American Microsystems Holding Corp
Application granted granted Critical
Publication of CA1131796A publication Critical patent/CA1131796A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10W10/0126—
    • H10W10/13—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CA339,798A 1979-01-08 1979-11-14 Method for fabricating mos device with self-aligned contacts Expired CA1131796A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US184079A 1979-01-08 1979-01-08
US1,840 1979-01-08

Publications (1)

Publication Number Publication Date
CA1131796A true CA1131796A (en) 1982-09-14

Family

ID=21698078

Family Applications (1)

Application Number Title Priority Date Filing Date
CA339,798A Expired CA1131796A (en) 1979-01-08 1979-11-14 Method for fabricating mos device with self-aligned contacts

Country Status (7)

Country Link
JP (1) JPS5593271A (cg-RX-API-DMAC10.html)
CA (1) CA1131796A (cg-RX-API-DMAC10.html)
DE (1) DE3000121A1 (cg-RX-API-DMAC10.html)
FR (1) FR2446011A1 (cg-RX-API-DMAC10.html)
GB (1) GB2040564A (cg-RX-API-DMAC10.html)
IT (1) IT8019078A0 (cg-RX-API-DMAC10.html)
NL (1) NL7908534A (cg-RX-API-DMAC10.html)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4455737A (en) * 1978-05-26 1984-06-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US4506437A (en) * 1978-05-26 1985-03-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US4409722A (en) * 1980-08-29 1983-10-18 International Business Machines Corporation Borderless diffusion contact process and structure
US4341009A (en) * 1980-12-05 1982-07-27 International Business Machines Corporation Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate
JPS57113289A (en) * 1980-12-30 1982-07-14 Fujitsu Ltd Semiconductor device and its manufacture
US4517729A (en) * 1981-07-27 1985-05-21 American Microsystems, Incorporated Method for fabricating MOS device with self-aligned contacts
US4686000A (en) * 1985-04-02 1987-08-11 Heath Barbara A Self-aligned contact process
JPS63207171A (ja) * 1987-02-24 1988-08-26 Nippon Telegr & Teleph Corp <Ntt> 半導体メモリ装置及びその製造方法
US5159353A (en) * 1991-07-02 1992-10-27 Hewlett-Packard Company Thermal inkjet printhead structure and method for making the same
KR100377833B1 (ko) * 2001-06-19 2003-03-29 삼성전자주식회사 보더리스 콘택 구조를 갖는 반도체 장치 및 그 제조방법

Also Published As

Publication number Publication date
FR2446011A1 (fr) 1980-08-01
JPS5593271A (en) 1980-07-15
NL7908534A (nl) 1980-07-10
DE3000121A1 (de) 1980-07-17
FR2446011B3 (cg-RX-API-DMAC10.html) 1981-11-06
GB2040564A (en) 1980-08-28
IT8019078A0 (it) 1980-01-08

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