BR9803441A - Dispositivo semicondutor tendo fileiras sobrepostas m·ltiplas de blocos de ligação com interconexões condutivas e método para disposição dos blocos. - Google Patents
Dispositivo semicondutor tendo fileiras sobrepostas m·ltiplas de blocos de ligação com interconexões condutivas e método para disposição dos blocos.Info
- Publication number
- BR9803441A BR9803441A BR9803441-3A BR9803441A BR9803441A BR 9803441 A BR9803441 A BR 9803441A BR 9803441 A BR9803441 A BR 9803441A BR 9803441 A BR9803441 A BR 9803441A
- Authority
- BR
- Brazil
- Prior art keywords
- blocks
- semiconductor device
- laying
- conductive interconnections
- connection
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
<B>DISPOSITIVO SEMICONDUTOR TENDO FILEIRAS SOBREPOSTAS MúLTIPLAS DE BLOCOS DE LIGAçãO COM INTERCONEXõES CONDUTIVAS E MéTODO PARA DISPOSIçãO DOS BLOCOS<D>. A presente invenção compreende um dispositivo semicondutor (20) tendo um circuito ativo (22) e uma área do bloco de ligação (24). Dentro da área do bloco de ligação há uma pluralidade de fileiras de blocos de ligação. Conjuntos de blocos de ligação (30-36) incluem um bloco de ligação de cada fileira. Os blocos de ligação (26) são posicionados unicamente dentro da área do bloco de ligação (24) para levar em consideração o passo do primeiro fio entre blocos que são adjacentes e no mesmo conjunto, e um passo do segundo fio entre blocos que são adjacentes e em conjunto diferentes. Um método para determinar a disposição dos blocos de ligação (26) é ensinado.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/940,605 US5962926A (en) | 1997-09-30 | 1997-09-30 | Semiconductor device having multiple overlapping rows of bond pads with conductive interconnects and method of pad placement |
Publications (1)
Publication Number | Publication Date |
---|---|
BR9803441A true BR9803441A (pt) | 1999-11-03 |
Family
ID=25475139
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR9803441-3A BR9803441A (pt) | 1997-09-30 | 1998-09-14 | Dispositivo semicondutor tendo fileiras sobrepostas m·ltiplas de blocos de ligação com interconexões condutivas e método para disposição dos blocos. |
Country Status (5)
Country | Link |
---|---|
US (1) | US5962926A (pt) |
JP (1) | JP3305664B2 (pt) |
KR (1) | KR100369913B1 (pt) |
BR (1) | BR9803441A (pt) |
TW (1) | TW411495B (pt) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5897379A (en) * | 1997-12-19 | 1999-04-27 | Sharp Microelectronics Technology, Inc. | Low temperature system and method for CVD copper removal |
US6495925B1 (en) * | 1998-11-17 | 2002-12-17 | Infineon Technologies A.G. | Semiconductor chip and a lead frame |
US6784558B2 (en) * | 1999-12-30 | 2004-08-31 | Intel Corporation | Semiconductor device inlcluding optimized driver layout for integrated circuit with staggered bond pads |
AU4305501A (en) * | 1999-12-30 | 2001-07-16 | Intel Corporation | Optimized driver layout for integrated circuits with staggered bond pads |
US6291898B1 (en) * | 2000-03-27 | 2001-09-18 | Advanced Semiconductor Engineering, Inc. | Ball grid array package |
US6405357B1 (en) * | 2000-05-02 | 2002-06-11 | Advanced Semiconductor Engineering, Inc. | Method for positioning bond pads in a semiconductor die |
US6459807B1 (en) | 2000-06-13 | 2002-10-01 | Semiconductor Technologies & Instruments, Inc. | System and method for locating irregular edges in image data |
JP2002033347A (ja) * | 2000-07-17 | 2002-01-31 | Rohm Co Ltd | 半導体装置 |
JP2003031610A (ja) * | 2001-07-16 | 2003-01-31 | Nec Corp | 半導体装置及びそのワイヤーボンディング方法 |
US6476506B1 (en) | 2001-09-28 | 2002-11-05 | Motorola, Inc. | Packaged semiconductor with multiple rows of bond pads and method therefor |
TW536765B (en) * | 2001-10-19 | 2003-06-11 | Acer Labs Inc | Chip package structure for array type bounding pad |
DE10156468A1 (de) * | 2001-11-16 | 2003-05-28 | Eupec Gmbh & Co Kg | Halbleiterbauelement und Verfahren zum Kontaktieren eines solchen Halbleiterbauelements |
US20050040539A1 (en) * | 2002-01-31 | 2005-02-24 | Carlsgaard Eric Stephen | Flip chip die bond pads, die bond pad placement and routing optimization |
KR100475740B1 (ko) * | 2003-02-25 | 2005-03-10 | 삼성전자주식회사 | 신호 완결성 개선 및 칩 사이즈 감소를 위한 패드배치구조를 갖는 반도체 집적 회로장치 |
KR101012696B1 (ko) * | 2003-06-05 | 2011-02-09 | 삼성테크윈 주식회사 | 그라운드 본딩 방법 |
KR100574954B1 (ko) * | 2003-11-15 | 2006-04-28 | 삼성전자주식회사 | 중앙부 패드와 재 배선된 패드에서 와이어 본딩된집적회로 칩패키지 |
US7536658B2 (en) * | 2004-10-29 | 2009-05-19 | Synopsys, Inc. | Power pad synthesizer for an integrated circuit design |
TWI357647B (en) * | 2007-02-01 | 2012-02-01 | Siliconware Precision Industries Co Ltd | Semiconductor substrate structure |
US8067830B2 (en) * | 2007-02-14 | 2011-11-29 | Nxp B.V. | Dual or multiple row package |
JP2009164195A (ja) * | 2007-12-28 | 2009-07-23 | Panasonic Corp | 半導体チップ |
US7932744B1 (en) * | 2008-06-19 | 2011-04-26 | Actel Corporation | Staggered I/O groups for integrated circuits |
US8389978B2 (en) * | 2010-02-22 | 2013-03-05 | Infinera Corporation | Two-shelf interconnect |
US8291368B2 (en) | 2010-04-05 | 2012-10-16 | Freescale Semiconductor, Inc. | Method for reducing surface area of pad limited semiconductor die layout |
US9401250B2 (en) * | 2011-05-19 | 2016-07-26 | Black & Decker, Inc. | Electronic switching module for a power tool |
US8754518B1 (en) | 2013-01-22 | 2014-06-17 | Freescale Semiconductor, Inc. | Devices and methods for configuring conductive elements for a semiconductor package |
US10608501B2 (en) | 2017-05-24 | 2020-03-31 | Black & Decker Inc. | Variable-speed input unit having segmented pads for a power tool |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63244853A (ja) * | 1987-03-31 | 1988-10-12 | Nec Corp | 半導体集積回路装置 |
US5195237A (en) * | 1987-05-21 | 1993-03-23 | Cray Computer Corporation | Flying leads for integrated circuits |
JPH01137640A (ja) * | 1987-11-24 | 1989-05-30 | Nec Corp | 半導体記憶回路装置 |
US4990996A (en) * | 1987-12-18 | 1991-02-05 | Zilog, Inc. | Bonding pad scheme |
JPH02184043A (ja) * | 1989-01-10 | 1990-07-18 | Nec Corp | 半導体装置の製造方法 |
US5468999A (en) * | 1994-05-26 | 1995-11-21 | Motorola, Inc. | Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding |
US5498767A (en) * | 1994-10-11 | 1996-03-12 | Motorola, Inc. | Method for positioning bond pads in a semiconductor die layout |
US5719449A (en) * | 1996-09-30 | 1998-02-17 | Lucent Technologies Inc. | Flip-chip integrated circuit with improved testability |
-
1997
- 1997-09-30 US US08/940,605 patent/US5962926A/en not_active Expired - Lifetime
-
1998
- 1998-09-14 BR BR9803441-3A patent/BR9803441A/pt not_active Application Discontinuation
- 1998-09-22 TW TW087115730A patent/TW411495B/zh not_active IP Right Cessation
- 1998-09-29 JP JP29152498A patent/JP3305664B2/ja not_active Expired - Lifetime
- 1998-09-30 KR KR10-1998-0040776A patent/KR100369913B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US5962926A (en) | 1999-10-05 |
TW411495B (en) | 2000-11-11 |
KR19990030291A (ko) | 1999-04-26 |
JP3305664B2 (ja) | 2002-07-24 |
JPH11195671A (ja) | 1999-07-21 |
KR100369913B1 (ko) | 2003-06-19 |
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FA10 | Dismissal: dismissal - article 33 of industrial property law |