TW411495B - Semiconductor device having multiple overlapping rows of bond pads with conductive interconnects and method of pad placement - Google Patents
Semiconductor device having multiple overlapping rows of bond pads with conductive interconnects and method of pad placement Download PDFInfo
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Description
五、發明說明⑴ 先前應用之相關說明 故申凊案業於1997年9月30日於美國提出申請 口月木號為第0 8/940, 605號。 發明之領域 本發明係關於一般之半導體裝置 之佈局以及半導體裝置之封裝。 ^ 發明之背景 士半導體產業對高腳數半導體裝置之需求向為熟 5之’高腳數之需求卻致使設計上受限於焊塾限 艮制之設計係指一種整體晶粒尺寸取決於焊墊數 且異於一般受限於為執行某種特殊元件功能之電 =核心限制之設計。一般即言,半導體裝置且有 翌間距之單列焊墊。固定焊墊間距則以半導體裝 之最劣封裝須求決定之《例如,就高腳數封裝而 間距通常由位處最接近晶粒角落之焊墊決定之。 —般須具備最大之焊墊間距以利焊線機工作而不 之焊線。因此,此種最劣之焊墊間距係習用於決 多少之焊墊可置於一半導體晶粒之單邊。而隨^ 間距配置之焊墊所遭遇之難題即是致使晶軚尺寸 一項優於習用之具備等墊距之單列焊墊之技藝 採行美國專利第5, 498, 7 67號教示之等線距者。_ 距裝置具有等線距之特性’而相鄰焊墊間之塾距 致。等線距係定義於由焊墊中心處至相鄰線之直 藉由保持跨越晶粒之單邊之線距相等,則焊塾即 ,專利申 更詳細言之即 焊墊 知 ° 一般^ 制。焊墊 目者,而 晶體數目 一列等焊 置所要求 言,焊墊 此等焊墊 影響相鄰 疋到底有 用單列等 太大。 改良係如 ''種等線 則非一· 交趄離。 不再受愚
C:\Program Fi1es\Patent\54489. ptd 第5頁 «1495 五 '發明說明(2) " 劣焊墊間距所限制…,可完成使用較小晶粒尺寸之理 想。無論如何,即使採行等線距之架構,顯而易見的’ 列之焊墊依然成為整體裝置尺寸之限制因子。 工業界業已建議採行雙列焊墊以進—步因應焊墊限制 計而且最佳化晶粒之尺寸…種此類建議,如美國專 5,4W,9 99號所述’即利用多重列之焊墊以完成直交組入 之焊塾。第4®為第,9 9 9號專利之圖*,係例示半導體裝 !非常有效地容納三列相同之焊墊d易言之,帛二列 弟一列之虛擬複製,就垂直晶粒邊之方向上而言偏離第^ 列。而此種應用確實有利於晶粒尺寸之縮小,但遭遇 題則係其中之結構必須利用多重迴路之高度以免造路 ^ ^ , 序中採仃多重迴路高度增加整體之 禝雜度、成本’並降低了整體半導體裝置之可靠度。此 外’此專利要求焊線均須大致以直交方向點焊之。 此係主要適用於低腳數裝置。 J Γ ^列建議係如美國專利第5,⑽,2 3 7號之說明, k採行夕重列帛墊。第3圖即為第’2 37號之專利,而 即為=9 9 9唬之專利’係列示半導體裝置如何有效地 rm!同列焊•,或具有共邊者,即垂直於晶: 邊之方向。無言,如~,此先前技
均具有相等之焊塾距1此,於最劣狀 :W 距則可ΐ納之總焊塾數目於為受m,可於焊墊H 之佈局中減低晶粒尺寸,以及可: 寸中之焊墊數目之半導體裝置與方法必然有效。尺
C:\Program F i1es\Patent\54489. ptd 第6頁 五、發明說明(3) ' -~*---- 圖示之簡述 第1圖例示一分缸+ θ 士工d ω 刀解成具有兩列焊墊之象限之半導體裝置 之平面圖。 第2圖例示與第彳闻+ * M ^ 象中相關之焊墊之平面圖。 Μ#/ /圖之象限中之局部圖,其中之焊墊業連接 至一封裝中之待烊區。 第4圖例示第1圖 车连 阔之牛導姑·裝置,其中之焊墊業連接至一 封裝中之待焊區& 第5圖例示一分赵士目士· _ 之平面圖。 解成具有二列焊墊之象限之半導體裝置 第6圖例示與第5圖之一爱 第7圖例示第5圖之半導中相關之焊墊之平面圖。 裝中之待焊區。 +導耻裴置,其中焊墊業連接至一封 第8、9以及11例示丰 法之流程圖。 '、一半導體裂置之焊墊之佈局之方 中之方法而將焊墊與待連J應用於第8 應了解此處之例子係為簡 件亦無須依比例繪制。y, 目緊意見,而且圖示中之物 、 例如,部、 而加以放大。再者,丑山 部伤物件之尺寸為清晰明暸 ^ 务中經過、益 已重覆引用以示對應或類似之、s考量’圖示中之序號業 ,^ ^發明之詳έ田^; Ba 本發明係應用具備雙等之說明 在雙等線距中,第一辇括 < 夕重列焊墊佈局之技術。 寸輝^距,役_j_t 饰h —焊墊組中之相鄰焊墊 第1 0以及1 2圖例示 9以及11圖
C:\Program Files\Patent\54489. ptd $ 7頁 4U495 五、發明說明(4) '----^ 之間而言。而雙等線距中之第二等線距,係指不同垾 中相關連之相鄰焊墊之間而言。本發明優於先前技蓺=奴 焊墊限制之設計中獲得較小晶粒區域。 β仰於 本發明參酌所有圖示即可深入了解。第1圊例示_ 體裝置20,其具有一主動電路區域22旨在執行特殊應用 輯’以及一週邊區域24具有焊墊26可容納輸入/輸出接腳 以及電源供應接腳。裝置20以中線軸103、1〇2,以及對角 線邊轴104,105分割裝置則可劃分成數個象限。象限1〇〇 係位於對角線邊轴1 〇 5,以及中線轴1 〇 3之間。 第2圖所示為第1圖之象限1〇〇。第2圖之特殊具體實施例 示用於兩列焊墊所採行之雙等線距。由象限之丨〇3中心軸 開始’鄰接之焊墊經劃分為特定之组別。組數一般相同於 指定列中焊墊之數目。易言之,各列1以及列2於每象限中 各具1 0個焊墊,則將各具有1 〇组以2個焊墊為一組之焊墊 組。請注意’焊墊列無須具備相等之焊墊數,然而,組數 將受限於具備較少數焊墊之列。在本具體實施例中,組合 中之物件相互重叠,而且有一軸與一焊墊之一側共邊旅與 組合内之至少另一焊墊内切。例如第2圖中之第3 7組’其 中焊墊60之軸61内切焊墊65,同時焊墊65之轴67内切焊墊 60。在各組之内,重疊部份至少大約25%或更高。闡釋此 關係之另一方式係於第一焊塾與同組中之至少另一焊蟄之 間有一共用之區域。例如》就兩列之實施例而言,兩個焊 墊共用X座標,假設X軸平行於連接焊墊之晶粒邊時。 第2圖更進·一步指出’各單/列之焊塾距皆異。例如’
C:\Program FiIes\Patent\54489. ptd 第8貢 411495 五、發明說明(5) 列1之第一焊墊距於相鄰焊墊之間亦不一。如具體實施例 中所示,第一焊墊距較小者接近中心軸1 〇 3而較大者則接 近as粒之對角線轴1 0 5。例如焊塾距p 1小於焊塾距p 2而焊 墊距P2又小於焊墊距P3。列2所對應之第二焊墊距於相鄰 焊墊之間亦不一。無論如何,第一焊墊距與第二焊墊距一 樣均不改變。 此外’各特定列中之相鄰焊墊之間之間距增率均為變 量。例如’列1之第一焊塾距亦為一變量。易言之,低於 焊墊距Ρ 2之值之焊墊距Ρ 3之值大於低於焊墊距Ρ1之值之焊 墊距Ρ2之值。然而,列2之第二焊墊距變率卻小於列1之焊 墊距變率。直覺地可了解,第2圖内之焊墊距D1係大於焊 墊距D2,其中D1係為最接近中心軸1 〇 3之列1焊墊至最接近 對角線轴丨〇 5之焊墊之距離,而D 2則為由最接近中心軸1 〇 3 之列2焊墊至最接近對角線軸105之焊墊之距離。 本發明之又一特點係,介於組合内之相鄰接焊墊(組焊 塾距)之間距對接近象限之中心邊之纽合者而言較大,例 如第3 4組,係大於接近象限之中心交又點之組合中之组焊 墊距,例如第3 6組。請注意,術語所指之中心交叉點於下 文中將更深入探討之。相同地,組焊墊距對接近象限角落 之組合而言較大,例如第3 5組,係大於較接近象限之中心 交叉點之組合中之組焊墊距,例如第3 6組。易言之,參考 第2圖,P1大於Ρ2,而P2大於P3 ° 本發明之再一特點係,接近象限之中心邊線之組合,正 角度t h e t a 2係介於線5 0,即垂直於晶粒之邊線,以及線
C:\Program Files\Patent\54489. ptd 第 9 頁 411495 五、發明說明(6) 5 1 ’即與一組合中焊墊之中心内切者之間之夾角。就本發 明之其他具體實施例而言,擁有3個或更多列者,焊墊内 僅有兩列之焊墊必須用來建立内切線。易言之,並非組合 中之所有焊塾皆需呈線性對準。然而,較接近象限角落 者,一負角度thetal係建立於線5〇,,即垂直於晶粒邊 線,以及線5 2,係内切於組合中之焊塾之中心者之間之爽 角。因此,存在一中心交又點,該處若非一具有角度, theta,即零度之焊墊組,就是具有相對垂直線5〇,5〇’夾 反向角度之相鄰焊墊组(即一為正而另一為負)。注意部份 之象限為反置或鏡像因而使得負角度接近中心拍,以及正 角度接近對角線軸》 第3圖例示本發明之特別具體實施例,其中晶粒子2 〇業 組 '焊線連接至封裝而形成封裝完成之裝置25。裝置25例示 雙定線距之裝置。雙定線距藉由各組合中之第一分析焊墊 即可深入了解。例如,第3圖例示之組合3 〇,包括有焊墊 205以及206,而組合31,則包括了焊墊2〇3以及204。在組 合3 0之内’焊墊2 〇 5以及2 0 6均有一線距WP1。注意,WP 1係 指焊墊2 0 6之中心與導線22 5之間之直交距離。在本發明中 之本具體實施例中,距離WP1,與其他之所有組合中之所 有相鄰焊墊之間者完全相等。因此,焊墊2〇3以及2〇4隸屬 於第3 1組亦具備線距值wpi。雙線距之第二者,可由分析 在不同組合中之相鄰焊塾推衍而得。例如,焊墊2 〇 5 ,隸 屬第30組,而焊墊204,為第31組,均視為相鄰之焊墊: 因為經過點焊後兩位置即相鄰接了。因此,線距wp2即為
411495 五、發明說明〔7) 介於焊墊2〇4之中心至線2 2 5之間之距離。線距肝2對位處 相異組合中之相鄰焊墊而言實為重覆者。因此,介於焊墊 202以及焊墊203之間亦為WP2。 誠如本發明中所說明其業已利用雙定線距而求出,因而 可能大幅地節省面積,同時仍然可應用習用之封裝技術而 使所有線墊維持在同一迴路高度。此舉旨在避免遭遇有關 先前技藝之難題’即採行變化迴路南度之方法來點焊連接 相異列。 實際上己提及本發明之兩列雙定線距之實施例,如第4 圖所示,在一單列定線距裝置中致使晶fe之面積縮減了大 約3 0%。此外,實際上業已証實利用多重迴路高度以及藉 由於此揭示之本發明來減低WP I可更進~步減少晶粒面 積。例如,實際上証實利用本發明之具有零微米之ffp 1之 兩列雙定線距之執行例使晶粒面積遠超過單列定線距裝置 者而縮減了大約6 8 %。 現將雙列具體實施例之討論延伸至其他之多重列實施 例。例如,第5以及6圖例示,一種三列之具體實施例可能 得以執行之。不過,一旦使用三列時’ ~組則定義為彼等 具有之共邊與該群内之至少一個其他焊墊内切之所有焊 墊。 實際上已証實,本發明之三列雙定線距執行例得使晶粒 面積較單列定線距裝置縮減了大約3 9%。此外,實際上業 註實利用多重迴路,以及減小W P 1,配合已揭示之發明可 更進一步減少晶粒面積。例如,業已站實以本發明之W P1
C:\Program Files\Patent\54489. ptd 第 11 頁 411495 五、發明說明(8) 等於零之三列執行例可令晶粒面積較單列定線距裝置縮減 大約8 1 %左右(設想裝置於邏輯區域2 2不會成為核心限 制)。 此外’一種雙列單定線距佈局(未列示出)本案申請者亦 一併提出討論。不過’實際資料証實雙列單線距佈局致使 晶粒尺寸遠較單列定線距者更大。然後,亦發現雙列雙定 線距之設計有益於改善晶粒之尺寸大小。 第8 ’ 9以及Π圖例示一項於一指定象限内決定烊墊佈局 之方法之特殊具體實施例。例示於第8、9以及1 1圖之方 法’參酌第1 0,以及1 2圖即可—目了然。 在第1001步驟中,所有待焊區之位置均已設定完成。一 般而言’位置係以X Y座標系統定義之。在第1 〇 0 2步驟中, 設定第一以及第二列位置(Rl,R2)。對各列而言,第一以 及第二列之位置相對於晶粒邊界有一偏移量存在。第丨〇以 及1 2圖内例示之R1以及R2係穿越位在列中各焊墊中心點之 線。注意,通過中心點或其他參考點並不重要,重點旨在 於指出焊墊之參考位置。下一步,於第1〇〇3步驟中設置第 一焊墊。一般言之’第一焊墊之配置係由焊墊距以及相對 晶粒邊界之偏移量’與象限内之中心線決定之。在一具體 實施例中,偏移量為1 5 0微米。本發明可預期,第一焊塾 將與中心線重疊。 第一以及第二線距(WP1,WP2)於第1004步驟内定義之。 包括決定選擇WP 1以及WP2之考量。就製造上而言,WP2係 最小之線距,因為它對焊線機之干擾程度有直接影響。焊
C:\Program Files\Patent\54489. ptd 第12頁 411495 五,發明說明(9) 線機之干擾在WP1之使用上並無問題,因而可知,較 WP2小。在一具體實施例中,ffPi是5〇微米,尺寸相等於兩 線徑之合,以及WP2為80微米。若fpi為零,就必須引用多 重迴路高度。 夕 於第1 0 0 7步驟中’必須決定焊墊2究竟為—個相鄰接焊 墊或一個列鄰接焊墊。若焊墊2為組鄰接焊墊則進行第 1005步驟。倘焊墊2為列鄰接焊墊則逕行第丨〇〇6步驟。 第9個例示在步驟1 〇〇5中決定組鄰接焊墊之佈局之詳細 方法。於第1101步驟中定義出P2S2線。誠如第η圖内所 示,P2S2線起於第二焊墊之位置並止於第二焊墊之待焊 區。應了解’第1101步驟僅為—項定義而已,因為第二焊 墊之位置仍未決定出。無論如何,此線之確定關係已知, 容後討論之。 在第1102步驟中,定義Ρ1 ί線β ΡΠ之長度為wpi(第一線 距)’因為它是一個組鄰接焊墊。PI I線直交於P2S2線。 P1 I線之一端點位於第一焊墊(p丨)内,另—端點)則連接 到P2S2線。 於步鄉1103中’決定P1M線之長度。此即焊墊1至焊墊2 之距離。在另一具體實施例中,p丨S 2線之長度係利用距離 公式以及端點之XY座標決定出。在步驟丨1 〇4中,決定I S2 線之長度。此係由P 2 S 2線之端點I至第二焊墊之待焊區之 距離。在一具體實施例中,距離係以畢氏定理以及三角形 IP1S2求得。在步驟11〇5當中,由piS2,IS2,以及P1I所 形成二角形之角度則由前述資料求出。在—具體實施例
C:\Program Fi1es\Patent\54489. ptd
_411495___ 五'發明說明(ίο) - —-------- 中,角度係以二角學決定出,即給定一個角度以及 於步驟1106中,ί點之XY座標乃由前述決定出之資料4 ° 得。在-具體實施例當中,I點之χγ座標係由已知之 與S2之ΧΥ座標之夾角而求得。在步驟11〇7中’找 '纺 R2之交點旨在定義出與第二烊墊(ρ2)之位置。在_且轴ς %例中,P2S2與R2之交點則從解兩條線之方程式而求、 最後,於步驟11 08中,配置焊墊Ρ2 ^ 一般言之,佈局牛驟 必會詳細地於半導體裝置佈局資料庫中定義出焊墊之^产 局。 第11圖例示決定一個列鄰接焊墊之佈局步驟丨〇〇6之 方法。於步驟1201中定義P2S2線。誠如第12圖所示,P2 = 線起始於第二焊墊之位置而止於第二焊墊之待焊區。於 驟1 202中,定義P3I線。P3I線長為WP2(第二焊墊^)°/p3i 線直交於P2S2線。P3I線一端點連接第三焊墊(p3),而另 一端點(I)連接P2S2線。因為焊墊3之最終佈局尚未定案所 以Ρ3ί線之實際XY座標仍未知。於步驟1203中,決定出” P2S2線與R1之ΧΥ父點(Ν)。在一具體實施例中,χγ交點係 由已知之R1之X座標與P2S2線之方程式解得。在步驟12〇4 當中’決定出Ρ3Ν線長。在步驟1 2 0 5中,Ρ3Ν線係指由焊墊 3連接至Ρ 2 S 2線之點Ν之直線。在一具體實施例中,ρ 3 ν線 長係指由WP2除以從步驟1202中獲得之角度1之餘弦值而求 出。在步驟1 20 6中,焊墊3之Υ座標係由ν之γ座標加上Ρ3Ν 之線長而求得。 一旦經指定之象限之佈局完成後,一則可直接複製或藉
C:\Program Files\Patent\54489.ptd 第 14 頁 411495 五、發明說明(11) 反轉或鏡像技術來完成晶粒之其餘象限之焊墊佈局工作。 雖然本發明業已藉特定之具體實施例加以詳述例釋,但 非意指本發明僅侷限於彼等例示之具體實施例。凡精於此 技藝者,應了解,在未悖離本發明之精神與範疇時所有之 改良與變化均可執行之。因此,本發明意於涵蓋隸屬於附 屬之申請專利範圍之範疇内之所有變化與改良。
C:\Program Files\Patent\54489, ptd 第15頁
Claims (1)
- _ 4tl495 六、申請專利範圍 — 1. 一種半導體裝置,包含: —晶粒(20) ’具有四邊,沿著晶粒之至少一第一邊至 少有一排第一列焊墊之位置幾乎沿著第一軸而且平行於晶 粒之第一邊並偏離一第一距離,而且第二列焊墊之位置幾 乎沿著第二軸而且平行於晶粒之第一邊並偏離—第二距 離,且係大於第一距離,焊墊與内含於晶粒内之電^連 接,其中第—列焊墊中之複數第一焊墊各有第—以及第二 邊,而且幾乎垂直於晶粒之第—邊’以及第二列焊墊中之 複數第二焊墊各有第一以及第二邊,而且亦幾乎垂直於晶 粒之第一邊,第二列内之複數焊墊中之每—焊墊之各第一 邊形成了複數焊墊配置軸之一,並與第一列焊墊之既定焊 摯内切而使第二列之每一焊墊以低於百分之一百之部份與 對應於沿著晶粒之邊界之第一列焊墊之少於百分之一百^ 部份接合。 2‘如申請專利範圍第1項之半導體裝置,另包含: 複數導電互連(14) ’每一導電互連(14)與第一以及第 一列之焊墊(26)之一預定電連接並且由晶粒之邊界外延至 晶粒以電連接至電路’複數導電互連(1 4 )係幾乎同處同一 平面上。 3 ·如申請專利範圍第2項之半導體裝置,其中複數導電 互連(1 4 )係位於焊墊,且複數倫離晶粒邊界之焊墊之間之 形成線塾迴路之複數線,各線呈迴路狀地位於預定焊塾 (26)以及具有與内含導電互連之平面幾乎同迴路高度之一 預定焊墊待焊區(1 2)之間。^11495 六'申锖專利範圍 4·如_請專利範圍第2項之半導體 互連(丨4)為複數線其於焊墊以及位於晶,、中複數導電 之待焊區之間形成線塾,而且其令第Γ以」之複數焊整 接線塾彼此接合而形成數組線塾,而每^二列t之鄰 '線距,係肖以定義位於焊線組合内之線路1 ,組亦具有第 …之鄰接線具有—第二線 著:之距離1 之第一線距均小於第二線距。 者阳粒之所有邊界 5如申請專利範圍第i項之半導體裝置, ,分成A區(100),而且人區⑴Q)内之每」、//粒之四 二各列中之各禪塾之間,間距係指鄰接焊塾 π ,其中對各列而言,單區内由該區之起始焊墊至該區 之最後一個焊墊之間距係為變量。 6.如申請專利範圍第5項之半導體裝置,其中各區内之 起始焊墊(2 6 )幾乎位處晶粒之四邊之一者之中心線上,而 且該區内之最後—個焊墊幾乎位處於晶粒之一對角線軸 上,由中心線至第—列焊墊内之角落之各焊墊之間距變化 幾乎為增量。 \如申請專利範圍第5項之半導體裝置,其中各區中介 於第一列之各焊墊間之間距變化異於第二列之間距變化。 8.種/CI著丰導體晶粒周邊配置焊墊之方法,包括以下 步驟: 提供第一焊墊之i主r- λ _找奴_ 塾之待烊區之位置並經由第一線電連接至 焊區之位置並經由苐二線電連接至 第一焊墊; 提供第二烊墊之待C:\Program Files\Patent\54489. ptd 第17 頁 ^ί!495 六、申請專利範圍 第二焊墊 提供第三焊墊之待焊區之位 第三焊墊; 置 由第三線電連接至 於f曰粒上定義出第一焊墊之位置; 計算出由第一焊墊至第二焊墊之 定義出第-線距以進行線路布置:焊區之間之距離; 利用第一線距,第—焊墊之位置以及 置決定第二焊墊之位置; 第一待焊區之位 定義出第二線距以進行線路布置;以 利用第二線距、第二焊墊之位 ― 置決定第三焊墊之位置。 及第二待焊區之位 9. 一種半導體裝置,包含: 少布置於粒第(2—〇)以及複第數二焊,墊(26)圍繞於周邊’焊墊(26)至 得第-列鲈坌 一列内,均幾乎平行而且偏離外圍使 外圍更遠’焊塾(26)經布置成數口 m焊塾,在每組中之第二列焊塾中之一焊:較y 且-更二此:墊區之每組中之各個焊墊均 '、人手+仃於晶粒外圍之邊界,而且以一範圍内之位罢 ΐ ί ί義r晶粒t ’其中位在同组中之第-以及第二列焊 接〇之。卩份較佳在同位置座標之所有者為少。 10..如申請專利範圍第9項之半導體裝置,包含: 複數導電互連(丨4)電連接至第一以及第二列中之 焊墊(26),所有之導電互連(14)幾乎位處於同一平面之C:\Program Files\Patent\54489. ptd 第 18 頁 六、申請專利範圍 内。 獼· C:\Program Files\Patent\54489. ptd 第19頁
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Application Number | Priority Date | Filing Date | Title |
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US08/940,605 US5962926A (en) | 1997-09-30 | 1997-09-30 | Semiconductor device having multiple overlapping rows of bond pads with conductive interconnects and method of pad placement |
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TW411495B true TW411495B (en) | 2000-11-11 |
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TW087115730A TW411495B (en) | 1997-09-30 | 1998-09-22 | Semiconductor device having multiple overlapping rows of bond pads with conductive interconnects and method of pad placement |
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US (1) | US5962926A (zh) |
JP (1) | JP3305664B2 (zh) |
KR (1) | KR100369913B1 (zh) |
BR (1) | BR9803441A (zh) |
TW (1) | TW411495B (zh) |
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-
1997
- 1997-09-30 US US08/940,605 patent/US5962926A/en not_active Expired - Lifetime
-
1998
- 1998-09-14 BR BR9803441-3A patent/BR9803441A/pt not_active Application Discontinuation
- 1998-09-22 TW TW087115730A patent/TW411495B/zh not_active IP Right Cessation
- 1998-09-29 JP JP29152498A patent/JP3305664B2/ja not_active Expired - Lifetime
- 1998-09-30 KR KR10-1998-0040776A patent/KR100369913B1/ko not_active IP Right Cessation
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KR100369913B1 (ko) | 2003-06-19 |
BR9803441A (pt) | 1999-11-03 |
US5962926A (en) | 1999-10-05 |
JPH11195671A (ja) | 1999-07-21 |
KR19990030291A (ko) | 1999-04-26 |
JP3305664B2 (ja) | 2002-07-24 |
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