BR112014024483A2 - receptor de entrada/saída e sistema - Google Patents
receptor de entrada/saída e sistemaInfo
- Publication number
- BR112014024483A2 BR112014024483A2 BR112014024483A BR112014024483A BR112014024483A2 BR 112014024483 A2 BR112014024483 A2 BR 112014024483A2 BR 112014024483 A BR112014024483 A BR 112014024483A BR 112014024483 A BR112014024483 A BR 112014024483A BR 112014024483 A2 BR112014024483 A2 BR 112014024483A2
- Authority
- BR
- Brazil
- Prior art keywords
- input
- output receiver
- receiver
- output
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03891—Spatial equalizers
- H04L25/03949—Spatial equalizers equalizer selection or adaptation based on feedback
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/0062—Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
- H04L7/0276—Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0332—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with an integrator-detector
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Analogue/Digital Conversion (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2012/034281 WO2013158106A1 (en) | 2012-04-19 | 2012-04-19 | Unequalized clock data recovery for serial i/o receiver |
Publications (2)
Publication Number | Publication Date |
---|---|
BR112014024483A2 true BR112014024483A2 (pt) | 2017-06-20 |
BR112014024483A8 BR112014024483A8 (pt) | 2021-05-25 |
Family
ID=49383875
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112014024483A BR112014024483A8 (pt) | 2012-04-19 | 2012-04-19 | receptor de entrada/saída e sistema |
Country Status (6)
Country | Link |
---|---|
US (3) | US9048999B2 (pt) |
EP (1) | EP2839582A4 (pt) |
CN (1) | CN203434996U (pt) |
BR (1) | BR112014024483A8 (pt) |
TW (3) | TWI516939B (pt) |
WO (1) | WO2013158106A1 (pt) |
Families Citing this family (47)
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EP2839582A4 (en) | 2012-04-19 | 2015-12-16 | Intel Corp | RECOVERING UNAUTHORIZED CLOCK DATA FOR SERIAL I / O RECEIVER |
US9397868B1 (en) | 2012-12-11 | 2016-07-19 | Rambus Inc. | Split-path equalizer and related methods, devices and systems |
US9325489B2 (en) * | 2013-12-19 | 2016-04-26 | Xilinx, Inc. | Data receivers and methods of implementing data receivers in an integrated circuit |
TWI555404B (zh) * | 2014-03-28 | 2016-10-21 | 晨星半導體股份有限公司 | 多通道串列連線信號接收系統 |
JP6703364B2 (ja) * | 2014-04-10 | 2020-06-03 | ザインエレクトロニクス株式会社 | 受信装置 |
US9356588B2 (en) | 2014-06-09 | 2016-05-31 | Qualcomm Incorporated | Linearity of phase interpolators using capacitive elements |
US9762418B2 (en) * | 2014-11-06 | 2017-09-12 | Dell Products, Lp | Repeatable backchannel link adaptation for high speed serial interfaces |
US9325546B1 (en) * | 2014-11-14 | 2016-04-26 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Data rate and PVT adaptation with programmable bias control in a SerDes receiver |
US9374250B1 (en) | 2014-12-17 | 2016-06-21 | Intel Corporation | Wireline receiver circuitry having collaborative timing recovery |
US10341145B2 (en) | 2015-03-03 | 2019-07-02 | Intel Corporation | Low power high speed receiver with reduced decision feedback equalizer samplers |
US9313017B1 (en) * | 2015-06-11 | 2016-04-12 | Xilinx, Inc. | Baud-rate CDR circuit and method for low power applications |
US9762416B2 (en) * | 2015-09-08 | 2017-09-12 | Abtum Inc. | Reflection coefficient reader |
CN105471787B (zh) * | 2015-11-23 | 2018-11-06 | 硅谷数模半导体(北京)有限公司 | 信号采样处理方法和系统 |
CN105577592A (zh) * | 2015-12-31 | 2016-05-11 | 浪潮(北京)电子信息产业有限公司 | 一种ctle值遍历优化方法及装置 |
US10389555B2 (en) | 2016-01-28 | 2019-08-20 | Hewlett Packard Enterprise Development Lp | Phase delay difference-based channel compensation |
US10069655B2 (en) * | 2016-03-10 | 2018-09-04 | Xilinx, Inc. | Half-rate integrating decision feedback equalization with current steering |
CN106535022B (zh) * | 2016-12-07 | 2019-03-22 | 北京工业大学 | 一种带均衡器的具有功放功能的耳机降噪电路 |
US10374785B2 (en) * | 2016-12-27 | 2019-08-06 | Intel Corporation | Clock phase adjustment using clock and data recovery scheme |
US10148469B2 (en) * | 2017-05-01 | 2018-12-04 | Intel Corporation | Apparatus and method for cancelling pre-cursor inter-symbol-interference |
US10425123B2 (en) * | 2017-07-18 | 2019-09-24 | Intel Corporation | Parts-per-million detection apparatus and method |
US11349523B2 (en) * | 2017-08-10 | 2022-05-31 | Intel Corporation | Spread-spectrum modulated clock signal |
CN107835139A (zh) * | 2017-09-29 | 2018-03-23 | 灿芯创智微电子技术(北京)有限公司 | 一种抑制过补偿的均衡器反馈控制电路及方法 |
CN107657978B (zh) | 2017-11-01 | 2018-09-21 | 睿力集成电路有限公司 | 随机存储器 |
CN110351066B (zh) * | 2018-04-02 | 2022-03-08 | 华为技术有限公司 | 时钟相位恢复装置、方法和芯片 |
US10728060B2 (en) * | 2018-09-28 | 2020-07-28 | Teletrx Co. | Two-step feed-forward equalizer for voltage-mode transmitter architecture |
US10498523B1 (en) * | 2018-10-25 | 2019-12-03 | Diodes Incorporated | Multipath clock and data recovery |
KR102661493B1 (ko) * | 2018-11-05 | 2024-04-30 | 에스케이하이닉스 주식회사 | 수신 회로, 이를 이용하는 반도체 장치 및 반도체 시스템 |
TWI693811B (zh) * | 2018-12-19 | 2020-05-11 | 國立交通大學 | 多位準脈衝振幅調變接收裝置 |
CN111786669B (zh) * | 2019-04-04 | 2023-09-12 | 智原微电子(苏州)有限公司 | 用来进行决策反馈均衡器自适应控制的装置 |
US10735227B1 (en) * | 2019-04-16 | 2020-08-04 | Dell Products, L.P. | System and method to monitor component wear on high speed serial interfaces |
US10951441B2 (en) | 2019-06-19 | 2021-03-16 | Samsung Electronics Co., Ltd. | Receiver systems and methods for AC and DC coupling of receiver |
CN112241384B (zh) * | 2019-07-19 | 2022-07-01 | 上海复旦微电子集团股份有限公司 | 一种通用的高速串行差分信号分路电路及方法 |
TWI716975B (zh) * | 2019-08-21 | 2021-01-21 | 智原科技股份有限公司 | 時間偵測電路及時間偵測方法 |
JP7542061B2 (ja) | 2019-09-19 | 2024-08-29 | メイコム テクノロジー ソリューションズ ホールディングス インコーポレイテッド | イコライザ設定を適合させるためのisiまたはq計算の使用 |
FR3101218B1 (fr) * | 2019-09-23 | 2022-07-01 | Macom Tech Solutions Holdings Inc | Adaptation d’égaliseur sur la base de mesures de dispositif de surveillance de l’œil |
WO2021076800A1 (en) | 2019-10-15 | 2021-04-22 | Macom Technology Solutions Holdings, Inc. | Finding the eye center with a low-power eye monitor using a 3-dimensional algorithm |
CN115191090B (zh) | 2020-01-10 | 2024-06-14 | Macom技术解决方案控股公司 | 最佳均衡划分 |
US11575437B2 (en) | 2020-01-10 | 2023-02-07 | Macom Technology Solutions Holdings, Inc. | Optimal equalization partitioning |
TWI730667B (zh) * | 2020-03-12 | 2021-06-11 | 瑞昱半導體股份有限公司 | 具有抗射頻干擾機制的訊號接收裝置及方法 |
JP2021150930A (ja) | 2020-03-23 | 2021-09-27 | キオクシア株式会社 | イコライザ制御装置、受信装置及び受信装置の制御方法 |
KR102711854B1 (ko) * | 2020-08-18 | 2024-09-30 | 삼성전자주식회사 | 적응적 등화를 수행하는 수신 회로 및 이를 포함하는 시스템 |
US11177986B1 (en) * | 2020-11-24 | 2021-11-16 | Texas Instruments Incorporated | Lane adaptation in high-speed serial links |
US11616529B2 (en) | 2021-02-12 | 2023-03-28 | Macom Technology Solutions Holdings, Inc. | Adaptive cable equalizer |
US11575546B2 (en) * | 2021-03-05 | 2023-02-07 | Texas Instruments Incorporated | Error sampler circuit |
CN113225073B (zh) * | 2021-04-28 | 2022-04-08 | 北京大学(天津滨海)新一代信息技术研究院 | 采样点优化的时钟数据恢复电路、方法、设备及存储介质 |
CN113824443B (zh) * | 2021-08-18 | 2023-06-30 | 深圳市紫光同创电子有限公司 | 时钟数据恢复电路 |
US11489657B1 (en) * | 2021-10-20 | 2022-11-01 | Diodes Incorporated | Bit-level mode retimer |
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WO1998009400A1 (en) * | 1996-08-30 | 1998-03-05 | International Business Machines Corporation | Receiving and equalizing signals for high-speed data transmission |
US6002717A (en) | 1997-03-06 | 1999-12-14 | National Semiconductor Corporation | Method and apparatus for adaptive equalization using feedback indicative of undercompensation |
JP3495311B2 (ja) * | 2000-03-24 | 2004-02-09 | Necエレクトロニクス株式会社 | クロック制御回路 |
JP3624848B2 (ja) * | 2000-10-19 | 2005-03-02 | セイコーエプソン株式会社 | クロック生成回路、データ転送制御装置及び電子機器 |
US6614296B2 (en) * | 2001-06-29 | 2003-09-02 | Intel Corporation | Equalization of a transmission line signal using a variable offset comparator |
US7233164B2 (en) * | 2003-12-17 | 2007-06-19 | Rambus Inc. | Offset cancellation in a multi-level signaling system |
US7782932B2 (en) | 2004-04-23 | 2010-08-24 | Texas Instruments Incorporated | Circuit and method for evaluating the performance of an adaptive decision feedback equalizer-based serializer deserializer and serdes incorporating the same |
US7577193B2 (en) | 2005-06-28 | 2009-08-18 | Intel Corporation | Adaptive equalizer |
EP2115929B1 (en) * | 2007-01-09 | 2014-05-21 | Rambus Inc. | Receiver with clock recovery circuit and adaptive sample and equalizer timing |
US7916780B2 (en) | 2007-04-09 | 2011-03-29 | Synerchip Co. Ltd | Adaptive equalizer for use with clock and data recovery circuit of serial communication link |
US7890788B2 (en) * | 2007-07-09 | 2011-02-15 | John Yin | Clock data recovery and synchronization in interconnected devices |
KR100965767B1 (ko) * | 2008-09-08 | 2010-06-24 | 주식회사 하이닉스반도체 | 클럭 복원 회로를 구비하는 결정 피드백 등화기 및 클럭 복원 방법 |
US8229020B2 (en) * | 2009-03-23 | 2012-07-24 | Oracle America, Inc. | Integrated equalization and CDR adaptation engine with single error monitor circuit |
US8619934B2 (en) * | 2009-08-11 | 2013-12-31 | Texas Instruments Incorporated | Clock data recovery system |
JP5597660B2 (ja) * | 2012-03-05 | 2014-10-01 | 株式会社東芝 | Ad変換器 |
EP2839582A4 (en) | 2012-04-19 | 2015-12-16 | Intel Corp | RECOVERING UNAUTHORIZED CLOCK DATA FOR SERIAL I / O RECEIVER |
US9178683B2 (en) * | 2012-05-23 | 2015-11-03 | Hughes Network Systems, Llc | Method and apparatus for parallel demodulation of high symbol rate data streams in a communications system |
-
2012
- 2012-04-19 EP EP12874749.0A patent/EP2839582A4/en not_active Withdrawn
- 2012-04-19 WO PCT/US2012/034281 patent/WO2013158106A1/en active Application Filing
- 2012-04-19 BR BR112014024483A patent/BR112014024483A8/pt active Search and Examination
- 2012-04-19 US US13/976,189 patent/US9048999B2/en not_active Expired - Fee Related
-
2013
- 2013-04-15 TW TW102113297A patent/TWI516939B/zh not_active IP Right Cessation
- 2013-04-15 TW TW104138350A patent/TWI564720B/zh not_active IP Right Cessation
- 2013-04-15 TW TW105133049A patent/TWI646426B/zh active
- 2013-04-19 CN CN201320199549.9U patent/CN203434996U/zh not_active Expired - Fee Related
-
2015
- 2015-05-13 US US14/711,259 patent/US9479364B2/en active Active
-
2016
- 2016-10-24 US US15/332,376 patent/US10009194B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
TWI564720B (zh) | 2017-01-01 |
BR112014024483A8 (pt) | 2021-05-25 |
EP2839582A1 (en) | 2015-02-25 |
US20150249556A1 (en) | 2015-09-03 |
US20170070370A1 (en) | 2017-03-09 |
US9479364B2 (en) | 2016-10-25 |
CN203434996U (zh) | 2014-02-12 |
TWI646426B (zh) | 2019-01-01 |
TW201608376A (zh) | 2016-03-01 |
US20140307769A1 (en) | 2014-10-16 |
TW201719421A (zh) | 2017-06-01 |
TW201411352A (zh) | 2014-03-16 |
US9048999B2 (en) | 2015-06-02 |
EP2839582A4 (en) | 2015-12-16 |
US10009194B2 (en) | 2018-06-26 |
WO2013158106A1 (en) | 2013-10-24 |
TWI516939B (zh) | 2016-01-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
B06F | Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette] | ||
B06U | Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette] | ||
B09A | Decision: intention to grant [chapter 9.1 patent gazette] | ||
B11D | Dismissal acc. art. 38, par 2 of ipl - failure to pay fee after grant in time |