WO1998009400A1  Receiving and equalizing signals for highspeed data transmission  Google Patents
Receiving and equalizing signals for highspeed data transmissionInfo
 Publication number
 WO1998009400A1 WO1998009400A1 PCT/IB1996/000873 IB9600873W WO9809400A1 WO 1998009400 A1 WO1998009400 A1 WO 1998009400A1 IB 9600873 W IB9600873 W IB 9600873W WO 9809400 A1 WO9809400 A1 WO 9809400A1
 Authority
 WO
 Grant status
 Application
 Patent type
 Prior art keywords
 filter
 estimate
 analog
 δ
 value
 Prior art date
Links
Classifications

 H—ELECTRICITY
 H04—ELECTRIC COMMUNICATION TECHNIQUE
 H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
 H04L7/00—Arrangements for synchronising receiver with transmitter
 H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
 H04L7/0062—Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection

 H—ELECTRICITY
 H04—ELECTRIC COMMUNICATION TECHNIQUE
 H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
 H04L25/00—Baseband systems
 H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
 H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks ; Receiver end arrangements for processing baseband signals
 H04L25/03006—Arrangements for removing intersymbol interference
 H04L25/03178—Arrangements involving sequence estimation techniques
 H04L25/03203—Trellis search techniques
 H04L25/03235—Trellis search techniques with statereduction using feedback filtering
Abstract
Description
DESCRIPTION
Receiving and Equalizing Signals for HighSpeed Data Transmission
FIELD OF THE INVENTION
This invention relates to transceivers for highspeed, i.e. several Mbitpersecond, data transmission over unshielded twistedpair cables or other transmission means with similar transfer characteristics. It specifically provides a solution for a low power transceiver in such systems. One implementation employs quaternary partialresponse classIV (PRIV) signaling in combination with new concepts for mixed adaptive analog and digital equalization, clock recovery, and Viterbi decoding. Another implementation is for fullresponse systems.
BACKGROUND AND PRIOR ART
Unshielded twistedpair (UTP) cables are a preferred transmission medium for many applications that require transmission of data at the speed of several Mbit/sec, in particular for local area networks (LANs). Data transmission systems with UTP cables are also employed to provide high speed connectivity to subscribers over the copper access network, e.g. by high speed digital subscriber lines (HDSLs) or asymmetric digital subscriber lines (ADSLs). Other applications can be found in networks deployed to collect measurement data, e.g. for seismic data acquisition.
In a digital transmission system, data can be recovered from the sequence of samples x_{n} taken at the output of the overall channel at instants / = nT+τ , where T s the modulation interval, and τ is a constant sampling phase. The sample x„can be expressed in general as the weighted sum
Λ/1 x_{n} =∑ h,a„, + w„ , ι=0 where a„ e A is the nih input symbol taken from the symbol set A, h_{t} , / = 0
N 1 representing the sampled overall system response and w_{n} denoting additive noise. In a binary transmission system, the input symbols are taken from the set A = { 1 , +1}. Higher spectral efficiency than in binary transmission is obtained by M ary multilevel transmission, where the symbol set is
A = { (M1), .... 1, +1, ... (M1)} with M > 2, M even, A = [ (M1), .... 2, 0, +2, ... (M1)} with M > 2, M odd.
Introducing the Zλtransform notation, the sampled overall response can be expressed by the system polynomial (D) =∑ h,D' , ι=0 wherein D denotes the unitdelay operator.
A fullresponse system is characterized by the absence of intersymbol interference, i.e. h(D) = 1. In partialresponse systems, intersymbol interference is introduced in a controlled fashion to shape the overall channel response. For example, partial response classIV (PRIV), defined by the system polynomial 1D^{2}, is wellsuited for DCfree and bandlimited transmission over metallic cables because the overall frequency response presents spectral nulls at f = 0 Hz and f = 1/2 Hz, where T denotes the modulation interval.
Overall signal shaping to full or partial response is obtained by proper design of the filters in the analog and the digital sections at the transmit and receive ends of the transmission link. Signal shaping functions at the receiver usually include variable gain amplification and fixed and adaptive equalization. Signal samples are obtained by analogtodigital (A/D) conversion of the signal at the analog frontend output at sampling instants that are determined by a timing recovery circuit. In fullresponse systems, a sampling rate larger than 1/Tsamples/s may be required to avoid aliasing. In this case, a sequence of signals at a rate of 1/Tsamples/s is obtained at the output of a digital filter that performs the functions of equalization and decimation.
Signal distortion introduced by homogeneous metallic transmission lines is mainly caused by the skin effect. In a receiver for a cable transmission system, signal distortion is usually compensated for by adaptive equalization. Adaptive equalization can be performed either in the analog domain by variable analog filters or in the digital domain, e.g. by adaptive linear transversal filters. A wellknown technique for adaptive analog equalization is the automatic line buildout (ALBO) technique. An ALBO equalizer can be described as a combination of a variablelength cable simulator and an appropriate fixed receive filter. Since, for transmission over metallic cables, signal distortion depends essentially on one quantity, i.e. the product of a cable parameter times the cable length, a single control parameter is traditionally adjusted such that a given output signal level is obtained. The combined lengths of the cable and the simulated cable add then up to a known cable length for which the overall channel is equalized.
Examples of ALBOtype equalizers are described in: "Transmission Systems for Communication", Bell Telephone Laboratories, Fourth Edition 1970, pp. 654655, and in US Patent 5455 843 to Cherubini et al., entitled "Adaptive Equalizing Appa ratus and Method for Token Ring Transmission System Using Unshielded Twisted Pair Cables". The patent discloses an analog equalizer and an associated method to adaptively adjust the equalizer transfer characteristic for a distance between stations that can typically extend up to 200 m. For this range, the attenuation of unshielded twisted pair (UTP) cables is about 10  12 dB/100 m at 16 MHz so that the channel attenuation at 16 MHz varies between 0 and 24 dB. The disclosed equalization method is limited to a specific application and cabling structure which makes the disclosed solution unsuitable to cope with the objects of the present invention. In present day cable systems, an ALBOtype equalizer can be realized as a single monolithic semiconductor chip, such as the serial data receiver LIU01 by Precision Monolithics Inc. In a paper entitled "Equalizer, Gain, and Timing Control in a Receiver for Multilevel PartialResponse Signals", in the Proceedings of the Fifth Tirrenia International Workshop on Digital Communications, Elsevier Science Publishers B.V., 1992, Cherubini and Ungerboeck describe the adjustment of a twoparameter equalizer consisting of a variable analog filter section and a vanable gain amplifier, as well as the adjustment of the sampling phase of an A/D converter in the frontend of a receiver for multilevel PRIV transmission. In the described device, a first control voltage adjusts the variable filter section and a second control voltage determines the frontend gain. The control voltages are derived from the digital output signals of the A/D converter.
The design of a twoparameter equalizer as well as fixed transmit and receive filter sections for PRIV systems was described by G. Cherubini, S. Oelcer, and G. Ungerboeck in "Optimum Filter Design for PartialResponse ClassIV Transmission Systems", Proc. IEEE Intl. Conf. on Communications, ICC '92, pp. 5156, Chicago, IL, USA, June 1992.
However, an ALBOtype equalizer cannot adequately compensate for the signal distortion if large deviations from the assumed values occur In this case, signal equalization can be performed  either partially or entirely  by digital filtering. A tutorial treatise on adaptive digital equalization can be found in E A Lee and D. G. Messerschmitt: "Digital Communication", Kluwer Academic Publishers, Boston, MASS, USA, 1988, Ch. 9.
For the present invention, decisionfeedback equalization is considered. A digital decisionfeedback equalizer (DFE) consists of a linear forward digital filter and a feedback digital filter where past decisions are employed to compute the filter out put. Initial convergence of the DFE coefficients to their optimum values is traditionally achieved by referencedirected training where a symbol sequence known to the receiver is sent prior to transmitting the data. When a training sequence is not available, initial DFE convergence must be achieved in a selftraining mode Selftraining adaptive linear equalization for fullresponse systems was described, e.g., by D.N. Godard in "Selfrecovering equalization and carrier tracking in twodimensional data communication systems", IEEE Trans. Commun., Vol. COM28, pp. 18671875, Nov. 1980, by S. Bellini in "Bussgang techniques for blind 5 equalization", Proc. of IEEE Globecom 1986, pp. 46.1.1  46.1.7 , Dec. 1986, and by G. Picchi et al. in "Blind equalization and carrier recovery using a "StopandGo" decision directed algorithm", IEEE Trans. Commun., Vol. COM35, pp. 877 887, Sept. 1987. For partialresponse systems, selftraining adaptive linear equalization was described by Y. Sato in "A method of selfrecovering equalization for multilevel 10 amplitudemodulation systems", IEEE Trans. Commun., Vol. COM23, pp. 679682, June 1975, and by G. Cherubini, S. Oelcer, and G. Ungerboeck in "Adaptive equalization for PRIV transmission systems", PCT International Patent Application, Publication Number WO 96/20551.
To achieve near maximumlikelihood sequence detection of signals in the presence 15 of intersymbol interference (ISI), the feedback filter of a DFE can be embedded in a Viterbi decoder, as described by A. DuelHallen and C. Heegard in "Delayed decisionfeedback equalization", IEEE Trans. Commun., Vol. COM37, pp. 428436, May 1989, and by M.V. Eyuboglu and S.U. Qureshi in "Reducedstate sequence estimation for coded modulation on intersymbol interference channel", IEEE Trans. 20 Commun., Vol. COM37, pp. 989 995, Aug. 1989. The implementation of a Viterbi decoder for partialresponse signals was described by S. Oelcer and G. Ungerboeck in "Differencemetric Viterbi decoding of multilevel classIV partialresponse signals", IEEE Trans. Commun., Vol. COM42, pp. 1558 1570, Apr. 1994.
25 Digital equalization for partialresponse systems leads to difficulties in connection with timing recovery. The problem arises from the fact that random time continuous PR signals are bandlimited to half of the modulation rate. Hence, they are wide sense stationary. This rules out timing recovery schemes based on cyclo stationarity, as described by E.A. Lee and D.G. Messerschmitt, cited above, pp.
30 560571. Schemes based on signal squaring and tracking a spectral line at f=1/7^{,}Hz, or observing signal transitions cannot be applied. Timing synchronization is usually accomplished by decisionaided schemes. A decisiondirected timing recovery scheme that can be applied to full and partialresponse systems was described by K. H. Mueller and M. Muller in "Timing recovery in digital synchronous data receivers", IEEE Trans. Commun., Vol. COM24, pp. 516531 , Sept. 1976. However, with the Mueller/Muller algorithm, undesirable falselock situations can be experienced during initial timing acquisition. Conversely, without recovered synchronization, adjustment of a selftraining digital adaptive equalizer is possible only by resorting to methods that require considerable complexity and power consumption, as described by Cherubini, Oelcer, and Ungerboeck in "Adaptive equalization for PRIV transmission systems", cited above.
In many applications, transceiver power consumption is not subject to particularly tight constraints. For example, transceivers employed in adapter cards installed in personal computers or the like have usually sufficient power available. However, as will be described, there are also situations where power is a scarce resource, which imposes that the employed transceivers operate with minimal power consumption. This is the case, for example, for LANs deployed outside of buildings where the various devices connected to the network are batteryoperated. Under such conditions, precise power management is required.
OBJECTS OF THE INVENTION
Based on the above, it is one object of the present invention to devise a method for timing recovery in a receiver for highspeed data transmission, which method avoids falselock situations during initial timing acquisition; it is also an object to design a receiver implementing this method. A further object is to devise a method and a receiver providing robustness against various channel impairments and be tolerant of inaccuracies present particularly in the analog receiver sections. Another object is to devise methods and apparatus to allow a receiver in a fullresponse or a partialresponse system to be able to acquire initial convergence of its parameters for timing recovery and decisionfeedback equalization using received random data signals only, i.e. without the need for a referencedirected startup procedure. It is a still further object to show a low power implementation which includes the variable linear forward equalizer of the decisionfeedback equalizer (DFE) in the analog frontend of a receiver.
SUMMARY OF THE INVENTION
The solution to these objects consists in employing, in the receiver, a novel timing recovery scheme, preferably in connection with novel approaches for selftraining decisionfeedback equalization to be applied to full or partialresponse transmission systems. Details of these solutions are given in the appended detailed description of a first implementation of the invention in a fourlevel PRIV system for data transmission over UTP cables, and in a second implementation in a fullresponse system. However, the principles and concepts of the disclosed receiving techniques are not limited to data transmission over UTP cables but can as well be applied, with appropriate modifications obvious to a person skilled in the art, for data transmission over other types of channels, e.g., magnetic recording channels. The invention addresses two different issues. First, it solves the problem of timing recovery. With this novel scheme, falselock situations that can be experienced during initial timing acquisition are avoided. Second, it solves the problem of initial DFE convergence by implementing a selftraining linear forward equalizer, for which convergence can be achieved using received random data signals, and a feedback filter with small adaptivity.
The solution according to the invention for a quaternary PRIV system shows the linear forward equalizer realized as a selftraining twoparameter variable analog filter. Twoparameter variable equalizer adjustment for partialresponse systems goes back to the theoretical principle explained by Cherubini and Ungerboeck in "Equalizer, Gain, and Timing Control in a Receiver for Multilevel PartialResponse Signals", cited above. The linear forward equalization by a variable analog filter leads to the advantage of low power consumption. After synchronization has been accomplished, convergence of the digital feedback filter embedded in a reduced state Viterbi decoder is achieved. This approach leads to an implementation with low complexity that permits to reduce power consumption even further. The small adaptivity provided by the Viterbi decoder allows compensating for the residual signal distortion at the output of the analog linear forward equalizer and ensures correct convergence of the feedback filter coefficients to their optimum values without the need for a training sequence.
The solution according to the invention for a fullresponse system shows the linear forward equalizer realized as a selftraining adaptive digital filter. The algorithm employed for selftraining equalization is an inventive extension to fullresponse systems of the algorithm for partialresponse systems described by Cherubini, Oelcer, and Ungerboeck in "Adaptive equalization for PRIV transmission systems", cited above. As in the case of PR systems, convergence of the feedback filter coefficients to their optimum values takes place without the need for a training sequence after timing recovery and convergence of the linear forward equalizer have been accomplished.
LIST OF DRAWINGS
Fιg.1 shows an overview of the system in which the invention is used; Fιg.2 illustrates a connection between two nodes in the system according to Fig.1 ; Fig.3 depicts a first embodiment, a transceiver in a partialresponse system; Fig.4 illustrates the computation of the timing control signal; Fig.5 shows a second embodiment, a transceiver in a fullresponse system. DETAILED DESCRIPTION
Fig.1 provides a simplified overview of a system which makes advantageous use of the invention, a system developed for seismic data acquisition. A backbone network connects router units (RUs) 2 via bidirectional highspeed fiber links 3 to a central system 1. Ground networks connect signal processing units (SPUs) 6 via bidirectional cable links 4 to the RUs. Each SPU 6 can receive analog signals from a plurality of geophones 7, digitize these signals, and send them upstream to central system 1. In addition, each SPU 6 receives and transmits control and status information.
Fig.2 illustrates the communication arrangement between two adjacent SPUs 6. The SPU functions are controlled by a controller 8 which interfaces with two transceivers 9 designated T1 and T2. In the embodiment, each transceiver 9 supports fullduplex transmission at a nominal rate of 16 Mbit/s, and at a fallback rate of 8 Mbit/s. The cable links 4 connecting two SPUs contain unshielded twistedpair ca bles 11 for digital transmission, and additional pairs 10 over which analog signals from geophones 7 (shown in Fig.1 ) are received and digitized by converter 5. Power consumption for simultaneous transmit and receive operation is less than 200 mW from a single 3.3V supply voltage.
The characteristics of the cables used for the cable links 4 are specified as follows:  30 dB signal attenuation at 4 MHz for maximum cable length,
 55 dB nearend crosstalk attenuation at 4 MHz, and
 a characteristic impedance of 108 +/ 15 Ohm.
The two transceivers 9 shown schematically in Fig.2 are controlled via a common microcontroller which permits setting of transceiver options, e.g. quaternary trans mission or binary transmission (as a fallback), and reading of receiver parameters, e.g. mean squarederror at the detection point of each receiver. In the following, a more detailed description of a transceiver 9 and its functions shall be given. The transceiver design is based on quaternary partialresponse classIV (QPRIV) signaling.
With QPRIV modulation, quaternary symbols a„ e {3, 1 , +1 , +3 } are transmitted. The signals at the output of the overall discretetime channel are shaped into the form x = a  a , + e „ , where e accounts for residual distortion and noise. Note that the output of an ideal QPRIV system is a sequence of signals from the set
{ 6, 4, 2, 0, +2, +4, +6 }.
The overall channel characteristic exhibits spectral nulls at 0 Hz and the bandedge frequencies of ±1/2 THz, where 1/7^{'}, here 8 MBaud, is the modulation rate. Hence, transmitted signal energy is greatly reduced at low frequencies, where the transfer function of the cable varies rapidly with frequency, and at high frequencies, where signals become more attenuated. Channel equalization can thus be accomplished more easily than for fullresponse signaling and partialresponse classl signaling (PRI) with spectral nulls only at ±1/27
Fig.3 gives an overview of one single transceiver incorporating the invention. Each transceiver consists of a digital section 12 in which digital signal processing functions are performed, and a frontend section 13 for signal conversion, analog filtering, receiver clock generation, and cable driver/receiver functions.
In the transmitter, incoming quaternary symbols are represented by a 2bit signal TDAT. These incoming information bits are scrambled in selfsynchronizing scrambler 14 using the scrambler polynomial ι+ D^{13} + D^{28}and encoded by a 2B1Q differential encoder 15 to achieve transparency with respect to received signal polarity. After 2bit digitaltoanalog conversion in D/A converter 16, the resulting signal is shaped by a fixed transmit filter 17 into approximate PRIV form, then amplified by power amplifier 18, and transmitted via cable 11. An incoming signal  from cable 11  is amplified by variable gain amplifier (VGA) 19 and shaped into PRIV form by an analog receive filter consisting of a variable filter section 20 and a fixed filter section 21. Two independent control voltages determine the adjustments carried out by the variable equalizer: one voltage determines the frequencyindependent gain of VGA 19, the other voltage controls the transfer characteristic of variable filter 20. The control signals for the variable equalizer are derived digitally in a manner that leads to optimum settings independently of the current sampling phase.
Received signal samples x_{n} are obtained in analogtodigital (A/D) converter 22 by 6bit A/D conversion at a rate equal to MT symbols per second. The sampling phase of A/D converter 22 is determined by a voltagecontrolled oscillator (VCO) 23 whose control voltage is adjusted by a decisiondirected timing recovery algorithm. For proper operation of the timing recovery algorithm, a sufficient degree of equalization has to be achieved by the samplingphase insensitive equalizer control method. To simplify conversion, the control voltage for VCO 23 is provided by control circuit 29 in binary sigmadelta modulated form, as are the control voltages for VGA 19 and the variable filter section 20. A bank of three sigmadelta demodulators 24 to 26 serves to derive the required analog control voltages.
The thus obtained 6bitwide digital signal samples are input to an adaptive reduced twostate Viterbi decoder, element 27, for maximumlikelihood sequence detection. Embedded in this Viterbi decoder is the adaptive feedback filter of a decision feedback equalizer (DFE) to remove residual intersymbol interference. Symbolby symbol detection can also be employed. In this case, element 27 consists of a memoryless decision element and a feedback filter.
An estimate of the average squared error signal (MSE) is computed in an MSE meter 28. The MSE and other digital section receiver parameters may be used to allow monitoring of a "transmissionlink quality". The signals at the output of the Viterbi decoder are differentially decoded and descrambled in descrambler 30. The recovered quaternary symbols are represented by the twobit signal RDAT at the output of the digital section 12 of the transceiver.
Light line 31 in Fιg.3 carries a receiver clock signal RCLK produced by VCO 23; this clock signal RCLK controls all digital receiver functions. In the transmit section of the transceiver, an externally provided transmitter clock signal TCLK serves the same function, as indicated.
The transceiver, as implemented, comprises a digital chip and a mixed analog/digital chip; it further includes various external components, such as analog filters, transformers, oscillator crystal, etc., which are not shown in detail; a person skilled in the art will be able to implement them. The digital chip performs the required digital signal processing functions and also incorporates a microcontroller interface. The mixed analog/digital chip performs the functions of D/A conversion and power amplification required for the transmit section of the transceiver frontend and the functions of variable gain amplification, signal buffering and A/D conversion needed for the receive section. Fixed passive analog filters for signal shaping are realized as a hybrid module. Analog signal equalization capability is provided by an external variable filter section. The variable elements of the variable filter can be realized, for example, by employing a matched nchannel JFET pair. As mentioned above, receiver timing is provided by VCO 23, which is here implemented as a voltage controlled crystal oscillator.
The main features of the transceiver as implemented for a LAN for seismic data acquisition, are:
 Transmission at 16 Mbit/s up to 250 m of voicegrade cable (UTP3) and up to 400 m of datagrade cable (UTP5);  Fallback rate of 8 Mbit/s (binary transmission);
 Power consumption of 200 mW at single +3.3 V operation voltage;
 Operating temperature from 50°C to +85°C;
 Link quality monitoring capability. The following is a more detailed description of the control functions as implemented in the above device. Variable gain, variable analog filter section, and timing are adjusted in the receiver's front end by three control voltages:
 control voltage u_{K}A} determines a frequencyindependent gain of amplifier 19,  control voltage u_{EQZ} varies the transfer function of the variable filter section 20,
 control voltage U^_{Q} controls the frequency of the voltagecontrolled oscillator 23 and thus the sampling phase t_{s} of A/D converter 22. The adjustments for these control voltages are computed in the digital transceiver section 12 by the following algorithms.
Gain Control
The value _{VCA π} stored in a digital accumulator of the VGA control loop at time n is adjusted according to the algorithm ^{u}vcA.n+ι ^{= u}vGA._{n}  ^{α}cΔ"^ > 0 < α_{G} « Λ where etc is the adaptation gain, and Δw_{rø π} = x„^{2}  2o_{a} ^{2} , where σ„ = E{a„^{2} } denotes the variance of the channel input symbols.
For a lowcomplexity implementation, the adjustment term Δu_{lϋA n} can be computed so that the A/D converter output signal samples achieve the same probability distribution as an ideal QPRIV signal: ( 7 if x„ > 6 ^{U} _{A}._{r}, = ( 1 if X» ≤ 2
( 0 if otherwise. The value _{VCA n} is then converted into a singlebit control signal by firstorder sigmadelta demodulation, not described here.
Adaptive Analog Equalizer Control
For an ideal PRIV signal x_{PRIV}(t), the autocorrelation function
^{R}«jwfl)' = ^{E} (^{x}PRnM ^{X}PRIl ^{t+ t}')} vanishes at /' = T. Since Δu^^ =x„x„_, represents an unbiased estimate of RJT), the value u_{EQZn} stored in a digital accumulator of the equalizer control loop is adjusted according to the algorithm:
^{U}EQZn l ^{= U}EQl.n " O^"^ > 0 < d_{E} « J , wherein ε is an adaptation gain. The value u_{EQZn} is then converted into a singlebit control signal by firstorder sigmadelta demodulation, not described here.
Timing Control
In a decisiondirected timing recovery algorithm, the sampling phase adjustment Δτ„ is computed to minimize the meansquare value of the error signal e_{n} = x_{n} s_{π} , where s_{n} denotes the signal sample at the output of an ideal channel at time n. The stochastic gradient of E{(x_{n} s } with respect to the sampling phase t_{s} is proportional to (x_{n} sj x„ « (x_{n} s (x_{π+l} x_{n} , wherein x„ is a time derivative of x_{n}. This leads to the definition of the gradient given by Muller and Mueller:
V_{τ}(<?^{2}) « e„ (x„_{+]} x_{n}_{]} ) = Aτ^{l}^^{i} _{<} where e„ = x„s„ is an estimate of the error signal obtained from a tentative decision s„ on the symbol s_{n}. However, using the above gradient has the disadvantage that the Scurve of the timing recovery loop, which is defined as the expectation of the gradient as a function of the sampling phase, exhibits a behavior that might determine falselock situations during initial timing acquisition. To overcome such difficulty, a modified MullerMueller algorithm is adopted, where the gradient is given by
V_{t}(ej) « e„ \ s„ J (*_{w+}ι  x,,] ) = Δτ„ .
This signal is then input to a secondorder loop filter. The filter output Δτ_{5},„ and a value Uacc.n, stored in the accumulator of the loop filter, are computed as follows: τ_{SJ}, = Uαccn + Y Δτ„ , Uαcc,n+\ = _{αcc},„ + ζ Δ^{"}C„ wherein γ and ζ are suitably selected loop gains. The value Δτ_{5},„ is then converted into a singlebit control signal by firstorder sigmadelta demodulation, not described here. To simplify the realization of the modified MullerMueller timing recovery algorithm, an approximation of the term (s„ )^{2} can be employed. Fιg.4 shows the block diagram of a simplified realization for a QPRIV system, where
Λ
( 2 e„ ( „_{+}ι  *„_ι ) if s„ = 6
Δτ„ = ( e„ (x„_{+]} x„_{\} ) if = 4
( 0 otherwise.
Viterbi Decoder with Embedded Feedback Filter
The received signal, denoted by x_{n}, is given by  ∑ ιa„ι + noise Since signal shaping into PRIV form is approximately achieved by analog equalization, one can assume for the system impulse response { h_{l} } h_{0} ~ + 1 , h_{2} » 1 , and h, = 0, C ≠ 0,2 Hence, one can rewrite the expression for the signal x_{n} as
9 x„ = (+1 + Aho)a„ + (1 + Afi_{2})a„_{2}+ ∑ Δ j/fl„_/ + noise,
/=] 1*1 where it is assumed that h_{l} = 0 for / 0 and / > 9
A simplified Viterbi decoding algorithm for the signal x„ is described as follows The received signal is first adjusted by removing the contribution of the intersymbol m
9 terference term ∑ Ahιa„ι An estimate of this term is provided by an auxiliary
/=l./*2 feedback filter in element 27 that uses tentative symbol decisions
Λ ' Λ f Λ I Λ I ^{a}n\ , ^{a}n _{5} ^{a}nA ^{■ a}n9 > from the most likely Viterbi decoder survivor path. The resulting signal is given by
where Δ hi „ represents an estimate of the coefficient Δhi at time n
The Viterbi decoder operates on the signals { _{n} } and determines the symbol sequence { a„ } which minimizes
The estimates of the channel impulse responses Δ ι_{0>},ι,ΔΛι,„, ΔΛ_{9,}„ are deter mined by an adaptive LMS algorithm such as to minimize ∑e„ .
To reduce implementation complexity, reducedstate Viterbi decoding is employed. State reduction is achieved by grouping the two states corresponding to the symbols +3 and 1 into one single state, and by grouping the two states corresponding to the symbols +1 and 3 into a second state. Note that state reduction requires that parallel transitions are resolved prior to the computation of the branch metrics. In order to reduce propagation delay, parallel transitions are resolved using the signal x_{n} rather than x„ . This approach is justified by our earlier assumption that the channel impulse response does not significantly deviate from the impulse response of an ideal PRIV channel. Note also that since at any time instant only two states are retained, the difference of the survivor metrics can be propagated from one iteration to the next, rather than the survivor metrics themselves.
A block diagram with the main functions of the adaptive Viterbi decoder with auxiliary feedback filter can be developed by someone skilled in the art. In an adaptive survivor metric unit, the difference metric is iteratively computed, the extension of
Λ Λ the survivor sequences is determined, and the estimates Δ A_{0,} „ and Δ h_{l n} are obtained by an adaptive LMS algorithm. A path history unit is used to store the two survivor sequences. An adaptive auxiliary feedback filter computes the signal correction term
9 _{Λ} ,
∑ Δ Λ_{/,}„ a„.,
I=\ , l≠2 using tentative symbol decisions stored in the path history unit, and adaptively gen
Λ Λ Λ erates the estimates Δ j_{]ιn} , Δ /._{3},„ , , Δ h_{9}„ . No detailed implementations of the adaptive survivor metric unit, the path memory, and the adaptive auxiliary feedback filter are shown since these can be implemented by someone skilled in the art. MeanSquared Error Computation
The meansquared error is computed in MSE meter 28 by lowpass filtering the metric increments. Such a device, again, can be implemented by someone skilled in the art and need therefore not be shown here in detail.
Descrambler and Differential Decoder
The bits representing the symbols output by the Viterbi decoder 27 are differentially decoded and descrambled by descrambler 29 which includes a descrambler whose transfer function is given by (l + D'^{3} + D^{28}). The descrambler output signal represents the recovered information bits. This concludes the description of the partial response system.
FullResponse System
An embodiment of the invention for a quaternary fullresponse system is shown in Fig.5 and described in the following. The filtering elements at the transmitter and the receiver must ensure that the signal y_{n} obtained at the decision element of an adaptive digital equalizer 57, in the embodiment a DFE, is free from intersymbol interference. This signal is given by y_{n} = a_{π}+ noise, where a„ e {3,l , + l, +3 } for quaternary modulation. In the embodiment, the linear forward equalizer of the
DFE is realized by a digital transversal filter.
Fig.5 gives an overview of a transceiver incorporating a fullresponse embodiment according to the invention. Each transceiver consists of a digital section 42, in which digital signal processing functions are performed, and a frontend section 43 for signal conversion, analog filtering, receiver clock generation, and cable driver/receiver functions.
In the transmitter, incoming quaternary symbols are represented by a 2bit signal TDAT. These incoming information bits are scrambled in scrambler 44 using the polynomial l+ D'^{3} + D^{28}and encoded by a 2B1Q differential encoder 45 to achieve transparency with respect to received signal polarity. After 2bit digitaltoanalog conversion in D/A converter 46, the resulting signal is shaped by a fixed transmit filter 47, then amplified by power amplifier 48, and transmitted via cable 41.
An incoming signal  from cable 41  is amplified by variable gain amplifier (VGA) 49 and filtered by a fixed analog filter 51. A control voltage determines the frequency independent gain of VGA 49. The control signal for the VGA is derived digitally.
Received signal samples x_{n} are obtained in analogtodigital (A/D) converter 52 by 6bit A/D conversion at a rate of MT symbols per second. The sampling phase of A/D converter 52 is determined by a voltagecontrolled oscillator (VCO) 53 whose control voltage is adjusted by the disclosed decisiondirected timing recovery algo rithm. To simplify conversion, the control voltage for VCO 53 is provided by control circuit 59 in binary sigmadelta modulated form, as is the control voltage for VGA 49. Two sigmadelta demodulators 54 and 56 serve to derive the required analog control voltages.
SelfTraining Equalization for FullResponse Systems The thus derived 6bitwide signal samples x_{n} are transferred into the delay line of the linear forward equalizer of an adaptive equalizer 57, here a decision feedback equalizer (DFE). The output of this equalizer is given by v = c x  dj b „ , wherein
c = {c_{0 n} c_{NΛ} „ } denotes the vector of coefficients of the linear forward equalizer,
&I = i „  •••• d_{LΛ n} } denotes the vector of coefficients of the feedback filter, x = {x_{n} x_{π Λ},_{+1} } represents the vector of signals stored in the equalizer delay line at time n , and b = {ύ_{π l} ό_{n L+i} } represents the vector of tentative quaternary decisions stored in the feedback filter delay line at time n. Traditionally, the LMS algorithm described in E. A. Lee, and D. G. Messerschmitt, cited above, Ch. 9, is employed for decisiondirected adjustment of the DFE coefficients: c_{π+1} = c_{n} α^ t_{n} x_{n} ,
where α^ is the adaptation gain and e_{n} an error signal given by &„ = y_{n}  b_{n}.
If the DFE operates in selftraining mode, the coefficients of the feedback filter are normally set to zero; then the output of the equalizer is given by y_{n} = c_{π} ^{τ} x_{n}.
For self training, we cannot rely on the correctness of decisions ύ_{π} , and hence on the error signals _{n} . We will use instead of ύ_{n} a pseudo error defined by ( y„  b„ if [v_{π}\ > 3
(  δ„ sιgn(y_{n}) otherwise, where δ_{π} is a parameter in the range (0. δ_{m} , δ_{m r} > 0. The parameter is updated at each iteration as follows:
_{=} ( δ„  3Δ if iv > 3, "^{4 } ( δ + Δ otherwise, and Δ is a small positive constant
The generation of the pseudo error J., is based on a priori knowledge of the statistics of the signal. In the case of accomplished equalization, y_{n} corresponds to the quaternary channel input symbols a_{r} embedded in noise. Therefore, whenever the event \y_{n}\ > 3 is observed, we can use y_{n}  ύ_{n} as a trusted error to update the equalizer coefficients. If we observe the event y_{n}\ < 3, no trusted error is available. In this case, we choose to update the equalizer coefficients so that the probabilities of the events \y_{π}\ < 3 and \y_{n}\ > 3 assume the values 3/4 and 1/4 , respectively, which are the probabilities of these events for an ideally equalized noisy quaternary signal, provided that the input symbols form a sequence of independent identically distributed random variables. This is achieved by setting the pseudo error equal to δ_{π} sign(y_{π}) whenever \y_{π}\ < 3 and updating the value of δ„at each iteration so that δ_{n} becomes larger if the event \y_{n}\ < 3 occurs more often than expected, and δ_{π} becomes smaller otherwise. The algorithm for selftraining adaptive equalization is then given by c„_{+l} = c_{π} _{st} ε_{n} x_{n} , where _{st} is the adaptation gain during self training.
Several variants of the algorithm can be obtained through different simplifications. For example, pseudo errors can be computed based on the signal energy at the equalizer output. If the signal energy is found to be too often below a given threshold, the error term is set equal to  c sιgn(y_{n}), where c is a positive constant, whenever \y_{n}\ < 3 , and trusted errors are used when \y_{n}\ > 3 .
In this embodiment, symbolrate sampling at the receiver is assumed . In practice, it is common to sample the received signal at a rate larger than the symbol rate and employ fractionallyspaced equalization. The extension of the described self training algorithm to this case is straightforward.
An estimate of the average squared error signal (MSE) at the decision point is computed in MSE meter 50 to monitor the "transmissionlink quality". If the MSE drops below a given threshold, tentative decisions on the transmitted symbols are sufficiently reliable. Then the DFE enters decisiondirected mode and updating of all DFE coefficients by the LMS algorithm takes place.
As an alternative to the above described freezing the coefficients of the feedback filter in the selftraining mode, these coefficients can be updated also during self training by ύf_{π+ 1} = d_{n} + _{sl} ε_{n} b_{n} .
The signals at the output of the decision feedback filter are differentially decoded and descrambled in descrambler 60. The recovered quaternary symbols are represented by the twobit signal RDAT at the output of the digital section 42 of the transceiver. Light line 61 in Fig.5 carries a receiver clock signal RCLK' produced by VCO 53; this clock signal RCLK' controls all digital receiver functions. In the transmit section of the transceiver, an externally provided transmitter clock signal TCLK' serves the same function, as indicated.
The invention has been shown and explained with reference to the drawings and the underlying theoretical considerations; these details, however, are not intended to limit the scope of the invention as defined in the appended claims.
Claims
Priority Applications (1)
Application Number  Priority Date  Filing Date  Title 

PCT/IB1996/000873 WO1998009400A1 (en)  19960830  19960830  Receiving and equalizing signals for highspeed data transmission 
Applications Claiming Priority (1)
Application Number  Priority Date  Filing Date  Title 

PCT/IB1996/000873 WO1998009400A1 (en)  19960830  19960830  Receiving and equalizing signals for highspeed data transmission 
Publications (1)
Publication Number  Publication Date 

WO1998009400A1 true true WO1998009400A1 (en)  19980305 
Family
ID=11004466
Family Applications (1)
Application Number  Title  Priority Date  Filing Date 

PCT/IB1996/000873 WO1998009400A1 (en)  19960830  19960830  Receiving and equalizing signals for highspeed data transmission 
Country Status (1)
Country  Link 

WO (1)  WO1998009400A1 (en) 
Cited By (8)
Publication number  Priority date  Publication date  Assignee  Title 

FR2786349A1 (en) *  19981014  20000526  Samsung Electronics Co Ltd  Equalizer againstreactionmaking and implementation process at day index coefficients of it 
WO2000065772A2 (en) *  19990422  20001102  Broadcom Corporation  Phy control module for a multipair gigabit transceiver 
US6363129B1 (en)  19981109  20020326  Broadcom Corporation  Timing recovery system for a multipair gigabit transceiver 
EP1420556A2 (en) *  20021115  20040519  STMicroelectronics, Inc.  Filter bank for long Ethernet links 
US6928106B1 (en)  19980828  20050809  Broadcom Corporation  Phy control module for a multipair gigabit transceiver 
US7634001B2 (en)  19980828  20091215  Broadcom Corporation  Dynamic regulation of power consumption of a highspeed communication system 
US7778313B2 (en)  19980828  20100817  Broadcom Corporation  PHY control module for a multipair gigabit transceiver 
WO2013158106A1 (en)  20120419  20131024  Intel Corporation  Unequalized clock data recovery for serial i/o receiver 
Citations (1)
Publication number  Priority date  Publication date  Assignee  Title 

EP0729251A2 (en) *  19950224  19960828  Matsushita Electric Industrial Co., Ltd.  Data reproducing method and data reproducing unit with sampling 
Patent Citations (1)
Publication number  Priority date  Publication date  Assignee  Title 

EP0729251A2 (en) *  19950224  19960828  Matsushita Electric Industrial Co., Ltd.  Data reproducing method and data reproducing unit with sampling 
NonPatent Citations (1)
Title 

CHERUBINI G ET AL: "ADAPTIVE ANALOG EQUALIZATION AND RECEIVER FRONTEND CONTROL FOR MULTILEVEL PARTIALRESPONSE TRANSMISSION OVER METALLIC CABLES", IEEE TRANSACTIONS ON COMMUNICATIONS, vol. 44, no. 6, 1 June 1996 (19960601), pages 675  685, XP000599965 * 
Cited By (18)
Publication number  Priority date  Publication date  Assignee  Title 

US7443910B2 (en)  19980828  20081028  Broadcom Corporation  PHY control module for a multipair gigabit transceiver 
US8077762B2 (en)  19980828  20111213  Broadcom Corporation  PHY control module for a multipair gigabit transceiver 
US7778313B2 (en)  19980828  20100817  Broadcom Corporation  PHY control module for a multipair gigabit transceiver 
US7672368B2 (en)  19980828  20100302  Broadcom Corporation  PHY control module for a multipair gigabit transceiver 
US7634001B2 (en)  19980828  20091215  Broadcom Corporation  Dynamic regulation of power consumption of a highspeed communication system 
US6928106B1 (en)  19980828  20050809  Broadcom Corporation  Phy control module for a multipair gigabit transceiver 
US6807229B1 (en)  19981014  20041019  Samsung Electronics Co., Ltd.  Decision feedback equalizer and method for updating tap coefficients thereof 
FR2786349A1 (en) *  19981014  20000526  Samsung Electronics Co Ltd  Equalizer againstreactionmaking and implementation process at day index coefficients of it 
US7116742B2 (en)  19981109  20061003  Broadcom Corporation  Timing recovery system for a multipair gigabit transceiver 
US6363129B1 (en)  19981109  20020326  Broadcom Corporation  Timing recovery system for a multipair gigabit transceiver 
WO2000065772A3 (en) *  19990422  20020103  Broadcom Corp  Phy control module for a multipair gigabit transceiver 
WO2000065772A2 (en) *  19990422  20001102  Broadcom Corporation  Phy control module for a multipair gigabit transceiver 
EP1420556A3 (en) *  20021115  20070411  STMicroelectronics, Inc.  Filter bank for long Ethernet links 
EP1420556A2 (en) *  20021115  20040519  STMicroelectronics, Inc.  Filter bank for long Ethernet links 
WO2013158106A1 (en)  20120419  20131024  Intel Corporation  Unequalized clock data recovery for serial i/o receiver 
EP2839582A4 (en) *  20120419  20151216  Intel Corp  Unequalized clock data recovery for serial i/o receiver 
US9479364B2 (en)  20120419  20161025  Intel Corporation  Unequalized clock data recovery for serial I/O receiver 
US10009194B2 (en)  20120419  20180626  Intel Corporation  Unequalized clock data recovery for serial I/O receiver 
Similar Documents
Publication  Publication Date  Title 

Tong et al.  Blind identification and equalization based on secondorder statistics: A time domain approach  
Giannakis  Filterbanks for blind channel identification and equalization  
Li et al.  Global convergence of fractionally spaced Godard (CMA) adaptive equalizers  
Belfiore et al.  Decision feedback equalization  
US5285482A (en)  Timing recovery device for receiver installation using adaptive equalization and oversampling associated with differentially coherent demodulation  
US5052024A (en)  Offset frequency multipoint modem and communications network  
US6259743B1 (en)  Automatic constellation phase recovery in blind startup of a dual mode CAPQAM receiver  
Ready et al.  Blind equalization based on radius directed adaptation  
US7016406B1 (en)  Adaptation structure and methods for analog continuous time equalizers  
US6212225B1 (en)  Startup protocol for high throughput communications systems  
US6570916B1 (en)  Adaptive equalization circuit and method  
US4995057A (en)  Technique for achieving the theoretical coding gain of digital signals incorporating error correction  
US5020078A (en)  Baudrate timing recovery technique  
Ungerboeck  Fractional tapspacing equalizer and consequences for clock recovery in data modems  
US5293401A (en)  Equalizer for linear modulated signal  
US20010035997A1 (en)  Highspeed transmission system for optical channels  
US5157690A (en)  Adaptive convergent decision feedback equalizer  
Stojanovic et al.  Phasecoherent digital communications for underwater acoustic channels  
US5432821A (en)  System and method for estimating data sequences in digital transmissions  
US20030134607A1 (en)  Multichannel communications transceiver  
US6363129B1 (en)  Timing recovery system for a multipair gigabit transceiver  
US7254198B1 (en)  Receiver system having analog prefilter and digital equalizer  
Cioffi et al.  MMSE decisionfeedback equalizers and coding. I. Equalization results  
US5003555A (en)  Data transmission system comprising a decision feedback equalizer and using partialresponse techniques  
US20030072380A1 (en)  Method and apparatus for crosstalk mitigation through joint multiuser adaptive precoding 
Legal Events
Date  Code  Title  Description 

AL  Designated countries for regional patents 
Kind code of ref document: A1 Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE 

AK  Designated states 
Kind code of ref document: A1 Designated state(s): JP KR US 

WWE  Wipo information: entry into national phase 
Ref document number: 09066475 Country of ref document: US 

121  Ep: the epo has been informed by wipo that ep was designated in this application  
NENP  Nonentry into the national phase in: 
Ref country code: JP Ref document number: 98511411 Format of ref document f/p: F 

NENP  Nonentry into the national phase in: 
Ref country code: CA 

122  Ep: pct application nonentry in european phase 