BR0002574A - Sistema com fase de relógio adc ajustável - Google Patents

Sistema com fase de relógio adc ajustável

Info

Publication number
BR0002574A
BR0002574A BR0002574-7A BR0002574A BR0002574A BR 0002574 A BR0002574 A BR 0002574A BR 0002574 A BR0002574 A BR 0002574A BR 0002574 A BR0002574 A BR 0002574A
Authority
BR
Brazil
Prior art keywords
clock phase
adc clock
clock
phases
selection circuit
Prior art date
Application number
BR0002574-7A
Other languages
English (en)
Inventor
Mark Francis Rumreich
David Lawrence Albean
John William Gyurek
Original Assignee
Thomson Licensing Sa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing Sa filed Critical Thomson Licensing Sa
Publication of BR0002574A publication Critical patent/BR0002574A/pt

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H03M1/0818Continuously compensating for, or preventing, undesired influence of physical parameters of noise of clock feed-through
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

"SISTEMA COM FASE DE RELóGIO ADC AJUSTáVEL" Conversores analógicos para digitais (80) com desempenho aperfeiçoado na presença de interferência por barulho de relógio são configurados com um circuito de seleção de fase de relógio de amostragem (85) a fim de possibilitar a operação do conversor a intervalos de tempo de amostragem ótimos com relação ao barulho de interferência. O circuito de seleção inclui o aparelho para a geração de uma pluralidade de fases de relógio de amostragem, e um multiplexador acoplado à pluralidade de fases de modo a selecionar a fase de relógio ótima.
BR0002574-7A 1999-06-04 2000-06-02 Sistema com fase de relógio adc ajustável BR0002574A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/327,088 US6310570B1 (en) 1999-06-04 1999-06-04 System with adjustable ADC clock phase

Publications (1)

Publication Number Publication Date
BR0002574A true BR0002574A (pt) 2001-01-02

Family

ID=23275112

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0002574-7A BR0002574A (pt) 1999-06-04 2000-06-02 Sistema com fase de relógio adc ajustável

Country Status (10)

Country Link
US (1) US6310570B1 (pt)
EP (2) EP1058387B1 (pt)
JP (2) JP2001053609A (pt)
KR (1) KR101054855B1 (pt)
CN (2) CN1187900C (pt)
BR (1) BR0002574A (pt)
DE (2) DE60035456T2 (pt)
HK (1) HK1070756A1 (pt)
MX (1) MXPA00005503A (pt)
MY (1) MY123664A (pt)

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US7209061B2 (en) * 2005-03-30 2007-04-24 Silicon Laboratories, Inc. Method and system for sampling a signal
JP2008544620A (ja) * 2005-06-14 2008-12-04 エヌエックスピー ビー ヴィ 干渉補償による信号処理
US8331512B2 (en) * 2006-04-04 2012-12-11 Rambus Inc. Phase control block for managing multiple clock domains in systems with frequency offsets
KR100835682B1 (ko) * 2006-07-18 2008-06-09 고려대학교 산학협력단 노이즈에 따라 샘플링 주기를 제어하는 아날로그 디지털변환 장치, 이를 이용한 오디오 기록 장치 및 심박 조율장치
US7612595B2 (en) * 2006-09-19 2009-11-03 Melexis Tessenderlo Nv Sequence independent non-overlapping digital signal generator with programmable delay
US7928884B2 (en) * 2007-01-11 2011-04-19 Siflare, Inc. Analog-to-digital converter with a balanced output
US7940202B1 (en) * 2008-07-31 2011-05-10 Cypress Semiconductor Corporation Clocking analog components operating in a digital system
EP2226963B1 (en) * 2009-03-04 2013-05-08 Sony Corporation Receiving apparatus and method with non-oversampling analog to digital conversion
JP5221446B2 (ja) 2009-05-19 2013-06-26 株式会社東芝 干渉除去装置および通信装置
US8279100B2 (en) * 2010-09-30 2012-10-02 Lockheed Martin Corporation Complex analog to digital converter (CADC) system on chip double rate architecture
CN101977057B (zh) * 2010-11-04 2013-05-22 青岛海信移动通信技术股份有限公司 一种模数转换电路
JP5547765B2 (ja) * 2012-03-23 2014-07-16 旭化成エレクトロニクス株式会社 D/a変換器、ジッタ周波数制御回路
JP5547767B2 (ja) * 2012-03-28 2014-07-16 旭化成エレクトロニクス株式会社 サンプリング回路、a/d変換器、d/a変換器、codec
DE102012208281A1 (de) * 2012-05-16 2013-11-21 Robert Bosch Gmbh Verfahren zur Entstörung eines Abtastprozesses sowie eine Vorrichtung zur Durchführung des Verfahrens
US9000809B2 (en) * 2012-05-30 2015-04-07 Infineon Technologies Austria Ag Method and device for sampling an input signal
CN104158542B (zh) * 2014-08-25 2017-04-05 东南大学 一种基于欠采样技术锁相环长周期抖动片上测量电路
US9496887B1 (en) * 2015-05-12 2016-11-15 Microchip Technology Incorporated Analog to digital converter with internal timer
US9312875B1 (en) * 2015-06-26 2016-04-12 Intel IP Corporation Signal processing apparatus and method for processing a signal
CN108345554B (zh) * 2017-01-22 2020-08-21 联发科技股份有限公司 决定出取样时脉信号的取样相位的方法及相关的电子装置
EP3591433B1 (en) * 2018-07-02 2023-06-14 NXP USA, Inc. Communication unit, integrated circuits and method for clock and data synchronization
CN113237501B (zh) * 2021-04-19 2022-06-17 上海季丰电子股份有限公司 一种高精度的多通道信号校准方法及装置
CN114389607B (zh) * 2021-12-24 2024-06-04 莱弗利科技(苏州)有限公司 一种低噪声干扰的数模混合芯片
CN117411466A (zh) * 2023-11-07 2024-01-16 上海芯炽科技集团有限公司 一种基于数字相位发生器和选择器的cdr电路

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US4791488A (en) * 1987-08-12 1988-12-13 Rca Licensing Corporation Line-locked clock signal generation system
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Also Published As

Publication number Publication date
DE60035456T2 (de) 2008-03-13
CN1187900C (zh) 2005-02-02
US6310570B1 (en) 2001-10-30
DE60044271D1 (de) 2010-06-02
CN100361394C (zh) 2008-01-09
EP1758252B1 (en) 2010-04-21
KR20010007195A (ko) 2001-01-26
MXPA00005503A (es) 2004-06-07
EP1058387B1 (en) 2007-07-11
EP1058387A3 (en) 2003-10-29
HK1070756A1 (en) 2005-06-24
JP2011223589A (ja) 2011-11-04
JP2001053609A (ja) 2001-02-23
CN1277492A (zh) 2000-12-20
MY123664A (en) 2006-05-31
DE60035456D1 (de) 2007-08-23
KR101054855B1 (ko) 2011-08-05
EP1058387A2 (en) 2000-12-06
EP1758252A1 (en) 2007-02-28
CN1578153A (zh) 2005-02-09

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B09B Patent application refused [chapter 9.2 patent gazette]

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