AU2003296321A1 - Integrated circuit structure with improved ldmos design - Google Patents

Integrated circuit structure with improved ldmos design

Info

Publication number
AU2003296321A1
AU2003296321A1 AU2003296321A AU2003296321A AU2003296321A1 AU 2003296321 A1 AU2003296321 A1 AU 2003296321A1 AU 2003296321 A AU2003296321 A AU 2003296321A AU 2003296321 A AU2003296321 A AU 2003296321A AU 2003296321 A1 AU2003296321 A1 AU 2003296321A1
Authority
AU
Australia
Prior art keywords
integrated circuit
circuit structure
improved ldmos
ldmos design
design
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003296321A
Other languages
English (en)
Other versions
AU2003296321A8 (en
Inventor
Jun Cai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Publication of AU2003296321A8 publication Critical patent/AU2003296321A8/xx
Publication of AU2003296321A1 publication Critical patent/AU2003296321A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30—Devices controlled by electric currents or voltages
    • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H10D48/36—Unipolar devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H10D30/0285—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs using formation of insulating sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
AU2003296321A 2002-12-10 2003-12-09 Integrated circuit structure with improved ldmos design Abandoned AU2003296321A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/315,517 US6870218B2 (en) 2002-12-10 2002-12-10 Integrated circuit structure with improved LDMOS design
US10/315,517 2002-12-10
PCT/US2003/038931 WO2004053939A2 (en) 2002-12-10 2003-12-09 Integrated circuit structure with improved ldmos design

Publications (2)

Publication Number Publication Date
AU2003296321A8 AU2003296321A8 (en) 2004-06-30
AU2003296321A1 true AU2003296321A1 (en) 2004-06-30

Family

ID=32468724

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003296321A Abandoned AU2003296321A1 (en) 2002-12-10 2003-12-09 Integrated circuit structure with improved ldmos design

Country Status (8)

Country Link
US (3) US6870218B2 (enExample)
JP (1) JP2006510206A (enExample)
KR (1) KR101030178B1 (enExample)
CN (1) CN100524812C (enExample)
AU (1) AU2003296321A1 (enExample)
DE (1) DE10393858T5 (enExample)
TW (1) TWI355074B (enExample)
WO (1) WO2004053939A2 (enExample)

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US6870218B2 (en) * 2002-12-10 2005-03-22 Fairchild Semiconductor Corporation Integrated circuit structure with improved LDMOS design
JP4800566B2 (ja) * 2003-10-06 2011-10-26 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US7180132B2 (en) * 2004-09-16 2007-02-20 Fairchild Semiconductor Corporation Enhanced RESURF HVPMOS device with stacked hetero-doping RIM and gradual drift region
JP4907920B2 (ja) * 2005-08-18 2012-04-04 株式会社東芝 半導体装置及びその製造方法
US7736984B2 (en) * 2005-09-23 2010-06-15 Semiconductor Components Industries, Llc Method of forming a low resistance semiconductor contact and structure therefor
CN100370625C (zh) * 2005-10-14 2008-02-20 西安电子科技大学 可集成的高压p型ldmos晶体管结构及其制备方法
KR100778861B1 (ko) * 2006-12-12 2007-11-22 동부일렉트로닉스 주식회사 Ｌｄｍｏｓ 반도체 소자의 제조 방법
US8035159B2 (en) * 2007-04-30 2011-10-11 Alpha & Omega Semiconductor, Ltd. Device structure and manufacturing method using HDP deposited source-body implant block
KR100840667B1 (ko) * 2007-06-26 2008-06-24 주식회사 동부하이텍 수평형 디모스 소자 및 그 제조방법
US8063443B2 (en) 2007-10-30 2011-11-22 Fairchild Semiconductor Corporation Hybrid-mode LDMOS
JP5329118B2 (ja) * 2008-04-21 2013-10-30 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー Ｄｍｏｓトランジスタ
US7906810B2 (en) * 2008-08-06 2011-03-15 United Microelectronics Corp. LDMOS device for ESD protection circuit
US8138558B2 (en) * 2010-08-20 2012-03-20 Great Wall Semiconductor Corporation Semiconductor device and method of forming low voltage MOSFET for portable electronic devices and data processing centers
JP5700649B2 (ja) * 2011-01-24 2015-04-15 旭化成エレクトロニクス株式会社 半導体装置の製造方法
CN102681370B (zh) * 2012-05-09 2016-04-20 上海华虹宏力半导体制造有限公司 光刻套刻方法和提高ldmos器件击穿稳定性的方法
CN103456734B (zh) * 2012-05-28 2016-04-13 上海华虹宏力半导体制造有限公司 一种非对称ldmos工艺偏差的监控结构及其制造方法
US9337284B2 (en) * 2014-04-07 2016-05-10 Alpha And Omega Semiconductor Incorporated Closed cell lateral MOSFET using silicide source and body regions
US10038063B2 (en) 2014-06-10 2018-07-31 International Business Machines Corporation Tunable breakdown voltage RF FET devices
US9397090B1 (en) * 2015-04-10 2016-07-19 Macronix International Co., Ltd. Semiconductor device
CN108493113A (zh) * 2018-03-30 2018-09-04 北京时代民芯科技有限公司 一种低电阻抗辐照vdmos芯片的制造方法
TWI666681B (zh) * 2018-07-18 2019-07-21 帥群微電子股份有限公司 半導體功率元件及其製造方法
CN111200020B (zh) * 2019-04-15 2021-01-08 合肥晶合集成电路股份有限公司 高耐压半导体元件及其制造方法
US20210020630A1 (en) * 2019-04-15 2021-01-21 Nexchip Semiconductor Co., Ltd. High-voltage tolerant semiconductor element
US12295155B2 (en) * 2020-07-14 2025-05-06 Newport Fab, Llc Asymmetric halo-implant body-source-tied semiconductor-on-insulator (SOI) device
US11581215B2 (en) * 2020-07-14 2023-02-14 Newport Fab, Llc Body-source-tied semiconductor-on-insulator (SOI) transistor
CN116207142B (zh) * 2023-05-04 2023-07-18 合肥晶合集成电路股份有限公司 一种半导体结构及其制作方法

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Also Published As

Publication number Publication date
US20050239253A1 (en) 2005-10-27
KR20050085383A (ko) 2005-08-29
KR101030178B1 (ko) 2011-04-18
AU2003296321A8 (en) 2004-06-30
WO2004053939A3 (en) 2005-07-21
CN100524812C (zh) 2009-08-05
US7220646B2 (en) 2007-05-22
US20040108548A1 (en) 2004-06-10
TWI355074B (en) 2011-12-21
WO2004053939A2 (en) 2004-06-24
CN1757118A (zh) 2006-04-05
US7608512B2 (en) 2009-10-27
DE10393858T5 (de) 2007-03-15
JP2006510206A (ja) 2006-03-23
US20070141792A1 (en) 2007-06-21
US6870218B2 (en) 2005-03-22
TW200503266A (en) 2005-01-16

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase