AU2002334182A1 - Integrated circuit layout modification - Google Patents

Integrated circuit layout modification

Info

Publication number
AU2002334182A1
AU2002334182A1 AU2002334182A AU2002334182A AU2002334182A1 AU 2002334182 A1 AU2002334182 A1 AU 2002334182A1 AU 2002334182 A AU2002334182 A AU 2002334182A AU 2002334182 A AU2002334182 A AU 2002334182A AU 2002334182 A1 AU2002334182 A1 AU 2002334182A1
Authority
AU
Australia
Prior art keywords
integrated circuit
circuit layout
layout modification
modification
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002334182A
Inventor
Gerard Anthony Allan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Edinburgh
Original Assignee
University of Edinburgh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Edinburgh filed Critical University of Edinburgh
Publication of AU2002334182A1 publication Critical patent/AU2002334182A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AU2002334182A 2002-04-26 2002-10-17 Integrated circuit layout modification Abandoned AU2002334182A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GBGB0209626.1A GB0209626D0 (en) 2002-04-26 2002-04-26 Integrated circuit layout modification
GB0209626.1 2002-04-26
PCT/GB2002/004690 WO2003092067A2 (en) 2002-04-26 2002-10-17 Integrated circuit layout modification

Publications (1)

Publication Number Publication Date
AU2002334182A1 true AU2002334182A1 (en) 2003-11-10

Family

ID=9935603

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002334182A Abandoned AU2002334182A1 (en) 2002-04-26 2002-10-17 Integrated circuit layout modification

Country Status (3)

Country Link
AU (1) AU2002334182A1 (en)
GB (1) GB0209626D0 (en)
WO (1) WO2003092067A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7698679B2 (en) 2006-07-13 2010-04-13 Infineon Technologies Ag Method and apparatus for automatic routing yield optimization
CN100449556C (en) * 2007-02-05 2009-01-07 智原科技股份有限公司 Circuit unit of integrated circuit and related technology and method
US9041069B2 (en) * 2011-01-14 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Distributed metal routing

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0756878B2 (en) * 1990-05-30 1995-06-14 シャープ株式会社 Inspection method of printed wiring board
US5798937A (en) * 1995-09-28 1998-08-25 Motorola, Inc. Method and apparatus for forming redundant vias between conductive layers of an integrated circuit
US5984510A (en) * 1996-11-01 1999-11-16 Motorola Inc. Automatic synthesis of standard cell layouts

Also Published As

Publication number Publication date
GB0209626D0 (en) 2002-06-05
WO2003092067A2 (en) 2003-11-06
WO2003092067A3 (en) 2004-04-01

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase