AU2001273526A1 - Devices and methods for addressing optical edge effects in connection with etched trenches - Google Patents

Devices and methods for addressing optical edge effects in connection with etched trenches

Info

Publication number
AU2001273526A1
AU2001273526A1 AU2001273526A AU7352601A AU2001273526A1 AU 2001273526 A1 AU2001273526 A1 AU 2001273526A1 AU 2001273526 A AU2001273526 A AU 2001273526A AU 7352601 A AU7352601 A AU 7352601A AU 2001273526 A1 AU2001273526 A1 AU 2001273526A1
Authority
AU
Australia
Prior art keywords
methods
devices
connection
edge effects
etched trenches
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001273526A
Other languages
English (en)
Inventor
Fwu-Iuan Hshieh
Koon Chong So
Yan Man Tsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Semiconductor Inc
Original Assignee
General Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Semiconductor Inc filed Critical General Semiconductor Inc
Publication of AU2001273526A1 publication Critical patent/AU2001273526A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
AU2001273526A 2000-07-17 2001-07-17 Devices and methods for addressing optical edge effects in connection with etched trenches Abandoned AU2001273526A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/617,356 US6555895B1 (en) 2000-07-17 2000-07-17 Devices and methods for addressing optical edge effects in connection with etched trenches
US09617356 2000-07-17
PCT/US2001/022456 WO2002007201A2 (en) 2000-07-17 2001-07-17 Method for etching trenches for the fabrication of semiconductor devices

Publications (1)

Publication Number Publication Date
AU2001273526A1 true AU2001273526A1 (en) 2002-01-30

Family

ID=24473331

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001273526A Abandoned AU2001273526A1 (en) 2000-07-17 2001-07-17 Devices and methods for addressing optical edge effects in connection with etched trenches

Country Status (8)

Country Link
US (3) US6555895B1 (zh)
EP (1) EP1303871A2 (zh)
JP (1) JP4122215B2 (zh)
KR (3) KR20070116909A (zh)
CN (1) CN1193411C (zh)
AU (1) AU2001273526A1 (zh)
TW (1) TW508694B (zh)
WO (1) WO2002007201A2 (zh)

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US7745289B2 (en) 2000-08-16 2010-06-29 Fairchild Semiconductor Corporation Method of forming a FET having ultra-low on-resistance and low gate charge
US6818513B2 (en) 2001-01-30 2004-11-16 Fairchild Semiconductor Corporation Method of forming a field effect transistor having a lateral depletion structure
US6916745B2 (en) 2003-05-20 2005-07-12 Fairchild Semiconductor Corporation Structure and method for forming a trench MOSFET having self-aligned features
US6803626B2 (en) 2002-07-18 2004-10-12 Fairchild Semiconductor Corporation Vertical charge control semiconductor device
JP3701227B2 (ja) * 2001-10-30 2005-09-28 三菱電機株式会社 半導体装置及びその製造方法
US7576388B1 (en) 2002-10-03 2009-08-18 Fairchild Semiconductor Corporation Trench-gate LDMOS structures
US6710418B1 (en) 2002-10-11 2004-03-23 Fairchild Semiconductor Corporation Schottky rectifier with insulation-filled trenches and method of forming the same
US6716709B1 (en) * 2002-12-31 2004-04-06 Texas Instruments Incorporated Transistors formed with grid or island implantation masks to form reduced diffusion-depth regions without additional masks and process steps
US7022247B2 (en) * 2003-03-26 2006-04-04 Union Semiconductor Technology Corporation Process to form fine features using photolithography and plasma etching
TWI223448B (en) * 2003-04-29 2004-11-01 Mosel Vitelic Inc DMOS device having a trenched bus structure
US7652326B2 (en) 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
KR100511045B1 (ko) * 2003-07-14 2005-08-30 삼성전자주식회사 리세스된 게이트 전극을 갖는 반도체 소자의 집적방법
US7138638B2 (en) * 2003-11-20 2006-11-21 Juni Jack E Edge effects treatment for crystals
KR100994719B1 (ko) 2003-11-28 2010-11-16 페어차일드코리아반도체 주식회사 슈퍼정션 반도체장치
US7368777B2 (en) 2003-12-30 2008-05-06 Fairchild Semiconductor Corporation Accumulation device with charge balance structure and method of forming the same
US7352036B2 (en) 2004-08-03 2008-04-01 Fairchild Semiconductor Corporation Semiconductor power device having a top-side drain using a sinker trench
JP2006196545A (ja) * 2005-01-11 2006-07-27 Toshiba Corp 半導体装置の製造方法
DE112006000832B4 (de) 2005-04-06 2018-09-27 Fairchild Semiconductor Corporation Trenched-Gate-Feldeffekttransistoren und Verfahren zum Bilden derselben
WO2006135746A2 (en) 2005-06-10 2006-12-21 Fairchild Semiconductor Corporation Charge balance field effect transistor
US20070157516A1 (en) * 2006-01-09 2007-07-12 Fischer Bernhard A Staged modular hydrocarbon reformer with internal temperature management
US7446374B2 (en) 2006-03-24 2008-11-04 Fairchild Semiconductor Corporation High density trench FET with integrated Schottky diode and method of manufacture
US7319256B1 (en) 2006-06-19 2008-01-15 Fairchild Semiconductor Corporation Shielded gate trench FET with the shield and gate electrodes being connected together
US8928077B2 (en) 2007-09-21 2015-01-06 Fairchild Semiconductor Corporation Superjunction structures for power devices
US7772668B2 (en) 2007-12-26 2010-08-10 Fairchild Semiconductor Corporation Shielded gate trench FET with multiple channels
US20120273916A1 (en) 2011-04-27 2012-11-01 Yedinak Joseph A Superjunction Structures for Power Devices and Methods of Manufacture
US8319290B2 (en) 2010-06-18 2012-11-27 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
JP5691259B2 (ja) * 2010-06-22 2015-04-01 株式会社デンソー 半導体装置
CN102183265A (zh) * 2011-02-10 2011-09-14 刘清惓 一种用于测量表面覆盖物的电容传感器及测量方法
US8836028B2 (en) 2011-04-27 2014-09-16 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8786010B2 (en) 2011-04-27 2014-07-22 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8673700B2 (en) 2011-04-27 2014-03-18 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8772868B2 (en) 2011-04-27 2014-07-08 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
EP3496153B1 (en) * 2017-12-05 2021-05-19 STMicroelectronics S.r.l. Manufacturing method of a semiconductor device with efficient edge structure
CN112864239B (zh) * 2021-03-17 2022-04-26 长江存储科技有限责任公司 场效应晶体管及其制备方法

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US5072266A (en) 1988-12-27 1991-12-10 Siliconix Incorporated Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
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JPH10199859A (ja) * 1997-01-08 1998-07-31 Hitachi Ltd 半導体装置の製造方法
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US6372605B1 (en) * 2000-06-26 2002-04-16 Agere Systems Guardian Corp. Additional etching to decrease polishing time for shallow-trench isolation in semiconductor processing

Also Published As

Publication number Publication date
WO2002007201A3 (en) 2002-04-18
KR20070116909A (ko) 2007-12-11
WO2002007201A2 (en) 2002-01-24
JP2004504719A (ja) 2004-02-12
KR20030018050A (ko) 2003-03-04
EP1303871A2 (en) 2003-04-23
KR100848850B1 (ko) 2008-07-29
US20020093048A1 (en) 2002-07-18
TW508694B (en) 2002-11-01
US6576952B2 (en) 2003-06-10
JP4122215B2 (ja) 2008-07-23
CN1193411C (zh) 2005-03-16
US20020008281A1 (en) 2002-01-24
KR100829047B1 (ko) 2008-05-16
US6555895B1 (en) 2003-04-29
US6475884B2 (en) 2002-11-05
CN1449573A (zh) 2003-10-15
KR20070107188A (ko) 2007-11-06

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