ATE67619T1 - Verfahren und schaltungsanordnung zur addition von gleitkommazahlen. - Google Patents

Verfahren und schaltungsanordnung zur addition von gleitkommazahlen.

Info

Publication number
ATE67619T1
ATE67619T1 AT86115152T AT86115152T ATE67619T1 AT E67619 T1 ATE67619 T1 AT E67619T1 AT 86115152 T AT86115152 T AT 86115152T AT 86115152 T AT86115152 T AT 86115152T AT E67619 T1 ATE67619 T1 AT E67619T1
Authority
AT
Austria
Prior art keywords
remainder
floating point
stage
sum
adder
Prior art date
Application number
AT86115152T
Other languages
German (de)
English (en)
Inventor
J Hartmut Bleher
Axel T Gerlicher
Siegfried M Rump
Dieter K Unkauf
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE67619T1 publication Critical patent/ATE67619T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/485—Adding; Subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Error Detection And Correction (AREA)
AT86115152T 1986-10-31 1986-10-31 Verfahren und schaltungsanordnung zur addition von gleitkommazahlen. ATE67619T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP86115152A EP0265555B1 (de) 1986-10-31 1986-10-31 Verfahren und Schaltungsanordnung zur Addition von Gleitkommazahlen

Publications (1)

Publication Number Publication Date
ATE67619T1 true ATE67619T1 (de) 1991-10-15

Family

ID=8195554

Family Applications (1)

Application Number Title Priority Date Filing Date
AT86115152T ATE67619T1 (de) 1986-10-31 1986-10-31 Verfahren und schaltungsanordnung zur addition von gleitkommazahlen.

Country Status (9)

Country Link
US (1) US4866651A (en, 2012)
EP (1) EP0265555B1 (en, 2012)
JP (1) JPS63123125A (en, 2012)
AT (1) ATE67619T1 (en, 2012)
AU (1) AU589049B2 (en, 2012)
BR (1) BR8705232A (en, 2012)
CA (1) CA1270955A (en, 2012)
DE (1) DE3681591D1 (en, 2012)
ES (1) ES2026444T3 (en, 2012)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5268856A (en) * 1988-06-06 1993-12-07 Applied Intelligent Systems, Inc. Bit serial floating point parallel processing system and method
JP2693800B2 (ja) * 1988-12-28 1997-12-24 甲府日本電気株式会社 浮動小数点データ総和演算回路
US5111421A (en) * 1990-02-26 1992-05-05 General Electric Company System for performing addition and subtraction of signed magnitude floating point binary numbers
US5493520A (en) * 1994-04-15 1996-02-20 International Business Machines Corporation Two state leading zero/one anticipator (LZA)
US5557734A (en) * 1994-06-17 1996-09-17 Applied Intelligent Systems, Inc. Cache burst architecture for parallel processing, such as for image processing
US5880983A (en) * 1996-03-25 1999-03-09 International Business Machines Corporation Floating point split multiply/add system which has infinite precision
US5790445A (en) * 1996-04-30 1998-08-04 International Business Machines Corporation Method and system for performing a high speed floating point add operation
US7827451B2 (en) * 2006-05-24 2010-11-02 International Business Machines Corporation Method, system and program product for establishing decimal floating point operands for facilitating testing of decimal floating point instructions
US10019227B2 (en) * 2014-11-19 2018-07-10 International Business Machines Corporation Accuracy-conserving floating-point value aggregation
CN105278923B (zh) * 2015-10-22 2017-10-03 合肥工业大学 一种基于aic信息准则的信号源个数估计硬件电路及其实现方法
US12039290B1 (en) * 2024-01-09 2024-07-16 Recogni Inc. Multiply accumulate (MAC) unit with split accumulator
US20250224929A1 (en) 2024-01-09 2025-07-10 Recogni Inc. Multiply accumulate (mac) unit with split accumulator

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188740A (ja) * 1983-04-11 1984-10-26 Hitachi Ltd フロ−テイング加算器

Also Published As

Publication number Publication date
CA1270955A (en) 1990-06-26
AU589049B2 (en) 1989-09-28
JPH0568725B2 (en, 2012) 1993-09-29
EP0265555A1 (de) 1988-05-04
EP0265555B1 (de) 1991-09-18
JPS63123125A (ja) 1988-05-26
BR8705232A (pt) 1988-05-24
AU8053587A (en) 1988-05-05
US4866651A (en) 1989-09-12
DE3681591D1 (de) 1991-10-24
ES2026444T3 (es) 1992-05-01

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