BR8705232A - Metodo e disposicao de circuitos para a soma de numeros com ponto flutuante - Google Patents
Metodo e disposicao de circuitos para a soma de numeros com ponto flutuanteInfo
- Publication number
- BR8705232A BR8705232A BR8705232A BR8705232A BR8705232A BR 8705232 A BR8705232 A BR 8705232A BR 8705232 A BR8705232 A BR 8705232A BR 8705232 A BR8705232 A BR 8705232A BR 8705232 A BR8705232 A BR 8705232A
- Authority
- BR
- Brazil
- Prior art keywords
- floating point
- remainder
- sum
- stage
- adder
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
- G06F7/485—Adding; Subtracting
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Mathematical Optimization (AREA)
- Computing Systems (AREA)
- Mathematical Analysis (AREA)
- Computational Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Nonlinear Science (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
- Error Detection And Correction (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP86115152A EP0265555B1 (de) | 1986-10-31 | 1986-10-31 | Verfahren und Schaltungsanordnung zur Addition von Gleitkommazahlen |
Publications (1)
Publication Number | Publication Date |
---|---|
BR8705232A true BR8705232A (pt) | 1988-05-24 |
Family
ID=8195554
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR8705232A BR8705232A (pt) | 1986-10-31 | 1987-10-02 | Metodo e disposicao de circuitos para a soma de numeros com ponto flutuante |
Country Status (9)
Country | Link |
---|---|
US (1) | US4866651A (pt) |
EP (1) | EP0265555B1 (pt) |
JP (1) | JPS63123125A (pt) |
AT (1) | ATE67619T1 (pt) |
AU (1) | AU589049B2 (pt) |
BR (1) | BR8705232A (pt) |
CA (1) | CA1270955A (pt) |
DE (1) | DE3681591D1 (pt) |
ES (1) | ES2026444T3 (pt) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5268856A (en) * | 1988-06-06 | 1993-12-07 | Applied Intelligent Systems, Inc. | Bit serial floating point parallel processing system and method |
JP2693800B2 (ja) * | 1988-12-28 | 1997-12-24 | 甲府日本電気株式会社 | 浮動小数点データ総和演算回路 |
US5111421A (en) * | 1990-02-26 | 1992-05-05 | General Electric Company | System for performing addition and subtraction of signed magnitude floating point binary numbers |
US5493520A (en) * | 1994-04-15 | 1996-02-20 | International Business Machines Corporation | Two state leading zero/one anticipator (LZA) |
US5557734A (en) * | 1994-06-17 | 1996-09-17 | Applied Intelligent Systems, Inc. | Cache burst architecture for parallel processing, such as for image processing |
US5880983A (en) * | 1996-03-25 | 1999-03-09 | International Business Machines Corporation | Floating point split multiply/add system which has infinite precision |
US5790445A (en) * | 1996-04-30 | 1998-08-04 | International Business Machines Corporation | Method and system for performing a high speed floating point add operation |
US7827451B2 (en) * | 2006-05-24 | 2010-11-02 | International Business Machines Corporation | Method, system and program product for establishing decimal floating point operands for facilitating testing of decimal floating point instructions |
US10019227B2 (en) * | 2014-11-19 | 2018-07-10 | International Business Machines Corporation | Accuracy-conserving floating-point value aggregation |
CN105278923B (zh) * | 2015-10-22 | 2017-10-03 | 合肥工业大学 | 一种基于aic信息准则的信号源个数估计硬件电路及其实现方法 |
US12039290B1 (en) * | 2024-01-09 | 2024-07-16 | Recogni Inc. | Multiply accumulate (MAC) unit with split accumulator |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59188740A (ja) * | 1983-04-11 | 1984-10-26 | Hitachi Ltd | フロ−テイング加算器 |
-
1986
- 1986-10-31 EP EP86115152A patent/EP0265555B1/de not_active Expired - Lifetime
- 1986-10-31 DE DE8686115152T patent/DE3681591D1/de not_active Expired - Fee Related
- 1986-10-31 ES ES198686115152T patent/ES2026444T3/es not_active Expired - Lifetime
- 1986-10-31 AT AT86115152T patent/ATE67619T1/de not_active IP Right Cessation
-
1987
- 1987-08-26 US US07/089,649 patent/US4866651A/en not_active Expired - Fee Related
- 1987-09-18 JP JP62232744A patent/JPS63123125A/ja active Granted
- 1987-10-02 BR BR8705232A patent/BR8705232A/pt not_active IP Right Cessation
- 1987-10-30 AU AU80535/87A patent/AU589049B2/en not_active Ceased
- 1987-10-30 CA CA000550740A patent/CA1270955A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
ATE67619T1 (de) | 1991-10-15 |
DE3681591D1 (de) | 1991-10-24 |
US4866651A (en) | 1989-09-12 |
AU589049B2 (en) | 1989-09-28 |
CA1270955A (en) | 1990-06-26 |
AU8053587A (en) | 1988-05-05 |
ES2026444T3 (es) | 1992-05-01 |
EP0265555A1 (de) | 1988-05-04 |
EP0265555B1 (de) | 1991-09-18 |
JPH0568725B2 (pt) | 1993-09-29 |
JPS63123125A (ja) | 1988-05-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Murakami | The Kauffman polynomial of links and representation theory | |
Warren | Hacker's delight | |
BR8705232A (pt) | Metodo e disposicao de circuitos para a soma de numeros com ponto flutuante | |
EP0181516A3 (en) | Data processing apparatus having efficient min and max functions | |
JPH07295790A (ja) | 2状態先行0/1予想機構(lza) | |
Tung | A division algorithm for signed-digit arithmetic | |
KR880014470A (ko) | 승산기 어레이 회로에서의 시프트 연산 수행장치 및 방법 | |
US4325129A (en) | Non-linear logic module for increasing complexity of bit sequences | |
US3557356A (en) | Pseudo-random 4-level m-sequences generators | |
US7072922B2 (en) | Integrated circuit and process for identifying minimum or maximum input value among plural inputs | |
US5798958A (en) | Zero detect for binary sum | |
SE9203683L (sv) | Anordning för omvandling av ett binärt flyttal till en 2- logaritm i binär form eller omvänt | |
RU2785770C1 (ru) | Устройство для объединения групп данных | |
US4041296A (en) | High-speed digital multiply-by-device | |
SU385272A1 (ru) | УСТРОЙСТВО дл УЛ1НОЖЕНИЯ | |
EP0242600A2 (en) | Carry look-ahead calculating method and circuits therefor | |
SU1635176A1 (ru) | Устройство дл умножени | |
US5745744A (en) | High speed mask generation using selection logic | |
RU2006929C1 (ru) | Вычислительная система для интервальных вычислений | |
SU1361542A1 (ru) | Устройство дл округлени суммы и разности двоично-кодированных чисел с плавающей зап той | |
RU1829119C (ru) | Устройство дл подсчета количества единиц | |
SU849206A2 (ru) | Арифметическое устройство | |
Gopi et al. | 128 Bit unsigned multiplier design and implementation using an efficient SQRT-CSLA | |
SU911725A1 (ru) | Преобразователь позиционного кода в кодлибау-крейга | |
SU436350A1 (ru) | Двоичный сумматор |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
B21A | Patent or certificate of addition expired [chapter 21.1 patent gazette] |
Free format text: PATENTE EXTINTA EM 02/10/2002 |