ATE56825T1 - Schaltungsanordnung fuer einen integrierten schaltkreis mit eingebauter selbsttestkonfiguration. - Google Patents

Schaltungsanordnung fuer einen integrierten schaltkreis mit eingebauter selbsttestkonfiguration.

Info

Publication number
ATE56825T1
ATE56825T1 AT85308853T AT85308853T ATE56825T1 AT E56825 T1 ATE56825 T1 AT E56825T1 AT 85308853 T AT85308853 T AT 85308853T AT 85308853 T AT85308853 T AT 85308853T AT E56825 T1 ATE56825 T1 AT E56825T1
Authority
AT
Austria
Prior art keywords
gate
circuit arrangement
input
built
self
Prior art date
Application number
AT85308853T
Other languages
English (en)
Inventor
David Frank Burrows
Mark Paraskeva
William Lawrence Knight
Original Assignee
Plessey Overseas
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Overseas filed Critical Plessey Overseas
Application granted granted Critical
Publication of ATE56825T1 publication Critical patent/ATE56825T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Amplifiers (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
AT85308853T 1985-01-17 1985-12-05 Schaltungsanordnung fuer einen integrierten schaltkreis mit eingebauter selbsttestkonfiguration. ATE56825T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB858501143A GB8501143D0 (en) 1985-01-17 1985-01-17 Integrated circuits
EP85308853A EP0190494B1 (de) 1985-01-17 1985-12-05 Schaltungsanordnung für einen integrierten Schaltkreis mit eingebauter Selbsttest-Konfiguration

Publications (1)

Publication Number Publication Date
ATE56825T1 true ATE56825T1 (de) 1990-10-15

Family

ID=10572973

Family Applications (1)

Application Number Title Priority Date Filing Date
AT85308853T ATE56825T1 (de) 1985-01-17 1985-12-05 Schaltungsanordnung fuer einen integrierten schaltkreis mit eingebauter selbsttestkonfiguration.

Country Status (10)

Country Link
US (1) US4740970A (de)
EP (1) EP0190494B1 (de)
JP (1) JPS61217779A (de)
AT (1) ATE56825T1 (de)
AU (1) AU581712B2 (de)
DE (1) DE3579804D1 (de)
DK (1) DK25186A (de)
GB (1) GB8501143D0 (de)
GR (1) GR860073B (de)
IE (1) IE57175B1 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8501143D0 (en) * 1985-01-17 1985-02-20 Plessey Co Plc Integrated circuits
DE3639577A1 (de) * 1986-11-20 1988-05-26 Siemens Ag Logikbaustein zur erzeugung von ungleich verteilten zufallsmustern fuer integrierte schaltungen
JPH0682146B2 (ja) * 1986-12-22 1994-10-19 日本電気株式会社 スキヤンパス方式の論理集積回路
US6304987B1 (en) 1995-06-07 2001-10-16 Texas Instruments Incorporated Integrated test circuit
EP0358371B1 (de) * 1988-09-07 1998-03-11 Texas Instruments Incorporated Erweiterte Prüfschaltung
US4894800A (en) * 1988-09-23 1990-01-16 Honeywell, Inc. Reconfigurable register bit-slice for self-test
JP3005250B2 (ja) 1989-06-30 2000-01-31 テキサス インスツルメンツ インコーポレイテツド バスモニター集積回路
US5361264A (en) * 1989-07-03 1994-11-01 Raytheon Company Mode programmable VLSI data registers
US5119378A (en) * 1990-03-02 1992-06-02 General Electric Company Testing of integrated circuits including internal test circuitry and using token passing to select testing ports
US5228040A (en) * 1990-03-09 1993-07-13 At&T Bell Laboratories Testable implementations of finite state machines and methods for producing them
US6675333B1 (en) 1990-03-30 2004-01-06 Texas Instruments Incorporated Integrated circuit with serial I/O controller
CA2057339C (en) * 1990-12-26 1996-10-22 John F. Blecha, Jr. Test interface for a digital circuit
US5260948A (en) * 1991-03-13 1993-11-09 Ncr Corporation Bidirectional boundary-scan circuit
US5230000A (en) * 1991-04-25 1993-07-20 At&T Bell Laboratories Built-in self-test (bist) circuit
US5260950A (en) * 1991-09-17 1993-11-09 Ncr Corporation Boundary-scan input circuit for a reset pin
US5258985A (en) * 1991-11-12 1993-11-02 Motorola, Inc. Combinational data generator and analyzer for built-in self test
US5661732A (en) * 1995-05-31 1997-08-26 International Business Machines Corporation Programmable ABIST microprocessor for testing arrays with two logical views
US5633877A (en) * 1995-05-31 1997-05-27 International Business Machines Corporation Programmable built-in self test method and controller for arrays
US5659551A (en) * 1995-05-31 1997-08-19 International Business Machines Corporation Programmable computer system element with built-in self test method and apparatus for repair during power-on
US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
US6408413B1 (en) 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US7058862B2 (en) 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state
GB9920077D0 (en) * 1999-08-24 1999-10-27 Sgs Thomson Microelectronics Scan latch circuit
DE19948902C1 (de) * 1999-10-11 2001-07-12 Infineon Technologies Ag Schaltungszelle zur Testmuster-Generierung und Testmuster-Kompression
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
GB2397675B (en) * 2000-12-06 2004-09-29 Fujitsu Ltd Verification circuitry
JP3842571B2 (ja) * 2001-03-29 2006-11-08 株式会社東芝 フリップフロップ回路
US7028238B2 (en) * 2002-04-18 2006-04-11 Lsi Logic Corporation Input/output characterization chain for an integrated circuit
US7162673B2 (en) * 2003-11-14 2007-01-09 Integrated Device Technology, Inc. Scan chain registers that utilize feedback paths within latch units to support toggling of latch unit outputs during enhanced delay fault testing
JP5792342B2 (ja) * 2014-03-13 2015-10-07 ルネサスエレクトロニクス株式会社 半導体集積回路
US10229748B1 (en) 2017-11-28 2019-03-12 International Business Machines Corporation Memory interface latch with integrated write-through function
US10381098B2 (en) 2017-11-28 2019-08-13 International Business Machines Corporation Memory interface latch with integrated write-through and fence functions
US12449472B2 (en) * 2022-09-27 2025-10-21 Infineon Technologies Ag Circuit and method for testing a circuit

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4320509A (en) * 1979-10-19 1982-03-16 Bell Telephone Laboratories, Incorporated LSI Circuit logic structure including data compression circuitry
US4377757A (en) * 1980-02-11 1983-03-22 Siemens Aktiengesellschaft Logic module for integrated digital circuits
US4340857A (en) * 1980-04-11 1982-07-20 Siemens Corporation Device for testing digital circuits using built-in logic block observers (BILBO's)
DE3176315D1 (en) * 1980-04-11 1987-08-20 Siemens Ag Device for testing a digital circuit with test circuits enclosed in this circuit
US4433413A (en) * 1981-10-22 1984-02-21 Siemens Corporation Built-in apparatus and method for testing a microprocessor system
US4493078A (en) * 1982-09-29 1985-01-08 Siemens Corporation Method and apparatus for testing a digital computer
US4594711A (en) * 1983-11-10 1986-06-10 Texas Instruments Incorporated Universal testing circuit and method
US4597080A (en) * 1983-11-14 1986-06-24 Texas Instruments Incorporated Architecture and method for testing VLSI processors
GB8432458D0 (en) * 1984-12-21 1985-02-06 Plessey Co Plc Integrated circuits
GB8432533D0 (en) * 1984-12-21 1985-02-06 Plessey Co Plc Integrated circuits
GB8501143D0 (en) * 1985-01-17 1985-02-20 Plessey Co Plc Integrated circuits

Also Published As

Publication number Publication date
EP0190494B1 (de) 1990-09-19
GR860073B (en) 1986-05-14
AU581712B2 (en) 1989-03-02
IE57175B1 (en) 1992-05-20
AU5148085A (en) 1986-07-24
DE3579804D1 (de) 1990-10-25
GB8501143D0 (en) 1985-02-20
IE860129L (en) 1986-07-17
DK25186A (da) 1986-07-18
EP0190494A1 (de) 1986-08-13
US4740970A (en) 1988-04-26
DK25186D0 (da) 1986-01-17
JPS61217779A (ja) 1986-09-27

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Legal Events

Date Code Title Description
UEP Publication of translation of european patent specification
EEIH Change in the person of patent owner
REN Ceased due to non-payment of the annual fee