ATE525744T1 - Verfahren zur herstellung von schichtgebundenem gruppe iii-nitridhalbleitersubstrat - Google Patents
Verfahren zur herstellung von schichtgebundenem gruppe iii-nitridhalbleitersubstratInfo
- Publication number
- ATE525744T1 ATE525744T1 AT09166067T AT09166067T ATE525744T1 AT E525744 T1 ATE525744 T1 AT E525744T1 AT 09166067 T AT09166067 T AT 09166067T AT 09166067 T AT09166067 T AT 09166067T AT E525744 T1 ATE525744 T1 AT E525744T1
- Authority
- AT
- Austria
- Prior art keywords
- nitride semiconductor
- group iii
- iii nitride
- semiconductor layer
- semiconductor substrate
- Prior art date
Links
- 150000004767 nitrides Chemical class 0.000 title abstract 9
- 239000004065 semiconductor Substances 0.000 title abstract 9
- 239000000758 substrate Substances 0.000 title abstract 9
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 150000002500 ions Chemical class 0.000 abstract 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract 1
- 238000000137 annealing Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 abstract 1
- 239000001307 helium Substances 0.000 abstract 1
- 229910052734 helium Inorganic materials 0.000 abstract 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 abstract 1
- 239000001257 hydrogen Substances 0.000 abstract 1
- 229910052739 hydrogen Inorganic materials 0.000 abstract 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Led Devices (AREA)
- Semiconductor Lasers (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008206933A JP4631946B2 (ja) | 2008-08-11 | 2008-08-11 | Ｉｉｉ族窒化物半導体層貼り合わせ基板の製造方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE525744T1 true ATE525744T1 (de) | 2011-10-15 |
Family
ID=41263649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT09166067T ATE525744T1 (de) | 2008-08-11 | 2009-07-22 | Verfahren zur herstellung von schichtgebundenem gruppe iii-nitridhalbleitersubstrat |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US8124498B2 (de) |
| EP (1) | EP2154709B1 (de) |
| JP (1) | JP4631946B2 (de) |
| KR (1) | KR20100019965A (de) |
| CN (1) | CN101651091A (de) |
| AT (1) | ATE525744T1 (de) |
| TW (1) | TW201006974A (de) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9064706B2 (en) * | 2006-11-17 | 2015-06-23 | Sumitomo Electric Industries, Ltd. | Composite of III-nitride crystal on laterally stacked substrates |
| JP5544875B2 (ja) * | 2009-12-25 | 2014-07-09 | 住友電気工業株式会社 | 複合基板 |
| CN102823000B (zh) * | 2010-04-08 | 2016-08-03 | 日亚化学工业株式会社 | 发光装置及其制造方法 |
| EP2562789A4 (de) * | 2010-04-20 | 2015-03-04 | Sumitomo Electric Industries | Verfahren zur herstellung eines verbundsubstrats |
| CN102918662B (zh) * | 2010-05-31 | 2015-11-25 | 日亚化学工业株式会社 | 发光装置及其制造方法 |
| CN101962804B (zh) * | 2010-10-30 | 2012-05-02 | 北京大学 | 基于外延材料应力控制的GaN厚膜自分离方法 |
| JP2012124473A (ja) | 2010-11-15 | 2012-06-28 | Ngk Insulators Ltd | 複合基板及び複合基板の製造方法 |
| CN108281378B (zh) * | 2012-10-12 | 2022-06-24 | 住友电气工业株式会社 | Iii族氮化物复合衬底、半导体器件及它们的制造方法 |
| US9281233B2 (en) * | 2012-12-28 | 2016-03-08 | Sunedison Semiconductor Limited | Method for low temperature layer transfer in the preparation of multilayer semiconductor devices |
| US9058990B1 (en) * | 2013-12-19 | 2015-06-16 | International Business Machines Corporation | Controlled spalling of group III nitrides containing an embedded spall releasing plane |
| CN103696022B (zh) * | 2013-12-27 | 2016-04-13 | 贵州蓝科睿思技术研发中心 | 一种离子注入分离蓝宝石的方法 |
| JP6268229B2 (ja) * | 2016-06-27 | 2018-01-24 | 株式会社サイオクス | 窒化物半導体積層物、窒化物半導体積層物の製造方法、半導体積層物の製造方法、および半導体積層物の検査方法 |
| CN113808925A (zh) * | 2021-09-28 | 2021-12-17 | 包头稀土研发中心 | 一种复合结构荧光衬底、复合方法及倒装led结构 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3658756B2 (ja) * | 1999-03-01 | 2005-06-08 | 住友電気工業株式会社 | 化合物半導体の製造方法 |
| PL207400B1 (pl) * | 2001-06-06 | 2010-12-31 | Ammono Społka Z Ograniczoną Odpowiedzialnością | Sposób i urządzenie do otrzymywania objętościowego monokryształu azotku zawierającego gal |
| JP2006210660A (ja) * | 2005-01-28 | 2006-08-10 | Hitachi Cable Ltd | 半導体基板の製造方法 |
| JP5003033B2 (ja) * | 2006-06-30 | 2012-08-15 | 住友電気工業株式会社 | ＧａＮ薄膜貼り合わせ基板およびその製造方法、ならびにＧａＮ系半導体デバイスおよびその製造方法 |
| US7575988B2 (en) * | 2006-07-11 | 2009-08-18 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating a hybrid substrate |
| JP2008159692A (ja) * | 2006-12-21 | 2008-07-10 | Covalent Materials Corp | 半導体基板の製造方法 |
-
2008
- 2008-08-11 JP JP2008206933A patent/JP4631946B2/ja active Active
-
2009
- 2009-07-22 EP EP09166067A patent/EP2154709B1/de not_active Not-in-force
- 2009-07-22 AT AT09166067T patent/ATE525744T1/de not_active IP Right Cessation
- 2009-07-28 TW TW098125392A patent/TW201006974A/zh unknown
- 2009-08-04 US US12/535,201 patent/US8124498B2/en active Active
- 2009-08-06 KR KR1020090072400A patent/KR20100019965A/ko not_active Application Discontinuation
- 2009-08-11 CN CN200910166065A patent/CN101651091A/zh active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| CN101651091A (zh) | 2010-02-17 |
| EP2154709A3 (de) | 2010-09-01 |
| US20100035406A1 (en) | 2010-02-11 |
| TW201006974A (en) | 2010-02-16 |
| EP2154709B1 (de) | 2011-09-21 |
| JP2010045098A (ja) | 2010-02-25 |
| US8124498B2 (en) | 2012-02-28 |
| EP2154709A2 (de) | 2010-02-17 |
| KR20100019965A (ko) | 2010-02-19 |
| JP4631946B2 (ja) | 2011-02-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| ATE525744T1 (de) | Verfahren zur herstellung von schichtgebundenem gruppe iii-nitridhalbleitersubstrat | |
| CN103035562B (zh) | 制造绝缘体上硅结构的工艺 | |
| TW200733195A (en) | Semiconductor layer structure and method for fabricating it | |
| ATE496392T1 (de) | Herstellungsverfahren für ein siliziumcarbidhalbleiterbauelement | |
| ATE503866T1 (de) | Verfahren zur herstellung von virtuellen ge- substraten zur iii/v-integration auf si(001) | |
| WO2011154360A3 (fr) | Circuit integre a dispositif de type fet sans jonction et a depletion | |
| EP1993127A3 (de) | Verfahren zur Herstellung eines SOI-Substrats und Verfahren zur Herstellung einer Halbleitervorrichtung | |
| TW200703462A (en) | Wafer separation technique for the fabrication of free-standing (Al, In, Ga)N wafers | |
| WO2006130360A3 (en) | Improved amorphization/templated recrystallization method for hybrid orientation substrates | |
| ATE521085T1 (de) | Verfahren zum herstellen einer halbleiter-auf- isolation-heterostruktur | |
| TW200639969A (en) | Treatmeny of a removed layer of Si1-yGey | |
| EP2472566A3 (de) | Vorlage, Verfahren zur Herstellung der Vorlage und Verfahren zur Herstellung einer vertikalen lichtemittierenden Halbleitervorrichtung auf Nitrid-Basis mit der Vorlage | |
| ATE515794T1 (de) | Verfahren zur herstellung eines geoi-wafers (germanium on insulator) | |
| WO2007019277A3 (en) | Method of forming semiconductor layers on handle substrates | |
| WO2010066626A3 (de) | Verfahren zum ausbilden eines dotierstoffprofils | |
| ATE486366T1 (de) | Verfahren zum herstellen einer halbleiter-auf- isolator-struktur | |
| WO2009152327A3 (en) | Post oxidation annealing of low temperature thermal or plasma based oxidation | |
| TW200511434A (en) | Controlled growth of highly uniform, oxide layers, especially ultrathin layers | |
| TW200943393A (en) | A semiconductor wafer with a heteroepitaxial layer and a method for producing the wafer | |
| JP2014518010A (ja) | 材料中にクラックを形成するための方法 | |
| TW200705712A (en) | Method of producing nitride-based semiconductor device, and light-emitting device produced thereby | |
| TW200705555A (en) | Method for manufacturing SIMOX wafer and SIMOX wafer | |
| TW200707635A (en) | Method for manufacturing SIMOX wafer and SIMOX wafer | |
| ATE548761T1 (de) | Verfahren zur selektiven dotierung von silizium | |
| ATE538494T1 (de) | Verfahren zur herstellung eines ssoi-substrats |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |