ATE418157T1 - Kerbenfreies ätzen von soi-strukturen mit hohem seitenverhältnis durch verwendung eines zeitlich gemultiplexten prozesses und hf-vormodulation - Google Patents

Kerbenfreies ätzen von soi-strukturen mit hohem seitenverhältnis durch verwendung eines zeitlich gemultiplexten prozesses und hf-vormodulation

Info

Publication number
ATE418157T1
ATE418157T1 AT04817803T AT04817803T ATE418157T1 AT E418157 T1 ATE418157 T1 AT E418157T1 AT 04817803 T AT04817803 T AT 04817803T AT 04817803 T AT04817803 T AT 04817803T AT E418157 T1 ATE418157 T1 AT E418157T1
Authority
AT
Austria
Prior art keywords
modulation
notch
aspect ratio
high aspect
soi structures
Prior art date
Application number
AT04817803T
Other languages
English (en)
Inventor
Sunil Srinivasan
David Johnson
Russell Westerman
Original Assignee
Unaxis Usa Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unaxis Usa Inc filed Critical Unaxis Usa Inc
Application granted granted Critical
Publication of ATE418157T1 publication Critical patent/ATE418157T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H10P50/244—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials comprising alternated and repeated etching and passivation steps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Drying Of Semiconductors (AREA)
  • Peptides Or Proteins (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Micromachines (AREA)
AT04817803T 2003-10-21 2004-10-19 Kerbenfreies ätzen von soi-strukturen mit hohem seitenverhältnis durch verwendung eines zeitlich gemultiplexten prozesses und hf-vormodulation ATE418157T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US51293303P 2003-10-21 2003-10-21
US10/968,823 US20050112891A1 (en) 2003-10-21 2004-10-18 Notch-free etching of high aspect SOI structures using a time division multiplex process and RF bias modulation

Publications (1)

Publication Number Publication Date
ATE418157T1 true ATE418157T1 (de) 2009-01-15

Family

ID=34576731

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04817803T ATE418157T1 (de) 2003-10-21 2004-10-19 Kerbenfreies ätzen von soi-strukturen mit hohem seitenverhältnis durch verwendung eines zeitlich gemultiplexten prozesses und hf-vormodulation

Country Status (6)

Country Link
US (2) US20050112891A1 (de)
EP (1) EP1676302B1 (de)
JP (1) JP2007509506A (de)
AT (1) ATE418157T1 (de)
DE (1) DE602004018531D1 (de)
WO (1) WO2005045904A2 (de)

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JP5967710B2 (ja) * 2012-09-28 2016-08-10 サムコ株式会社 プラズマエッチングの終点検出方法
CN103928283B (zh) * 2013-01-10 2016-06-15 中微半导体设备(上海)有限公司 一种真空处理腔室的射频脉冲功率匹配的方法及其装置
US9653316B2 (en) * 2013-02-18 2017-05-16 Tokyo Electron Limited Plasma processing method and plasma processing apparatus
JP6173086B2 (ja) * 2013-07-19 2017-08-02 キヤノン株式会社 シリコン基板のエッチング方法
US20150371889A1 (en) * 2014-06-20 2015-12-24 Applied Materials, Inc. Methods for shallow trench isolation formation in a silicon germanium layer
US9978606B2 (en) * 2015-10-02 2018-05-22 Applied Materials, Inc. Methods for atomic level resolution and plasma processing control
US9691625B2 (en) * 2015-11-04 2017-06-27 Lam Research Corporation Methods and systems for plasma etching using bi-modal process gas composition responsive to plasma power level
KR102145815B1 (ko) * 2016-01-18 2020-08-19 주식회사 히타치하이테크 플라스마 처리 방법 및 플라스마 처리 장치
US11170981B2 (en) * 2019-09-17 2021-11-09 Tokyo Electron Limited Broadband plasma processing systems and methods
US11295937B2 (en) * 2019-09-17 2022-04-05 Tokyo Electron Limited Broadband plasma processing systems and methods
RU2715412C1 (ru) * 2019-11-26 2020-02-28 Акционерное общество «Российская корпорация ракетно-космического приборостроения и информационных систем» (АО «Российские космические системы») Многослойная коммутационная плата СВЧ-гибридной интегральной микросхемы космического назначения и способ её получения (варианты)
JP7075540B1 (ja) * 2020-09-02 2022-05-25 株式会社日立ハイテク プラズマ処理装置及びプラズマ処理方法
JP7621145B2 (ja) * 2021-03-15 2025-01-24 東京エレクトロン株式会社 基板処理方法および基板処理装置
US11917806B2 (en) 2021-08-12 2024-02-27 Changxin Memory Technologies, Inc. Method of manufacturing semiconductor structure and semiconductor structure
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Also Published As

Publication number Publication date
DE602004018531D1 (de) 2009-01-29
EP1676302A2 (de) 2006-07-05
US20070175856A1 (en) 2007-08-02
US20050112891A1 (en) 2005-05-26
JP2007509506A (ja) 2007-04-12
WO2005045904A3 (en) 2005-09-09
WO2005045904A2 (en) 2005-05-19
EP1676302B1 (de) 2008-12-17

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