ATE330362T1 - Phasenregelschleife mit phasenrotation - Google Patents
Phasenregelschleife mit phasenrotationInfo
- Publication number
- ATE330362T1 ATE330362T1 AT02716131T AT02716131T ATE330362T1 AT E330362 T1 ATE330362 T1 AT E330362T1 AT 02716131 T AT02716131 T AT 02716131T AT 02716131 T AT02716131 T AT 02716131T AT E330362 T1 ATE330362 T1 AT E330362T1
- Authority
- AT
- Austria
- Prior art keywords
- loop
- phase
- transmitter
- pll
- logic
- Prior art date
Links
- 230000009977 dual effect Effects 0.000 abstract 1
- 230000005405 multipole Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0004—Initialisation of the receiver
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Disintegrating Or Milling (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US26244101P | 2001-01-16 | 2001-01-16 | |
| US09/996,053 US6993107B2 (en) | 2001-01-16 | 2001-11-28 | Analog unidirectional serial link architecture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE330362T1 true ATE330362T1 (de) | 2006-07-15 |
Family
ID=26949217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT02716131T ATE330362T1 (de) | 2001-01-16 | 2002-01-15 | Phasenregelschleife mit phasenrotation |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US6993107B2 (de) |
| EP (1) | EP1352475B1 (de) |
| KR (1) | KR100702423B1 (de) |
| CN (1) | CN1265554C (de) |
| AT (1) | ATE330362T1 (de) |
| DE (1) | DE60212329T2 (de) |
| TW (1) | TW546925B (de) |
| WO (1) | WO2002058243A1 (de) |
Families Citing this family (42)
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|---|---|---|---|---|
| US7082484B2 (en) * | 2001-01-16 | 2006-07-25 | International Business Machines Corporation | Architecture for advanced serial link between two cards |
| US7242229B1 (en) | 2001-05-06 | 2007-07-10 | Altera Corporation | Phase locked loop (PLL) and delay locked loop (DLL) counter and delay element programming in user mode |
| US7093041B2 (en) * | 2001-12-20 | 2006-08-15 | Lsi Logic Corporation | Dual purpose PCI-X DDR configurable terminator/driver |
| US7778351B2 (en) * | 2002-04-09 | 2010-08-17 | International Business Machines Corporation | Tunable CMOS receiver apparatus |
| AU2003241234A1 (en) * | 2002-05-28 | 2003-12-12 | Igor Anatolievich Abrosimov | Reference voltage generator for logic elements providing stable and predefined gate propagation time |
| WO2004015869A1 (en) * | 2002-07-31 | 2004-02-19 | International Business Machines Corporation | Phase-locked-loop circuit and method |
| US7039885B1 (en) | 2003-01-21 | 2006-05-02 | Barcelona Design, Inc. | Methodology for design of oscillator delay stage and corresponding applications |
| US7102449B1 (en) * | 2003-01-21 | 2006-09-05 | Barcelona Design, Inc. | Delay stage for oscillator circuit and corresponding applications |
| US20060012408A1 (en) * | 2004-07-06 | 2006-01-19 | Kenet, Inc. | Differential clock input buffer |
| JP4425735B2 (ja) * | 2004-07-22 | 2010-03-03 | 株式会社アドバンテスト | ジッタ印加回路、及び試験装置 |
| US7409019B2 (en) * | 2004-09-30 | 2008-08-05 | International Business Machines Corporation | High Speed Multi-Mode Receiver with adaptive receiver equalization and controllable transmitter pre-distortion |
| GB2430090B (en) * | 2005-09-08 | 2007-10-17 | Motorola Inc | RF synthesizer and RF transmitter or receiver incorporating the synthesizer |
| EP1976126B1 (de) * | 2006-01-26 | 2010-04-21 | Nihon Dempa Kogyo Co., Ltd. | Vco-ansteuerschaltung und frequenzsynthesizer |
| US7848719B2 (en) * | 2006-05-12 | 2010-12-07 | University Of Southern California | Ultra-wideband variable-phase ring-oscillator arrays, architectures, and related methods |
| US7840199B2 (en) * | 2006-05-12 | 2010-11-23 | University Of Southern California | Variable-phase ring-oscillator arrays, architectures, and related methods |
| US9397580B1 (en) | 2006-06-06 | 2016-07-19 | Ideal Power, Inc. | Dual link power converter |
| EP1912108A1 (de) * | 2006-10-12 | 2008-04-16 | Rohde & Schwarz GmbH & Co. KG | Anordnung zur Erzeugung von mehreren Taktsignalen |
| CN101677236B (zh) * | 2008-09-19 | 2013-02-13 | 阿尔特拉公司 | 用于调整反馈时钟信号的数字环路滤波器和方法 |
| TWI381169B (zh) * | 2009-01-14 | 2013-01-01 | Prolific Technology Inc | 電壓穩壓電路 |
| US8843692B2 (en) | 2010-04-27 | 2014-09-23 | Conversant Intellectual Property Management Inc. | System of interconnected nonvolatile memories having automatic status packet |
| US8421542B2 (en) | 2010-05-28 | 2013-04-16 | Marvell World Trade Ltd. | Method and apparatus for drift compensation in PLL |
| US8410834B2 (en) * | 2011-03-10 | 2013-04-02 | Realtek Semiconductor Corp. | All digital serial link receiver with low jitter clock regeneration and method thereof |
| US8816782B2 (en) * | 2011-05-10 | 2014-08-26 | Freescale Semiconductor, Inc. | Phase locked loop circuit having a voltage controlled oscillator with improved bandwidth |
| US8948330B1 (en) * | 2011-08-23 | 2015-02-03 | Marvell International Ltd. | Systems and methods for performing variable structure timing recovery |
| CN103259533B (zh) * | 2012-02-15 | 2017-11-28 | 上海期成微电子技术有限公司 | 电感电容振荡器的锁相环电路及其温度补偿方法 |
| CN102830408B (zh) * | 2012-09-11 | 2014-05-14 | 中国人民解放军国防科学技术大学 | 一种惯性信息辅助的卫星接收机基带信号处理方法 |
| US9166605B2 (en) * | 2013-03-18 | 2015-10-20 | Terasquare Co., Ltd. | Low-power and all-digital phase interpolator-based clock and data recovery architecture |
| US8854096B1 (en) * | 2013-10-24 | 2014-10-07 | Analog Devices Technology | System and method of clock generation in high speed serial communication |
| CN103684452B (zh) * | 2013-12-17 | 2017-01-04 | 华为技术有限公司 | 一种动态单元匹配的方法和装置 |
| EP2955812B1 (de) | 2014-06-09 | 2022-07-27 | General Electric Technology GmbH | Leistungsübertragungsnetz |
| EP3304743A4 (de) * | 2015-06-03 | 2019-01-16 | Marvell World Trade Ltd. | Verzögerungsregelschleife |
| US9722832B1 (en) * | 2016-06-23 | 2017-08-01 | Himax Technologies Limited | Frequency control circuit, frequency control method and phase locked loop circuit |
| JP6690708B2 (ja) * | 2016-06-24 | 2020-04-28 | 株式会社ソシオネクスト | 等化回路,受信回路および集積回路装置 |
| US10277435B2 (en) | 2017-08-07 | 2019-04-30 | Micron Technology, Inc. | Method to vertically align multi-level cells |
| US10403337B2 (en) | 2017-08-07 | 2019-09-03 | Micron Technology, Inc. | Output driver for multi-level signaling |
| US10530617B2 (en) | 2017-08-07 | 2020-01-07 | Micron Technology, Inc. | Programmable channel equalization for multi-level signaling |
| US10425260B2 (en) | 2017-08-07 | 2019-09-24 | Micron Technology, Inc. | Multi-level signaling in memory with wide system interface |
| US10447512B2 (en) | 2017-08-07 | 2019-10-15 | Micron Technology, Inc. | Channel equalization for multi-level signaling |
| KR102480629B1 (ko) | 2018-08-02 | 2022-12-26 | 삼성전자주식회사 | 디스플레이 드라이버 및 출력 버퍼 |
| US10784875B2 (en) * | 2018-12-23 | 2020-09-22 | Texas Instruments Incorporated | Loop filter for a phase-locked loop |
| CN113644912B (zh) * | 2021-07-27 | 2024-04-16 | 矽力杰半导体技术(杭州)有限公司 | 锁相环电路及其控制方法 |
| CN116300374B (zh) * | 2022-11-25 | 2025-04-11 | 中山大学 | 一种嵌套式延时锁定环电路及游标型时间数字转换器 |
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| DE3707761A1 (de) | 1987-03-11 | 1988-09-29 | Ant Nachrichtentech | Demodulator |
| JPH01132253A (ja) * | 1987-11-18 | 1989-05-24 | Hitachi Ltd | 位相制御装置 |
| US5276661A (en) * | 1990-07-18 | 1994-01-04 | Sundstrand Corporation | Master clock generator for a parallel variable speed constant frequency power system |
| US5422917A (en) * | 1993-01-04 | 1995-06-06 | Novatel Communications Ltd. | Frequency offset estimation using the phase rotation of channel estimates |
| JPH06303570A (ja) | 1993-04-12 | 1994-10-28 | Seiko Instr Inc | ビデオインターフェース回路 |
| IT1272078B (it) | 1993-12-16 | 1997-06-11 | Cselt Centro Studi Lab Telecom | Ricetrasmettitore per segnali numerici ad alta velocita' in tecnologiacmos |
| US5475707A (en) * | 1994-02-28 | 1995-12-12 | Westinghouse Norden Systems | Broadband communications system |
| KR100219709B1 (ko) * | 1994-03-15 | 1999-09-01 | 윤종용 | 디지탈무선통신장치에있어서송수신신호처리회로 |
| US5812594A (en) | 1994-10-14 | 1998-09-22 | Rakib; Selim | Method and apparatus for implementing carrierless amplitude/phase encoding in a network |
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| US6002717A (en) * | 1997-03-06 | 1999-12-14 | National Semiconductor Corporation | Method and apparatus for adaptive equalization using feedback indicative of undercompensation |
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| DE69839197T2 (de) * | 1997-07-17 | 2009-03-05 | Matsushita Electric Industrial Co., Ltd., Kadoma-shi | Synchronisationsverfahren in einem Kodemultiplexvielfachzugriffsystem |
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-
2001
- 2001-11-28 US US09/996,053 patent/US6993107B2/en not_active Expired - Lifetime
-
2002
- 2002-01-11 TW TW091100310A patent/TW546925B/zh not_active IP Right Cessation
- 2002-01-15 WO PCT/GB2002/000143 patent/WO2002058243A1/en not_active Ceased
- 2002-01-15 KR KR1020037009225A patent/KR100702423B1/ko not_active Expired - Fee Related
- 2002-01-15 CN CNB028037103A patent/CN1265554C/zh not_active Expired - Lifetime
- 2002-01-15 AT AT02716131T patent/ATE330362T1/de not_active IP Right Cessation
- 2002-01-15 EP EP02716131A patent/EP1352475B1/de not_active Expired - Lifetime
- 2002-01-15 DE DE60212329T patent/DE60212329T2/de not_active Expired - Lifetime
-
2005
- 2005-09-13 US US11/225,600 patent/US7142624B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1265554C (zh) | 2006-07-19 |
| DE60212329D1 (de) | 2006-07-27 |
| EP1352475A1 (de) | 2003-10-15 |
| US6993107B2 (en) | 2006-01-31 |
| CN1486534A (zh) | 2004-03-31 |
| DE60212329T2 (de) | 2007-06-06 |
| TW546925B (en) | 2003-08-11 |
| KR20030081382A (ko) | 2003-10-17 |
| EP1352475B1 (de) | 2006-06-14 |
| US20060008042A1 (en) | 2006-01-12 |
| US20020136343A1 (en) | 2002-09-26 |
| WO2002058243A1 (en) | 2002-07-25 |
| US7142624B2 (en) | 2006-11-28 |
| KR100702423B1 (ko) | 2007-04-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |