ATE270001T1 - Verfahren zur trennung einer schicht - Google Patents

Verfahren zur trennung einer schicht

Info

Publication number
ATE270001T1
ATE270001T1 AT98302218T AT98302218T ATE270001T1 AT E270001 T1 ATE270001 T1 AT E270001T1 AT 98302218 T AT98302218 T AT 98302218T AT 98302218 T AT98302218 T AT 98302218T AT E270001 T1 ATE270001 T1 AT E270001T1
Authority
AT
Austria
Prior art keywords
layer
substrate
producing
porous
separated
Prior art date
Application number
AT98302218T
Other languages
English (en)
Inventor
Masaaki Iwane
Takao Yonehara
Kazuaki Ohmi
Original Assignee
Canon Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Kk filed Critical Canon Kk
Application granted granted Critical
Publication of ATE270001T1 publication Critical patent/ATE270001T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B43/00—Operations specially adapted for layered products and not otherwise provided for, e.g. repairing; Apparatus therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/96—Porous semiconductor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/974—Substrate surface preparation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Recrystallisation Techniques (AREA)
  • Photovoltaic Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Separation Using Semi-Permeable Membranes (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
AT98302218T 1997-03-26 1998-03-24 Verfahren zur trennung einer schicht ATE270001T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7377097 1997-03-26

Publications (1)

Publication Number Publication Date
ATE270001T1 true ATE270001T1 (de) 2004-07-15

Family

ID=13527788

Family Applications (1)

Application Number Title Priority Date Filing Date
AT98302218T ATE270001T1 (de) 1997-03-26 1998-03-24 Verfahren zur trennung einer schicht

Country Status (8)

Country Link
US (1) US6140209A (de)
EP (1) EP0867923B1 (de)
KR (1) KR100266954B1 (de)
AT (1) ATE270001T1 (de)
AU (1) AU744858B2 (de)
CA (1) CA2232796C (de)
DE (1) DE69824655T2 (de)
TW (1) TW389958B (de)

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US7148119B1 (en) * 1994-03-10 2006-12-12 Canon Kabushiki Kaisha Process for production of semiconductor substrate
EP0926709A3 (de) 1997-12-26 2000-08-30 Canon Kabushiki Kaisha Herstellungsmethode einer SOI Struktur
FR2785217B1 (fr) * 1998-10-30 2001-01-19 Soitec Silicon On Insulator Procede et dispositif pour separer en deux tranches une plaque de materiau notamment semi-conducteur
JP2000223683A (ja) * 1999-02-02 2000-08-11 Canon Inc 複合部材及びその分離方法、貼り合わせ基板及びその分離方法、移設層の移設方法、並びにｓｏｉ基板の製造方法
FR2796491B1 (fr) * 1999-07-12 2001-08-31 Commissariat Energie Atomique Procede de decollement de deux elements et dispositif pour sa mise en oeuvre
JP3948930B2 (ja) * 2001-10-31 2007-07-25 大日本スクリーン製造株式会社 薄膜形成装置および薄膜形成方法
US7452757B2 (en) * 2002-05-07 2008-11-18 Asm America, Inc. Silicon-on-insulator structures and methods
JP2004140120A (ja) * 2002-10-16 2004-05-13 Canon Inc 多結晶シリコン基板
US7176528B2 (en) 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
US7399681B2 (en) 2003-02-18 2008-07-15 Corning Incorporated Glass-based SOI structures
KR20060017771A (ko) * 2003-05-06 2006-02-27 캐논 가부시끼가이샤 반도체기판, 반도체디바이스, 발광다이오드 및 그 제조방법
JP2004335642A (ja) * 2003-05-06 2004-11-25 Canon Inc 基板およびその製造方法
US20050124137A1 (en) * 2003-05-07 2005-06-09 Canon Kabushiki Kaisha Semiconductor substrate and manufacturing method therefor
JP2005005509A (ja) * 2003-06-12 2005-01-06 Canon Inc 薄膜トランジスタ及びその製造方法
US20050082526A1 (en) * 2003-10-15 2005-04-21 International Business Machines Corporation Techniques for layer transfer processing
JP2005135942A (ja) * 2003-10-28 2005-05-26 Canon Inc 電極配設方法
JP4771510B2 (ja) * 2004-06-23 2011-09-14 キヤノン株式会社 半導体層の製造方法及び基板の製造方法
WO2006012544A2 (en) * 2004-07-22 2006-02-02 The Board Of Trustees Of The Leland Stanford Junior University Germanium substrate-type materials and approach therefor
WO2006023289A2 (en) * 2004-08-18 2006-03-02 Corning Incorporated Strained semiconductor-on-insulator structures and methods for making strained semiconductor-on-insulator structures
KR101121798B1 (ko) * 2004-08-18 2012-03-20 코닝 인코포레이티드 고 변형 유리/유리-세라믹 함유 반도체-온-절연체 구조물
US7268051B2 (en) * 2005-08-26 2007-09-11 Corning Incorporated Semiconductor on glass insulator with deposited barrier layer
DE102005047509B4 (de) * 2005-10-04 2017-10-26 Degotec Gmbh Vorrichtung zur Separierung eines flächigen Objektes von einem Körper, mit dem das Objekt mittels Adhäsionskraft verbunden ist
US7691730B2 (en) * 2005-11-22 2010-04-06 Corning Incorporated Large area semiconductor on glass insulator
US20070264796A1 (en) * 2006-05-12 2007-11-15 Stocker Mark A Method for forming a semiconductor on insulator structure
JP5171016B2 (ja) * 2006-10-27 2013-03-27 キヤノン株式会社 半導体部材、半導体物品の製造方法、その製造方法を用いたｌｅｄアレイ
US20080277778A1 (en) 2007-05-10 2008-11-13 Furman Bruce K Layer Transfer Process and Functionally Enhanced Integrated Circuits Products Thereby
JP2009094144A (ja) * 2007-10-04 2009-04-30 Canon Inc 発光素子の製造方法
DE102007050483A1 (de) 2007-10-19 2009-09-10 Meyer Burger Ag Mischung aus einem thixotropen Dispersionsmedium sowie abrasiv wirkenden Körnern als Schleifmittel
US8950459B2 (en) 2009-04-16 2015-02-10 Suss Microtec Lithography Gmbh Debonding temporarily bonded semiconductor wafers
US8366873B2 (en) * 2010-04-15 2013-02-05 Suss Microtec Lithography, Gmbh Debonding equipment and methods for debonding temporary bonded wafers
WO2010121068A2 (en) * 2009-04-16 2010-10-21 Suss Microtec, Inc. Improved apparatus for temporary wafer bonding and debonding
US8592294B2 (en) * 2010-02-22 2013-11-26 Asm International N.V. High temperature atomic layer deposition of dielectric oxides
US9755015B1 (en) 2016-05-10 2017-09-05 Globalfoundries Inc. Air gaps formed by porous silicon removal
CN108242424B (zh) 2016-12-26 2019-09-03 京东方科技集团股份有限公司 柔性面板的制作方法、柔性面板及显示装置
KR20210075176A (ko) * 2018-10-18 2021-06-22 어플라이드 머티어리얼스, 인코포레이티드 기판을 유지하기 위한 유지 디바이스, 기판을 유지하기 위한 캐리어, 및 유지 디바이스로부터 기판을 해제하기 위한 방법
CN111855636B (zh) * 2019-04-29 2023-10-27 中国科学院微电子研究所 一种sers基底

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4445965A (en) * 1980-12-01 1984-05-01 Carnegie-Mellon University Method for making thin film cadmium telluride and related semiconductors for solar cells
JPH01156480A (ja) * 1987-12-14 1989-06-20 Somar Corp 薄膜剥離装置
KR950014609B1 (ko) * 1990-08-03 1995-12-11 캐논 가부시끼가이샤 반도체부재 및 반도체부재의 제조방법
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP3257580B2 (ja) * 1994-03-10 2002-02-18 キヤノン株式会社 半導体基板の作製方法
JP3381443B2 (ja) * 1995-02-02 2003-02-24 ソニー株式会社 基体から半導体層を分離する方法、半導体素子の製造方法およびｓｏｉ基板の製造方法
DE69627252T2 (de) * 1995-08-02 2004-01-29 Canon Kk Halbleitersubstrat und Herstellungsverfahren

Also Published As

Publication number Publication date
KR100266954B1 (ko) 2000-10-02
KR19980080586A (ko) 1998-11-25
CA2232796C (en) 2002-01-22
AU744858B2 (en) 2002-03-07
TW389958B (en) 2000-05-11
AU5952398A (en) 1998-10-01
CA2232796A1 (en) 1998-09-26
EP0867923A2 (de) 1998-09-30
EP0867923B1 (de) 2004-06-23
DE69824655D1 (de) 2004-07-29
EP0867923A3 (de) 1999-07-28
US6140209A (en) 2000-10-31
DE69824655T2 (de) 2005-08-04

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Legal Events

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