ATE249089T1 - Flashspeicherarchitektur unter verwendung von drei metalschichtenverbindung - Google Patents

Flashspeicherarchitektur unter verwendung von drei metalschichtenverbindung

Info

Publication number
ATE249089T1
ATE249089T1 AT00948688T AT00948688T ATE249089T1 AT E249089 T1 ATE249089 T1 AT E249089T1 AT 00948688 T AT00948688 T AT 00948688T AT 00948688 T AT00948688 T AT 00948688T AT E249089 T1 ATE249089 T1 AT E249089T1
Authority
AT
Austria
Prior art keywords
decoder
global
sub
electrically connected
metal layer
Prior art date
Application number
AT00948688T
Other languages
English (en)
Inventor
Colin S Bill
Johathan Shi-Chang Su
Ravi P Gutala
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE249089T1 publication Critical patent/ATE249089T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Pens And Brushes (AREA)
  • Mechanical Pencils And Projecting And Retracting Systems Therefor, And Multi-System Writing Instruments (AREA)
  • Non-Volatile Memory (AREA)
AT00948688T 1999-08-23 2000-07-14 Flashspeicherarchitektur unter verwendung von drei metalschichtenverbindung ATE249089T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/379,479 US6088287A (en) 1999-08-23 1999-08-23 Flash memory architecture employing three layer metal interconnect for word line decoding
PCT/US2000/019303 WO2001015171A2 (en) 1999-08-23 2000-07-14 Flash memory architecture employing three layer metal interconnect

Publications (1)

Publication Number Publication Date
ATE249089T1 true ATE249089T1 (de) 2003-09-15

Family

ID=23497433

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00948688T ATE249089T1 (de) 1999-08-23 2000-07-14 Flashspeicherarchitektur unter verwendung von drei metalschichtenverbindung

Country Status (9)

Country Link
US (1) US6088287A (de)
EP (1) EP1256116B1 (de)
JP (1) JP4832691B2 (de)
KR (1) KR100629987B1 (de)
CN (1) CN100543867C (de)
AT (1) ATE249089T1 (de)
DE (1) DE60005064T2 (de)
TW (1) TW477986B (de)
WO (1) WO2001015171A2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6781914B2 (en) 2001-08-23 2004-08-24 Winbond Electronics Corp. Flash memory having a flexible bank partition
US6704241B1 (en) 2002-09-06 2004-03-09 Winbond Electronics Corporation Memory architecture with vertical and horizontal row decoding
US6466512B1 (en) * 2001-11-13 2002-10-15 Hewlett Packard Company Method of generating address configurations for solid state memory
US8189390B2 (en) 2009-03-05 2012-05-29 Mosaid Technologies Incorporated NAND flash architecture with multi-level row decoding
JP5249394B2 (ja) * 2011-09-28 2013-07-31 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置
CN103456350A (zh) * 2012-05-30 2013-12-18 辉达公司 半导体存储装置及字线译码布线方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3024687B2 (ja) * 1990-06-05 2000-03-21 三菱電機株式会社 半導体記憶装置
JP3533227B2 (ja) * 1992-09-10 2004-05-31 株式会社日立製作所 半導体記憶装置
US5410508A (en) * 1993-05-14 1995-04-25 Micron Semiconductor, Inc. Pumped wordlines
JPH0878433A (ja) * 1994-08-31 1996-03-22 Nec Corp 半導体装置
JPH0969287A (ja) * 1995-08-31 1997-03-11 Hitachi Ltd 半導体集積回路装置
JPH103794A (ja) * 1996-06-12 1998-01-06 Hitachi Ltd 不揮発性記憶装置および駆動方法
KR100246311B1 (ko) * 1996-09-17 2000-03-15 김영환 반도체 메모리소자
JP3938803B2 (ja) * 1997-03-31 2007-06-27 株式会社日立製作所 ダイナミック型ｒａｍ
KR100254565B1 (ko) * 1997-08-28 2000-05-01 윤종용 분할된 워드 라인 구조를 갖는 플래시 메모리 장치의 행 디코더회로
US5978277A (en) * 1998-04-06 1999-11-02 Aplus Flash Technology, Inc. Bias condition and X-decoder circuit of flash memory array
WO2005109440A1 (ja) * 2004-05-12 2005-11-17 Spansion Llc 半導体装置及びその制御方法

Also Published As

Publication number Publication date
EP1256116B1 (de) 2003-09-03
CN1468435A (zh) 2004-01-14
TW477986B (en) 2002-03-01
DE60005064T2 (de) 2004-06-03
US6088287A (en) 2000-07-11
KR100629987B1 (ko) 2006-09-29
CN100543867C (zh) 2009-09-23
WO2001015171A2 (en) 2001-03-01
EP1256116A2 (de) 2002-11-13
KR20030009289A (ko) 2003-01-29
JP2003517170A (ja) 2003-05-20
WO2001015171A3 (en) 2002-09-12
DE60005064D1 (de) 2003-10-09
JP4832691B2 (ja) 2011-12-07

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