ATE101749T1 - Verfahren zur herstellung einer integrierten schaltungsanordnung mit gate-elektrode und unterliegendem oxid. - Google Patents

Verfahren zur herstellung einer integrierten schaltungsanordnung mit gate-elektrode und unterliegendem oxid.

Info

Publication number
ATE101749T1
ATE101749T1 AT86309559T AT86309559T ATE101749T1 AT E101749 T1 ATE101749 T1 AT E101749T1 AT 86309559 T AT86309559 T AT 86309559T AT 86309559 T AT86309559 T AT 86309559T AT E101749 T1 ATE101749 T1 AT E101749T1
Authority
AT
Austria
Prior art keywords
floating gate
gate electrode
integrated circuit
tunnel oxide
making
Prior art date
Application number
AT86309559T
Other languages
English (en)
Inventor
William P Cox
Mong-Song Liang
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE101749T1 publication Critical patent/ATE101749T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/683—Floating-gate IGFETs having only two programming levels programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation

Landscapes

  • Non-Volatile Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
AT86309559T 1985-12-17 1986-12-09 Verfahren zur herstellung einer integrierten schaltungsanordnung mit gate-elektrode und unterliegendem oxid. ATE101749T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/811,057 US4789883A (en) 1985-12-17 1985-12-17 Integrated circuit structure having gate electrode and underlying oxide and method of making same
EP86309559A EP0228206B1 (de) 1985-12-17 1986-12-09 Verfahren zur Herstellung einer integrierten Schaltungsanordnung mit Gate-Elektrode und unterliegendem Oxid

Publications (1)

Publication Number Publication Date
ATE101749T1 true ATE101749T1 (de) 1994-03-15

Family

ID=25205428

Family Applications (1)

Application Number Title Priority Date Filing Date
AT86309559T ATE101749T1 (de) 1985-12-17 1986-12-09 Verfahren zur herstellung einer integrierten schaltungsanordnung mit gate-elektrode und unterliegendem oxid.

Country Status (5)

Country Link
US (1) US4789883A (de)
EP (1) EP0228206B1 (de)
JP (1) JP2648749B2 (de)
AT (1) ATE101749T1 (de)
DE (1) DE3689651T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6437876A (en) * 1987-08-03 1989-02-08 Fujitsu Ltd Manufacture of semiconductor device
JPH0388370A (ja) * 1989-08-31 1991-04-12 Toshiba Corp 半導体記憶装置の製造方法
EP0491976B1 (de) * 1990-12-21 2000-10-25 Siemens Aktiengesellschaft Verfahren zur Herstellung einer mit Arsen dotierten glatten polykristallinen Siliziumschicht für höchstintegrierte Schaltungen
US5517037A (en) * 1992-03-25 1996-05-14 Kanegafuchi Chemical Industry Co., Ltd. Polysilicon thin film with a particulate product of SiOx
JP4070249B2 (ja) * 1994-11-22 2008-04-02 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
JPH08250609A (ja) * 1995-03-13 1996-09-27 Toshiba Corp 半導体記憶装置及びその使用方法
JPH0964209A (ja) * 1995-08-25 1997-03-07 Toshiba Corp 半導体装置およびその製造方法
US5834358A (en) * 1996-11-12 1998-11-10 Micron Technology, Inc. Isolation regions and methods of forming isolation regions
US5888870A (en) * 1997-10-22 1999-03-30 Advanced Micro Devices, Inc. Memory cell fabrication employing an interpoly gate dielectric arranged upon a polished floating gate
US6025240A (en) * 1997-12-18 2000-02-15 Advanced Micro Devices, Inc. Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices
US6015736A (en) * 1997-12-19 2000-01-18 Advanced Micro Devices, Inc. Method and system for gate stack reoxidation control
US6162716A (en) * 1999-03-26 2000-12-19 Taiwan Semiconductor Manufacturing Company Amorphous silicon gate with mismatched grain-boundary microstructure
US6117717A (en) * 1999-06-07 2000-09-12 Fairchild Semiconductor Corporation Method for after gate implant of threshold adjust with low impact on gate oxide integrity
JP2006310601A (ja) * 2005-04-28 2006-11-09 Toshiba Corp 半導体装置およびその製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4288256A (en) * 1977-12-23 1981-09-08 International Business Machines Corporation Method of making FET containing stacked gates
US4499557A (en) * 1980-10-28 1985-02-12 Energy Conversion Devices, Inc. Programmable cell for use in programmable electronic arrays
JPS5836506B2 (ja) * 1980-11-20 1983-08-09 富士通株式会社 半導体記憶装置
US4422885A (en) * 1981-12-18 1983-12-27 Ncr Corporation Polysilicon-doped-first CMOS process
JPS58212178A (ja) * 1982-06-02 1983-12-09 Matsushita Electric Ind Co Ltd 薄膜電界効果トランジスタおよびその製造方法
GB2130009B (en) * 1982-11-12 1986-04-03 Rca Corp Polycrystalline silicon layers for semiconductor devices
US4545111A (en) * 1983-01-18 1985-10-08 Energy Conversion Devices, Inc. Method for making, parallel preprogramming or field programming of electronic matrix arrays
JPS59154068A (ja) * 1983-02-22 1984-09-03 Toshiba Corp 半導体記憶装置及びその製造方法
JPH0236204B2 (ja) * 1983-05-17 1990-08-16 Mitsubishi Agricult Mach Konbainnohaiwarashorisochi
EP0160965B1 (de) * 1984-05-07 1990-01-31 Kabushiki Kaisha Toshiba Verfahren zum Herstellen einer Halbleiteranordnung mit einer Gateelektrodenstapel-Struktur

Also Published As

Publication number Publication date
JPS62145872A (ja) 1987-06-29
DE3689651D1 (de) 1994-03-24
EP0228206B1 (de) 1994-02-16
EP0228206A2 (de) 1987-07-08
JP2648749B2 (ja) 1997-09-03
EP0228206A3 (en) 1988-04-27
US4789883A (en) 1988-12-06
DE3689651T2 (de) 1994-08-11

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Legal Events

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