DE3481667D1 - Mos-speicherzelle mit schwimmendem gate und verfahren zu ihrer verfertigung. - Google Patents

Mos-speicherzelle mit schwimmendem gate und verfahren zu ihrer verfertigung.

Info

Publication number
DE3481667D1
DE3481667D1 DE8484903331T DE3481667T DE3481667D1 DE 3481667 D1 DE3481667 D1 DE 3481667D1 DE 8484903331 T DE8484903331 T DE 8484903331T DE 3481667 T DE3481667 T DE 3481667T DE 3481667 D1 DE3481667 D1 DE 3481667D1
Authority
DE
Germany
Prior art keywords
floating gate
memory device
substrate
production
storage cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484903331T
Other languages
English (en)
Inventor
Gust Perlegos
Tsung-Ching Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Seeq Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24100566&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE3481667(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Seeq Technology Inc filed Critical Seeq Technology Inc
Application granted granted Critical
Publication of DE3481667D1 publication Critical patent/DE3481667D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/46—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with an inter-gate dielectric layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
DE8484903331T 1983-08-29 1984-08-29 Mos-speicherzelle mit schwimmendem gate und verfahren zu ihrer verfertigung. Expired - Lifetime DE3481667D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US52721383A 1983-08-29 1983-08-29
PCT/US1984/001380 WO1985001146A1 (en) 1983-08-29 1984-08-29 Mos floating gate memory cell and process for fabricating same

Publications (1)

Publication Number Publication Date
DE3481667D1 true DE3481667D1 (de) 1990-04-19

Family

ID=24100566

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484903331T Expired - Lifetime DE3481667D1 (de) 1983-08-29 1984-08-29 Mos-speicherzelle mit schwimmendem gate und verfahren zu ihrer verfertigung.

Country Status (4)

Country Link
EP (1) EP0160003B1 (de)
JP (1) JPS60502128A (de)
DE (1) DE3481667D1 (de)
WO (1) WO1985001146A1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2760983B2 (ja) * 1987-02-12 1998-06-04 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP2635638B2 (ja) * 1987-12-28 1997-07-30 株式会社東芝 不揮発性半導体メモリ装置の製造方法
US5012307A (en) * 1988-07-15 1991-04-30 Texas Instruments Incorporated Electrically-erasable, electrically-programmable read-only memory
US5017980A (en) * 1988-07-15 1991-05-21 Texas Instruments Incorporated Electrically-erasable, electrically-programmable read-only memory cell
EP0326877B1 (de) * 1988-02-05 1995-04-05 Texas Instruments Incorporated Elektrisch löschbare und programmierbare Nur-Lesespeicherzelle
DE68918771T2 (de) * 1988-07-15 1995-02-16 Texas Instruments Inc., Dallas, Tex. Elektrisch löschbare und elektrisch programmierbare Nurlesespeicherzelle mit einem selbstjustierten Tunneleffekt-Fenster.
US5262846A (en) * 1988-11-14 1993-11-16 Texas Instruments Incorporated Contact-free floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates
US5063171A (en) * 1990-04-06 1991-11-05 Texas Instruments Incorporated Method of making a diffusionless virtual drain and source conductor/oxide semiconductor field effect transistor
US5150179A (en) * 1990-07-05 1992-09-22 Texas Instruments Incorporated Diffusionless source/drain conductor electrically-erasable, electrically-programmable read-only memory and method for making and using the same
US5057446A (en) * 1990-08-06 1991-10-15 Texas Instruments Incorporated Method of making an EEPROM with improved capacitive coupling between control gate and floating gate
US5086325A (en) * 1990-11-21 1992-02-04 Atmel Corporation Narrow width EEPROM with single diffusion electrode formation
US5273926A (en) * 1991-06-27 1993-12-28 Texas Instruments Incorporated Method of making flash EEPROM or merged FAMOS cell without alignment sensitivity
US5225700A (en) * 1991-06-28 1993-07-06 Texas Instruments Incorporated Circuit and method for forming a non-volatile memory cell
US5218568A (en) * 1991-12-17 1993-06-08 Texas Instruments Incorporated Electrically-erasable, electrically-programmable read-only memory cell, an array of such cells and methods for making and using the same
EP0752717A1 (de) * 1995-05-10 1997-01-08 STMicroelectronics S.r.l. Herstellungsverfahren für eine integrierte Schaltung mit Komponenten mit unterschiedlichem Dielektrum
US5914514A (en) * 1996-09-27 1999-06-22 Xilinx, Inc. Two transistor flash EPROM cell

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7500550A (nl) 1975-01-17 1976-07-20 Philips Nv Halfgeleider-geheugeninrichting.
US4115194A (en) 1977-02-22 1978-09-19 The Babcock & Wilcox Company Reactor pressure vessel support
US4142926A (en) 1977-02-24 1979-03-06 Intel Corporation Self-aligning double polycrystalline silicon etching process
US4203158A (en) 1978-02-24 1980-05-13 Intel Corporation Electrically programmable and erasable MOS floating gate memory device employing tunneling and method of fabricating same
CH631287A5 (fr) * 1979-03-14 1982-07-30 Centre Electron Horloger Element de memoire non-volatile, electriquement reprogrammable.
JPS57112078A (en) * 1980-12-29 1982-07-12 Fujitsu Ltd Manufacture of electrically rewritable fixed memory
JPS57141969A (en) * 1981-02-27 1982-09-02 Toshiba Corp Nonvolatile semiconductor memory
JPS5864069A (ja) * 1981-10-14 1983-04-16 Hitachi Ltd 半導体装置およびその製造方法
US4477825A (en) * 1981-12-28 1984-10-16 National Semiconductor Corporation Electrically programmable and erasable memory cell
JPS58130571A (ja) * 1982-01-29 1983-08-04 Hitachi Ltd 半導体装置

Also Published As

Publication number Publication date
JPH0548632B2 (de) 1993-07-22
EP0160003A4 (de) 1986-07-23
WO1985001146A1 (en) 1985-03-14
EP0160003A1 (de) 1985-11-06
JPS60502128A (ja) 1985-12-05
EP0160003B1 (de) 1990-03-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: ATMEL CORP., SAN JOSE, CALIF., US

8328 Change in the person/name/address of the agent

Free format text: KAHLER, KAECK & FIENER, 86899 LANDSBERG