Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/66—Vertical DMOS [VDMOS] FETs

Definitions

• This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.
• a known semiconductor device configuration is one in which a sidewall electrode is provided extending from a wide trench in the termination region to the exterior (see, for example, Patent Document 1).
• a proposed semiconductor device configuration involves providing a gate electrode in a gate trench in the active region via a gate insulating film, and providing the entire interlayer insulating film within the gate trench above the gate electrode.
• the gate electrode and sidewall electrodes are formed by etching the same conductive film.
• the gate electrode is etched more than conventionally in order to lower the upper end of the gate electrode within the gate trench.
• the sidewall electrodes are also etched more than conventionally, and the sidewall electrodes are provided within a wide trench and have a tapered portion that narrows toward the upper side.
• the out-of-plane direction of the top surface of the tapered portion is significantly different from the deposition direction in which the interlayer insulating film is likely to deposit on the tapered portion. Therefore, when the sidewall electrode has only a tapered portion, the thickness of the interlayer insulating film in the tapered portion becomes partially thin, resulting in a problem of reduced insulation properties of the interlayer insulating film in the termination region.
• This disclosure has been made in consideration of the above-mentioned problems, and aims to provide technology that can improve the insulation properties of the interlayer insulating film in the termination region.
• the semiconductor device disclosed herein comprises a semiconductor layer having a first trench in an active region and a second trench in a termination region, the second trench being wider than the first trench; a gate electrode provided in the first trench with a first insulating film interposed therebetween; a first interlayer insulating film provided in the first trench above the gate electrode; a termination electrode made of the same material as the gate electrode and provided on the bottom surface of the second trench and on the side surface facing the active region with a second insulating film interposed therebetween; and a second interlayer insulating film provided on the termination electrode, the termination electrode including a tapered portion provided along the side surface of the second trench and tapering upward, and a continuous portion provided along the bottom surface of the second trench and continuous with the tapered portion.
• FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment
• FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment.
• 10 is a flowchart showing a method for manufacturing a semiconductor device according to a second embodiment.
• a certain portion having a higher concentration than another portion may mean, for example, that the average concentration of the certain portion is higher than the average concentration of the other portion.
• a certain portion having a lower concentration than another portion may mean, for example, that the average concentration of the certain portion is lower than the average concentration of the other portion.
• the first conductivity type is n-type and the second conductivity type is p-type; however, the first conductivity type may also be p-type and the second conductivity type may also be n-type.
• Fig. 1 is a plan view showing the configuration of a semiconductor device according to the first embodiment.
• Fig. 2 is a cross-sectional view taken along line A-A in Fig. 1
• Fig. 3 is a cross-sectional view taken along line B-B in Fig. 1.
• Fig. 4 is a cross-sectional view showing an enlarged portion of Fig. 3. For convenience, some of the components in Fig. 4 are omitted or simplified in Figs. 2 and 3.
• the following description will be given of the semiconductor device according to the first embodiment as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but the present invention is not limited to this.
• the semiconductor device according to the first embodiment may also be, for example, an IGBT (Insulated Gate Bipolar Transistor), or an RC-IGBT (Reverse Conducting-IGBT), which is a semiconductor switching element including a diode.
• IGBT Insulated Gate Bipolar Transistor
• RC-IGBT Reverse Conducting-IGBT
• the semiconductor device includes a semiconductor layer 1, a gate insulating film 2 serving as a first insulating film, a gate electrode 3, a first interlayer insulating film 4, a termination insulating film 5 serving as a second insulating film, a sidewall electrode 6 serving as a termination electrode, a second interlayer insulating film 7, and a source electrode 8.
• the semiconductor layer 1 is made of, for example, silicon (Si) or a wide bandgap semiconductor, and includes at least one of a normal semiconductor wafer and an epitaxial growth layer.
• “at least one of A, B, C, ..., and Z” means any one of all combinations of one or more types extracted from the group A, B, C, ..., and Z.
• Wide bandgap semiconductors include, for example, silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ), diamond, etc.
• an active region 1j and a termination region 1k are defined in the semiconductor layer 1.
• a semiconductor cell that functions as a MOSFET is provided in the active region 1j.
• the termination region 1k is a region that surrounds the active region 1j, and is provided with a breakdown voltage structure such as a guard ring (not shown).
• the gate pad 31 in Figure 1 is provided roughly above the semiconductor layer 1 in the termination region 1k, and the source pad 32 is provided roughly above the semiconductor layer 1 in the active region 1j.
• the semiconductor layer 1 of the active region 1j includes a drift region 1a, a low-resistance region 1b, a well region (also called a base region) 1c, a source region 1d, a contact region 1e, and an electric field relaxation region 1f.
• the contact region 1e is a p + type region and is provided on the well region 1c where the source region 1d is not provided. As shown in FIG. 2, the contact region 1e may or may not be provided depending on the position in the extension direction of the gate trench 1p described later.
• the active region 1j of the semiconductor layer 1 has a gate trench 1p, which is a first trench that penetrates from the top surface of the source region 1d through the well region 1c.
• the multiple gate trenches 1p may or may not have a striped shape.
• the electric field relaxation region 1f is a p-type region and is provided on the bottom surface of the gate trench 1p.
• the termination region 1k of the semiconductor layer 1 includes a wide trench 1q, which is a second trench that extends from the top surface of the source region 1d through the well region 1c and is wider than the gate trench 1p.
• the width here corresponds to the horizontal distance in FIG. 4 .
• the mesa portion 1r which is the upper portion of the semiconductor layer 1, is located between the gate trench 1p and the wide trench 1q.
• the depths of the gate trench 1p and the wide trench 1q are the same or substantially the same. This configuration allows the depletion layer depths in the drift region 1a to be uniform, thereby suppressing a decrease in the breakdown voltage of the semiconductor device due to electric field concentration around the periphery of the active region 1j.
• the vertical thicknesses of the gate electrode 3 and the sidewall electrode 6 would be the same, but in this first embodiment, the opening sizes of these trenches are different, so the thicknesses of these electrodes differ slightly from each other.
• the sidewall electrode 6 includes a tapered portion 6a and a continuous portion 6b.
• the tapered portion 6a is provided along the side surface 1q2 of the wide trench 1q and tapers upward.
• the continuous portion 6b is provided along the bottom surface 1q1 of the wide trench 1q and is continuous with the tapered portion 6a.
• the tapered portion 6a includes a first portion and a second portion that is closer to the continuous portion 6b than the first portion, and the out-of-plane direction D1 of the first portion is closer to the vertical direction than the out-of-plane direction D2 of the second portion.
• the second interlayer insulating film 7 is provided on the sidewall electrode 6.
• the second interlayer insulating film 7 is provided on the tapered portion 6a, the continuous portion 6b, and the mesa portion 1r.
• ⁇ Manufacturing method> 5 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment. Since each region of the semiconductor layer 1 can be formed using a general semiconductor device manufacturing process, the following mainly describes the formation of the gate electrode 3 and the sidewall electrodes 6.
• step S1 a gate trench 1p is formed in the active region 1j of the semiconductor layer 1, and a wide trench 1q is formed in the termination region 1k of the semiconductor layer 1.
• step S2 an insulating film 9 is formed in the gate trench 1p and the wide trench 1q, as shown in FIG. 6.
• step S3 a conductive film 10 is formed on the insulating film 9 as shown in FIG. 6.
• step S4 the conductive film 10 is patterned as shown in FIG. 6 to form the gate electrode 3 and sidewall electrode 6 in parallel. Note that in the sidewall electrode 6, by adjusting the position of the mask used to pattern the conductive film 10, the thickness of the continuous portion 6b, and the etching conditions, it is possible to make the continuous portion 6b continuous with the tapered portion 6a.
• step S5 an interlayer insulating film is formed in the gate trench 1p above the gate electrode 3, and an interlayer insulating film is formed on the sidewall electrode 6.
• the interlayer insulating film is then patterned to form the first interlayer insulating film 4 and the second interlayer insulating film 7, and the insulating film 9 is patterned to form the gate insulating film 2 and the termination insulating film 5.
• the first interlayer insulating film 4 and the second interlayer insulating film 7 may be formed in parallel or separately. Thereafter, the source electrode 8, the drain electrode, etc. are formed, and the semiconductor device is completed.
• ⁇ Summary of First Embodiment> 7 is a cross-sectional view showing the configuration of a related device, which is a semiconductor device related to the semiconductor device according to the first embodiment.
• the sidewall electrode 6 does not include the continuous portion 6 b but includes the tapered portion 6 a.
• the out-of-plane direction D of the upper surface of the tapered portion 6a is significantly different from the deposition direction (corresponding to the up-and-down direction in Figure 7) in which the second interlayer insulating film 7 is likely to deposit on the tapered portion 6a. For this reason, if the sidewall electrode 6 only has the tapered portion 6a, the thickness of the second interlayer insulating film 7 in the out-of-plane direction D becomes thin, resulting in a problem of reduced insulation properties of the second interlayer insulating film 7 in the termination region 1k.
• the sidewall electrode 6 includes a tapered portion 6a and a continuous portion 6b that is continuous with the tapered portion 6a.
• the upper surface of the tapered portion 6a where the out-of-plane direction is significantly different from the deposition direction, can be reduced by the continuous portion 6b. This allows the thickness of the second interlayer insulating film 7 to be increased, thereby improving the insulating properties of the second interlayer insulating film 7 in the termination region 1k.
• the gate voltage can be maintained by increasing the insulating properties of the second interlayer insulating film 7 in the termination region 1k as described above.
• tapered portion 6a includes a first portion and a second portion that is closer to continuous portion 6b than the first portion, and the out-of-plane direction D1 of the first portion is closer to the vertical direction than the out-of-plane direction D2 of the second portion.
• the out-of-plane direction of tapered portion 6a can be made closer to the deposition direction of second interlayer insulating film 7, and therefore the thickness of second interlayer insulating film 7 near side surface 1q2 at the boundary between active region 1j and termination region 1k can be made thicker. Note that this is not limited to the configuration of FIG. 4, and also applies to a configuration such as that of FIG. 8, in which the portion of continuous portion 6b on the tapered portion 6a side is thinner than other portions of continuous portion 6b.
• the sidewall electrode 6 is electrically connected to the gate electrode 3, but this is not limiting.
• the sidewall electrode 6 may be electrically connected to the source electrode 8 instead of the gate electrode 3.
• the source voltage can be maintained by increasing the insulating properties of the second interlayer insulating film 7 in the termination region 1k as described above.
• the sidewall electrode 6 may be a floating electrode that is not electrically connected to either the gate electrode 3 or the source electrode 8.
• increasing the insulating properties of the second interlayer insulating film 7 in the termination region 1k as described above can reduce an increase in resistance due to a short circuit between the gate electrode 3 or the source electrode 8 and the sidewall electrode 6, which is a floating electrode.
• ⁇ Second Embodiment> 9 is a cross-sectional view showing the configuration of a semiconductor device according to the second embodiment, specifically a cross-sectional view corresponding to FIG. 4.
• components according to the second embodiment components that are the same as or similar to the components described above will be given the same or similar reference numerals, and different components will be mainly described.
• the sidewall electrode 6 including the tapered portion 6a described in the related device is not provided within the wide trench 1q. Instead, a second interlayer insulating film 7 is provided on the bottom surface 1q1 of the wide trench 1q and on the side surface 1q2 on the active region 1j side, via a termination insulating film 5. Note that a sidewall electrode that does not include the tapered portion 6a may be provided within the wide trench 1q.
• Fig. 10 is a flowchart showing a method for manufacturing a semiconductor device according to the second preferred embodiment. Since steps S1 to S3 in Fig. 10 are the same as steps S1 to S3 in Fig. 5, the following description will mainly focus on steps S4a and S5a.
• step S4a the conductive film 10 is patterned to form the gate electrode 3, but the sidewall electrode 6 is not formed in the wide trench 1q.
• the conductive film 10 in the wide trench 1q may be removed using a mask, or it may be removed without using a mask by appropriately adjusting the opening size of the wide trench 1q.
• a first interlayer insulating film 4 is formed in the gate trench 1p above the gate electrode 3, and a second interlayer insulating film 7 is formed on the bottom surface 1q1 and side surface 1q2 of the wide trench 1q via a termination insulating film 5.
• the first interlayer insulating film 4 and the second interlayer insulating film 7 may be formed in parallel or separately. Subsequently, a source electrode 8, a drain electrode, etc. are formed, and the semiconductor device is completed.
• Second interlayer insulating film 7 is provided in wide trench 1q via termination insulating film 5.
• the tapered shape that would have made second interlayer insulating film 7 thinner is not provided, so the thickness of second interlayer insulating film 7 can be increased, and as a result, the insulating properties of second interlayer insulating film 7 in termination region 1k can be improved.
• the sidewall electrode 6 is described as being continuous with the gate electrode 3, and the termination insulating film 5 is described as being continuous with the gate insulating film 2.
• this is not limitative.
• the sidewall electrode 6 may be separated from the gate electrode 3, and the termination insulating film 5 may be separated from the gate insulating film 2.
• the sidewall electrode 6 including the tapered portion 6a and the continuous portion 6b is applied to the cross-sectional configuration along line B-B in FIG. 1, but this is not limited to this.
• the sidewall electrode 6 may be applied to the cross-sectional configuration along line A-A in FIG. 1.
• 'a' and 'an' mean one or more. Therefore, 'a', 'an', 'one or more', and 'at least one' can be used interchangeably.

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