WO2024185127A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
WO2024185127A1
WO2024185127A1 PCT/JP2023/009053 JP2023009053W WO2024185127A1 WO 2024185127 A1 WO2024185127 A1 WO 2024185127A1 JP 2023009053 W JP2023009053 W JP 2023009053W WO 2024185127 A1 WO2024185127 A1 WO 2024185127A1
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WIPO (PCT)
Prior art keywords
semiconductor device
heat dissipation
dissipation member
semiconductor
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/009053
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English (en)
French (fr)
Japanese (ja)
Inventor
佑毅 吉岡
佑樹 矢野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2025505031A priority Critical patent/JP7778271B2/ja
Priority to DE112023005941.1T priority patent/DE112023005941T5/de
Priority to PCT/JP2023/009053 priority patent/WO2024185127A1/ja
Priority to CN202380095365.4A priority patent/CN120814047A/zh
Publication of WO2024185127A1 publication Critical patent/WO2024185127A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
    • H10W40/77—Auxiliary members characterised by their shape
    • H10W40/778—Auxiliary members characterised by their shape in encapsulations

Definitions

  • This disclosure relates to a semiconductor device and a manufacturing method thereof, and in particular to a semiconductor device having a structure that dissipates heat generated by a semiconductor element through a base plate.
  • Patent Document 1 One example of a semiconductor device with a structure that dissipates heat generated by a semiconductor element is the semiconductor device disclosed in Patent Document 1.
  • the conventional semiconductor device disclosed in Patent Document 1 is provided with a heat dissipation mechanism that relieves the thermal stress acting on the joint between the semiconductor element and the connection wiring caused by the difference in thermal expansion coefficient between the components.
  • the conventional semiconductor device realizes the heat dissipation mechanism by inserting a thermal stress buffering member between the semiconductor element and the connection wiring and bonding the thermal stress buffering member to both the semiconductor element and the connection wiring.
  • the thermal stress buffering member used in the heat dissipation mechanism is composed of a composite material in which a sintered body of a carbon base material or metal base material is infiltrated and dispersed with a metal having a lower melting point than the above-mentioned base material.
  • Conventional semiconductor devices with a heat dissipation mechanism generally use a one-sided cooling method in which the semiconductor element is bonded via an insulating substrate as the heat dissipation mechanism, thereby cooling the semiconductor element from the insulating substrate side.
  • the top surface of the semiconductor element is sealed with an encapsulating resin layer, so heat generated by the semiconductor element during power-on operation accumulates in the encapsulating resin layer.
  • the encapsulating resin layer is provided on the opposite side of the insulating substrate relative to the semiconductor element, it is difficult for conventional heat dissipation mechanisms that use the one-sided cooling method described above to dissipate the heat accumulated in the encapsulating resin layer.
  • the thermal expansion coefficients of components used in semiconductor devices are values in the range of ⁇ 2 ⁇ 10 -6 /K to 22 ⁇ 10 -6 /K ⁇ when the components in the device are semiconductor elements, connection wiring, insulating substrates, base plates, and sealing resin layers. Therefore, the maximum difference in linear expansion coefficients between components in a conventional semiconductor device can be as much as 20 ⁇ 10 -6 /K.
  • connection wiring and base plate tend to be components that increase the difference in thermal expansion coefficient.
  • the sealing resin layer is in contact with all the components and is particularly affected by the difference in thermal expansion coefficient.
  • Components contained within the semiconductor device include the semiconductor element, connection wiring, insulating substrate, base plate, etc.
  • the junction temperature Tj of the semiconductor element rises to, for example, 125°C when it is in operation
  • conventional semiconductor devices have a cooling mechanism for a single-sided cooling method, so the temperature of each component remains close to the design temperature of the cooling mechanism.
  • the sealing resin layer on the top surface of the semiconductor element rises to 125°C and the heat propagates throughout the sealing resin layer, causing peeling from each component due to differences in the thermal expansion coefficient between the components, resulting in a problem of reduced reliability of the semiconductor device.
  • the conventional semiconductor device disclosed in Patent Document 1 has a structure in which a thermal stress buffer member is inserted between the semiconductor element and the connection wiring. Therefore, by cooling the heat generated when the semiconductor element is energized through the thermal stress buffer member, the thermal stress generated at the interface between the semiconductor element and the encapsulating resin layer is alleviated, preventing peeling between the semiconductor element and the encapsulating resin layer and improving the reliability of the device.
  • thermal stress buffer material is electrically connected to the semiconductor element that constitutes the main current circuit and functions as part of the wiring of the semiconductor element, there is a problem in that electrical loss occurs when the semiconductor element is energized.
  • electrical loss is an increase in inductance.
  • the present disclosure aims to solve the problems described above and provide a semiconductor device structure that improves the reliability of the device without causing electrical loss during operation of the semiconductor element.
  • the semiconductor device includes a base plate having a first main surface and a second main surface, an insulating circuit board having a circuit pattern provided on the first main surface side of the base plate, at least one semiconductor element provided on the first main surface side of the insulating circuit board, a heat dissipation member having electrical conductivity and including a plurality of pillars and a plate portion provided between the plurality of pillars, the plate portion being located on the first main surface side of the insulating circuit board and the at least one semiconductor element, and the plurality of pillars being provided in an upright manner on the first main surface of the base plate, and a resin layer provided on the first main surface of the base plate to cover the insulating circuit board, the at least one semiconductor element, and the heat dissipation member, the heat dissipation member being provided away from the at least one semiconductor element so that the resin layer between the heat dissipation member and the at least one semiconductor element does not cause dielectric breakdown during operation of the at least one semiconductor element, and the
  • the heat dissipation member in the semiconductor device disclosed herein is electrically insulated from at least one semiconductor element, so the presence of the heat dissipation member does not cause electrical loss during operation of the at least one semiconductor element.
  • the heat dissipation member is located away from the at least one semiconductor element so that the resin layer does not experience dielectric breakdown when the at least one semiconductor element is in operation, and therefore dielectric breakdown does not occur in the resin layer when the at least one semiconductor element is in operation.
  • the heat dissipation member is conductive and the column portion is arranged in an upright manner on the first main surface of the base plate, it can perform a heat dissipation function of dissipating heat accumulated in the resin layer during operation of at least one semiconductor element through a heat dissipation path including the heat dissipation member and the base plate.
  • the semiconductor device disclosed herein can mitigate the effects of differences in thermal expansion coefficient between the resin layer and other components, and can reliably avoid interfacial peeling between the resin layer and at least one semiconductor element, the insulating circuit board, and the base plate.
  • the semiconductor device disclosed herein can increase the reliability of the device without generating electrical losses during operation of at least one semiconductor element.
  • FIG. 1 is a plan view showing a top surface structure of a semiconductor device according to a first embodiment
  • 2 is a cross-sectional view (part 1) showing a cross-sectional structure of the semiconductor device according to the first embodiment shown in FIG. 1
  • 2 is a cross-sectional view (part 2) showing the cross-sectional structure of the semiconductor device according to the first embodiment shown in FIG. 1
  • FIG. 11 is a plan view showing a top surface structure of a semiconductor device according to a second embodiment.
  • 11 is a cross-sectional view showing a cross-sectional structure of a semiconductor device according to a third embodiment
  • FIG. 13 is a plan view showing a top surface structure of a semiconductor device according to a fourth embodiment.
  • FIG. 1 is a plan view showing a top surface structure of a semiconductor device according to a first embodiment
  • 2 is a cross-sectional view (part 1) showing a cross-sectional structure of the semiconductor device according to the first embodiment shown in FIG. 1
  • 2 is a cross-section
  • FIG. 7 is a cross-sectional view (part 1) showing a cross-sectional structure of the semiconductor device according to the fourth embodiment shown in FIG. 6;
  • FIG. 7 is a cross-sectional view (part 2) showing the cross-sectional structure of the semiconductor device according to the fourth embodiment shown in FIG. 6;
  • FIG. 13 is a cross-sectional view showing a cross-sectional structure of a semiconductor device according to a fifth embodiment.
  • FIG. 13 is a cross-sectional view showing a cross-sectional structure of a semiconductor device according to a sixth embodiment.
  • Fig. 1 is a plan view showing a top surface structure of a semiconductor device 51 according to a first embodiment of the present disclosure.
  • Fig. 2 is a cross-sectional view showing an A-A cross-sectional structure of the semiconductor device 51 according to the first embodiment shown in Fig. 1.
  • Fig. 3 is a cross-sectional view showing a B-B cross-sectional structure of the semiconductor device 51 according to the first embodiment shown in Fig. 1.
  • An XYZ orthogonal coordinate system is depicted in each of Figs. 1 to 3. Note that Fig. 1 omits the illustration of the sealing resin layer 8 in order to clearly show the internal structure of the semiconductor device 51.
  • first main surface the upper end of the paper of each component of semiconductor device 51 shown in the cross-sectional views of Figures 2 and 3
  • second main surface the lower end of the paper
  • the surface on the +Z direction side will be the “first main surface”
  • the surface on the -Z direction side will be the "second main surface.”
  • the top surface of the metal base plate 1, which is the base plate, is the first main surface
  • the bottom surface is the second main surface.
  • the +Z direction may be referred to as the first main surface side and the -Z direction may be referred to as the second main surface side with respect to each component.
  • a resin case 2 is provided on a first main surface of a metal base plate 1, which is a base plate.
  • the metal base plate 1 is made of a material with excellent thermal conductivity, such as an aluminum alloy or copper.
  • the resin case 2 has a rectangular frame structure with four side walls when viewed in the XY plane, and is provided on the peripheral region of the first main surface of the metal base plate 1.
  • a plurality of external electrodes 11 are provided on the upper surfaces of the side walls of the resin case 2.
  • two external electrodes 11 are illustrated as the plurality of external electrodes 11.
  • the resin case 2 is made of a highly heat-resistant resin such as PPS (Poly Phenylene Sulfide) or PBT (Poly Butylen Terefthalate).
  • the combination of the metal base plate 1 and the resin case 2 forms an open-top housing with an internal storage area, with the metal base plate 1 as the bottom and the resin case 2 as the side.
  • a number of intermediate connection members 21 are provided in the resin case 2 from the inner surface of the side wall to the inside in correspondence with the number of external electrodes 11.
  • two intermediate connection members 21 are illustrated as the number of intermediate connection members 21.
  • Corresponding external electrodes 11 and intermediate connection members 21 are electrically connected to each other via embedded connection wires 22.
  • the embedded connection wires 22 are embedded inside the side wall of the resin case 2. In this way, there is a one-to-one correspondence between the number of external electrodes 11, the number of intermediate connection members 21, and the number of embedded connection wires 22.
  • An insulating circuit board 3 is provided on the first main surface of the metal base plate 1.
  • the insulating circuit board 3 is provided in such a manner that it fits within the storage area defined by the combination of the metal base plate 1 and the resin case 2.
  • the insulating circuit board 3 is a substrate having a combined structure of an insulating layer 30 and a circuit pattern 5 provided on both sides of the insulating layer 30.
  • the insulating layer 30 is made of a material such as ceramic with excellent thermal conductivity, such as aluminum nitride or silicon nitride, or resin.
  • Circuit patterns 5 are provided on both sides of the insulating layer 30.
  • the circuit patterns 5 are made of aluminum alloy, copper, or the like. Note that in Figures 2 and 3 and the cross-sectional views shown below, the circuit patterns 5 provided on the second main surface of the insulating layer 30 are omitted.
  • a plurality of semiconductor elements 6 are provided on the first main surface of the circuit pattern 5 via a conductive bonding material 10.
  • a conductive bonding material 10 is made of solder, soft solder, or the like. Therefore, the circuit pattern 5 of the insulating circuit board 3 and the plurality of semiconductor elements 6 are bonded via the conductive bonding material 10.
  • the multiple semiconductor elements 6 are each electrically connected to the intermediate connection member 21 via the electrical connection member 7. Therefore, signals that flow when the multiple semiconductor elements 6 are energized can be obtained from the multiple external electrodes 11.
  • silicon (Si) IGBTs Insulated Gate Bipolar Transistors
  • diodes diodes
  • reverse conducting IGBTs are often used as each of the multiple semiconductor elements 6.
  • MOSFETs metal-oxide-semiconductor field effect transistors
  • GaN gallium nitride
  • the number of semiconductor elements 6 mounted on the first main surface side of the insulating circuit board 3 is not limited, and the required number of semiconductor elements 6 are mounted depending on the application.
  • the semiconductor device 51 of the first embodiment needs to have at least one semiconductor element 6.
  • the structure including the insulating circuit board 3, the multiple semiconductor elements 6, and the multiple conductive bonding materials 10 may be referred to as the "intermediate structure.”
  • the electrical connection member 7 is shown diagrammatically. That is, the electrical connection member 7 includes a linear connection member such as a wire that is bonded and fixed by ultrasonic wire bonding processing, and a plate-shaped connection member whose main portion is formed in a plate shape. In Figures 1 to 3, the electrical connection member 7 is shown as a linear connection member.
  • a main current circuit is formed including the multiple semiconductor elements 6, the electrical connection members 7, and the circuit pattern 5 portion of the insulating circuit board 3.
  • the main current circuit is the circuit through which the main current flows when the multiple semiconductor elements 6 are energized.
  • the semiconductor device 51 of the first embodiment is characterized by further comprising a heat dissipation member 4.
  • the heat dissipation member 4 is conductive, includes a plurality of pillars 4b and one plate portion 4a provided between the plurality of pillars 4b, and has a flat gate shape in the XZ cross section as shown in FIG. 3. In FIG. 3, two pillars 4b are illustrated as the plurality of pillars 4b.
  • the plate portion 4a of the heat dissipation member 4 has a rectangular shape when viewed in a plan view on the XY plane as shown in FIG. 1.
  • the second main surface of the plate portion 4a is arranged to face the first main surface of each component that constitutes the intermediate structure.
  • the plate portion 4a of the heat dissipation member 4 is arranged at a position spaced a distance in the +Z direction from the first main surfaces of the insulating circuit board 3 and the multiple semiconductor elements 6.
  • the plate portion 4a of the heat dissipation member 4 is located on the first main surface side of the insulating circuit board 3 and the multiple semiconductor elements 6.
  • the multiple pillars 4b are provided in a manner that they stand upright on the first main surface of the metal base plate 1 without contacting the intermediate structure. In other words, some or all of the lower ends of the multiple pillars 4b are in contact with the first main surface of the metal base plate 1. In this way, the heat dissipation member 4 is provided on the first main surface of the metal base plate 1 in a manner that straddles the intermediate structure.
  • the storage area is sealed by filling it with the sealing resin layer 8.
  • the sealing resin layer 8, which is a resin layer is provided on the first main surface of the metal base plate 1, covering the insulating circuit board 3, the circuit pattern 5, the multiple semiconductor elements 6, the multiple electrical connection members 7, and the heat dissipation members 4.
  • the sealing resin layer 8 is often made of silicone gel or epoxy resin, but is not limited to these materials. Any material that has the desired elastic modulus, heat resistance, adhesiveness, linear expansion coefficient, and other physical properties can be used.
  • the sealing resin layer 8 is present between the second main surface of the plate portion 4a of the heat dissipation member 4 and the intermediate structure. In other words, the sealing resin layer 8 is present between the second main surface of the plate portion 4a and the first main surface of each of the multiple semiconductor elements 6.
  • a cooling mechanism 9 is attached to the second main surface side of the metal base plate 1, which is the base plate.
  • the cooling mechanism 9 employs a water-cooling method or an air-cooling method, and performs a cooling operation to cool the metal base plate 1. Therefore, the heat dissipation member 4 is cooled by the cooling operation of the cooling mechanism 9 via the metal base plate 1.
  • the heat dissipation member 4 is provided away from the multiple semiconductor elements 6 so that the sealing resin layer 8 between the heat dissipation member 4 and the multiple semiconductor elements 6 does not cause dielectric breakdown when the multiple semiconductor elements 6 are energized.
  • the heat dissipation member 4 is electrically insulated from the multiple semiconductor elements 6, and the potential of the heat dissipation member 4 is set to 0V.
  • the potential of the heat dissipation member 4 is set, for example, by setting the metal base plate 1 to a reference potential of 0V.
  • the heat dissipation member 4 is provided at a position that is an insulation distance of more than 30 ⁇ m between the semiconductor elements 6 and the heat dissipation member 4 when the semiconductor elements 6 are in an electrically conductive operation.
  • “30 ⁇ m” is the value obtained by dividing the operating voltage of 600 V by the breakdown voltage of 20 kV/mm.
  • the "insulation distance" can be calculated from two factors (the breakdown voltage of the sealing resin layer 8 and the voltage when the semiconductor elements 6 are in a conductive operation).
  • the distance between the second main surface of the plate portion 4a of the heat dissipation member 4 facing each other in the Z direction and the first main surface of each of the multiple semiconductor elements 6 is set to satisfy the above insulation distance.
  • the shortest distance between each of the multiple column portions 4b and the side surface of each of the multiple semiconductor elements 6 is set to satisfy the above insulation distance.
  • the shortest distance between each of the multiple pillars 4b and the side of each of the multiple circuit patterns 5 is set to satisfy the above-mentioned insulation distance, and that the shortest distance between each of the multiple electrical connection members 7 and the heat dissipation member 4 is set to satisfy the above-mentioned insulation distance.
  • the plate portion 4a and the multiple pillar portions 4b are positioned so that they are not in contact with any of the multiple semiconductor elements 6, and a sealing resin layer 8 is provided between the heat dissipation member 4 and the multiple semiconductor elements 6, so that the heat dissipation member 4 is electrically insulated from the multiple semiconductor elements 6.
  • the heat dissipation member 4 in the semiconductor device 51 of embodiment 1 is electrically insulated from the multiple semiconductor elements 6, so the presence of the heat dissipation member 4 does not cause electrical loss during operation of the multiple semiconductor elements 6.
  • the heat dissipation member 4 is disposed at an insulating distance away from the semiconductor elements 6 so that the sealing resin layer 8, which is a resin layer, does not experience dielectric breakdown when electrical current is applied to the semiconductor elements 6. This means that the sealing resin layer 8 does not experience dielectric breakdown when electrical current is applied to the semiconductor elements 6.
  • the heat dissipation member 4 is cooled via the metal base plate 1 by the cooling action of the cooling mechanism 9. Therefore, the heat dissipation member 4 can perform a heat dissipation function of dissipating heat accumulated in the sealing resin layer 8 during the operation of passing current through the multiple semiconductor elements 6 via a heat dissipation path including the heat dissipation member 4 and the metal base plate 1.
  • the heat accumulated in the sealing resin layer 8 can be effectively dissipated by the above-mentioned heat dissipation function of the heat dissipation member 4.
  • the semiconductor device 51 of the first embodiment can mitigate the effects of differences in thermal expansion coefficients between the sealing resin layer 8 and each of the components due to the heat dissipation function of the heat dissipation member 4, and can reliably avoid interfacial peeling between the sealing resin layer 8 and each of the multiple semiconductor elements 6, the insulating circuit board 3, and the metal base plate 1.
  • the semiconductor device 51 of the first embodiment can improve the reliability of the device without generating electrical losses when the multiple semiconductor elements 6 are energized.
  • the degree of freedom in the arrangement of the multiple electrical connection members 7 is relatively high.
  • the semiconductor device 51 of the first embodiment can perform a double-sided cooling operation on the sealing resin layer 8 by simultaneously performing a first cooling operation in which the first main surface side of the sealing resin layer 8 is cooled by the heat dissipation path of the heat dissipation member 4, the metal base plate 1, and the cooling mechanism 9, and a second cooling operation in which the second main surface side of the sealing resin layer 8 is cooled by the heat dissipation path of the insulating circuit board 3, the metal base plate 1, and the cooling mechanism 9.
  • the semiconductor device 51 of the first embodiment performs a double-sided cooling operation including the first and second cooling operations described above, thereby effectively dissipating the heat accumulated in the sealing resin layer 8 and mitigating the effects of differences in the thermal expansion coefficient between the sealing resin layer 8 and each of its components.
  • the semiconductor device 51 of the first embodiment can simplify the device configuration by performing the cooling operation of the double-sided cooling method described above using a single cooling mechanism 9.
  • the semiconductor device 51 of the first embodiment has a structure having multiple semiconductor elements 6, a similar effect can be achieved with a structure having one semiconductor element 6.
  • the semiconductor device 51 of the first embodiment can be applied to a structure having at least one semiconductor element 6.
  • Fig. 4 is a plan view showing a top surface structure of a semiconductor device 52 according to a second embodiment of the present disclosure.
  • An XYZ orthogonal coordinate system is shown in Fig. 4.
  • Fig. 4 omits the illustration of the sealing resin layer 8 in order to clearly show the internal structure of the semiconductor device 52. That is, Fig. 4 shows a state before resin sealing with the sealing resin layer 8 is performed.
  • the semiconductor device 52 of the second embodiment has a structure in which the heat dissipation member 4 is replaced with a heat dissipation member 42.
  • the heat dissipation member 42 is conductive and includes a plurality of pillars 42b (not shown) and a plate portion 42a provided between the plurality of pillars 42b.
  • the plate portion 42a of the heat dissipation member 42 has a rectangular shape in plan view as shown in FIG. 4, and is arranged so as to overlap with most of the plurality of semiconductor elements 6 in plan view. Specifically, except for the bonding areas with the plurality of electrical connection members 7 on the first main surfaces of the plurality of semiconductor elements 6, the plate portion 42a of the heat dissipation member 42 overlaps with the first main surfaces of the plurality of semiconductor elements 6 in plan view.
  • the heat dissipation member 42 is arranged so that the second main surface of the plate portion 42a faces the first main surface of the intermediate structure. Therefore, the plate portion 42a of the heat dissipation member 42 is arranged at a position spaced a distance in the +Z direction from the first main surfaces of the insulating circuit board 3 and the multiple semiconductor elements 6. In other words, the plate portion 42a of the heat dissipation member 42 is located on the first main surface side of the insulating circuit board 3 and the multiple semiconductor elements 6.
  • the multiple pillars 42b are provided in a manner that they stand upright on the first main surface of the metal base plate 1, similar to the multiple pillars 4b in embodiment 1. That is, the heat dissipation member 42 is provided on the first main surface of the metal base plate 1 in a manner that they straddle the intermediate structure, similar to the heat dissipation member 4 in embodiment 1.
  • the heat dissipation member 42 like the heat dissipation member 4 in the first embodiment, is provided away from the semiconductor elements 6 so that the sealing resin layer 8 between the heat dissipation member 42 and the semiconductor elements 6 does not cause dielectric breakdown when the semiconductor elements 6 are energized. Furthermore, the heat dissipation member 42 is electrically insulated from the semiconductor elements 6, like the heat dissipation member 4 in the first embodiment.
  • the semiconductor device 52 of the second embodiment most of the first main surface of each of the multiple semiconductor elements 6 faces the second main surface of the plate portion 42a. Therefore, by the first cooling operation that cools along a heat dissipation path including the heat dissipation member 42, the metal base plate 1, and the cooling mechanism 9, the heat generated from the multiple semiconductor elements 6 and propagated to the sealing resin layer 8 can be dissipated, and the temperature rise in the area of the sealing resin layer 8 close to the multiple semiconductor elements 6 can be minimized.
  • the semiconductor device 52 of the second embodiment can increase the reliability of the device without generating electrical losses during operation of the multiple semiconductor elements 6.
  • the semiconductor device 52 of the second embodiment can simplify the device configuration by performing the cooling operation of the double-sided cooling method described above using a single cooling mechanism 9.
  • the multiple semiconductor elements 6 generate heat when current is applied, which makes it easier for warping to occur in the warping areas of the metal base plate 1 that overlap the multiple semiconductor elements 6 in a plan view.
  • the second main surface of the plate portion 42a of the heat dissipation member 42 is provided over a relatively large area, overlapping most of the first main surfaces of each of the multiple semiconductor elements 6 in a plan view, and multiple column portions 42b are provided on the first main surface of the metal base plate 1, so that the warpage fluctuation in the warpage-occurring region of the metal base plate 1 can be suppressed mainly by the action of the column portions 42b.
  • the semiconductor device 52 of embodiment 2 can suppress warping of the metal base plate 1, which is a cause of warping of the entire device, and can prevent interfacial peeling between the sealing resin layer 8 and the metal base plate 1 due to fluctuations in warping of the metal base plate 1, thereby further improving the reliability of the device.
  • the second main surface of the plate portion 42a of the heat dissipation member 42 overlaps in a plan view by at least half the total area of the first main surfaces of the multiple semiconductor elements 6.
  • the semiconductor device 52 of the second embodiment can be applied to a structure having at least one semiconductor element 6, similar to the first embodiment.
  • ⁇ Third embodiment> 5 is a cross-sectional view showing a cross-sectional structure of a semiconductor device 53 according to a third embodiment of the present disclosure.
  • An XYZ orthogonal coordinate system is shown in Fig. 5.
  • Fig. 5 corresponds to the A-A cross section of the semiconductor device 51 shown in Fig. 1.
  • the semiconductor device 53 of the third embodiment has a structure in which the heat dissipation member 4 is replaced with a heat dissipation member 43.
  • the heat dissipation member 43 is conductive and includes a plurality of pillars 43b (not shown) and a plate portion 43a provided between the plurality of pillars 43b.
  • the shape of the heat dissipation member 43 is substantially the same as the heat dissipation member 4 of the first embodiment, with the plurality of pillars 43b corresponding to the plurality of pillars 4b and the plate portion 43a corresponding to the plate portion 4a.
  • the heat dissipation member 43 is provided away from the multiple semiconductor elements 6 so that the sealing resin layer 8 between the heat dissipation member 43 and the multiple semiconductor elements 6 does not cause dielectric breakdown when the multiple semiconductor elements 6 are energized. Furthermore, like the heat dissipation member 4 in the first embodiment, the heat dissipation member 43 is electrically insulated from the multiple semiconductor elements 6.
  • the semiconductor device 53 uses a variety of components, such as multiple semiconductor elements 6, multiple electrical connection members 7, an insulating circuit board 3, and a metal base plate 1, each of which has a different thermal expansion coefficient.
  • the multiple electrical connection members 7 are made of a first material having electrical conductivity and are electrically connected to the multiple semiconductor elements 6.
  • the constituent material of the heat dissipation member 43 is matched to the material used in the semiconductor device 53, thereby reducing the mismatch in the thermal expansion coefficient within the semiconductor device 53.
  • the material constituting the heat dissipation member 43 is also the first material, which is aluminum or copper.
  • the sealing resin layer 8 can be cooled efficiently.
  • the semiconductor device 53 of the third embodiment is characterized in that the constituent material of the heat dissipation member 43 is the same first material as the electrical connection member 7, which is made of a first material having electrical conductivity.
  • the first material includes the above-mentioned aluminum, copper, etc.
  • the heat dissipation member 43 like the heat dissipation member 4 in the first embodiment, is provided away from the semiconductor elements 6 so that the sealing resin layer 8 between the heat dissipation member 43 and the semiconductor elements 6 does not cause dielectric breakdown when the semiconductor elements 6 are energized. Furthermore, the heat dissipation member 43 is electrically insulated from the semiconductor elements 6, like the heat dissipation member 4 in the first embodiment.
  • the semiconductor device 53 of the third embodiment can increase the reliability of the device without generating electrical losses during operation of the multiple semiconductor elements 6.
  • the semiconductor device 53 of the third embodiment can simplify the device configuration by performing the cooling operation of the double-sided cooling method described above using a single cooling mechanism 9.
  • the constituent material of the electrical connection members 7, which are electrical connection members, and the constituent material of the heat dissipation members 43 are both the same first material, so that each of the multiple electrical connection members 7 and the heat dissipation members 43 have the same thermal expansion coefficient.
  • the semiconductor device 53 of the third embodiment can reduce the difference in thermal expansion coefficient between the multiple electrical connection members 7 and the heat dissipation member 43 in the sealing resin layer 8 to "0". Therefore, the semiconductor device 53 of the third embodiment can increase the heat dissipation effect of the heat dissipation member 43 and efficiently cool the sealing resin layer 8 without being affected by the difference in thermal expansion coefficient in the sealing resin layer 8 between the multiple electrical connection members 7 and the heat dissipation member 43.
  • the semiconductor device 53 of the third embodiment can be applied to a structure having at least one semiconductor element 6, similar to the first and second embodiments.
  • Fig. 6 is a plan view showing the top surface structure of a semiconductor device 54 according to a fourth embodiment of the present disclosure.
  • Fig. 7 is a cross-sectional view showing the CC cross-sectional structure of the semiconductor device 54 according to the fourth embodiment shown in Fig. 6.
  • Fig. 8 is a cross-sectional view showing the D-D cross-sectional structure of the semiconductor device 54 according to the fourth embodiment shown in Fig. 6.
  • An XYZ orthogonal coordinate system is depicted in each of Figs. 6 to 8. Note that Fig. 6 omits the illustration of the heat dissipation member 4 and the sealing resin layer 8 in order to clearly show the internal structure of the semiconductor device 54.
  • the semiconductor device 54 of the fourth embodiment is newly equipped with a metal lead wiring member 12 and a conductive bonding material 14, and has a structure in which the heat dissipation member 4 is replaced with a heat dissipation member 44.
  • the heat dissipation member 44 is conductive and includes a plurality of pillars 44b (not shown) and a plate portion 44a provided between the plurality of pillars 44b.
  • the plate portion 44a of the heat dissipation member 44 has a rectangular shape in a plan view, and has a relatively wide heat dissipation member forming region R44, as shown in FIG. 7.
  • the semiconductor device 54 of the fourth embodiment further includes a metal lead wiring member 12 and a plurality of conductive bonding materials 14 between the intermediate structure and the heat dissipation member 44.
  • the semiconductor device 54 of the fourth embodiment includes, as the electrical connection member 7, a plurality of wires 13 that serve as linear connection members and a metal lead wiring member 12 that serves as a plate-shaped connection member.
  • the multiple conductive bonding materials 14 correspond to the multiple semiconductor elements 6, and the second main surface of the metal lead wiring member 12 is electrically connected to the multiple semiconductor elements 6 via the multiple conductive bonding materials 14.
  • the metal lead wiring member 12 is bonded to the multiple semiconductor elements 6 by the multiple conductive bonding materials 14.
  • the conductive bonding materials 14 are made of solder, soft solder, etc.
  • the metal lead wiring member 12 which is a plate-shaped connecting member, has a plate portion 12a that is rectangular in plan view, and as shown in FIG. 6, a connection portion 12b that extends in the -Y direction from a part of the -Y direction side of the plate portion 12a when viewed in plan in the XY plane.
  • the plate portion 12a is the main portion of the metal lead wiring member 12.
  • the metal lead wiring member 12 is a plate-shaped connecting member whose main portion is configured in a plate shape.
  • connection portion 12b extends in the -Z direction, and the lower end of the connection portion 12b is provided on the first main surface of the circuit pattern 5 of the insulating circuit board 3. Therefore, the metal lead wiring member 12 is electrically connected to the circuit pattern 5 via the connection portion 12b. Furthermore, the first main surface of the plate portion 12a and the intermediate connection member 21 are electrically connected via the wire 13, and the first main surface of the semiconductor element 6 and the intermediate connection member 21 are connected via the wire 13.
  • the metal lead wiring member 12, together with the multiple wires 13, the multiple semiconductor elements 6, and the circuit pattern 5 of the insulating circuit board 3, constitutes a main current circuit.
  • the area of the plate portion 12a that passes current between the multiple semiconductor elements 6 via the multiple conductive bonding materials 14 becomes the main wiring area R12, and it is expected that a relatively large current will flow in the main wiring area R12.
  • the area of the first main surface of the metal lead wiring member 12 that overlaps or is close to any of the multiple conductive bonding materials 14 in a plan view is the wire bonding area. At least one point in the wire bonding area is electrically connected to the intermediate connection member 21 via the wire 13.
  • the intermediate connection member 21 is electrically connected to the external electrode 11 via the embedded connection wire 22. Therefore, the wire bonding region of the metal lead wiring member 12 is electrically connected to the external electrode 11 via the wire 13, the intermediate connection member 21, and the embedded connection wire 22.
  • the external electrode 11, intermediate connection member 21, and embedded connection wire 22 are shown as separate components, but a metal plate that serves as the external electrode 11, intermediate connection member 21, and embedded connection wire 22 may be insert molded into the resin case 2.
  • the electrical connection between the metal lead wiring member 12 and the external electrode 11 is not limited to the configurations shown in Figures 6 to 8.
  • the following first to third connection configurations are possible.
  • the first connection mode is a mode in which the wire bonding area of the metal lead wiring member 12 and the external electrode 11 are directly connected by a wire.
  • the second connection mode is a mode in which a conductive bonding material such as solder or soft solder is used instead of the wire 13, and the wire bonding region of the metal lead wiring member 12 and the intermediate connection member 21 are electrically connected by the conductive bonding material.
  • a conductive bonding material such as solder or soft solder
  • the third connection mode is a mode in which the plate portion 12a is extended along the +X direction toward the side wall of the metal lead wiring member 12, and the plate portion 12a is brought into contact with the embedded connection wire 22 provided in the side wall of the resin case 2, thereby integrating the external electrode 11 and the embedded connection wire 22 provided on the +X direction side with the plate portion 12a.
  • a structure including an insulating circuit board 3, a plurality of semiconductor elements 6, a plurality of conductive bonding materials 10, a metal lead wiring member 12, and a plurality of conductive bonding materials 14 may be referred to as an "extended intermediate structure.”
  • the heat dissipation member 44 is arranged so that the second main surface of the plate portion 44a faces the first main surface of the extended intermediate structure. Therefore, the plate portion 44a of the heat dissipation member 44 is arranged at a distance from the first main surfaces of the metal lead wiring member 12, the insulating circuit board 3, and the multiple semiconductor elements 6.
  • the heat dissipation member 44 is provided in a manner such that multiple pillars 44b are erected on the first main surface of the metal base plate 1, similar to the heat dissipation member 4 of the first embodiment. In other words, the heat dissipation member 44 is provided on the first main surface of the metal base plate 1 in a manner that spans the extended intermediate structure.
  • the heat dissipation member 44 is provided away from the metal lead wiring member 12 and the semiconductor elements 6 so that the sealing resin layer 8 between the heat dissipation member 44 and the semiconductor elements 6 does not cause dielectric breakdown when the semiconductor elements 6 are energized. Furthermore, the heat dissipation member 44 is electrically insulated from the metal lead wiring member 12 and the semiconductor elements 6.
  • the heat dissipation member forming region R44 of the heat dissipation member 44 is disposed to include the main wiring region R12 of the metal lead wiring member 12 in plan view.
  • the heat dissipation member forming region R44 is wider than the main wiring region R12 and includes the entire main wiring region R12 in plan view.
  • the bonding area between the first main surface of the plate portion 12a and the first main surface of the multiple semiconductor elements 6 formed by the multiple conductive bonding materials 14 is larger than that of a wiring structure using linear connecting members such as wires, and therefore a large amount of heat is propagated when the multiple semiconductor elements 6 are energized.
  • the volume of the metal lead wiring member 12, which is a plate-shaped connecting member, is larger than the volume of linear connecting members such as the wire 13, and therefore the amount of thermal expansion is large. Therefore, when the interface between the end of the metal lead wiring member 12 and the sealing resin layer 8 peels off, cracks are likely to occur in the sealing resin layer 8 starting from the peeled area.
  • the thermal expansion of the sealing resin layer 8 is suppressed by cooling the sealing resin layer 8 through a heat dissipation path including the heat dissipation member 44, thereby suppressing the thermal expansion of the metal lead wiring member 12 and preventing peeling between the end of the metal lead wiring member 12 and the sealing resin layer 8, thereby maintaining the reliability of the device at a high level.
  • the heat dissipation member forming region R44 of the plate portion 44a includes the main wiring region R12 of the metal lead wiring member 12, and since the heat dissipation member forming region R44 is wider than the main wiring region R12, the thermal expansion of the metal lead wiring member 12 can be effectively suppressed.
  • the heat dissipation member forming region R44 is set in a positional relationship that includes the main wiring region R12 of the metal lead wiring member 12 in a planar view. Therefore, by the first cooling operation that cools through a heat dissipation path including the heat dissipation member 44, the metal base plate 1, and the cooling mechanism 9, the heat generated from the multiple semiconductor elements 6 and the metal lead wiring member 12 and propagated to the sealing resin layer 8 can be dissipated, and the temperature rise in the region of the sealing resin layer 8 close to the multiple semiconductor elements 6 and the metal lead wiring member 12 can be minimized.
  • the semiconductor device 54 of the fourth embodiment can increase the reliability of the device without generating electrical losses during operation of the multiple semiconductor elements 6.
  • the semiconductor device 54 of the fourth embodiment can simplify the device configuration by performing the cooling operation of the double-sided cooling method described above using a single cooling mechanism 9.
  • the metal lead wiring member 12 which is a plate-shaped connecting member, has the plate portion 12a as its main portion, a relatively large current can flow in the main wiring region R12 of the plate portion 12a when the multiple semiconductor elements 6 are energized.
  • the semiconductor device 54 of the fourth embodiment can pass a relatively large current.
  • the semiconductor device 54 of the fourth embodiment a relatively large current flows through the main wiring region R12, making it easier for peeling to occur starting from the interface between the plate portion 12a of the metal lead wiring member 12 and the sealing resin layer 8.
  • a relatively large current flows through the main wiring region R12, making it easier for peeling to occur starting from the interface between the plate portion 12a of the metal lead wiring member 12 and the sealing resin layer 8.
  • the plate portion 44a of the heat dissipation member 44 overlaps with the plate portion 12a of the metal lead wiring member 12 in a plan view, so that the metal lead wiring member 12 can be cooled by the first cooling operation that cools the heat dissipation path including the heat dissipation member 44, thereby suppressing the above-mentioned peeling phenomenon.
  • the plate portion 44a of the heat dissipation member 44 in embodiment 4 includes the main wiring region R12 of the metal lead wiring member 12 in plan view, so that the metal lead wiring member 12 can be cooled more effectively.
  • the semiconductor device 54 of the fourth embodiment can reliably avoid malfunctions in the multiple semiconductor elements 6 and improve the reliability of the device through which a relatively large current flows.
  • the semiconductor device 54 of the fourth embodiment can achieve a large current and a long life.
  • the metal lead wiring member 12 which is a plate-shaped connecting member, includes the main wiring region R12, a relatively large current flows through the main wiring region R12 when the multiple semiconductor elements 6 are energized, resulting in a large amount of heat generation.
  • the plate portion 44a of the heat dissipation member 44 in the fourth embodiment is positioned to include the main wiring region R12 in the metal lead wiring member 12 in a plan view, so that the main wiring region R12 can be effectively cooled by the first cooling operation that cools the heat dissipation path that includes the plate portion 44a.
  • the semiconductor device 54 of the fourth embodiment can reliably avoid problems associated with heat generation in the main wiring region R12, and improve the reliability of the semiconductor device 54, which passes a relatively large current.
  • the semiconductor device 54 of embodiment 4 can be applied to a structure having at least one semiconductor element 6, similar to embodiments 1 to 3.
  • Fig. 9 is a cross-sectional view showing a cross-sectional structure of a semiconductor device 55 according to a fifth embodiment of the present disclosure.
  • An XYZ orthogonal coordinate system is shown in Fig. 9.
  • Fig. 9 corresponds to the A-A cross section of the semiconductor device 51 shown in Fig. 1.
  • the semiconductor device 55 of the fifth embodiment is characterized in that it uses a plurality of wires 13, which are a plurality of linear connection members, as the electrical connection members 7 for the plurality of semiconductor elements 6.
  • the plurality of wires 13 are generally made of a metal material with low electrical resistance, such as aluminum or copper.
  • the multiple wires 13, which are multiple linear connection members, include a main wire 13m that electrically connects between the multiple semiconductor elements 6. This main wire 13m serves as the main current wiring member.
  • the multiple wires 13 it is expected that a relatively large current will flow through the main wire 13m, which functions as a main current wiring member that passes current between the multiple semiconductor elements 6.
  • both ends of each of the multiple wires 13, including the main wire 13m, are bonded to the object to be bonded by ultrasonic wire bonding, which is an ultrasonic bonding process.
  • the object to be bonded is the first main surface of either the intermediate connection member 21 or one of the multiple semiconductor elements 6. In this way, both ends of the multiple wires 13 are bonded to the object to be bonded as bonding ends by ultrasonic bonding.
  • the manufacturing method of the semiconductor device 55 of the fifth embodiment includes the following steps (a) and (b) as part of it.
  • Step (a) is a step of placing an intermediate structure including an insulating circuit board 3 and a plurality of semiconductor elements 6 on the first main surface of the metal base plate 1.
  • Step (b) is a step of performing an ultrasonic bonding process to bond both ends of each of the multiple wires 13 to a bonding object.
  • the bonding object includes a first main surface of any of the multiple semiconductor elements 6 or a first main surface of the multiple intermediate connection members 21. Therefore, step (b) includes a step of performing an ultrasonic bonding process to bond one end of each of the multiple wires 13 to any of the multiple semiconductor elements 6.
  • ultrasonic bonding is performed to bond one end of the main wire 13m to a first main surface of one of the multiple semiconductor elements 6, and the other end of the main wire 13m to a first main surface of the other of the multiple semiconductor elements 6. In this case, both ends of the main wire 13m become bonding ends.
  • the above step (a) is performed by an existing manufacturing process, and the above step (b) is performed by performing an ultrasonic wire bonding process, and the ends of each of the multiple wires 13 that have been subjected to the ultrasonic bonding process in the above step (b) become bonding ends.
  • the structure including the insulating circuit board 3, the multiple semiconductor elements 6, and the multiple wires 13 may be referred to as the "extended intermediate structure.”
  • the heat dissipation member 45 is positioned so that the plate portion 45a overlaps most of the semiconductor elements 6 in a plan view.
  • the heat dissipation member 45 is arranged so that the second main surface of the plate portion 45a of the heat dissipation member 45 faces the first main surface of the extended intermediate structure. Therefore, the plate portion 45a of the heat dissipation member 45 is arranged at a distance from the first main surfaces of the insulating circuit board 3 and the multiple semiconductor elements 6.
  • the heat dissipation member 45 is provided in a manner in which a plurality of pillars 45b are erected on the first main surface of the metal base plate 1, similar to the heat dissipation member 4 of the first embodiment. In other words, the heat dissipation member 45 is provided on the first main surface of the metal base plate 1 in a manner in which it straddles the extended intermediate structure.
  • the heat dissipation member 45 in the semiconductor device 55 of the fifth embodiment is provided away from the main wires 13m and the multiple semiconductor elements 6 so that the sealing resin layer 8 between the heat dissipation member 45 and the multiple semiconductor elements 6 does not cause dielectric breakdown when the multiple semiconductor elements 6 are energized. Furthermore, the heat dissipation member 45 is electrically insulated from the main wires 13m and the multiple semiconductor elements 6.
  • the heat dissipation member forming region R45 in the center of the heat dissipation member 45 is positioned to include the main wire 13m in a planar view.
  • the main wire 13m is present within the heat dissipation member forming region R45 in a planar view.
  • a relatively large current flows through the main wires 13m that electrically connect the multiple semiconductor elements 6 when the multiple semiconductor elements 6 are energized.
  • the semiconductor element 6 may be damaged, resulting in a decrease in the reliability of the device.
  • the heat dissipation member forming region R45 is set to include the main wire 13m in a plan view.
  • heat generated during electrical conduction through the semiconductor elements 6 and main wires 13m is propagated throughout the entire semiconductor device 55 via the sealing resin layer 8.
  • the heat generated from the semiconductor elements 6 and main wires 13m and propagated to the sealing resin layer 8 is dissipated by the first cooling operation via a heat dissipation path including the heat dissipation member 45, the metal base plate 1, and the cooling mechanism 9, so that the temperature rise in the area of the sealing resin layer 8 close to the semiconductor elements 6 and main wires 13m can be minimized.
  • the semiconductor device 55 of the fifth embodiment can increase the reliability of the device without generating electrical losses during operation of the multiple semiconductor elements 6.
  • the semiconductor device 55 of the fifth embodiment can simplify the device configuration by performing the cooling operation of the double-sided cooling method using a single cooling mechanism 9.
  • the joint ends of the multiple wires 13, which are multiple linear connection members, may become disconnected and electrically disconnected from the multiple semiconductor elements 6 due to thermal expansion of the sealing resin layer 8.
  • the sealing resin layer 8 thermally expands, the difference in the thermal expansion coefficient between the semiconductor element 6 and the sealing resin layer 8 may cause stress to be applied to the joints between the semiconductor element 6 and the multiple wires 13, which may result in breakage of the wires 13.
  • the semiconductor device 55 of the fifth embodiment can improve the reliability of the semiconductor device by cooling the heat accumulated in the sealing resin layer 8 through a first cooling operation using a heat dissipation path including the plate portion 45a of the heat dissipation member 45, thereby preventing any of the multiple wires 13 from becoming disconnected.
  • the semiconductor device 55 of the fifth embodiment cools the heat accumulated in the sealing resin layer 8 due to the presence of the heat dissipation member 45 provided inside the sealing resin layer 8, thereby suppressing the expansion of the sealing resin layer 8 and preventing breakage of the wire 13.
  • the semiconductor device 55 of the fifth embodiment uses multiple wires 13 as electrical connection members, allowing for a high degree of freedom in wiring. Therefore, flexible circuit design can be implemented for the semiconductor device 55.
  • the multiple wires 13 include a main wire 13m that serves as the main current wiring member, so that a relatively large current flows through the main wire 13m when the multiple semiconductor elements 6 are energized, resulting in a large amount of heat generation.
  • the heat dissipation member forming region R45 in the plate portion 45a of the heat dissipation member 45 is arranged to include the main wire 13m in a plan view. Therefore, the main wire 13m can be effectively cooled by the first cooling operation through the heat dissipation path including the column portion 45b.
  • the semiconductor device 55 of the fifth embodiment can reliably avoid defects associated with heat generation in the main wire 13m and improve the reliability of a device that passes a relatively large current through the main wire 13m.
  • the semiconductor device 55 of the fifth embodiment which is manufactured by a manufacturing method including the above-mentioned steps (a) and (b), can ensure a highly stable electrical connection state with any of the multiple semiconductor elements 6 at the joint ends of each of the multiple wires 13, which are multiple linear connection members, by the above-mentioned step (b).
  • each of the multiple wires 13 is joined to one of the multiple semiconductor elements 6 in units of single wiring, but they may also be joined to one of the multiple semiconductor elements 6 in units of multiple wiring. Also, when joining in units of multiple wiring, they may be joined using ribbon-shaped wiring in which multiple wirings are arranged.
  • the semiconductor device 55 of the fifth embodiment can be applied to a structure having at least one semiconductor element 6, similar to the first to fourth embodiments.
  • Fig. 10 is a cross-sectional view showing a cross-sectional structure of a semiconductor device 56 according to a sixth embodiment of the present disclosure.
  • An XYZ orthogonal coordinate system is shown in Fig. 10.
  • Fig. 10 corresponds to the A-A cross section of the semiconductor device 51 shown in Fig. 1.
  • the semiconductor device 56 of the sixth embodiment has a structure in which the multiple semiconductor elements 6 are replaced with multiple SiC semiconductor elements 60.
  • each of the multiple SiC semiconductor elements 60 is a semiconductor element made of SiC (silicon carbide), and generates a greater amount of heat when energized compared to semiconductor elements made of Si. For this reason, the operating temperature of the multiple SiC semiconductor elements 60 increases to a greater extent than the operating temperature of the multiple semiconductor elements 6.
  • the heat dissipation member 4 is provided away from the multiple SiC semiconductor elements 60 so that the sealing resin layer 8 between the heat dissipation member 4 and the multiple SiC semiconductor elements 60 does not cause dielectric breakdown when the multiple SiC semiconductor elements 60 are energized. Furthermore, the heat dissipation member 4 is electrically insulated from the multiple SiC semiconductor elements 60.
  • the semiconductor device 56 of the sixth embodiment can increase the reliability of the device without generating electrical losses during the energization of the multiple SiC semiconductor elements 60.
  • the semiconductor device 56 of the sixth embodiment has multiple SiC semiconductor elements 60, and therefore has the basic SiC operating characteristics of being able to pass a relatively large current, operating at high frequencies, operating in high temperature environments, having high insulation properties, and having a low off-state voltage.
  • the semiconductor device 56 of the sixth embodiment can simplify the device configuration by performing the cooling operation of the double-sided cooling method described above using a single cooling mechanism 9.
  • the SiC semiconductor elements 60 generate a relatively large amount of heat when they are energized, causing the operating temperature to rise. This increases the effect of thermal stress caused by differences in the thermal expansion coefficients between the components of the semiconductor device 56, which reduces the reliability of the device.
  • the semiconductor device 56 of the sixth embodiment has a heat dissipation function that dissipates heat accumulated in the sealing resin layer 8 during the operation of the multiple SiC semiconductor elements 60 through a heat dissipation path including the heat dissipation member 4 and the metal base plate 1, and therefore can suppress thermal expansion of the sealing resin layer 8.
  • the semiconductor device 56 of the sixth embodiment can minimize the effects of thermal stress caused by differences in thermal expansion coefficients between the components of the semiconductor device 56, thereby improving the reliability of the device having the above-mentioned SiC operating characteristics.
  • the semiconductor device 56 of the sixth embodiment can be applied to a structure having at least one SiC semiconductor element 60, similar to the first to fifth embodiments.

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
PCT/JP2023/009053 2023-03-09 2023-03-09 半導体装置及びその製造方法 Ceased WO2024185127A1 (ja)

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JP2025505031A JP7778271B2 (ja) 2023-03-09 2023-03-09 半導体装置及びその製造方法
DE112023005941.1T DE112023005941T5 (de) 2023-03-09 2023-03-09 Halbleitervorrichtung und Fertigungsverfahren dafür
PCT/JP2023/009053 WO2024185127A1 (ja) 2023-03-09 2023-03-09 半導体装置及びその製造方法
CN202380095365.4A CN120814047A (zh) 2023-03-09 2023-03-09 半导体装置及其制造方法

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JP2004327555A (ja) * 2003-04-22 2004-11-18 Matsushita Electric Works Ltd 半導体装置
JP2008042041A (ja) * 2006-08-09 2008-02-21 Fuji Electric Holdings Co Ltd 半導体装置
JP2012009726A (ja) * 2010-06-28 2012-01-12 Fujitsu Semiconductor Ltd 半導体装置
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