WO2024176947A1 - 半導体装置、電力変換装置および半導体装置の製造方法 - Google Patents

半導体装置、電力変換装置および半導体装置の製造方法 Download PDF

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WO2024176947A1
WO2024176947A1 PCT/JP2024/005317 JP2024005317W WO2024176947A1 WO 2024176947 A1 WO2024176947 A1 WO 2024176947A1 JP 2024005317 W JP2024005317 W JP 2024005317W WO 2024176947 A1 WO2024176947 A1 WO 2024176947A1
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Prior art keywords
solder
semiconductor device
bisn
circuit element
manufacturing
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English (en)
French (fr)
Japanese (ja)
Inventor
純司 藤野
稔 江草
智香 川添
裕基 滝下
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N

Definitions

  • This disclosure relates to a semiconductor device manufactured using solder bonding and a method for manufacturing the same.
  • semiconductor devices that use SiC semiconductors as their material have a high operating temperature and are highly efficient, so they are likely to become mainstream in the future. For this reason, semiconductor devices are also required to be packaged in a form that is compatible with SiC semiconductors.
  • solder the bottom surface of the semiconductor device In order to ensure the heat dissipation of a semiconductor device, it may be necessary to solder the bottom surface of the semiconductor device to the base plate. In particular, in the case of transfer mold type semiconductor devices, there is a concern that if the internally mounted solder of the semiconductor device remelts when soldering the semiconductor device to the base plate, its volume will expand and the internally mounted solder may leak from the gaps in the sealing resin. For this reason, the soldering between the semiconductor device and the base plate must basically be performed at a process temperature below the melting point of the internally mounted solder.
  • Patent Document 1 discloses a technology for necking (connecting) the liquid phase of BiSn solder to a Cu core material. With this technology, it is expected that the diffusion of Cu into the BiSn solder will increase the melting point of the solder and improve heat resistance. However, the technology in Patent Document 1 is related to materials that fill through holes, and does not take into account the problems of BiSn solder's low heat resistance and brittleness.
  • This disclosure has been made to solve the problems described above, and aims to ensure the heat resistance and reliability of solder joints while reducing the temperature of the bonding process in the manufacture of semiconductor devices.
  • the method for manufacturing a semiconductor device includes: (a) stacking a first solder and a second solder having a melting point higher than that of the first solder between a first circuit element and a second circuit element; and (b) heating the first solder and the second solder to a temperature between the melting points of the first solder and the second solder to solder the first circuit element and the second circuit element, whereby in the step (b), a part of the second solder diffuses into the liquid phase of the first solder, forming a solder joint layer in which the second solder partially remains.
  • the semiconductor device comprises a first circuit element, a second circuit element, and a solder joint layer that joins the first circuit element and the second circuit element and includes a layer in which a second solder having a higher melting point than the first solder is diffused into the first solder, and a layer made of the second solder.
  • 3A to 3C are conceptual diagrams showing a bonding process of a semiconductor element in the manufacturing method of the semiconductor device according to the first embodiment.
  • 3A to 3C are conceptual diagrams showing a bonding process of a semiconductor element in the manufacturing method of the semiconductor device according to the first embodiment.
  • 3A to 3C are conceptual diagrams showing a bonding process of a semiconductor element in the manufacturing method of the semiconductor device according to the first embodiment.
  • FIG. 2 is a Bi—Sn equilibrium diagram.
  • 10A to 10C are conceptual diagrams showing a modified example of the method for manufacturing the semiconductor device according to the first embodiment.
  • 11A to 11C are conceptual diagrams showing a bonding process of a semiconductor element in a manufacturing method of a semiconductor device according to a second embodiment.
  • 11A to 11C are conceptual diagrams showing a bonding process of a semiconductor element in a manufacturing method of a semiconductor device according to a second embodiment.
  • 11A to 11C are conceptual diagrams showing a bonding process of a semiconductor element in a manufacturing method of a semiconductor device according to a second embodiment.
  • 11A to 11C are conceptual diagrams showing a bonding process of a semiconductor element in a manufacturing method of a semiconductor device according to a second embodiment.
  • 13A to 13C are conceptual diagrams showing a bonding process of a semiconductor element in a manufacturing method of a semiconductor device according to a third embodiment.
  • 13A to 13C are conceptual diagrams showing a bonding process of a semiconductor element in a manufacturing method of a semiconductor device according to a third embodiment.
  • 13A to 13C are conceptual diagrams showing a bonding process of a semiconductor element in a manufacturing method of a semiconductor device according to a third embodiment.
  • 13A to 13C are conceptual diagrams showing a bonding process of a semiconductor element in a manufacturing method of a semiconductor device according to a third embodiment.
  • 13A to 13C are conceptual diagrams showing a bonding process of a semiconductor element in a manufacturing method of a semiconductor device according to a third embodiment.
  • 13A to 13C are conceptual diagrams showing a bonding process of a semiconductor element in a manufacturing method of a semiconductor device according to a third embodiment.
  • 13 is a conceptual diagram showing a manufacturing method of a power module as a semiconductor device according to a fourth embodiment.
  • FIG. 13 is a conceptual diagram showing a manufacturing method of a power module as a semiconductor device according to a fourth embodiment.
  • FIG. 13 is a conceptual diagram showing a manufacturing method of a power module as a semiconductor device according to a fourth embodiment.
  • FIG. 13 is a conceptual diagram showing a manufacturing method of a power module as a semiconductor device according to a fourth embodiment.
  • FIG. 13 is a conceptual diagram showing a manufacturing method of a power module as a semiconductor device according to a fourth embodiment.
  • FIG. 13 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a fifth embodiment is applied.
  • FIG. 13 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a fifth embodiment is applied.
  • First embodiment> 1 to 5 are conceptual diagrams showing a bonding process of a semiconductor element in a manufacturing method of a semiconductor device according to embodiment 1. The bonding process will be described with reference to these drawings.
  • laminated solder 30 is placed between ceramic substrate 10 as a first circuit element and semiconductor element 20 as a second circuit element, and then laminated.
  • Laminated solder 30 is configured such that BiSn solder 31 as a first solder, which is a tin (Sn)-based solder containing bismuth (Bi), is provided on both sides of SnCu solder 32 as a second solder.
  • the ceramic substrate 10 is made of an aluminum nitride base material with Cu conductor layers formed on both sides and has a size of 25 mm x 25 mm.
  • the semiconductor element 20 is made of Si, has Ni/Au plating on the back side as soldering metallization, and has a size of 13 mm x 13 mm x 0.4 mm.
  • the laminated solder 30 is made of 13 mm x 13 mm x 0.176 mm.
  • the BiSn solder 31 has a composition ratio of 57 wt% Bi-43 wt% Sn, a melting point of 139°C, and a thickness of 0.012 mm.
  • the SnCu solder 32 has a composition ratio of 99.3 wt% Sn-0.7 wt% Cu, a melting point of 229°C, and a thickness of 0.21 mm.
  • the semiconductor element 20 may be made of a wide band gap semiconductor such as SiC, GaN, or diamond.
  • the semiconductor element 20, which uses a wide band gap semiconductor as the semiconductor material, is superior to semiconductor elements made of silicon in terms of operation at high voltages, large currents, and high temperatures.
  • the SnCu solder 32 is not limited to 99.3 wt% Sn-0.7 wt% Cu, which is a eutectic, and may contain trace amounts of additive elements such as Ag.
  • SnCu solder 32 with added Ag has a eutectic point (217°C) where the Ag concentration is around 3%. If the melting point of SnCu solder 32 drops too much, it becomes difficult to bond the SnCu solder 32 while leaving a layer of the solder remaining, so it is desirable to keep the concentration of Ag added to SnCu solder 32 below 1%.
  • BiSn solder 31 may also contain trace amounts of Ag, Sb, etc. However, if the amount of the additive element increases, flexibility is lost, so it is desirable to keep the concentration of the element added to BiSn solder 31 to 1% or less.
  • a hot plate is used to heat the laminated solder 30 to a temperature between the melting point of the BiSn eutectic solder 31 (139°C) and the melting point of the SnCu solder 32 (229°C), for example to 160°C.
  • the BiSn solder 31 on the front and back of the laminated solder 30 melts, and liquid phases 311 are generated between the ceramic substrate 10 and the laminated solder 30 and between the semiconductor element 20 and the laminated solder 30, respectively, and solder bonding is completed.
  • the SnCu solder 32 in the center of the laminated solder 30 gradually melts and diffuses into the liquid phase 311.
  • solder joint layer 33 made of an alloy with a nearly uniform composition is formed between the ceramic substrate 10 and the semiconductor element 20, as shown in Figure 3.
  • the final Bi composition ratio of the solder joint layer 33 is approximately 7 wt%.
  • the solder joint layer 33 which has a low Bi composition ratio in this way, has high heat resistance and strength, and can ensure the heat resistance and reliability of the solder joint.
  • FIG. 4 is an equilibrium diagram of Sn-Bi. From the equilibrium diagram in FIG. 4, it can be seen that the solder joint layer 33 with a Bi composition ratio of about 7 wt% has a liquidus temperature of about 220°C and a solidus temperature of about 200°C. In other words, in order to perform solder jointing using BiSn solder with a Bi composition ratio of 7 wt% from the beginning, the liquid phase will not occur unless it is heated to 200°C or higher.
  • the fluidity of the liquid phase of the solder cannot be ensured unless it is heated to a temperature about 20°C to 30°C higher than the liquidus temperature of the solder, so in order to perform solder jointing using BiSn solder with a Bi composition ratio of 7 wt% from the beginning, it is necessary to heat it to 235°C to 245°C.
  • the BiSn solder 31 of the laminated solder 30 exhibits sufficient fluidity at 160°C to 170°C, enabling good joining.
  • the ceramic substrate 10 and the semiconductor element 20 can be bonded even in the state shown in FIG. 2.
  • the composition of the solder bonding layer 33 will not be uniform, but it is believed that no major problems will occur in terms of the strength, thermal conductivity, electrical conductivity, etc. of the joint.
  • the bonding temperature in the bonding process of this embodiment is 180°C
  • the Bi composition ratio of the liquid phase 311 is thought to be about 12 wt% due to isothermal solidification, but the bonding strength and elastic modulus of this part are about twice as high as those of the SnCu solder 32. Therefore, if a solder bonding layer 33 with an uneven composition (as shown in FIG.
  • the Bi composition ratio of the BiSn solder 31 provided on the front and back of the laminated solder 30 may be 10 wt% or more, but is preferably 21 wt% or more and 57 wt% or less, at which the solidus temperature is 139°C. Even if the Bi composition ratio of the BiSn solder 31 is lower than 57 wt%, it can generate a liquid phase at a low temperature of about 170°C. By keeping the Bi composition ratio of the BiSn solder 31 to the minimum necessary, the amount of scarce Bi used can be reduced.
  • the SnCu solder 32 provided in the center of the laminated solder 30 may be replaced with another solder material with a higher melting point than the BiSn solder 31, for example, SnAgCu solder with a composition ratio of 96.5Sn-3Ag-0.5Cu. When SnAgCu solder is used, it is expected that the melting point of the joining process can be lowered.
  • the laminated solder 30 may be a clad material formed by cold rolling, or may be a laminate in which BiSn solder 31 is plated onto a core material SnCu solder 32, or a laminate in which BiSn solder 31 is solder-wetted onto a core material SnCu solder 32.
  • a solder paste 312 cream solder
  • BiSn solder may be supplied to both sides of the SnCu solder 32 to form a laminated solder 30.
  • flux When heating with a hot plate, flux may be used to improve the wettability of the solder. It is also effective to use a reduction reflow oven that uses formic acid.
  • ⁇ Embodiment 2> 6 to 9 are conceptual diagrams showing a bonding process of a semiconductor element in a manufacturing method of a semiconductor device according to the second embodiment. The bonding process will be described with reference to these drawings.
  • BiSn solder 31 is placed between the semiconductor element 20, which has SnCu solder 32 applied to its backside, and the ceramic substrate 10, and then they are stacked together.
  • the semiconductor element 20 is made of Si, has Ni/Au plating on the back surface as a soldering metallization, and is 13 mm x 13 mm x 0.4 mm in size.
  • the thickness of the SnCu solder 32 is 0.176 mm, and the thickness of the BiSn solder 31 is 0.024 mm.
  • a hot plate is used to heat to a temperature between the melting point of the BiSn eutectic solder 31 (139°C) and the melting point of the SnCu solder 32 (229°C), for example to 160°C. Then, as shown in FIG. 7, the BiSn solder 31 melts, and a liquid phase 311 is generated between the ceramic substrate 10 and the SnCu solder 32, forming a solder joint. At this time, the SnCu solder 32 on the back surface of the semiconductor element 20 gradually melts and diffuses into the liquid phase 311.
  • solder joint layer 33 made of an alloy with a nearly uniform composition is formed between the ceramic substrate 10 and the semiconductor element 20, as shown in Figure 8.
  • the final Bi composition ratio of the solder joint layer 33 is approximately 7 wt%, and similarly to embodiment 1, the heat resistance and reliability of the solder joint can be ensured.
  • two liquid phases 311 are generated by two layers of BiSn solder 31, but in the second embodiment, one liquid phase 311 is generated by one layer of BiSn solder 31. Therefore, the thickness of one BiSn solder 31 is set to 0.024 mm, which is twice that of the first embodiment (0.012 mm).
  • each BiSn solder 31 Increasing the thickness of each BiSn solder 31 and increasing the amount of liquid phase 311 generated makes it possible to accommodate warping and surface irregularities of the semiconductor element 20 and ceramic substrate 10, improving bonding properties.
  • the thickness of the BiSn solder 31 is too large, the Bi composition ratio of the final solder bonding layer 33 will be high, lowering the solidus temperature and making it difficult to ensure heat resistance.
  • SnCu solder 32 is supplied in advance to the rear surface of the semiconductor element 20, even if voids occur, they will occur at a position far away from the semiconductor element 20, which is the heat source, by the thickness of the SnCu solder 32, and deterioration of heat dissipation due to voids is suppressed.
  • SnCu solder 32 has a lower tensile strength and greater elongation than BiSn solder 31, and therefore has superior reliability, including temperature cycle resistance. Therefore, by arranging SnCu solder 32 at the interface with the brittle semiconductor element 20, as in embodiment 2, the reliability of the solder joint of the semiconductor element 20 is improved.
  • the composition of the solder bonding layer 33 will not be uniform, but it is believed that no major problems will arise in terms of the strength, thermal conductivity, electrical conductivity, etc. of the bonded portion.
  • the bonding temperature in the bonding process of this embodiment is 180°C
  • the Bi composition ratio of the liquid phase 311 is thought to be about 12 wt% due to isothermal solidification, but fatigue-related changes such as cracks and peeling will occur in the SnCu solder 32 portion, so it is believed that reliability equivalent to that of SnCu solder can be obtained.
  • BiSn solder paste 312 cream solder
  • BiSn solder paste 312 cream solder
  • ⁇ Third embodiment> 10 to 15 are conceptual diagrams showing a bonding process of a semiconductor element in a manufacturing method of a semiconductor device according to embodiment 3. The bonding process will be described with reference to these drawings.
  • a mixed solder paste 331 is applied to the upper surface of the ceramic substrate 10, and the semiconductor element 20 is placed on top of the mixed solder paste 331. This is heated with a hot plate to melt the mixed solder paste 331, and as shown in FIG. 11, a solder bonding layer 33 is formed to perform solder bonding.
  • the mixed solder paste 331 is a dispersion of BiSn solder particles 313 and SnCu solder particles 323 in a solvent 330.
  • the ratio of the BiSn solder particles 313 to the SnCu solder particles 323 in the mixed solder paste 331 is 12:88.
  • this mixed solder paste 331 is heated to 160°C, as shown in Figure 13, the solvent 330 evaporates and the BiSn solder particles 313, which have a melting point of 139°C, melt to generate a liquid phase 311 of BiSn solder, thereby forming a solder joint between the semiconductor element 20 and the ceramic substrate 10.
  • the SnCu solder particles 323 diffuse into the liquid phase 311 of BiSn solder, forming a solder joint layer 33 with a high Bi concentration. This portion then gradually expands, and as shown in Figure 15, a uniform solder joint layer 33 is formed overall.
  • the final Bi composition ratio of the solder joint layer 33 is about 7 wt%, and similarly to embodiment 1, the heat resistance and reliability of the solder joint can be ensured.
  • the SnCu solder is supplied in a particulate state (SnCu solder particles 323), the contact area of the BiSn solder with the liquid phase 311 is increased, and the diffusion of the liquid phase 311 is quickly completed.
  • the composition of the solder bonding layer 33 will not be uniform, but as explained in the first embodiment, it is believed that this will not cause any major problems in terms of the strength, thermal conductivity, electrical conductivity, etc. of the bonded portion.
  • the mixed solder paste 331 used in the third embodiment may be used instead of the solder paste 312 of BiSn solder.
  • the mixed solder paste 331 it becomes easier to adjust the temperature at which the liquid phase 311 of the BiSn solder occurs. For example, if there is variation in the temperature of the components in the heating process, the timing and time at which the liquid phase 311 occurs can be adjusted by changing the mixing ratio of the mixed solder paste 331 depending on the location.
  • the physical properties of the solder bonding layer 33 such as heat resistance, strength, and flexibility, can also be adjusted by changing the mixing ratio of the mixed solder paste 331.
  • ⁇ Fourth embodiment> 16A to 16C are conceptual diagrams showing a bonding process of a semiconductor element in a manufacturing method of a power module as a semiconductor device according to embodiment 4. The bonding process will be described with reference to these drawings.
  • an IGBT (Insulated Gate Bipolar Transistor) 21 and a diode 22 are joined to a ceramic substrate 10 using SnCu solder 32.
  • a convex SnCu solder 32 is formed on the main electrodes on the upper surfaces of the IGBT 21 and the diode 22.
  • a solder paste 312 of BiSn solder is supplied on the SnCu solder 32 on the IGBT 21 and the diode 22.
  • the ratio of the SnCu solder 32 to the solder paste 312 of BiSn solder is adjusted to 88:12.
  • the semiconductor elements mounted on the semiconductor device are not limited to IGBTs and diodes, and may be, for example, MOSFETs.
  • the case 5 is positioned and glued to the outer edge of the ceramic substrate 10.
  • An external main terminal 62, an electrode plate 61 connected to it, and a signal terminal 63 are inserted into the case 5.
  • solder joint layer 33 that is an alloy with a nearly uniform composition throughout.
  • FIG. 19 shows a top view of the power module shown in FIG. 19 (the sealing resin 7 is omitted in FIG. 20).
  • the composition of the solder bonding layer 33 will not be uniform, but as explained in the first embodiment, it is believed that this will not cause any major problems in terms of the strength, thermal conductivity, electrical conductivity, etc. of the bonded portion.
  • the mixed solder paste 331 used in the third embodiment may be used instead of the solder paste 312 of BiSn solder.
  • the mixed solder paste 331 it becomes easier to adjust the temperature at which the liquid phase 311 of BiSn solder is generated and the physical properties of the solder joint layer 33.
  • the semiconductor device according to the above-mentioned embodiments 1 to 4 is applied to a power conversion device.
  • the application of the semiconductor device according to the embodiments 1 to 4 is not limited to a specific power conversion device, a case in which the semiconductor device according to the embodiments 1 to 4 is applied to a three-phase inverter will be described below as embodiment 5.
  • FIG. 21 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.
  • the power conversion system shown in FIG. 21 is composed of a power source 100, a power conversion device 200, and a load 300.
  • the power source 100 is a DC power source, and supplies DC power to the power conversion device 200.
  • the power source 100 can be composed of various things, for example, a DC system, a solar cell, or a storage battery, or it may be composed of a rectifier circuit connected to an AC system or an AC/DC converter.
  • the power source 100 may also be composed of a DC/DC converter that converts the DC power output from the DC system into a specified power.
  • the power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts the DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. As shown in FIG. 21, the power conversion device 200 includes a main conversion circuit 201 that converts the DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal to the main conversion circuit 201 to control the main conversion circuit 201.
  • the load 300 is a three-phase motor that is driven by AC power supplied from the power conversion device 200.
  • the load 300 is not limited to a specific use, but is a motor mounted on various electrical devices, and is used, for example, as a motor for hybrid cars, electric cars, railroad cars, elevators, or air conditioning equipment.
  • the main conversion circuit 201 includes switching elements and free wheel diodes (not shown), and converts the DC power supplied from the power source 100 into AC power by switching the switching elements, and supplies the AC power to the load 300.
  • the main conversion circuit 201 is a two-level three-phase full bridge circuit, and can be configured with six switching elements and six free wheel diodes connected in reverse parallel to each switching element.
  • Each switching element and each free wheel diode of the main conversion circuit 201 is configured by a semiconductor module 202 corresponding to any one of the above-mentioned embodiments 1 to 4.
  • the six switching elements are connected in series with two switching elements to configure upper and lower arms, and each upper and lower arm configures each phase (U phase, V phase, W phase) of the full bridge circuit.
  • the output terminals of each upper and lower arm i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.
  • the main conversion circuit 201 also includes a drive circuit (not shown) that drives each switching element, but the drive circuit may be built into the semiconductor module 202, or the drive circuit may be provided separately from the semiconductor module 202.
  • the drive circuit generates drive signals that drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with a control signal from the control circuit 203 (described later), a drive signal that turns the switching element on and a drive signal that turns the switching element off are output to the control electrodes of each switching element.
  • the drive signal When the switching element is to be maintained in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when the switching element is to be maintained in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.
  • the control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300.
  • the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. Then, it outputs a control command (control signal) to a drive circuit provided in the main conversion circuit 201 so that an on signal is output to the switching element that should be in the on state at each point in time, and an off signal is output to the switching element that should be in the off state.
  • the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.
  • the semiconductor modules according to embodiments 1 to 4 are used as the switching elements and free wheel diodes of the main conversion circuit 201, thereby improving reliability.
  • an example of applying the semiconductor device according to embodiments 1 to 4 to a two-level three-phase inverter has been described, but the application of the semiconductor device according to embodiments 1 to 4 is not limited to this and can be applied to various power conversion devices.
  • a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used, and when supplying power to a single-phase load, the semiconductor device according to embodiments 1 to 4 may be applied to a single-phase inverter.
  • the semiconductor device according to embodiments 1 to 4 can also be applied to a DC/DC converter or an AC/DC converter.
  • the power conversion device to which the semiconductor device according to the fifth embodiment is applied is not limited to the case where the load described above is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.
  • step (b) In the step (b), the second solder diffuses into the liquid phase of the first solder, and a solder joint layer made of an alloy having a uniform composition as a whole is formed. 2.
  • step (b) In the step (b), a part of the second solder diffuses into the liquid phase of the first solder, and a solder joint layer in which the second solder partially remains is formed. 2. A method for manufacturing the semiconductor device according to claim 1.
  • the first solder is a tin-based solder containing 10 wt % or more of bismuth. 4.
  • step (b) In the step (b), the second solder diffuses into the liquid phase of the first solder, and a solder joint layer made of an alloy having a uniform composition as a whole is formed. 7. A method for manufacturing a semiconductor device according to claim 6.
  • step (b) In the step (b), a part of the second solder diffuses into the liquid phase of the first solder, and a solder joint layer in which the second solder partially remains is formed. 7. A method for manufacturing a semiconductor device according to claim 6.
  • the first solder is a tin-based solder containing 10 wt % or more of bismuth. 9. A method for manufacturing a semiconductor device according to any one of claims 6 to 8.
  • a semiconductor device comprising:
  • the solder joint layer includes a layer in which the second solder is diffused into the first solder, and a layer made of the second solder; 11.
  • the first solder is a tin-based solder containing 10 wt % or more of bismuth. 13.
  • a power conversion device comprising:

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PCT/JP2024/005317 2023-02-22 2024-02-15 半導体装置、電力変換装置および半導体装置の製造方法 Pending WO2024176947A1 (ja)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59169694A (ja) * 1983-03-16 1984-09-25 Hitachi Ltd 半田接着方法
JPH0596395A (ja) * 1991-10-04 1993-04-20 Mitsubishi Electric Corp 接合材、接合方法および半導体装置
JP2006339174A (ja) * 2005-05-31 2006-12-14 Hitachi Ltd 半導体装置
JP2014050871A (ja) * 2012-09-10 2014-03-20 Renesas Electronics Corp 半導体装置の製造方法
WO2016190205A1 (ja) * 2015-05-26 2016-12-01 三菱電機株式会社 半導体装置、半導体装置の製造方法、及び接合材料
JP2019204828A (ja) * 2018-05-22 2019-11-28 三菱電機株式会社 半導体装置、電力変換装置、および半導体装置の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59169694A (ja) * 1983-03-16 1984-09-25 Hitachi Ltd 半田接着方法
JPH0596395A (ja) * 1991-10-04 1993-04-20 Mitsubishi Electric Corp 接合材、接合方法および半導体装置
JP2006339174A (ja) * 2005-05-31 2006-12-14 Hitachi Ltd 半導体装置
JP2014050871A (ja) * 2012-09-10 2014-03-20 Renesas Electronics Corp 半導体装置の製造方法
WO2016190205A1 (ja) * 2015-05-26 2016-12-01 三菱電機株式会社 半導体装置、半導体装置の製造方法、及び接合材料
JP2019204828A (ja) * 2018-05-22 2019-11-28 三菱電機株式会社 半導体装置、電力変換装置、および半導体装置の製造方法

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