WO2024169054A1 - 半导体结构及其制备方法、电子设备 - Google Patents

半导体结构及其制备方法、电子设备 Download PDF

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Publication number
WO2024169054A1
WO2024169054A1 PCT/CN2023/092508 CN2023092508W WO2024169054A1 WO 2024169054 A1 WO2024169054 A1 WO 2024169054A1 CN 2023092508 W CN2023092508 W CN 2023092508W WO 2024169054 A1 WO2024169054 A1 WO 2024169054A1
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Prior art keywords
layer
conductive
material layer
channel region
forming
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PCT/CN2023/092508
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English (en)
French (fr)
Inventor
王桂磊
毛淑娟
赵超
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北京超弦存储器研究院
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Publication of WO2024169054A1 publication Critical patent/WO2024169054A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the embodiments of the present application relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for preparing the same, and an electronic device.
  • MOSFET metal-oxide semiconductor field-effect transistor
  • DRAM Cell dynamic random access device unit
  • vertical ring-gate transistors with weaker short channel effect, stronger gate control capability and smaller area will replace traditional MOSFET and be used in DRAM.
  • a semiconductor structure and a method for manufacturing the same, and an electronic device are provided.
  • the present application provides a method for preparing a semiconductor structure, comprising:
  • the upper surface layer of the substrate comprises a silicon material layer and a conductive material layer located on the upper surface of the silicon material layer;
  • the first direction intersects with the second direction, the metal silicide layer and the first conductive layer form a first conductive structure, and the resistivity of the first conductive layer is greater than the resistivity of the metal silicide layer.
  • the first conductive layer includes a silicon doped layer
  • the method further includes:
  • the drain region is electrically connected to the first conductive layer; the vertical transistor includes a channel region located on the upper surface of the drain region and a source region located on the upper surface of the channel region.
  • an epitaxial doping process is used to form a drain region of a vertical transistor on a first conductive layer, comprising:
  • the stacked structure comprising a first filling layer, a sacrificial layer, and a second filling layer stacked upward from the first conductive layer, a plurality of first through holes being opened in the stacked structure, the first through holes penetrating the stacked structure and exposing a portion of the surface of the first conductive layer;
  • the upper surface of the drain region is flush with the upper surface of the first filling layer.
  • the method further includes:
  • An epitaxial process is adopted to form a source region on the upper surface of the channel region, and the doping concentration of the source region is greater than the doping concentration of the channel region.
  • the method further includes:
  • the second conductive layer comprises a second conductive structure extending along a second direction
  • the upper surface of the dielectric layer, the upper surface of the second conductive layer and the upper surface of the channel region are located on the same horizontal plane.
  • removing the sacrificial layer includes:
  • a sacrificial pattern layer consisting of a remaining sacrificial layer
  • the remaining sacrificial layer includes a sacrificial layer located between a sidewall of the channel region and a sidewall of an adjacent second trench and a sacrificial layer located between adjacent second trenches, wherein the second trenches penetrate the second filling layer and expose a portion of the surface of the first filling layer, and wherein the second trenches extend along a second direction and are arranged in parallel along the first direction;
  • the sacrificial pattern layer is removed through the second trench.
  • the method further comprises:
  • an upper surface of the second isolation structure is higher than an upper surface of the source region.
  • the method before removing the sacrificial layer, the method further comprises:
  • a dielectric layer surrounding the channel region is formed on the sidewall of the channel region, including:
  • the dielectric layer is formed by a thermal oxidation process.
  • the method further includes:
  • a capacitor structure is formed on the vertical transistor, wherein the capacitor structure is electrically connected to the source region.
  • a substrate wherein the upper surface layer of the substrate includes a silicon material layer and a conductive material layer located on the upper surface of the silicon material layer, including:
  • the portion of the silicon substrate close to the conductive material layer is the silicon material layer.
  • the conductive material layer is patterned to obtain a plurality of adjacent first conductive layers and first trenches between the adjacent first conductive layers, including:
  • patterned mask layer on the conductive material layer, wherein the patterned mask layer defines the shape and position of the first conductive layer
  • the conductive material layer is patterned using the patterned mask layer as a mask to obtain a first conductive layer.
  • forming an isolation layer in the first trench includes:
  • the isolation material layer located between the upper surface of the silicon material layer and the lower surface of the silicon material layer in the first trench is removed to obtain an isolation layer composed of a remaining isolation material layer.
  • the method further comprises:
  • a third filling layer is formed on the isolation layer, and an upper surface of the third filling layer is flush with an upper surface of the first conductive layer.
  • the silicon material layer is processed to form a metal silicide layer, comprising:
  • An annealing process is performed at a preset temperature to allow the silicon material layer to react with the metal material layer to form a metal silicide layer.
  • the present application also provides a semiconductor structure obtained by using any of the above-mentioned methods for preparing a semiconductor structure, the semiconductor structure comprising:
  • a substrate wherein the upper surface layer of the substrate comprises a plurality of adjacent metal silicide layers and a first conductive layer located on the upper surface of the metal silicide layer, wherein the first conductive layer extends along a first direction and is arranged in parallel along a second direction;
  • An isolation layer located between adjacent first conductive layers, wherein an upper surface of the isolation layer is flush with a lower surface of the metal silicide layer;
  • the first direction intersects with the second direction, and the metal silicide layer and the first conductive layer form a first conductive structure.
  • the resistivity of the first conductive layer is greater than the resistivity of the metal silicide layer.
  • the first conductive layer includes a silicon doped layer
  • the semiconductor structure further includes:
  • a vertical transistor wherein a drain region of the vertical transistor is located on the first conductive layer and is electrically connected to the first conductive layer;
  • the vertical transistor includes a channel region located on an upper surface of the drain region and a source region located on an upper surface of the channel region.
  • the vertical transistor further comprises:
  • the dielectric layer surrounding the sidewalls of the channel region
  • a second conductive layer is located on a side wall of the dielectric layer away from the channel region, the second conductive layer comprises a second conductive structure, and the second conductive structure extends along the second direction;
  • the upper surface of the dielectric layer, the upper surface of the second conductive layer and the upper surface of the channel region are located on the same horizontal plane.
  • the semiconductor structure further comprises:
  • the capacitor structure is located on the vertical transistor and is electrically connected to the source region of the vertical transistor.
  • the present application also provides an electronic device, comprising any semiconductor structure as described above.
  • the cross-section of the semiconductor structure along the first direction penetrates the first conductive structure
  • the cross-section of the semiconductor structure along the second direction penetrates the second conductive layer.
  • the first direction is, for example, the X direction
  • the second direction is, for example, the Y direction.
  • FIG1 is a schematic flow diagram of a method for preparing a semiconductor structure in one embodiment
  • FIG2 is a schematic diagram of a flow chart of step S102 in one embodiment
  • FIG3 is a schematic cross-sectional view of a substrate in one embodiment
  • FIG4 is a schematic diagram of a flow chart of step S104 in one embodiment
  • FIG. 5 is a schematic cross-sectional view of a semiconductor structure along a first direction after a first conductive layer is formed in an embodiment corresponding to FIG. 3 ;
  • FIG6 is a schematic cross-sectional view of the semiconductor structure corresponding to FIG5 along the second direction;
  • FIG7 is a schematic diagram of a flow chart of step S106 in one embodiment
  • FIG8 is a schematic cross-sectional view of a semiconductor structure after a protective layer is formed in one embodiment corresponding to FIG5 ;
  • FIG9 is a schematic cross-sectional view of the semiconductor structure corresponding to FIG8 along the second direction;
  • FIG10 is a schematic cross-sectional view of a semiconductor structure after an isolation layer is formed in one embodiment corresponding to FIG8 ;
  • FIG11 is a schematic cross-sectional view of the semiconductor structure corresponding to FIG10 along the second direction;
  • FIG12 is a schematic diagram of a flow chart of step S108 in one embodiment
  • FIG13 is a cross-sectional schematic diagram of a semiconductor structure after a metal silicide layer is formed in an embodiment corresponding to FIG10;
  • FIG14 is a schematic cross-sectional view of the semiconductor structure corresponding to FIG13 along the second direction;
  • FIG15 is a cross-sectional schematic diagram of a semiconductor structure after a vertical transistor is formed in an embodiment corresponding to FIG13;
  • FIG16 is a schematic cross-sectional view of the semiconductor structure corresponding to FIG15 along the second direction;
  • FIG. 17 is a schematic diagram of a process of forming a vertical transistor on a first conductive layer in one embodiment
  • FIG18 is a schematic flow chart of a method for preparing a semiconductor structure in another embodiment
  • FIG19 is a schematic cross-sectional view of a semiconductor structure after a second conductive layer is formed in an embodiment corresponding to FIG15 ;
  • FIG20 is a schematic cross-sectional view of the semiconductor structure corresponding to FIG19 along the second direction;
  • FIG21 is a schematic diagram of a flow chart of step S702 in one embodiment
  • FIG22 is a cross-sectional schematic diagram of a semiconductor structure after a capacitor structure is formed in an embodiment corresponding to FIG19;
  • FIG. 23 is a schematic cross-sectional view of the semiconductor structure corresponding to FIG. 22 along the second direction.
  • 102 substrate; 104, protection layer; 106, isolation layer; 108, first conductive structure; 110, first isolation structure; 112, vertical transistor; 114, stacked structure; 116, source protection layer; 118, second conductive layer; 120, second trench; 122, capacitor structure; 124, second isolation structure; 126, capacitor contact structure; 202, silicon substrate; 204, conductive material layer; 206, silicon material layer; 208, patterned mask layer; 21 0, first trench; 212, isolation material layer; 214, drain region; 216, channel region; 218, source region; 220, first filling layer; 222, sacrificial layer; 224, second filling layer; 302, first conductive layer; 304, metal silicide layer; 306, third filling layer; 308, first through hole; 310, dielectric layer; 312, second conductive structure; 314, third conductive structure; 316, lower electrode; 318, capacitor dielectric layer; 320, upper electrode.
  • first, second, etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element.
  • a first conductive structure may be referred to as a second conductive structure, and similarly, a second conductive structure may be referred to as a first conductive structure.
  • Both the first conductive structure and the second conductive structure are conductive structures, but they are not the same conductive structure.
  • first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.
  • a feature defined as “first” or “second” may explicitly or implicitly include at least one of the features.
  • the meaning of “multiple” is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
  • severeal is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.
  • FIG. 1 is a schematic flow chart of a method for preparing a semiconductor structure in an embodiment. As shown in FIG. 1 , in this embodiment, a method for preparing a semiconductor structure is provided, comprising:
  • a substrate wherein the upper surface layer of the substrate includes a silicon material layer and a conductive material layer located on the upper surface of the silicon material layer;
  • the portion outside the upper surface layer of the substrate (substrate) can be a silicon substrate, i.e., undoped single crystal silicon, single crystal silicon doped with impurities, or silicon on insulator (SOI), in which case the silicon material layer can be the portion of the substrate itself close to the conductive material layer, and the conductive material layer can be a silicon doped layer obtained by doping a portion of the substrate surface with a preset thickness;
  • the portion outside the upper surface layer of the substrate (substrate) can also be a stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), etc., and the silicon material layer and the conductive material layer located on the upper surface of the silicon
  • the conductive material layer is patterned to obtain a plurality of adjacent first conductive layers and first grooves between adjacent first conductive layers, wherein the first conductive layers extend along a first direction and are arranged in parallel along a second direction, and the first grooves penetrate the silicon material layer and extend into the substrate.
  • a first groove is provided in the conductive material layer, wherein the first groove penetrates the upper surface layer of the substrate and extends to the middle of the substrate, that is, the bottom of the first groove is lower than the lower surface of the silicon material layer, and the first groove divides the conductive material layer into a plurality of first conductive layers arranged at intervals, each of the first conductive layers extends along a first direction, and different first conductive layers are arranged in parallel along a second direction, and the first direction and the second direction intersect.
  • the first direction and the second direction intersect orthogonally.
  • an isolation layer is formed in the first trench, wherein the upper surface of the isolation layer is flush with the lower surface of the silicon material layer.
  • the constituent material of the isolation layer includes at least one of nitride (eg, silicon nitride), oxynitride (eg, silicon oxynitride) or oxide (eg, silicon dioxide).
  • the silicon material layer is processed to form a metal silicide layer; wherein the metal silicide layer and the first conductive layer together constitute a first conductive structure, and the resistivity of the first conductive layer is greater than the resistivity of the metal silicide layer.
  • the method for preparing the above-mentioned semiconductor structure forms a metal silicide layer by processing the silicon material layer on the lower surface of the first conductive layer, wherein the resistivity of the first conductive layer is greater than the resistivity of the metal silicide layer, thereby obtaining a first conductive structure composed of the metal silicide layer and the first conductive layer.
  • the resistance of the first conductive structure is smaller and the performance of the semiconductor structure is better.
  • the semiconductor structure is a memory device and the first conductive structure is a bit line structure of the memory device, the resistance of the bit line structure is reduced and the storage performance of the memory device is improved.
  • FIG. 2 is a schematic flow chart of step S102 in one embodiment
  • FIG. 3 is a schematic cross-sectional diagram of a substrate in one embodiment.
  • step S102 includes:
  • a silicon substrate 202 is provided, where the silicon substrate 202 is made of undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), or stacked silicon on insulator (SSOI).
  • SOI silicon on insulator
  • SSOI stacked silicon on insulator
  • the upper surface layer of the silicon substrate 202 is doped by ion implantation and annealing to obtain a conductive material layer 204.
  • the concentration of doped impurity ions is 1*10 20 cm -3 .
  • the portion of the silicon substrate 202 close to the conductive material layer 204 is the silicon material layer 206 .
  • the substrate 102 includes the silicon substrate 202 , the silicon material layer 206 and the conductive material layer 204 .
  • the upper surface layer of the substrate 102 includes the silicon material layer 206 and the conductive material layer 204 .
  • FIG. 4 is a schematic flow chart of step S104 in one embodiment
  • FIG. 5 is a schematic cross-sectional view of a semiconductor structure along a first direction after forming a first conductive layer in one embodiment corresponding to FIG. 3
  • FIG. 6 is a schematic cross-sectional view of a semiconductor structure along a second direction corresponding to FIG. 5
  • step S104 includes:
  • a patterned mask layer 208 is formed on the conductive material layer 204, and the patterned mask layer 208 defines the shape and position of the first conductive layer 302; illustratively, the constituent material of the patterned mask layer 208 includes at least one of photoresist, anti-reflective material, nitride (e.g., silicon nitride), oxynitride (e.g., silicon oxynitride) or oxide (e.g., silicon dioxide).
  • nitride e.g., silicon nitride
  • oxynitride e.g., silicon oxynitride
  • oxide e.g., silicon dioxide
  • the conductive material layer 204 is patterned using the patterned mask layer 208 as a mask, and the conductive material layer 204 not covered by the patterned mask layer 208 and the silicon material layer 206 thereunder, as well as part of the silicon substrate 202 are etched away to obtain a first groove 210 having a bottom lower than the lower surface of the silicon material layer 206, and a plurality of first conductive layers 302 arranged at intervals and formed by the remaining conductive material layer 204, wherein the morphology and position of the remaining silicon material layer 206 are the same as those of the first conductive layer 302.
  • step S304 further includes a step of removing the patterned mask layer 208 .
  • FIG. 7 is a schematic diagram of a flow chart of step S106 in one embodiment
  • FIG. 8 is a schematic diagram of a cross-sectional view of a semiconductor structure after a protective layer is formed in one embodiment corresponding to FIG. 5
  • FIG. 9 is a schematic diagram of a cross-sectional view of a semiconductor structure along a second direction corresponding to FIG. 8.
  • forming an isolation layer in the first trench includes:
  • the isolation material layer 212 is filled in the first trench 210 through a film forming process well known to those skilled in the art, wherein the upper surface of the isolation material layer 212 is flush with the lower surface of the first conductive layer 302 .
  • a protective layer 104 is formed on the top of the first conductive layer 302, and the protective layer 104 extends along the top of the first conductive layer 302 to cover the sidewalls of the first conductive layer 302.
  • the constituent material of the protective layer 104 includes at least one of nitride (e.g., silicon nitride), oxynitride (e.g., silicon oxynitride) or oxide (e.g., silicon dioxide).
  • a thermal oxidation process can be used to oxidize the silicon material on the top and sidewalls of the first conductive layer 302 to form a protective layer 104 composed of silicon dioxide material.
  • FIG10 is a schematic cross-sectional view of a semiconductor structure after an isolation layer is formed in an embodiment corresponding to FIG8
  • FIG11 is a schematic cross-sectional view of the semiconductor structure corresponding to FIG10 along the second direction.
  • the isolation material layer 212 located between the upper surface of the silicon material layer 206 and the lower surface of the silicon material layer 206 in the first trench 210 is removed to obtain an isolation layer 106 composed of the remaining isolation material layer 212.
  • the sidewall of the silicon material layer 206 can be exposed at the sidewall of the first trench 210, so as to prepare for the subsequent processing of the silicon material layer 206 to obtain a metal silicide layer.
  • FIG. 12 is a schematic flow chart of step S108 in one embodiment
  • FIG. 13 is a schematic cross-sectional view of a semiconductor structure after a metal silicide layer is formed in one embodiment corresponding to FIG. 10
  • FIG. 14 is a schematic cross-sectional view of the semiconductor structure along a second direction corresponding to FIG. 13 .
  • the silicon material layer 206 is processed to form a metal silicide layer 304, including:
  • a metal material layer of a preset thickness is formed on the upper surface of the isolation layer 106, wherein the preset thickness is a value greater than or equal to a critical thickness, and the critical thickness is the minimum thickness of the metal material layer that enables the silicon material layer 206 to completely react to form the metal silicide layer 304 in step S504.
  • an annealing process is performed at a preset temperature to allow the silicon material layer 206 to react with the metal material layer to form a metal silicide layer 304, wherein the preset temperature is a value greater than or equal to a critical temperature, and the critical temperature is the lowest temperature at which the silicon material layer 206 can react with the metal material layer to form the metal silicide layer 304; the upper surface of the metal silicide layer 304 is flush with the lower surface of the first conductive layer 302, and the lower surface of the metal silicide layer 304 is flush with the upper surface of the isolation layer 106; the metal silicide layer 304 and the first conductive layer 302 together constitute a first conductive structure 108.
  • the method further includes:
  • the first step is to remove the protective layer 104.
  • the second step is to form a third filling layer 306 on the isolation layer 106, and the upper surface of the third filling layer 306 is flush with the upper surface of the first conductive layer 302, that is, the third filling layer 306 fills the first trench 210.
  • the constituent material of the third filling layer 306 includes at least one of nitride (e.g., silicon nitride), oxynitride (e.g., silicon oxynitride) or oxide (e.g., silicon dioxide). It can be understood that the isolation layer 106 and the third filling layer 306 together constitute the first isolation structure 110 located between the first conductive structure 108.
  • FIG. 15 is a schematic cross-sectional view of a semiconductor structure after a vertical transistor is formed in an embodiment corresponding to FIG. 13
  • FIG. 16 is a schematic cross-sectional view of the semiconductor structure corresponding to FIG. 15 along a second direction.
  • the first conductive layer 302 includes a silicon doped layer
  • the silicon material layer 206 is processed to form a metal silicide layer 304, the following further includes:
  • the drain region 214 of the vertical transistor 112 is formed on the first conductive layer 302 by an epitaxial doping process; wherein the drain region 214 is electrically connected to the first conductive layer 302 ; the vertical transistor 112 includes a channel region 216 located on the upper surface of the drain region 214 and a source region 218 located on the upper surface of the channel region 216 .
  • FIG. 17 is a schematic diagram of a process of forming a vertical transistor on a first conductive layer in an embodiment. As shown in FIG. 15 , FIG. 16 , and FIG. 17 , in one embodiment, an epitaxial doping process is used to form a drain region 214 of a vertical transistor 112 on a first conductive layer 302 , including:
  • a stacked structure 114 is formed on the first conductive layer 302 , and the stacked structure 114 includes a first filling layer 220 , a sacrificial layer 222 , and a second filling layer 224 stacked upward from the first conductive layer 302 .
  • a plurality of first through holes 308 are opened in the stacked structure 114 , and the first through holes 308 penetrate the stacked structure 114 and expose a portion of the surface of the first conductive layer 302 .
  • an epitaxial doping process is used to form a drain region 214 in the first through hole 308, and the upper surface of the drain region 214 is flush with the upper surface of the first filling layer 220.
  • a heavily doped drain region 214 can be obtained.
  • the semiconductor structure includes a memory device, and the first conductive structure 108 and the drain region 214 are used together as a bit line structure of the memory device, the heavily doped drain region 214 can further reduce the resistance of the bit line structure and improve the storage performance of the memory device.
  • the constituent materials of the first filling layer 220, the sacrificial layer 222, and the second filling layer 224 can all include one or more of nitride (e.g., silicon nitride), oxynitride (e.g., silicon oxynitride) or oxide (e.g., silicon dioxide).
  • nitride e.g., silicon nitride
  • oxynitride e.g., silicon oxynitride
  • oxide e.g., silicon dioxide
  • the method further includes:
  • an epitaxial doping process (or epitaxial process, doping process) is used to form a channel region 216 on the upper surface of the drain region 214, wherein the doping concentration of the channel region 216 is less than the doping concentration of the drain region 214, and the upper surface of the channel region 216 is flush with the upper surface of the sacrificial layer 222.
  • an epitaxial doping process (or epitaxial process, doping process) is used to form a source region 218 on the upper surface of the channel region 216, wherein the doping concentration of the source region 218 is greater than the doping concentration of the channel region 216.
  • the upper surface of the source region 218 is flush with the upper surface of the second filling layer 224.
  • the concentration of impurity ions doped in the drain region 214 and the source region 218 of the vertical transistor 112 is 1*10 20 cm ⁇ 3
  • the concentration of impurity ions doped in the channel region 216 is 1*10 18 cm ⁇ 3 ⁇ 1*10 19 cm ⁇ 3 .
  • FIG. 18 is a schematic flow diagram of a method for preparing a semiconductor structure in another embodiment
  • FIG. 19 is a schematic cross-sectional diagram of a semiconductor structure after forming a second conductive layer in an embodiment corresponding to FIG. 15
  • FIG. 20 is a schematic cross-sectional diagram of a semiconductor structure along a second direction corresponding to FIG. 19 .
  • the method further includes:
  • a dielectric layer 310 surrounding the channel region 216 is formed on the sidewall of the channel region 216, and the upper surface of the dielectric layer 310 and the upper surface of the channel region 216 are located at the same level.
  • the constituent material of the dielectric layer 310 includes one of silicon dioxide, a low-k gate dielectric material, or a high-k gate dielectric material.
  • a second conductive layer 118 is formed on the sidewall of the dielectric layer 310 away from the channel region 216, and the upper surface of the second conductive layer 118 and the upper surface of the channel region 216 are located at the same horizontal plane.
  • the second conductive layer 118 includes a second conductive structure 312 and a third conductive structure 314, wherein the second conductive structure 312 and the third conductive structure 314 are made of the same material and structure.
  • the sidewall of the dielectric layer 310 away from the channel region 216 includes a first sidewall that is opposite to each other in the first direction and a second sidewall that is opposite to each other in the second direction.
  • the second conductive structure 312 is formed on the surface of the second sidewall and extends along the second direction.
  • the third conductive structure 314 is formed on the surface of the first sidewall.
  • the second conductive structure 312 is opposite to each other in the second direction.
  • the thickness is greater than the thickness of the third conductive structure 314 in the first direction. In the first direction, there is a gap between adjacent vertical transistors 112.
  • the second conductive layer 118 includes a titanium nitride layer and a tungsten metal layer stacked from the side wall of the dielectric layer 310 to the direction away from the dielectric layer 310, wherein the upper surfaces of the titanium nitride layer and the tungsten metal layer are flush; at this time, the difference between the second conductive structure 312 and the third conductive structure 314 is that the thickness of the tungsten metal layer in the second conductive structure 312 in the second direction is greater than the thickness of the tungsten metal layer in the third conductive structure 314 in the first direction.
  • the constituent material of the second conductive layer 118 includes at least one of a metal material or a metal nitride material, wherein, when the constituent material of the second conductive layer 118 includes a metal material, the type of the metal material is at least one.
  • the method before removing the sacrificial layer 222, the method further includes: forming a source protection layer 116 on the source region 218; forming a dielectric layer 310 surrounding the channel region 216 on the sidewall of the channel region 216, including: forming the dielectric layer 310 by a thermal oxidation process.
  • the source protection layer 116 is formed to prevent the thermal oxidation process from affecting the performance of the source region 218 from above the source region 218, and the second filling layer 224 located on the sidewall of the source region 218 prevents the thermal oxidation process from affecting the performance of the source region 218 from the sidewall of the source region 218; the first filling layer 220 on the first conductive layer 302 prevents the thermal oxidation process from affecting the performance of the first conductive layer 302.
  • the constituent material of the source protection layer 116 includes at least one of nitride (e.g., silicon nitride), oxynitride (e.g., silicon oxynitride) or oxide (e.g., silicon dioxide).
  • FIG. 21 is a flow chart of step S702 in one embodiment.
  • step S702 includes:
  • a plurality of adjacent second grooves 120 are formed in the stacked structure 114 to obtain a sacrificial graphic layer composed of a remaining sacrificial layer 222; the second grooves 120 penetrate the second filling layer 224 and expose a portion of the surface of the first filling layer 220, and the second grooves 120 extend along the second direction and are arranged parallel to the first direction; exemplarily, a portion of the second filling layer 224 is provided between the sidewalls of the second grooves 120 and the sidewalls of the source region 218.
  • the remaining sacrificial layer 222 includes a sacrificial layer 222 located between the sidewall of the channel region 216 and the sidewall of the adjacent second trench 120 (in the first direction, the sacrificial layer 222 between the sidewall of the channel region 216 and the sidewall of the second trench 120, the sacrificial layer 222 at this position is removed and filled to form a dielectric layer 310 and a third conductive structure 314) and a sacrificial layer 222 located between adjacent second trenches 120 (in the second direction, the sacrificial layer 222 between the sidewalls of adjacent channel regions 216, the sacrificial layer 222 at this position is removed and filled to form a dielectric layer 310 and a second conductive structure 312).
  • the sacrificial pattern layer is removed through the second trench 120 to obtain a gap structure, which is subsequently filled with a dielectric layer 310 and a second conductive layer 118 , wherein the dielectric layer 310 and the second conductive layer 118 are stacked along the sidewall of the channel region 216 in a direction away from the channel region.
  • FIG22 is a cross-sectional schematic diagram of a semiconductor structure after a capacitor structure is formed in an embodiment corresponding to FIG19
  • FIG23 is a cross-sectional schematic diagram of the semiconductor structure corresponding to FIG22 along the second direction.
  • the method further includes: forming a capacitor structure 122 on the vertical transistor 112, wherein the capacitor structure 122 is electrically connected to the source region 218.
  • the capacitor structure 122 includes a lower electrode 316, a capacitor dielectric layer 318 located on a surface of the lower electrode 316 away from the source region 218, and an upper electrode 320 located on a surface of the capacitor dielectric layer 318.
  • the method further includes: filling and forming a second isolation structure 124 in the second trench 120, wherein the second isolation structure 124 fills the second trench 120; wherein the upper surface of the second isolation structure 124 is higher than the upper surface of the source region 218.
  • the lower electrode 316 of the capacitor structure 122 is electrically connected to the source region 218 through the capacitor contact structure 126 that penetrates the second isolation structure 124. It is understood that before forming the second isolation structure 124, the source protection layer 116 can be removed, or the source protection layer 116 can be retained.
  • the constituent material of the second isolation structure 124 includes at least one of nitride (e.g., silicon nitride), oxynitride (e.g., silicon oxynitride) or oxide (e.g., silicon dioxide).
  • nitride e.g., silicon nitride
  • oxynitride e.g., silicon oxynitride
  • oxide e.g., silicon dioxide
  • the semiconductor structure includes a memory device, the first conductive structure 108 is a bit line of the memory device, and the second conductive structure 312 is a word line of the memory device.
  • steps in Figures 1, 2, 4, 7, 12, 17, 18, and 21 may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.
  • the present application also provides a semiconductor structure, which is obtained by using the method for preparing the semiconductor structure as described in any of the above items, and the semiconductor structure includes: a substrate 102, and an isolation layer 106; the upper surface layer of the substrate 102 includes a plurality of adjacent metal silicide layers 304 and a first conductive layer 302 located on the upper surface of the metal silicide layer 304, wherein the first conductive layer 302 extends along a first direction and is arranged in parallel along a second direction; the portion (substrate) outside the upper surface layer of the substrate 102 can be a silicon substrate, i.e., undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), or stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insul
  • the upper surface layer here refers to the portion between the surface of the substrate 102 and the inner surface obtained by extending a preset thickness into the inside of the substrate 102.
  • the constituent material of the substrate 102 is selected to be single crystal silicon.
  • the isolation layer 106 is located between adjacent first conductive layers 302, and the upper surface of the isolation layer 106 is flush with the lower surface of the metal silicide layer 304; wherein the first direction intersects with the second direction, the metal silicide layer 304 and the first conductive layer 302 constitute the first conductive structure 108, and the resistivity of the first conductive layer 302 is greater than the resistivity of the metal silicide layer 304.
  • a metal silicide layer is formed by processing the silicon material layer on the lower surface of the first conductive layer, wherein the resistivity of the first conductive layer is greater than the resistivity of the metal silicide layer, thereby obtaining a first conductive structure composed of the metal silicide layer and the first conductive layer.
  • the resistance of the first conductive structure is smaller, and the performance of the semiconductor structure is better.
  • the material constituting the isolation layer 106 includes at least one of nitride (eg, silicon nitride), oxynitride (eg, silicon oxynitride), or oxide (eg, silicon dioxide).
  • nitride eg, silicon nitride
  • oxynitride eg, silicon oxynitride
  • oxide eg, silicon dioxide
  • the first conductive layer 302 includes a silicon doped layer.
  • the concentration of impurity ions doped in the silicon doped layer is 1*10 20 cm -3 .
  • the semiconductor structure further includes: a third filling layer 306, which is located on the upper surface of the isolation layer 106, and the upper surface of the third filling layer 306 is flush with the upper surface of the first conductive layer 302.
  • the constituent material of the third filling layer 306 includes at least one of nitride (e.g., silicon nitride), oxynitride (e.g., silicon oxynitride) or oxide (e.g., silicon dioxide). It is understood that the isolation layer 106 and the third filling layer 306 together constitute the first isolation structure 110 located between the first conductive structure 108.
  • the semiconductor structure also includes: a vertical transistor 112; the drain region 214 of the vertical transistor 112 is located on the first conductive layer 302 and is electrically connected to the first conductive layer 302; the vertical transistor 112 includes a channel region 216 located on the upper surface of the drain region 214 and a source region 218 located on the upper surface of the channel region 216.
  • the vertical transistor 112 includes: a dielectric layer 310 and a second conductive layer 118 .
  • the dielectric layer 310 surrounds the sidewall of the channel region 216 ; the second conductive layer 118 is located on the sidewall of the dielectric layer 310 away from the channel region 216 , and the upper surface of the dielectric layer 310 , the upper surface of the second conductive layer 118 , and the upper surface of the channel region 216 are located at the same horizontal plane.
  • the second conductive layer 118 includes a second conductive structure 312 and a third conductive structure 314 , wherein the second conductive structure 312 and the third conductive structure 314 are made of the same material and structure.
  • the sidewall of the dielectric layer 310 away from the channel region 216 includes a first sidewall that is opposite to each other in the first direction and a second sidewall that is opposite to each other in the second direction, the second conductive structure 312 is formed on the surface of the second sidewall and extends along the second direction, the third conductive structure 314 is formed on the surface of the first sidewall, and the thickness of the second conductive structure 312 in the second direction is greater than the thickness of the third conductive structure 314 in the first direction.
  • the second conductive layer 118 is illustratively composed of a titanium nitride layer and a tungsten metal layer stacked from the sidewall of the dielectric layer 310 to a direction away from the dielectric layer 310, wherein the upper surfaces of the titanium nitride layer and the tungsten metal layer are flush with each other; at this time, the difference between the second conductive structure 312 and the third conductive structure 314 is that the thickness of the tungsten metal layer in the second conductive structure 312 in the second direction is greater than the thickness of the tungsten metal layer in the third conductive structure 314 in the first direction.
  • the constituent material of the second conductive layer 118 includes at least one of a metal material or a metal nitride material, wherein when the constituent material of the second conductive layer 118 includes a metal material, the type of the metal material is at least one.
  • the semiconductor structure further includes: a capacitor structure 122, which is located on the vertical transistor 112 and is electrically connected to the source region 218 of the vertical transistor 112. It is understood that the capacitor structure 122 includes a lower electrode 316, a capacitor dielectric layer 318 located on a surface of the lower electrode 316 away from the source region 218, and an upper electrode 320 located on a surface of the capacitor dielectric layer 318.
  • the semiconductor structure further includes: a second isolation structure 124, located between adjacent vertical transistors 112, the second isolation structure 124 extending along the second direction and arranged in parallel along the first direction, wherein the upper surface of the second isolation structure 124 is higher than the upper surface of the source region 218.
  • the constituent material of the second isolation structure 124 includes at least one of a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), or an oxide (e.g., silicon dioxide). It is understood that the lower electrode 316 of the capacitor structure 122 is electrically connected to the source region 218 via a capacitor contact structure 126 that penetrates the second isolation structure 124.
  • the semiconductor structure includes a memory device, the first conductive structure 108 is a bit line of the memory device, and the second conductive structure 312 is a word line of the memory device.
  • the embodiment of the present application also provides an electronic device, including any of the semiconductor structures described above.
  • the electronic device may include a smart phone, a computer, a tablet computer, artificial intelligence, a wearable device, or a smart mobile terminal.
  • the embodiment of the present application does not impose any special restrictions on the specific form of the above electronic device.

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Abstract

本申请公开了一种半导体结构及其制备方法、电子设备，涉及半导体技术领域，用来解决存储器件中位线结构电阻大的问题。该方法包括：提供包括硅材料层(206)及导电材料层(204)的基底(102)；对导电材料层(204)进行图形化处理，以得到第一导电层(302)及位于相邻第一导电层(302)之间的第一沟槽(210)，第一沟槽(210)贯穿硅材料层(206)并延伸至基底(102)中；于第一沟槽(210)中形成隔离层(106)；对硅材料层(206)进行处理以形成金属硅化物层(304)；第一导电层(302)的电阻率大于金属硅化物层(304)的电阻率。

Description

半导体结构及其制备方法、电子设备
相关申请
本申请要求2023年02月14日申请的，申请号为2023101592138，名称为“半导体结构及其制备方法、电子设备”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请实施例涉及半导体技术领域，特别是涉及一种半导体结构及其制备方法、电子设备。
背景技术
传统MOSFET(金属-氧化物半导体场效应晶体管)存在短沟道效应，随着DRAM Cell(动态随机存取器件单元)的缩小，与传统MOSFET相比，短沟道效应弱、栅控能力更强、面积更小的垂直环栅晶体管将取代传统MOSFT应用于DRAM中。
发明内容
根据本申请的各种实施例，提供一种半导体结构及其制备方法、电子设备。
本申请提供一种半导体结构的制备方法，包括：
提供基底，所述基底的上表层包括硅材料层及位于所述硅材料层上表面的导电材料层；
对导电材料层进行图形化处理，以得到多个相邻的第一导电层及位于相邻第一导电层之间的第一沟槽，所述第一导电层沿第一方向延伸，且沿第二方向平行排布，所述第一沟槽贯穿所述硅材料层并延伸至基底中；
于第一沟槽中形成隔离层，所述隔离层的上表面与所述硅材料层的下表面相齐平；及
对所述硅材料层进行处理以形成金属硅化物层；
其中，第一方向和第二方向相交，金属硅化物层和第一导电层构成第一导电结构，第一导电层的电阻率大于金属硅化物层的电阻率。
在其中一个实施例中，第一导电层包括硅掺杂层，对所述硅材料层进行处理以形成金属硅化物层之后，还包括：
采用外延掺杂工艺于第一导电层上形成垂直晶体管的漏极区；
其中，所述漏极区与第一导电层电连接；垂直晶体管包括位于漏极区上表面的沟道区和位于沟道区上表面的源极区。
在其中一个实施例中，采用外延掺杂工艺于第一导电层上形成垂直晶体管的漏极区，包括：
于第一导电层上形成叠层结构，所述叠层结构包括自第一导电层向上叠置的第一填充层、牺牲层、第二填充层，所述叠层结构中开设有多个第一通孔，所述第一通孔贯穿叠层结构并暴露出第一导电层的部分表面；及
采用外延掺杂工艺于第一通孔中形成漏极区；
其中，漏极区的上表面与第一填充层的上表面相齐平。
在其中一个实施例中，采用外延掺杂工艺于第一通孔中形成漏极区之后，还包括：
采用外延工艺于漏极区的上表面形成沟道区，所述沟道区的掺杂浓度小于漏极区的掺杂浓度，所述沟道区的上表面与牺牲层的上表面相齐平；及
采用外延工艺于沟道区的上表面形成源极区，所述源极区的掺杂浓度大于沟道区的掺杂浓度。
在其中一个实施例中，采用外延掺杂工艺于第一导电层上形成垂直晶体管的漏极区之后，还包括：
去除牺牲层；
于沟道区的侧壁形成环绕沟道区的介质层；及
于介质层远离沟道区的侧壁形成第二导电层，所述第二导电层包括第二导电结构，所述第二导电结构沿第二方向延伸；
其中，介质层的上表面、第二导电层的上表面和沟道区的上表面位于同一水平面。
在其中一个实施例中，去除牺牲层，包括：
于叠层结构中形成多个相邻的第二沟槽，以得到由剩余牺牲层构成的牺牲图形层，所述剩余牺牲层包括位于沟道区的侧壁与相邻第二沟槽的侧壁之间的牺牲层以及位于相邻第二沟槽之间的牺牲层，所述第二沟槽贯穿第二填充层并暴露出第一填充层的部分表面，所述第二沟槽沿第二方向延伸，且沿第一方向平行排布；及
通过第二沟槽去除牺牲图形层。
在其中一个实施例中，于介质层远离沟道区的侧壁形成第二导电层之后，还包括：
于第二沟槽中填充形成第二隔离结构，所述第二隔离结构填满第二沟槽；
其中，所述第二隔离结构的上表面高于所述源极区的上表面。
在其中一个实施例中，去除牺牲层之前，还包括：
于源极区上形成源极保护层；
于沟道区的侧壁形成环绕沟道区的介质层，包括：
采用热氧工艺形成所述介质层。
在其中一个实施例中，采用外延掺杂工艺于第一导电层上形成垂直晶体管的漏极区之后，还包括：
于垂直晶体管上形成电容结构，所述电容结构与源极区电连接。
在其中一个实施例中，提供基底，所述基底的上表层包括硅材料层及位于所述硅材料层上表面的导电材料层，包括：
提供硅基底；及
采用离子注入于硅基底的上表层形成所述导电材料层；
其中，所述硅基底靠近所述导电材料层的部分为所述硅材料层。
在其中一个实施例中，对导电材料层进行图形化处理，以得到多个相邻的第一导电层及位于相邻第一导电层之间的第一沟槽，包括：
于导电材料层上形成图形化掩膜层，所述图形化掩膜层定义出第一导电层的形状和位置；及
以图形化掩膜层为掩膜对导电材料层进行图形化处理，以得到第一导电层。
在其中一个实施例中，于第一沟槽中形成隔离层，包括：
于第一沟槽中形成隔离材料层，所述隔离材料层的上表面与第一导电层的下表面相齐平；
于第一导电层的顶部和侧壁形成保护层；及
去除第一沟槽中位于硅材料层的上表面与硅材料层的下表面之间的隔离材料层，以得到由剩余隔离材料层构成的隔离层。
在其中一个实施例中，对所述硅材料层进行处理以形成金属硅化物层之后，还包括：
去除所述保护层；及
于隔离层上形成第三填充层，第三填充层的上表面与第一导电层的上表面相齐平。
在其中一个实施例中，对所述硅材料层进行处理以形成金属硅化物层，包括：
于隔离层上形成预设厚度的金属材料层；及
在预设温度下进行退火工艺，以使所述硅材料层与所述金属材料层反应形成金属硅化物层。
本申请还提供一种半导体结构，采用如上述任一项所述的半导体结构的制备方法而得到，所述半导体结构包括：
基底，所述基底的上表层包括多个相邻的金属硅化物层和位于金属硅化物层上表面的第一导电层，所述第一导电层沿第一方向延伸，且沿第二方向平行排布；及
隔离层，位于相邻第一导电层之间，所述隔离层的上表面与金属硅化物层的下表面相齐平；
其中，第一方向和第二方向相交，金属硅化物层和第一导电层构成第一导电结构，所 述第一导电层的电阻率大于所述金属硅化物层的电阻率。
在其中一个实施例中，第一导电层包括硅掺杂层，半导体结构还包括：
垂直晶体管，所述垂直晶体管的漏极区位于所述第一导电层上，且与所述第一导电层电连接；
其中，所述垂直晶体管包括位于所述漏极区上表面的沟道区和位于所述沟道区上表面的源极区。
在其中一个实施例中，垂直晶体管还包括：
介质层，所述介质层环绕所述沟道区的侧壁；及
第二导电层，所述第二导电层位于所述介质层远离所述沟道区的侧壁上，所述第二导电层包括第二导电结构，所述第二导电结构沿所述第二方向延伸；
其中，所述介质层的上表面、所述第二导电层的上表面和所述沟道区的上表面位于同一水平面。
在其中一个实施例中，半导体结构还包括：
电容结构，位于垂直晶体管上，且与垂直晶体管放入源极区电连接。
本申请还提供一种电子设备，包括如上任一所述的半导体结构。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和有点将从说明书、附图以及权利要求变得明显。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据公开的附图获得其他的附图。本申请中，半导体结构沿第一方向的剖面贯穿第一导电结构，半导体结构沿第二方向的剖面贯穿第二导电层，第一方向例如为X方向，第二方向例如为Y方向。
图1为一实施例中半导体结构的制备方法的流程示意图；
图2为一实施例中步骤S102的流程示意图；
图3为一实施例中基底的剖面示意图；
图4为一实施例中步骤S104的流程示意图；
图5为图3对应的一实施例中形成第一导电层后沿第一方向半导体结构的剖面示意图；
图6为图5对应的半导体结构沿第二方向的剖面示意图；
图7为一实施例中步骤S106的流程示意图；
图8图5对应的一实施例中形成保护层后半导体结构的剖面示意图；
图9为图8对应的半导体结构沿第二方向的剖面示意图；
图10图8对应的一实施例中形成隔离层后半导体结构的剖面示意图；
图11为图10对应的半导体结构沿第二方向的剖面示意图；
图12为一实施例中步骤S108的流程示意图；
图13为图10对应的一实施例中形成金属硅化物层后半导体结构的剖面示意图；
图14为图13对应的半导体结构沿第二方向的剖面示意图；
图15为图13对应的一实施例中形成垂直晶体管后半导体结构的剖面示意图；
图16为图15对应的半导体结构沿第二方向的剖面示意图；
图17为一实施例中于第一导电层上形成垂直晶体管的流程示意图；
图18为另一实施例中半导体结构的制备方法的流程示意图；
图19为图15对应的一实施例中形成第二导电层后半导体结构的剖面示意图；
图20为图19对应的半导体结构沿第二方向的剖面示意图；
图21为一实施例中步骤S702的流程示意图；
图22为图19对应的一实施例中形成电容结构后半导体结构的剖面示意图；
图23为图22对应的半导体结构沿第二方向的剖面示意图。
附图标记说明：
102、基底；104、保护层；106、隔离层；108、第一导电结构；110、第一隔离结构；112、垂直晶体管；114、叠层结构；116、源极保护层；118、第二导电层；120、第二沟槽；122、电容结构；124、第二隔离结构；126、电容接触结构；202、硅基底；204、导电材料层；206、硅材料层；208、图形化掩膜层；210、第一沟槽；212、隔离材料层；214、漏极区；216、沟道区；218、源极区；220、第一填充层；222、牺牲层；224、第二填充层；302、第一导电层；304、金属硅化物层；306、第三填充层；308、第一通孔；310、介质层；312、第二导电结构；314、第三导电结构；316、下电极；318、电容介质层；320、上电极。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请实施例的技术领域的技术人员通常理解的含义相同。本文中在本申请实施例的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请实施例。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在本申请实施例的描述中，需要理解的是，术语“上”、“下”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本申请实施例和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请实施例的限制。
可以理解，本申请所使用的术语“第一”、“第二”等可在本文中用于描述各种元件，但这些元件不受这些术语限制。这些术语仅用于将第一个元件与另一个元件区分。举例来说，在不脱离本申请的范围的情况下，可以将第一导电结构称为第二导电结构，且类似地，可将第二导电结构称为第一导电结构。第一导电结构和第二导电结构两者都是导电结构，但其不是同一导电结构。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本申请的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。在本申请的描述中，“若干”的含义是至少一个，例如一个，两个等，除非另有明确具体的限定。
图1为一实施例中半导体结构的制备方法的流程示意图，如图1所示，在本实施例中，提供一种半导体结构的制备方法，包括：
S102，提供上表层包括硅材料层及导电材料层的基底。
具体地，提供基底，所述基底的上表层包括硅材料层及位于所述硅材料层上表面的导电材料层；该基底上表层之外的部分(衬底)可以采用硅基底，即未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)，此时，硅材料层可以是基底本身靠近导电材料层的部分，导电材料层可以是对基底表面预设厚度的部分进行掺杂得到的硅掺杂层；该基底上表层之外的部分(衬底)也可以采用绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等，硅材料层及位于所述硅材料层上表面的导电材料层也可以是形成在衬底表面上的膜层。这里的上表层指的是基底表面与向基底内部延伸预设厚度后得到的内表面之间的部分。作为示例，在本实施例中，基底的构成材料选用单晶硅。
S104，对导电材料层进行图形化处理，得到多个第一导电层及位于第一导电层之间的 第一沟槽。
对导电材料层进行图形化处理，以得到多个相邻的第一导电层及位于相邻第一导电层之间的第一沟槽，所述第一导电层沿第一方向延伸，且沿第二方向平行排布，所述第一沟槽贯穿所述硅材料层并延伸至基底中。具体地，在导电材料层中开设第一沟槽，所述第一沟槽贯穿所述基底的上表层并延伸至基底的中，即第一沟槽的底部低于硅材料层的下表面，所述第一沟槽将所述导电材料层分割成若干个间隔排布的第一导电层，各所述第一导电层沿第一方向延伸，不同第一导电层沿第二方向平行排布，第一方向和第二方向相交。作为示例，在本实施例中，第一方向和第二方向正相交。
S106，于第一沟槽中形成隔离层。
于第一沟槽中形成隔离层，所述隔离层的上表面与所述硅材料层的下表面相齐平，示例性的，隔离层的构成材料至少包括氮化物(例如氮化硅)、氮氧化物(例如氮氧化硅)或氧化物(例如二氧化硅)中的一种。
S108，对硅材料层进行处理以得到金属硅化物层。
具体地，对所述硅材料层进行处理以形成金属硅化物层；其中，金属硅化物层和第一导电层共同构成第一导电结构，第一导电层的电阻率大于金属硅化物层的电阻率。
上述半导体结构的制备方法，通过对第一导电层下表面的硅材料层进行处理形成金属硅化物层，其中，第一导电层的电阻率大于金属硅化物层的电阻率，得到由金属硅化物层和第一导电层构成的第一导电结构，与仅由第一导电层形成的导电结构相比，第一导电结构的电阻较小，半导体结构的性能较好，当半导体结构为存储器件，第一导电结构为所述存储器件的位线结构时，位线结构的电阻降低，存储器件的存储性能得到提高。
图2为一实施例中步骤S102的流程示意图，图3为一实施例中基底的剖面示意图，如图2、图3所示，在其中一个实施例中，步骤S102包括：
S202,提供硅基底。
具体地，提供硅基底202，这里的硅基底202采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)。
S204，采用离子注入于硅基底的上表层形成导电材料层；
其中，采用离子注入工艺和退火工艺对硅基底202的上表层进行掺杂，以得到导电材料层204，示例性的，掺杂的杂质离子浓度为1*1020cm-3；硅基底202靠近导电材料层204的部分为硅材料层206，此时，基底102包括硅基底202、硅材料层206和导电材料层204，基底102的上表层包括硅材料层206和导电材料层204。
图4为一实施例中步骤S104的流程示意图，图5为图3对应的一实施例中形成第一导电层后沿第一方向半导体结构的剖面示意图，图6为图5对应的半导体结构沿第二方向的剖面示意图，如图4、图5、图6所示，在其中一个实施例中，步骤S104包括：
S302，于导电材料层上形成图形化掩膜层。
具体地，于导电材料层204上形成图形化掩膜层208，所述图形化掩膜层208定义出第一导电层302的形状和位置；示例性的，图像化掩膜层208的构成材料至少包括光刻胶、抗反射材料、氮化物(例如氮化硅)、氮氧化物(例如氮氧化硅)或氧化物(例如二氧化硅)中的一种。
S304，以图形化掩膜层为掩膜对导电材料层进行图形化处理，以得到第一导电层。
以图形化掩膜层208为掩膜对导电材料层204进行图形化处理，刻蚀去除未被图形化掩膜层208覆盖的导电材料层204及其下方的硅材料层206、部分硅基底202，得到底部低于硅材料层206的下表面的第一沟槽210，以及由剩余导电材料层204构成的多个间隔排布的第一导电层302，其中，剩余硅材料层206的形貌和位置与第一导电层302相同。
在其中一个实施例中，步骤S304之后还包括去除图形化掩膜层208的步骤。
图7为一实施例中步骤S106的流程示意图，图8图5对应的一实施例中形成保护层后半导体结构的剖面示意图，图9为图8对应的半导体结构沿第二方向的剖面示意图，如 图7、图8、图9所示，在其中一个实施例中，于第一沟槽中形成隔离层，包括：
S402，于第一沟槽中形成隔离材料层。
具体地，通过本领域技术人员熟知的成膜工艺，在第一沟槽210中填充隔离材料层212，其中，隔离材料层212的上表面与第一导电层302的下表面相齐平。
S404，于第一导电层的顶部和侧壁形成保护层。
具体地，在第一导电层302的顶部形成保护层104，并且保护层104沿第一导电层302的顶部延伸覆盖在第一导电层302的侧壁，通过形成保护层104可以避免其他制程对第一导电层302的影响。示例性的，保护层104的构成材料至少包括氮化物(例如氮化硅)、氮氧化物(例如氮氧化硅)或氧化物(例如二氧化硅)中的一种。示例性的，当第一导电层的构成材料为掺杂的硅材料时，可以采用热氧工艺对第一导电层302顶部和侧壁的硅材料进行氧化形成由二氧化硅材料构成的保护层104。
S406，去除高于硅材料层下表面的隔离材料层，得到由剩余隔离材料层构成的隔离层。
图10图8对应的一实施例中形成隔离层后半导体结构的剖面示意图，图11为图10对应的半导体结构沿第二方向的剖面示意图，如图10、图11所示，去除第一沟槽210中位于硅材料层206的上表面与硅材料层206的下表面之间的隔离材料层212，以得到由剩余隔离材料层212构成的隔离层106。通过去除第一沟槽210中位于硅材料层206的上表面与硅材料层206的下表面之间的隔离材料层212，可以在第一沟槽210的侧壁暴露出硅材料层206的侧壁，为后续对硅材料层206进行处理得到金属硅化物层做准备。
图12为一实施例中步骤S108的流程示意图，图13为图10对应的一实施例中形成金属硅化物层后半导体结构的剖面示意图，图14为图13对应的半导体结构沿第二方向的剖面示意图，如图12、图13、图14所示，在其中一个实施例中，对硅材料层206进行处理以形成金属硅化物层304，包括：
S502，于隔离层上形成预设厚度的金属材料层。
具体地，在隔离层106的上表面形成预设厚度的金属材料层，其中，预设厚度为大于或等于临界厚度的值，临界厚度为步骤S504中能使硅材料层206完全反应形成金属硅化物层304的金属材料层的最小厚度。
S504，进行退火工艺，以使硅材料层与金属材料层反应形成金属硅化物层。
具体地，在预设温度下进行退火工艺，以使硅材料层206与所述金属材料层反应形成金属硅化物层304，其中，预设温度为大于或等于临界温度的值，临界温度为能使硅材料层206与金属材料层反应形成金属硅化物层304的最低温度；金属硅化物层304的上表面与第一导电层302的下表面相齐平，且金属硅化物层304的下表面与隔离层106的上表面相齐平；金属硅化物层304和第一导电层302共同构成第一导电结构108。
继续参考图13、图14，在其中一个实施例中，对硅材料层206进行处理以形成金属硅化物层304之后，还包括：
第一步，去除保护层104。第二步，于隔离层106上形成第三填充层306，第三填充层306的上表面与第一导电层302的上表面相齐平，即第三填充层306填满第一沟槽210。示例性的，第三填充层306的构成材料至少包括氮化物(例如氮化硅)、氮氧化物(例如氮氧化硅)或氧化物(例如二氧化硅)中的一种。可以理解的是，隔离层106和第三填充层306共同构成位于第一导电结构108之间的第一隔离结构110。
图15为图13对应的一实施例中形成垂直晶体管后半导体结构的剖面示意图，图16为图15对应的半导体结构沿第二方向的剖面示意图，如图15、图16所示，在其中一个实施例中，第一导电层302包括硅掺杂层，对硅材料层206进行处理以形成金属硅化物层304之后，还包括：
采用外延掺杂工艺于第一导电层302上形成垂直晶体管112的漏极区214；其中，漏极区214与第一导电层302电连接；垂直晶体管112包括位于漏极区214上表面的沟道区216和位于沟道区216上表面的源极区218。
图17为一实施例中于第一导电层上形成垂直晶体管的流程示意图，如图15、图16、图17所示，在其中一个实施例中，采用外延掺杂工艺于第一导电层302上形成垂直晶体管112的漏极区214，包括：
S602，于第一导电层上形成叠层结构。
具体地，在第一导电层302上形成叠层结构114，叠层结构114包括自第一导电层302向上叠置的第一填充层220、牺牲层222、第二填充层224，叠层结构114中开设有多个第一通孔308，第一通孔308贯穿叠层结构114并暴露出第一导电层302的部分表面。
S604，采用外延掺杂工艺于第一通孔中形成漏极区；
具体地，采用外延掺杂工艺在第一通孔308中形成漏极区214，漏极区214的上表面与第一填充层220的上表面相齐平，通过采用外延掺杂工艺可以得到重掺杂的漏极区214。当半导体结构包括存储器件，且第一导电结构108和漏极区214共同做为存储器件的位线结构时，重掺杂的漏极区214可以进一步降低位线结构的电阻，提高存储器件的存储性能。示例性的，在满足牺牲层222的去除速率大于第一填充层220的去除速率，且牺牲层222的去除速率大于第二填充层224的去除速率的条件下，第一填充层220、牺牲层222、第二填充层224的构成材料均可以包括氮化物(例如氮化硅)、氮氧化物(例如氮氧化硅)或氧化物(例如二氧化硅)中的一种或多种。
继续参考15、图16、图17所示，在其中一个实施例中，采用外延掺杂工艺于第一通孔中形成漏极区之后，还包括：
S606，采用外延工艺于漏极区的上表面形成沟道区。
具体地，采用外延掺杂工艺(或外延工艺、掺杂工艺)在漏极区214的上表面形成沟道区216,其中，沟道区216的掺杂浓度小于漏极区214的掺杂浓度，沟道区216的上表面与牺牲层222的上表面相齐平。
S608，采用外延工艺于沟道区的上表面形成源极区。
具体地，采用外延掺杂工艺(或外延工艺、掺杂工艺)在沟道区216的上表面形成源极区218,其中，源极区218的掺杂浓度大于沟道216区的掺杂浓度。示例性的，源极区218的上表面与第二填充层224的上表面相齐平。
示例性的，垂直晶体管112的漏极区214和源极区218中掺杂的杂质离子浓度为1*1020cm-3，沟道区216中掺杂的杂质离子浓度为1*1018cm-3～1*1019cm-3。
在其他实施例中，也可以采用其他制备工艺形成垂直晶体管112的沟道区216和源极区218。
图18为另一实施例中半导体结构的制备方法的流程示意图，图19为图15对应的一实施例中形成第二导电层后半导体结构的剖面示意图，图20为图19对应的半导体结构沿第二方向的剖面示意图，如图18、图19、图20所示，在其中一个实施例中，采用外延掺杂工艺于第一导电层302上形成垂直晶体管112的漏极区214之后，还包括：
S702，去除牺牲层。
S704，于沟道区的侧壁形成环绕沟道区的介质层。
具体地，在沟道区216的侧壁形成环绕沟道区216的介质层310，介质层310的上表面和沟道区216的上表面位于同一水平面。示例性的，介质层310的构成材料包括二氧化硅、低k栅介质材料或高k栅介质材料中的一种。
S706，于介质层远离沟道区的侧壁形成第二导电层。
具体地，在介质层310远离沟道区216的侧壁形成第二导电层118，第二导电层118的上表面和沟道区216的上表面位于同一水平面。所述第二导电层118包括第二导电结构312和第三导电结构314，其中，第二导电结构312和第三导电结构314的构成材料和结构相同。介质层310远离沟道区216的侧壁包括在第一方向上相对存在的第一侧壁和在第二方向上相对存在的第二侧壁，第二导电结构312形成于第二侧壁的表面上，且沿第二方向延伸，第三导电结构314形成于第一侧壁的表面上，第二导电结构312在第二方向上的 厚度大于第三导电结构314在第一方向上的厚度。在第一方向上，相邻垂直晶体管112之间存在缝隙。示例性的，第二导电层118包括自介质层310的侧壁向远离介质层310的方向叠置的氮化钛层和钨金属层，其中，氮化钛层和钨金属层的上表面相齐平；此时，第二导电结构312和第三导电结构314的区别在于，第二导电结构312中钨金属层在第二方向上的厚度大于第三导电结构314中的钨金属层在第一方向上的厚度。示例性的，第二导电层118的构成材料至少包括金属材料或金属氮化物材料中的一种，其中，当第二导电层118的构成材料包括金属材料时，金属材料的种类至少为一种。
继续参见图19和图20，在其中一个实施例中，去除牺牲层222之前，还包括：于源极区218上形成源极保护层116；于沟道区216的侧壁形成环绕沟道区216的介质层310，包括：采用热氧工艺形成所述介质层310。通过形成源极保护层116避免热氧化工艺从源极区218的上方影响源极区218的性能，位于源极区218侧壁的第二填充层224避免热氧化工艺从源极区218的侧壁影响源极区218的性能；第一导电层302上的第一填充层220使得热氧化工艺不会影响第一导电层302的性能。示例性的，源极保护层116的构成材料至少包括氮化物(例如氮化硅)、氮氧化物(例如氮氧化硅)或氧化物(例如二氧化硅)中的一种。
图21为一实施例中步骤S702的流程示意图，在其中一个实施例中，步骤S702包括：
S802，于叠层结构中形成多个相邻的第二沟槽，以得到牺牲图形层。
具体地，于叠层结构114中形成多个相邻的第二沟槽120，以得到由剩余牺牲层222构成的牺牲图形层；所述第二沟槽120贯穿第二填充层224并暴露出第一填充层220的部分表面，所述第二沟槽120沿第二方向延伸，且沿第一方向平行排布；示例性的，第二沟槽120的侧壁与源极区218的侧壁之间具有部分第二填充层224。所述剩余牺牲层222包括位于沟道区216的侧壁与相邻第二沟槽120的侧壁之间的牺牲层222(在第一方向上，沟道区216的侧壁与第二沟槽120的侧壁之间的牺牲层222，该位置的牺牲层222被去除后填充形成介质层310和第三导电结构314)以及位于相邻第二沟槽120之间的牺牲层222(在第二方向上，相邻沟道区216的侧壁之间的牺牲层222，该位置的牺牲层222被去除后填充形成介质层310和第二导电结构312)。
S804，通过第二沟槽去除牺牲图形层。
通过第二沟槽120去除牺牲图形层，得到空隙结构，该空隙结构后续填充介质层310和第二导电层118，其中，介质层310和第二导电层118沿沟道区216的侧壁向远离沟道区的方向叠置。
图22为图19对应的一实施例中形成电容结构后半导体结构的剖面示意图，图23为图22对应的半导体结构沿第二方向的剖面示意图，如图22、图23所示，在其中一个实施例中，采用外延掺杂工艺于第一导电层302上形成垂直晶体管112的漏极区214之后，还包括：于垂直晶体管112上形成电容结构122，所述电容结构122与源极区218电连接。可以理解的是，电容结构122包括下电极316、位于下电极316远离源极区218的表面上的电容介质层318和位于电容介质层318表面上的上电极320。
如图22、图23所示，在其中一个实施例中，于介质层310远离沟道区216的侧壁形成第二导电层118之后，还包括：于第二沟槽120中填充形成第二隔离结构124，所述第二隔离结构124填满第二沟槽120；其中，第二隔离结构124的上表面高于源极区218的上表面。可以理解的是，电容结构122的下电极316通过贯穿第二隔离结构124的电容接触结构126与源极区218电连接。可以理解的是，在形成第二隔离结构124之前可以去除源极保护层116，也可以保留源极保护层116，当保留源极保护层116时，电容接触结构126贯穿源极保护层116。示例性的，第二隔离结构124的构成材料至少包括氮化物(例如氮化硅)、氮氧化物(例如氮氧化硅)或氧化物(例如二氧化硅)中的一种。
在其中一个实施例中，半导体结构包括存储器件，第一导电结构108为所述存储器件的位线，第二导电结构312为所述存储器件的字线。
应该理解的是，虽然图1、图2、图4、图7、图12、图17、图18、图21的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图1、图2、图4、图7、图12、图17、图18、图21中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
如图3、图22、图23所示，本申请还提供一种半导体结构，采用如上述任一项所述的半导体结构的制备方法而得到，所述半导体结构包括：基底102、和隔离层106；基底102的上表层包括多个相邻的金属硅化物层304和位于金属硅化物层304上表面的第一导电层302，所述第一导电层302沿第一方向延伸，且沿第二方向平行排布；该基底102上表层之外的部分(衬底)可以采用硅基底，即未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)，也可以采用绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。这里的上表层指的是基底102表面与向基底102内部延伸预设厚度后得到的内表面之间的部分。作为示例，在本实施例中，基底102的构成材料选用单晶硅。隔离层106位于相邻第一导电层302之间，所述隔离层106的上表面与金属硅化物层304的下表面相齐平；其中，第一方向和第二方向相交，金属硅化物层304和第一导电层302构成第一导电结构108，第一导电层302的电阻率大于金属硅化物层304的电阻率。
上述半导体结构，在制备过程中通过对第一导电层下表面的硅材料层进行处理形成金属硅化物层，其中，第一导电层的电阻率大于金属硅化物层的电阻率，得到由金属硅化物层和第一导电层构成的第一导电结构，与第一导电层形成的导电结构相比，第一导电结构的电阻较小，半导体结构的性能较好，当半导体结构为存储器件，第一导电结构为所述存储器件的位线结构时，存储器件的存储性能得到提高。
在其中一个实施例中，隔离层106的构成材料至少包括氮化物(例如氮化硅)、氮氧化物(例如氮氧化硅)或氧化物(例如二氧化硅)中的一种。
在其中一个实施例中，第一导电层302包括硅掺杂层。示例性的，硅掺杂层中掺杂的杂质离子浓度为1*1020cm-3。
如图22、图23所示，在其中一个实施例中，半导体结构还包括：第三填充层306，位于隔离层106的上表面，第三填充层306的上表面与第一导电层302的上表面相齐平。示例性的，第三填充层306的构成材料至少包括氮化物(例如氮化硅)、氮氧化物(例如氮氧化硅)或氧化物(例如二氧化硅)中的一种。可以理解的是，隔离层106和第三填充层306共同构成位于第一导电结构108之间的第一隔离结构110。
如图22、图23所示，在其中一个实施例中，半导体结构还包括：垂直晶体管112；垂直晶体管112的漏极区214位于第一导电层302上，且与第一导电层302电连接；垂直晶体管112包括位于漏极区214上表面的沟道区216和位于沟道区216上表面的源极区218。
如图15、图22、图23所示，在其中一个实施例中，垂直晶体管112包括：介质层310和第二导电层118。介质层310环绕沟道区216的侧壁；第二导电层118位于介质层310远离沟道区216的侧壁上，介质层310的上表面、第二导电层118的上表面和沟道区216的上表面位于同一水平面。所述第二导电层118包括第二导电结构312和第三导电结构314，其中，第二导电结构312和第三导电结构314的构成材料和结构相同。介质层310远离沟道区216的侧壁包括在第一方向上相对存在的第一侧壁和在第二方向上相对存在的第二侧壁，第二导电结构312形成于第二侧壁的表面上，且沿第二方向延伸，第三导电结构314形成于第一侧壁的表面上，第二导电结构312在第二方向上的厚度大于第三导电结构314在第一方向上的厚度。在第一方向上，相邻垂直晶体管112之间隔离(即存在第二隔 离结构124)。示例性的，第二导电层118包括自介质层310的侧壁向远离介质层310的方向叠置的氮化钛层和钨金属层，其中，氮化钛层和钨金属层的上表面相齐平；此时，第二导电结构312和第三导电结构314的区别在于，第二导电结构312中钨金属层在第二方向上的厚度大于第三导电结构314中的钨金属层在第一方向上的厚度。示例性的，第二导电层118的构成材料至少包括金属材料或金属氮化物材料中的一种，其中，当第二导电层118的构成材料包括金属材料时，金属材料的种类至少为一种。
在其中一个实施例中，半导体结构还包括：电容结构122，位于垂直晶体管112上，且与垂直晶体管112的源极区218电连接。可以理解的是，电容结构122包括下电极316、位于下电极316远离源极区218的表面上的电容介质层318和位于电容介质层318表面上的上电极320。
在其中一个实施例中，半导体结构还包括：第二隔离结构124，位于相邻垂直晶体管112之间，所述第二隔离结构124沿第二方向延伸，且沿第一方向平行排布，其中，第二隔离结构124的上表面高于源极区218的上表面。示例性的，第二隔离结构124的构成材料至少包括氮化物(例如氮化硅)、氮氧化物(例如氮氧化硅)或氧化物(例如二氧化硅)中的一种。可以理解的是，电容结构122的下电极316通过贯穿第二隔离结构124的电容接触结构126与源极区218电连接。
在其中一个实施例中，半导体结构包括存储器件，第一导电结构108为所述存储器件的位线，第二导电结构312为所述存储器件的字线。
本申请实施例还提供了一种电子设备，包括前面任一所述的半导体结构。该电子设备可以包括智能电话、计算机、平板电脑、人工智能、可穿戴设备或智能移动终端。本申请实施例对上述电子设备的具体形式不做特殊限制。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (19)

  1. 一种半导体结构的制备方法，包括：
    提供基底，所述基底的上表层包括硅材料层及位于所述硅材料层上表面的导电材料层；
    对所述导电材料层进行图形化处理，以得到多个相邻的第一导电层及位于相邻所述第一导电层之间的第一沟槽，所述第一导电层沿第一方向延伸，且沿第二方向平行排布，所述第一沟槽贯穿所述硅材料层并延伸至所述基底中；
    于所述第一沟槽中形成隔离层，所述隔离层的上表面与所述硅材料层的下表面相齐平；及
    对所述硅材料层进行处理以形成金属硅化物层；
    其中所述第一方向和所述第二方向相交，所述金属硅化物层和所述第一导电层构成第一导电结构，所述第一导电层的电阻率大于所述金属硅化物层的电阻率。
  2. 根据权利要求1所述的制备方法，其中所述第一导电层包括硅掺杂层，所述对所述硅材料层进行处理以形成金属硅化物层之后，还包括：
    采用外延掺杂工艺于所述第一导电层上形成垂直晶体管的漏极区；
    其中所述漏极区与所述第一导电层电连接；所述垂直晶体管包括位于所述漏极区上表面的沟道区和位于所述沟道区上表面的源极区。
  3. 根据权利要求2所述的制备方法，其中所述采用外延掺杂工艺于所述第一导电层上形成垂直晶体管的漏极区，包括：
    于所述第一导电层上形成叠层结构，所述叠层结构包括自第一导电层向上叠置的第一填充层、牺牲层、第二填充层，所述叠层结构中开设有多个第一通孔，所述第一通孔贯穿所述叠层结构并暴露出所述第一导电层的部分表面；以及
    采用外延掺杂工艺于所述第一通孔中形成所述漏极区；所述漏极区的上表面与所述第一填充层的上表面相齐平。
  4. 根据权利要求3所述的制备方法，其中所述采用外延掺杂工艺于所述第一通孔中形成所述漏极区之后，还包括：
    采用外延工艺于所述漏极区的上表面形成所述沟道区，所述沟道区的掺杂浓度小于所述漏极区的掺杂浓度，所述沟道区的上表面与所述牺牲层的上表面相齐平；以及
    采用外延工艺于所述沟道区的上表面形成所述源极区，所述源极区的掺杂浓度大于所述沟道区的掺杂浓度。
  5. 根据权利要求3所述的制备方法，其中所述采用外延掺杂工艺于所述第一导电层上形成所述垂直晶体管的漏极区之后，还包括：
    去除所述牺牲层；
    于所述沟道区的侧壁形成环绕所述沟道区的介质层；以及
    于所述介质层远离所述沟道区的侧壁形成第二导电层，所述第二导电层包括第二导电结构，所述第二导电结构沿所述第二方向延伸；
    其中所述介质层的上表面、所述第二导电层的上表面和所述沟道区的上表面位于同一水平面。
  6. 根据权利要求5所述的制备方法，其中所述去除所述牺牲层，包括：
    于所述叠层结构中形成多个相邻的第二沟槽，以得到由剩余牺牲层构成的牺牲图形层，所述剩余牺牲层包括位于所述沟道区的侧壁与相邻所述第二沟槽的侧壁之间的牺牲层以及位于相邻所述第二沟槽之间的牺牲层，所述第二沟槽贯穿所述第二填充层并暴露出所述第一填充层的部分表面，所述第二沟槽沿所述第二方向延伸，且沿所述第一方向平行排布；以及
    通过所述第二沟槽去除所述牺牲图形层。
  7. 根据权利要求6所述的制备方法，其中所述于所述介质层远离所述沟道区的侧壁形成第二导电层之后，还包括：
    于所述第二沟槽中填充形成第二隔离结构，所述第二隔离结构填满所述第二沟槽；
    其中所述第二隔离结构的上表面高于所述源极区的上表面。
  8. 根据权利要求5所述的制备方法，其中所述去除所述牺牲层之前，还包括：
    于所述源极区上形成源极保护层；
    所述于所述沟道区的侧壁形成环绕所述沟道区的介质层，包括：
    采用热氧工艺形成所述介质层。
  9. 根据权利要求2-8任一项所述的制备方法，其中所述采用外延掺杂工艺于所述第一导电层上形成垂直晶体管的漏极区之后，还包括：
    于所述垂直晶体管上形成电容结构，所述电容结构与所述源极区电连接。
  10. 根据权利要求1-8任一项所述的制备方法，其中所述提供基底，所述基底的上表层包括硅材料层及位于所述硅材料层上表面的导电材料层，包括：
    提供硅基底；以及
    采用离子注入于所述硅基底的上表层形成所述导电材料层；
    其中所述硅基底靠近所述导电材料层的部分为所述硅材料层。
  11. 根据权利要求1-8任一项所述的制备方法，其中所述对所述导电材料层进行图形化处理，以得到多个相邻的第一导电层及位于相邻所述第一导电层之间的第一沟槽，包括：
    于所述导电材料层上形成图形化掩膜层，所述图形化掩膜层定义出所述第一导电层的形状和位置；以及
    以所述图形化掩膜层为掩膜对所述导电材料层进行图形化处理，以得到所述第一导电层。
  12. 根据权利要求1-8任一项所述的制备方法，其中所述于所述第一沟槽中形成隔离层，包括：
    于所述第一沟槽中形成隔离材料层，所述隔离材料层的上表面与所述第一导电层的下表面相齐平；
    于所述第一导电层的顶部和侧壁形成保护层；以及
    去除所述第一沟槽中位于所述硅材料层的上表面与所述硅材料层的下表面之间的所述隔离材料层，以得到由剩余所述隔离材料层构成的所述隔离层。
  13. 根据权利要求12所述的制备方法，其中所述对所述硅材料层进行处理以形成金属硅化物层之后，还包括：
    去除所述保护层；以及
    于所述隔离层上形成第三填充层，所述第三填充层的上表面与所述第一导电层的上表面相齐平。
  14. 根据权利要求1-8任一项所述的制备方法，其中所述对所述硅材料层进行处理以形成金属硅化物层，包括：
    于所述隔离层上形成预设厚度的金属材料层；以及
    在预设温度下进行退火工艺，以使所述硅材料层与所述金属材料层反应形成所述金属硅化物层。
  15. 一种半导体结构，采用如权利要求1-14任一项所述的半导体结构的制备方法而得到，所述半导体结构包括：
    基底，所述基底的上表层包括多个相邻的金属硅化物层和位于所述金属硅化物层上表面的第一导电层，所述第一导电层沿第一方向延伸，且沿第二方向平行排布；以及
    隔离层，位于相邻所述第一导电层之间，所述隔离层的上表面与所述金属硅化物层的下表面相齐平；
    其中所述第一方向和所述第二方向相交，所述金属硅化物层和所述第一导电层构成第一导电结构，所述第一导电层的电阻率大于所述金属硅化物层的电阻率。
  16. 根据权利要求15所述的半导体结构，其中所述第一导电层包括硅掺杂层，所述半 导体结构还包括：
    垂直晶体管，所述垂直晶体管的漏极区位于所述第一导电层上，且与所述第一导电层电连接；其中所述垂直晶体管包括位于所述漏极区上表面的沟道区和位于所述沟道区上表面的源极区。
  17. 根据权利要求16所述的半导体结构，其中所述垂直晶体管还包括：
    介质层，所述介质层环绕所述沟道区的侧壁；以及
    第二导电层，所述第二导电层位于所述介质层远离所述沟道区的侧壁上，所述第二导电层包括第二导电结构，所述第二导电结构沿所述第二方向延伸；
    其中所述介质层的上表面、所述第二导电层的上表面和所述沟道区的上表面位于同一水平面。
  18. 根据权利要求16或17所述的半导体结构，其中还包括：
    电容结构，位于所述垂直晶体管上，且与所述源极区电连接。
  19. 一种电子设备，包括如权利要求15至18任一所述的半导体结构。
PCT/CN2023/092508 2023-02-14 2023-05-06 半导体结构及其制备方法、电子设备 WO2024169054A1 (zh)

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