WO2024109670A1 - 电路板组件及电路板组件的制备方法 - Google Patents
电路板组件及电路板组件的制备方法 Download PDFInfo
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- WO2024109670A1 WO2024109670A1 PCT/CN2023/132506 CN2023132506W WO2024109670A1 WO 2024109670 A1 WO2024109670 A1 WO 2024109670A1 CN 2023132506 W CN2023132506 W CN 2023132506W WO 2024109670 A1 WO2024109670 A1 WO 2024109670A1
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- Prior art keywords
- pads
- circuit board
- board assembly
- pad
- printed circuit
- Prior art date
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- 238000002360 preparation method Methods 0.000 title abstract 2
- 229910000679 solder Inorganic materials 0.000 claims description 72
- 238000000034 method Methods 0.000 claims description 22
- 230000001965 increasing effect Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 238000005476 soldering Methods 0.000 description 7
- 238000003466 welding Methods 0.000 description 6
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000005553 drilling Methods 0.000 description 3
- 230000002708 enhancing effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 101001121408 Homo sapiens L-amino-acid oxidase Proteins 0.000 description 1
- 101000827703 Homo sapiens Polyphosphoinositide phosphatase Proteins 0.000 description 1
- 102100026388 L-amino-acid oxidase Human genes 0.000 description 1
- 102100023591 Polyphosphoinositide phosphatase Human genes 0.000 description 1
- 101100233916 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) KAR5 gene Proteins 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
Definitions
- the present application belongs to the field of chip technology, and specifically relates to a circuit board assembly and a method for preparing the circuit board assembly.
- the charging power of electronic devices has increased from the ordinary 18W to the fast charging 66W, 80W, and now 120W, and even 200W. It can be seen that increasing the charging power is the key to improving the charging speed of electronic devices. While increasing the charging power of electronic devices, the current that the chip in the charging module needs to pass through also increases, from 2A for ordinary charging to 10A for super fast charging, and even higher charging currents.
- PCB printed circuit board
- holes are usually punched on the pads and surface traces are run to increase the current capacity.
- the current can reach 10A. It is difficult to meet the current capacity requirements of high current during high-power charging by punching holes on the pads and running traces on the surface. Therefore, a solution of setting vias between pads is proposed.
- the purpose of the embodiment of the present application is to provide a circuit board assembly and a method for preparing the circuit board assembly, which can The problem of poor reliability of circuit board components after improving current flow capacity is solved.
- an embodiment of the present application provides a circuit board assembly, comprising: a printed circuit board and M solder pads, the M solder pads being arranged at intervals on the printed circuit board, N of the M solder pads being provided with first vias, a second via being provided on the printed circuit board and between any two adjacent solder pads among the N solder pads, the center of the second via being offset from a center line connecting any two adjacent solder pads, M and N being integers greater than 1, and N being less than or equal to M.
- an embodiment of the present application further provides a method for preparing a circuit board assembly, the method comprising:
- a second via hole is drilled at a position between any two adjacent pads among the N pads, and the center of the second via hole deviates from the center line connecting the any two adjacent pads, to obtain a printed circuit board;
- M and N are both integers greater than 1, and N is less than or equal to M.
- M pads are spaced apart on a printed circuit board, first vias are provided on N of the M pads, and second vias are provided between any two adjacent pads of the N pads to improve the current passing capacity; at the same time, the center of the second via deviates from the center line connecting any two adjacent pads, thereby increasing the spacing distance between the second via and the pad, thereby reducing the encroachment of the second via on the pad, improving the integrity of the pad, and further enhancing the reliability of the circuit board assembly.
- FIG1 is a schematic diagram of a circuit board assembly according to an embodiment of the present invention.
- FIG. 2 is one of the physical images of the circuit board assembly provided in the embodiment of the present application.
- FIG3 is a second physical diagram of a circuit board assembly provided in an embodiment of the present application.
- FIG4 is a schematic diagram of the connection relationship between the circuit board assembly and the chip provided in an embodiment of the present application.
- FIG5 is a second schematic diagram of the structure of a circuit board assembly provided in an embodiment of the present application.
- FIG6 is a third structural schematic diagram of a circuit board assembly provided in an embodiment of the present application.
- FIG7 is a fourth structural schematic diagram of a circuit board assembly provided in an embodiment of the present application.
- FIG. 8 is a flow chart of a method for preparing a circuit board assembly provided in an embodiment of the present application.
- first, second, etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first”, “second”, etc. are generally of one type, and the number of objects is not limited.
- the first object can be one or more.
- “and/or” in the specification and claims represents at least one of the connected objects, and the character “/" generally indicates that the objects associated with each other are in an "or” relationship.
- the circuit board assembly includes: a printed circuit board 101 and M pads, the M pads are arranged on the printed circuit board 101 at intervals, and N pads 102 among the M pads are provided with first vias 103.
- a second via 104 is also provided on the printed circuit board 101 and between any two adjacent pads 102 among the N pads 102, and the center of the second via 104 deviates from the center line connecting any two adjacent pads 102.
- M and N are both integers greater than 1, and N is less than or equal to M.
- the M pads on the printed circuit board 101 further include an independent pad 105 , that is, the pad 105 is not provided with the first via 103 .
- the M pads may be arranged in an array on the printed circuit board 101 to improve the uniformity of the spacing between the pads and facilitate the subsequent arrangement of the second vias 104 between the pads.
- the first via hole 103 and the second via hole 104 may have the same size, and copper foil may be disposed on the first via hole 103 and the second via hole 104 to enhance conductivity.
- M pads are arranged at intervals on a printed circuit board 101, first vias 103 are arranged on N pads 102 among the M pads, and second vias 104 are arranged between any two adjacent pads 102 among the N pads 102 to improve the current passing capacity; at the same time, the center of the second via 104 deviates from the center line connecting any two adjacent pads 102.
- the spacing distance between the second via 104 and the pad 102 is increased, thereby reducing the encroachment of the second via 104 on the pad 102, improving the integrity of the pad 102, and further enhancing the reliability of the circuit board assembly.
- the M pads on the printed circuit board 101 can all be non-solder mask defined pads (NSMD).
- NSMD non-solder mask defined pads
- each of the M pads includes a pad body 1022 and a solder resist groove 1021, the solder resist groove 1021 surrounds the pad body 1022, and the solder resist groove 1021 is located between the pad body 1022 and the second via 104, that is, a circle of solder resist groove 1021 is arranged around the pad body 1022, wherein the solder resist groove 1021 may be formed by the gap between the ink 107 and the pad body 1022.
- the solder resist groove 1021 may separate the pad body 1022 and the surrounding ink 107 by a certain distance, and when the pad body 1022 is welded to the material end (e.g., the pad 401 on the chip), the excess solder paste may flow into the solder resist groove 1021, thereby reducing the occurrence of tinning between adjacent pads.
- the ink 107 may be a barrier layer provided on the printed circuit board and having acid corrosion resistance and alkali corrosion resistance.
- the ink 107 may prevent circuit corrosion and protect the circuit during the etching process.
- the second via 104 provided on the printed circuit board 101 is located between any two adjacent pads 102 among the N pads 102, and is easy to encroach on the adjacent pads 102, and the encroachment on the solder resist groove 1021 is particularly serious. Due to the encroachment of the second via 104, only part of the solder resist groove 1021 is retained, and when the excess solder paste cannot flow into the solder resist groove 1021, solder paste is easy to accumulate, resulting in the situation that different pads are connected and short-circuited, and then the terminal device fails in function.
- the second via hole 104 is disposed between any two adjacent pads 102 among the N pads 102, and the center of the second via hole 104 deviates from the center of any two adjacent pads 102.
- the center connection line is formed to increase the spacing distance between the second via hole 104 and the solder resist groove 1021, reduce the encroachment of the second via hole 104 on the solder resist groove 1021, and improve the integrity of the pad 102 and the solder resist groove 1021, thereby improving the shape of the solder joint, solving the problems of cold solder joint and bridging solder during welding, thereby improving the welding reliability of the PCB board.
- first via 103 and the second via 104 are electrically connected via a wiring 106 .
- a first via 103 is set on N solder pads 102 among M solder pads
- a second via 104 is set between any two adjacent solder pads 102 among the N solder pads 102
- a trace 106 is set between the first via 103 and the second via 104, so that signals can be transmitted between adjacent solder pads 102 through the trace 106.
- the center of the second via 104 deviates from the center line of any two adjacent pads 102, so that the second via 104 is staggered between any two adjacent pads 102, and the trace 106 led out from the first via 103 of each pad of the two adjacent pads 102 can extend toward the location of the second via 104 to be electrically connected to the second via 104, so as to reduce redundant traces between the pads 102, and avoid the situation where the trace 106 and the second via 104 invade the pad 102 from different directions when the trace 106 and the second via 104 are located in different directions of the pad 102, thereby improving the integrity of the pad 102 and the solder resist groove 1021. While improving the current passing capacity, the circuit board assembly has higher reliability.
- the second via 104 is connected to one of any two adjacent pads 102 among the N pads 102 through a first routing line, and the second via 104 is connected to the other of any two adjacent pads 102 among the N pads 102 through a second routing line, and the angle between the first routing line and the second routing line is greater than or equal to 90 degrees.
- the second via 104 is disposed between any two adjacent pads 102 among the N pads 102, and the center of the second via 104 deviates from the center line connecting any two adjacent pads 102, and the routing 106 includes a first routing and a second routing, so that one of any two adjacent pads 102 among the N pads 102 can be extended to be electrically connected to the second via 104 through the first routing, and the other of any two adjacent pads 102 among the N pads 102 can be extended to be electrically connected to the second via 104 through the second routing, and the angle between the first routing and the second routing is greater than or equal to 90 degrees, thereby reducing the situation where the routing 106 and the second via 104 encroach on the pad 102 from different directions, thereby The integrity of the pad 102 and the solder resist groove 1021 is improved.
- the circuit board assembly has higher reliability while improving the current flow capacity.
- the second via hole 104 is disposed in a central area of any L adjacently disposed pads 102 among the N pads 102 , where L is an integer greater than 1 and less than or equal to N.
- the second via 104 can be disposed in the central area of any three adjacent pads 102 among the N pads 102, the three pads 102 can be distributed in a triangle, and the second via 104 can be located in the middle area of the triangle.
- the center of the second via 104 deviates from the center line connecting any two adjacent pads 102 among the three pads 102, thereby reducing the encroachment of the second via 104 on any of the three pads 102, and the trace 106 led out from the first via 103 of each of the three pads 102 can be directed toward the second via.
- the position of 104 extends to be electrically connected to the second via 104, which reduces the situation where the trace 106 and the second via 104 invade the pad 102 from different directions, thereby improving the regularity of the pad 102, improving the shape of the solder joint, and reducing the situation where the pad 102 on the PCB is larger in area and the solder ball size at the material end is smaller, and the solder joint is in the shape of an inverted funnel, resulting in poor stress resistance of the circuit board assembly; and increasing the integrity of the solder mask groove 1021, reducing the situation where excess solder paste cannot flow into the solder mask groove 1021 and accumulates, thereby improving the reliability of the circuit board assembly.
- the three pads 102 can be distributed in an equilateral triangle, and the second via 104 can be located at the center point of the equilateral triangle, so that the center of the second via 104 is equal to the first distance D1 of the center of each of the three pads 102.
- the influence of the same second via 104 on each of the three pads 102 can be dispersed.
- the traces 106 of each of the three pads 102 extending from the first via 103 can extend toward the location of the second via 104 to be electrically connected to the second via 104, so as to reduce redundant traces between the three pads 102. Since the first distance D1 between each of the three pads 102 and the second via 104 is equal, the length of the traces 106 between each pad 102 and the second via 104 is uniform, further improving the regularity of the pads 102 and the integrity of the solder resist groove 1021. While improving the current passing capacity, the circuit board assembly has higher reliability.
- the second via 104 can be arranged in the central area of any four adjacent pads 102 among the N pads 102, the four pads 102 can be distributed in a rectangular shape, and the second via 104 can be located in the middle area of the rectangle.
- the center of the second via 104 deviates from the center line connecting any two adjacent pads 102 among the four pads 102, thereby reducing the encroachment of the second via 104 on any of the four pads 102, and the trace 106 led out from the first via 103 of each of the four pads 102 can be directed toward
- the position of the second via 104 extends to be electrically connected to the second via 104, and the pads 102 at the diagonal position can also be connected by sharing the same routing 106, thereby reducing the redundant routing between the four pads 102, and reducing the situation where the routing 106 and the second via 104 invade the pad 102 from different directions, thereby improving the regularity of the pad 102, increasing the integrity of the solder resist groove 1021, and reducing the
- the four pads 102 can be distributed in a square shape, and the second via 104 can be located at the intersection of the diagonal lines of the square, so that the center of the second via 104 is equal to the first distance D1 of the center of each of the four pads 102.
- the influence of the same second via 104 on each of the four pads 102 can be dispersed.
- the length of the trace 106 between each pad 102 and the second via 104 is made uniform, further improving the regularity of the pad 102 and the integrity of the solder resist groove 1021. While improving the current flow capacity, the circuit board assembly has higher reliability.
- the second via 104 may be disposed in the central area of any five adjacent pads 102 among the N pads 102, the five pads 102 may be distributed in a pentagon, and the second via 104 may be located in the middle area of the pentagon.
- the center of the second via 104 deviates from the center line connecting any two adjacent pads 102 among the five pads 102, thereby reducing the encroachment of the second via 104 on any of the five pads 102, and the trace 106 led out from the first via 103 of each of the five pads 102 may extend toward the location of the second via 104 to be electrically connected to the second via 104, thereby reducing the redundant traces between the five pads 102, and reducing the situation where the trace 106 and the second via 104 encroach on the pad 102 from different directions, thereby improving the regularity of the pad 102.
- the integrity of the solder resist groove 1021 is increased, and the accumulation of excess solder paste that cannot flow into the solder resist groove 1021 is reduced, thereby improving the reliability of the circuit board assembly.
- the five pads 102 can be distributed in a regular pentagon, and the second via 104 can be located at the center point of the regular pentagon, so that the center of the second via 104 is equal to the first distance D1 of the center of each of the five pads 102.
- the influence of the same second via 104 on each of the five pads 102 can be dispersed.
- the length of the trace 106 between each pad 102 and the second via 104 is uniform, further improving the regularity of the pad 102 and the integrity of the solder resist groove 1021. While improving the current flow capacity, the circuit board assembly has higher reliability.
- the second via 104 may be disposed in the central area of any six adjacent pads 102 among the N pads 102, the six pads 102 may be distributed in a hexagon, and the second via 104 may be located in the middle area of the hexagon.
- the center of the second via 104 deviates from the center line connecting any two adjacent pads 102 among the six pads 102, thereby reducing the encroachment of the second via 104 on any of the six pads 102, and the trace 106 led out from the first via 103 to each of the six pads 102, It can extend toward the position of the second via 104 to be electrically connected to the second via 104, and the pads 102 at the diagonal position can also be connected by sharing the same routing 106, thereby reducing redundant routing between the six pads 102, and reducing the situation where the routing 106 and the second via 104 invade the pad 102 from different directions, thereby improving the regularity of the pad 102, increasing the integrity of the solder resist groove 1021, and reducing the situation where excess solder paste cannot flow into the solder resist groove 1021 and accumulates, thereby improving the reliability of the circuit board assembly.
- the six pads 102 can be distributed in a regular hexagon, and the second via 104 can be located at the intersection of the diagonals of the regular hexagon, so that the first distance D1 between the center of the second via 104 and the center of each of the six pads 102 is equal.
- the influence of the same second via 104 on each of the six pads 102 can be dispersed.
- the length of the trace 106 between each pad 102 and the second via 104 is uniform, which further improves the pad 102.
- the regularity and integrity of the solder resist groove 1021 While improving the current carrying capacity, the circuit board assembly has higher reliability.
- the second via 104 is arranged in the central area of any L adjacent pads 102 among the N pads 102.
- L can also be other numbers, such as 8, 9, 12, etc., which can be adjusted according to actual conditions and can also achieve the same technical effect, which will not be repeated here.
- first distance D1 between the center of the second via 104 and the center of each of the L pads 102
- second distance D2 between the centers of any two adjacent pads 102 among the L pads 102.
- the ratio of the first distance D1 to the second distance D2 is greater than 1:2, so as to increase the spacing distance between the second via 104 and the pad 102, reduce the encroachment of the second via 104 on the pad 102 and/or the solder resist groove 1021, and improve the integrity of the pad 102 and the solder resist groove 1021, thereby improving the morphology of the solder joint, solving the problems of cold solder joints and bridging during soldering, and thus improving the reliability of the circuit board assembly.
- the size of the trace 106 is smaller than or equal to the size of the pad 102 , and/or the size of the trace 106 is smaller than or equal to the size of the second via 104 .
- the size of the routing 106 is made smaller than or equal to the size of the pad 102, and/or the size of the routing 106 is smaller than or equal to the size of the second via 104, thereby reducing the situation where the routing 106 and the pad 102 have large-area interference, resulting in poor integrity of the solder resist groove 1021.
- the PCB surface routing and the increase of vias are realized to achieve the effect of increasing the current flow capacity, and the size and integrity of the solder resist groove 1021 are retained to the maximum extent, thereby improving the problems of bridging tin and cold soldering that may occur during welding.
- the number of the second via holes 104 adjacent to each of the N pads 102 is less than or equal to two.
- the N pads 102 may include a plurality of pad networks, and a pad network may include at least two pads 102.
- a second via 104 may be provided between any two adjacent pads 102 of the at least two pads 102, so that the center of the second via 104 deviates from the center line connecting any two adjacent pads 102.
- the trace 106 led out of each pad of the two adjacent pads 102 extends toward the location of the second via 104 to be electrically connected to the second via 104, and the line width of the trace 106 may be
- the width of the second vias 104 is less than or equal to the width of the pad 102, and the number of the second vias 104 electrically connected to each pad 102 is less than or equal to two.
- one or more pads 102 can be connected to an independent pad 105 through a trace 106 according to actual needs, and a second via 104 can be set on the trace 106 between the pad 102 and the independent pad 105, so that the traces led out of the independent pad 105 are oriented toward the second via 104, and the traces led out of the pad 102 are oriented toward the second via 104, reducing the redundant traces between the pad 102 and the independent pad 105, reducing the invasion of the pad by the trace 106 and the second via 104, and thus improving the integrity of the pad. While improving the current flow capacity, the circuit board assembly has a higher reliability.
- FIG. 8 is a flow chart of a method for preparing a circuit board assembly provided in an embodiment of the present application, which is used to prepare the above-mentioned circuit board assembly, and the method includes:
- Step 801 obtaining a first printed circuit board to be prepared, wherein M pads are arranged at intervals on the first printed circuit board to be prepared, and first vias are arranged on N pads of the M pads;
- the first printed circuit board to be prepared can be a PCB board to be processed on which the second via hole has not yet been set.
- the M soldering pads can be arranged in an array of the first printed circuit board to be prepared, and N of the M soldering pads are provided with first via holes so that subsequent welding can be performed through the soldering pads and the material end.
- Step 802 On the first printed circuit board to be prepared, a second via hole is drilled between any two adjacent pads among the N pads, and the center of the second via hole deviates from the center line of the any two adjacent pads, to obtain a printed circuit board;
- M and N are both integers greater than 1, and N is less than or equal to M.
- the current carrying capacity of the circuit board assembly can be improved by setting vias, and the second via is located between any two adjacent pads, and the center of the second via deviates from the center line of any two adjacent pads to reduce the encroachment of the second via on the pad and improve the morphology of the solder joint.
- the first printed circuit board to be prepared M pads are provided, and first vias are provided on N pads among the M pads.
- a second via is punched between any two adjacent pads among the N pads of the first printed circuit board to be prepared to improve the current passing capacity, and the center of the second via deviates from the center line of any two adjacent pads, so as to obtain a printed circuit board.
- the spacing distance between the second via and the pad is increased, thereby reducing the encroachment of the second via on the pad, improving the integrity of the pad, and further enhancing the reliability of the circuit board assembly.
- a second via hole is punched at a position between any two adjacent pads among the N pads, and the center of the second via hole deviates from the center line connecting the any two adjacent pads, to obtain a printed circuit board, comprising:
- a second via hole is drilled between any two adjacent pads among the N pads, and the center of the second via hole deviates from the center line of the any two adjacent pads, to obtain a second printed circuit board to be prepared;
- the second printed circuit boards to be prepared are connected by wires to obtain a printed circuit board, wherein the wiring between any two adjacent pads on the printed circuit board extends toward the location of the second via hole to be electrically connected to the second via hole.
- a routing line can be arranged between two adjacent pads, and the routing line led out of each of the two adjacent pads is extended toward the location of the second via hole to be electrically connected to the via hole, so as to reduce redundant routing lines between pads, and avoid the situation where the routing line and the via hole invade the pad from different directions when the routing line and the via hole are located in different directions of the pad, thereby improving the integrity of the pad. While improving the current passing capacity, the circuit board assembly has higher reliability.
- a second via hole is punched at a position between any two adjacent pads among the N pads, and the center of the second via hole deviates from the center line of the any two adjacent pads, to obtain a printed circuit board, comprising:
- the target area is a position between any two adjacent pads among the N pads, and the target area deviates from a center line connecting the any two adjacent pads.
- the interference of the second via with adjacent pads among the N pads is taken into consideration.
- the interference of the second via with the pad is less than the target threshold, that is, when the spacing between any two adjacent pads among the N pads is large, a second via can be set between the two pads. Otherwise, drilling is not performed, thereby improving the integrity of the pad.
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Abstract
一种电路板组件及电路板组件的制备方法，属于芯片技术领域，电路板组件包括：印制电路板（101）和M个焊盘，M个焊盘间隔设置于印制电路板（101）上，M个焊盘中的N个焊盘（102）上设置有第一过孔（103），印制电路板（101）上，且N个焊盘（102）中任意两个相邻的焊盘（102）之间的位置还设置有第二过孔（104），第二过孔（104）的中心偏离任意两个相邻的焊盘（102）的中心连线，M和N均为大于1的整数，且N小于或等于M。
Description
相关申请的交叉引用
本申请主张在2022年11月25日在中国提交的中国专利申请No.202211493981.9的优先权，其全部内容通过引用包含于此。
本申请属于芯片技术领域，具体涉及电路板组件及电路板组件的制备方法。
随着电子技术的发展，消费者对手机等电子设备充电速度的要求越来越高。电子设备的充电功率由普通的18W到快充的66W、80W，再到现在的120W，甚至是200W，由此可见增加充电功率，是提升电子设备充电速度的关键。而增加电子设备充电功率的同时，充电模块中的芯片需要通过的电流也随之增大，从普充的2A到超级快充的10A，乃至更大的充电电流。
在印制电路板(Printed Circuit Board，PCB)设计时，通常在焊盘上打孔以及表层走线，以增加过流能力；但是对于像120W甚至200W功率的情况，电流可以达到10A，通过在焊盘上打孔以及表层走线的方式，已经难以满足大功率充电时大电流的过流能力要求。因此，提出了在在焊盘间设置过孔的方案。
然而，相关技术中在焊盘间设置过孔的方案，提升了大功率充电时大电流的过流能力，但是在实际制作后PCB的焊接可靠性存在明显的不足。例如，焊盘周围被走线和过孔占据，导致焊盘间出现虚焊或连锡而短路等情况。可见，在提升电流过流能力后电路板组件的可靠性较差。
发明内容
本申请实施例的目的是一种电路板组件及电路板组件的制备方法，能够
解决在提升电流过流能力后电路板组件的可靠性较差的问题。
第一方面，本申请实施例提供了一种电路板组件，包括：印制电路板和M个焊盘，所述M个焊盘间隔设置于所述印制电路板上，所述M个焊盘中的N个焊盘上设置有第一过孔，所述印制电路板上，且所述N个焊盘中任意两个相邻的焊盘之间的位置还设置有第二过孔，所述第二过孔的中心偏离所述任意两个相邻的焊盘的中心连线，M和N均为大于1的整数，且N小于或等于M。
第二方面，本申请实施例还提供了一种电路板组件的制备方法，所述方法包括：
获取第一待制备印制电路板，所述第一待制备印制电路板上间隔设置有M个焊盘，所述M个焊盘中的N个焊盘上设置有第一过孔；
在所述第一待制备印制电路板上，所述N个焊盘中任意两个相邻的焊盘之间的位置打第二过孔，且所述第二过孔的中心偏离所述任意两个相邻的焊盘的中心连线，得到印制电路板；
其中，M和N均为大于1的整数，且N小于或等于M。
本申请实施例中，将M个焊盘间隔设置于印制电路板上，在M个焊盘中的N个焊盘上设置上第一过孔，并在N个焊盘中任意两个相邻的焊盘之间的位置设置有第二过孔，以提升电流过流能力；同时，第二过孔的中心偏离任意两个相邻的焊盘的中心连线，这样，增加了第二过孔与焊盘之间的间隔距离，从而减少第二过孔对焊盘的侵占，提升了焊盘的完整性，进而增强了电路板组件的可靠性。
图1是本申请实施例提供的电路板组件的结构示意图之一；
图2是本申请实施例提供的电路板组件的实物图之一；
图3是本申请实施例提供的电路板组件的实物图之二；
图4是本申请实施例提供的电路板组件与芯片的连接关系示意图；
图5是本申请实施例提供的电路板组件的结构示意图之二；
图6是本申请实施例提供的电路板组件的结构示意图之三；
图7是本申请实施例提供的电路板组件的结构示意图之四；
图8是本申请实施例提供的电路板组件的制备方法的流程图。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施，且“第一”、“第二”等所区分的对象通常为一类，并不限定对象的个数，例如第一对象可以是一个，也可以是多个。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
请参阅图1，图1是本申请实施例提供的电路板组件的结构示意图之一，如图1所示，电路板组件包括：印制电路板101和M个焊盘，M个焊盘间隔设置于印制电路板101上，M个焊盘中的N个焊盘102上设置有第一过孔103，印制电路板101上，且N个焊盘102中任意两个相邻的焊盘102之间的位置还设置有第二过孔104，第二过孔104的中心偏离任意两个相邻的焊盘102的中心连线，M和N均为大于1的整数，且N小于或等于M。
其中，印制电路板101上的M个焊盘中，还包括独立的焊盘105，即焊盘105上未设置第一过孔103。
其中，M个焊盘在印制电路板101上可以是阵列设置的，以提升焊盘之间间距的均匀性，便于后续在焊盘之间设置第二过孔104。
其中，第一过孔103和第二过孔104的尺寸可以相同，第一过孔103和第二过孔104上可以设置有铜箔，以增强导电性。
在本申请实施例中，将M个焊盘间隔设置于印制电路板101上，在M个焊盘中的N个焊盘102上设置上第一过孔103，并在N个焊盘102中任意两个相邻的焊盘102之间的位置设置有第二过孔104，以提升电流过流能力；同时，第二过孔104的中心偏离任意两个相邻的焊盘102的中心连线，这样，相较于将第二过孔设置在任意两个相邻焊盘的中心连线上的方式，增加了第二过孔104与焊盘102之间的间隔距离，从而减少第二过孔104对焊盘102的侵占，提升了焊盘102的完整性，进而增强了电路板组件的可靠性。
可选地，印制电路板101上的M个焊盘均可以是非阻焊定义焊盘(Non-Solder Mask Defined Pad，NSMD)。
如图3和图4所示，M个焊盘中每个焊盘(包括焊盘102和焊盘105)包括焊盘本体1022和阻焊槽1021，阻焊槽1021环绕焊盘本体1022，且阻焊槽1021位于焊盘本体1022与第二过孔104之间，即在焊盘本体1022周围设置有一圈阻焊槽1021，其中，阻焊槽1021可以是由油墨107与焊盘本体1022之间的间隙构成的。通过阻焊槽1021可以将焊盘本体1022和周围油墨107隔开一定距离，在焊盘本体1022与物料端(例如芯片上的焊盘401)焊接时，多余的锡膏可以流入该阻焊槽1021，减少相邻的焊盘之间出现连锡的情况。
其中，油墨107可以是设置在印制电路板上的具有耐酸腐蚀性和耐碱腐蚀性的阻挡层，通过油墨107可以防止电路腐蚀，并在蚀刻过程中保护电路。
在印制电路板101上设置的第二过孔104，位于N个焊盘102中任意两个相邻的焊盘102之间，容易侵占相邻的焊盘102，其中，对阻焊槽1021的侵占尤为严重。由于受到第二过孔104的侵占，阻焊槽1021只有局部被保留，当多余的锡膏无法流入阻焊槽1021时，容易发生锡膏堆积，从而导致不同焊盘之间连锡而短路的情况，进而导致终端设备功能上的失效。
在一示例中，将第二过孔104设置于N个焊盘102中任意两个相邻的焊盘102之间，并使得第二过孔104的中心偏离任意两个相邻的焊盘102的中
心连线，以增加了第二过孔104与阻焊槽1021之间的间隔距离，减少了第二过孔104对阻焊槽1021的侵占，提升了焊盘102和阻焊槽1021的完整性，从而改善焊点的形态，解决焊接时的虚焊和连锡问题，从而提升PCB板的焊接可靠性。
可选地，第一过孔103与第二过孔104之间通过走线106电连接。
在一示例中，在M个焊盘中的N个焊盘102上设置上第一过孔103，在N个焊盘102中任意两个相邻的焊盘102之间的位置设置有第二过孔104，并在第一过孔103与第二过孔104之间设置走线106，使得相邻的焊盘102之间可以通过走线106进行信号传输。其中，第二过孔104的中心偏离任意两个相邻的焊盘102的中心连线，使得第二过孔104交错于任意相邻两个焊盘102之间，相邻两个焊盘102中各焊盘自第一过孔103引出的走线106，可以朝向第二过孔104所在位置延伸至与第二过孔104电连接，以减少焊盘102之间冗余的走线，避免走线106和第二过孔104分别位于焊盘102的不同方向时，走线106和过第二过孔104从不同方向对焊盘102进行侵占的情况，从而提升了焊盘102和阻焊槽1021的完整性。在提升电流过流能力的同时电路板组件具有较高的可靠性。
可选地，第二过孔104与N个焊盘102中任意两个相邻的焊盘102中的一者通过第一走线连接，第二过孔104与N个焊盘102中任意两个相邻的焊盘102中的另一者通过第二走线连接，第一走线和所述第二走线之间的夹角大于或等于90度。
在一示例中，第二过孔104设置在N个焊盘102中任意两个相邻的焊盘102之间，且第二过孔104的中心偏离任意两个相邻的焊盘102的中心连线，走线106包括第一走线和第二走线，这样，N个焊盘102中任意两个相邻的焊盘102中的一者可以通过第一走线延伸至与第二过孔104电连接，N个焊盘102中任意两个相邻的焊盘102中的另一者可以通过第二走线延伸至与第二过孔104电连接，且第一走线和所述第二走线之间的夹角大于或等于90度，减少走线106和过第二过孔104从不同方向对焊盘102进行侵占的情况，从
而提升了焊盘102和阻焊槽1021的完整性。在提升电流过流能力的同时电路板组件具有较高的可靠性。
可选地，第二过孔104设置于N个焊盘102中任意相邻设置的L个焊盘102的中心区域，L为大于1，且小于或等于N的整数。
在一示例中，如图5所示，第二过孔104可以设置于N个焊盘102中任意相邻设置的三个焊盘102的中心区域，三个焊盘102可以呈三角形分布，第二过孔104可以位于三角形的中间区域，换言之，第二过孔104的中心偏离这三个焊盘102中任意两个相邻的焊盘102的中心连线，减少了第二过孔104对这三个焊盘102中任一者的侵占，且这三个焊盘102各焊盘自第一过孔103引出的走线106，可以朝向第二过孔104所在位置延伸至与第二过孔104电连接，减少了走线106和第二过孔104从不同方向对焊盘102进行侵占的情况，从而提升了焊盘102的规则度，改善了焊点的形态，减少了PCB上焊盘102面积较大而物料端的焊球尺寸较小、焊点呈倒扣的漏斗状，导致电路板组件抗应力的能力较差的情况；以及增加了阻焊槽1021的完整性，减少多余的锡膏无法流入阻焊槽1021而发生堆积的情况，进而提升电路板组件的可靠性。
其中，三个焊盘102可以呈正三角形分布，第二过孔104可以位于正三角形的中心点位置，使得第二过孔104的中心与三个焊盘102中每一个焊盘102的中心的第一距离D1相等，这样，在第二过孔104与焊盘102存在干涉，和/或，第二过孔104与阻焊槽1021存在干涉的情况下，可以分散同一个第二过孔104作用在三个焊盘102中每个焊盘上的影响。并这三个焊盘102各焊盘自第一过孔103引出的走线106，可以朝向第二过孔104所在位置延伸至与第二过孔104电连接，以减少三个焊盘102之间冗余的走线，由于三个焊盘102中每一个焊盘102与第二过孔104之间的第一距离D1相等，使得每个焊盘102与第二过孔104之间的走线106长度均匀，进一步提升了焊盘102的规则度和阻焊槽1021的完整性。在提升电流过流能力的同时电路板组件具有较高的可靠性。
在另一示例中，第二过孔104可以设置于N个焊盘102中任意相邻设置的四个焊盘102的中心区域，四个焊盘102可以呈矩形分布，第二过孔104可以位于矩形的中间区域，换言之，第二过孔104的中心偏离这四个焊盘102中任意两个相邻的焊盘102的中心连线，减少了第二过孔104对这四个焊盘102中任一者的侵占，且这四个焊盘102各焊盘自第一过孔103引出的走线106，可以朝向第二过孔104所在位置延伸至与第二过孔104电连接，对角线位置的焊盘102也可以通过共用相同走线106的方式进行连接，从而减少了四个焊盘102之间冗余的走线，减少了走线106和第二过孔104从不同方向对焊盘102进行侵占的情况，从而提升了焊盘102的规则度，增加了阻焊槽1021的完整性，减少多余的锡膏无法流入阻焊槽1021而发生堆积的情况，进而提升电路板组件的可靠性。
其中，四个焊盘102可以呈正方形分布，第二过孔104可以位于正方形的对角线的交点位置，使得第二过孔104的中心与四个焊盘102中每一个焊盘102的中心的第一距离D1相等，这样，在第二过孔104与焊盘102存在干涉，和/或，第二过孔104与阻焊槽1021存在干涉的情况下，可以分散同一个第二过孔104作用在四个焊盘102中每个焊盘上的影响。且使得每个焊盘102与第二过孔104之间的走线106长度均匀，进一步提升了焊盘102的规则度和阻焊槽1021的完整性。在提升电流过流能力的同时电路板组件具有较高的可靠性。
在另一示例中，如图6所示，第二过孔104可以设置于N个焊盘102中任意相邻设置的五个焊盘102的中心区域，五个焊盘102可以呈五边形分布，第二过孔104可以位于五边形的中间区域，换言之，第二过孔104的中心偏离这五个焊盘102中任意两个相邻的焊盘102的中心连线，减少了第二过孔104对这五个焊盘102中任一者的侵占，且这五个焊盘102各焊盘自第一过孔103引出的走线106，可以朝向第二过孔104所在位置延伸至与第二过孔104电连接，减少了五个焊盘102之间冗余的走线，减少了走线106和第二过孔104从不同方向对焊盘102进行侵占的情况，从而提升了焊盘102的规
则度，增加了阻焊槽1021的完整性，减少多余的锡膏无法流入阻焊槽1021而发生堆积的情况，进而提升电路板组件的可靠性。
其中，五个焊盘102可以呈正五边形分布，第二过孔104可以位于正五边形的中心点位置，使得第二过孔104的中心与五个焊盘102中每一个焊盘102的中心的第一距离D1相等，这样，在第二过孔104与焊盘102存在干涉，和/或，第二过孔104与阻焊槽1021存在干涉的情况下，可以分散同一个第二过孔104作用在五个焊盘102中每个焊盘上的影响。且使得每个焊盘102与第二过孔104之间的走线106长度均匀，进一步提升了焊盘102的规则度和阻焊槽1021的完整性。在提升电流过流能力的同时电路板组件具有较高的可靠性。
在另一示例中，如图7所示，第二过孔104可以设置于N个焊盘102中任意相邻设置的六个焊盘102的中心区域，六个焊盘102可以呈六边形分布，第二过孔104可以位于六边形的中间区域，换言之，第二过孔104的中心偏离这六个焊盘102中任意两个相邻的焊盘102的中心连线，减少了第二过孔104对这六个焊盘102中任一者的侵占，且这六个焊盘102各焊盘自第一过孔103引出的走线106，可以朝向第二过孔104所在位置延伸至与第二过孔104电连接，对角线位置的焊盘102也可以通过共用相同走线106的方式进行连接，从而减少了六个焊盘102之间冗余的走线，减少了走线106和第二过孔104从不同方向对焊盘102进行侵占的情况，从而提升了焊盘102的规则度，增加了阻焊槽1021的完整性，减少多余的锡膏无法流入阻焊槽1021而发生堆积的情况，进而提升电路板组件的可靠性。
其中，六个焊盘102可以呈正六边形分布，第二过孔104可以位于正六边形的对角线的交点位置，使得第二过孔104的中心与六个焊盘102中每一个焊盘102的中心的第一距离D1相等，这样，在第二过孔104与焊盘102存在干涉，和/或，第二过孔104与阻焊槽1021存在干涉的情况下，可以分散同一个第二过孔104作用在六个焊盘102中每个焊盘上的影响。且使得每个焊盘102与第二过孔104之间的走线106长度均匀，进一步提升了焊盘102
的规则度和阻焊槽1021的完整性。在提升电流过流能力的同时电路板组件具有较高的可靠性。
需要说明的是，第二过孔104设置于N个焊盘102中任意相邻设置的L个焊盘102的中心区域，L还可以是其他数量，例如8、9、12等，可以根据实际情况进行调整，同样可以达到相同的技术效果，在此不再赘述。
其中，第二过孔104的中心与L个焊盘102中每一个焊盘102的中心之间具有第一距离D1，L个焊盘102中任意两个相邻的焊盘102的中心之间具有第二距离D2，第一距离D1与第二距离D2之间的比值大于1:2，以增加了第二过孔104与焊盘102之间的间隔距离，减少了第二过孔104对焊盘102和/或阻焊槽1021的侵占，提升了焊盘102和阻焊槽1021的完整性，从而改善焊点的形态，解决焊接时的虚焊和连锡问题，从而提升电路板组件的可靠性。
可选地，走线106的尺寸小于或等于焊盘102的尺寸，和/或，走线106的尺寸小于或等于第二过孔104的尺寸。
在本申请实施例中，通过减小M个焊盘中各焊102之间的走线106的宽度，使得走线106的尺寸小于或等于焊盘102的尺寸，和/或，走线106的尺寸小于或等于第二过孔104的尺寸，从而减少走线106与焊盘102发生大面积干涉导致阻焊槽1021的完整性较差的情况，这样既实现PCB表层走线和增加过孔，达到增加过流能力的效果，也最大限度的保留了阻焊槽1021的大小和完整，改善焊接时会产生的连锡虚焊等问题。
可选地，N个焊盘102中每个焊盘102相邻的第二过孔104的数量小于或等于两个。
在本申请实施例中，N个焊盘102可以包括多个焊盘网络，一个焊盘网络可以包括至少两个焊盘102，这至少两个焊盘102中任意相邻的两个焊盘102之间可以设置有第二过孔104，使得第二过孔104的中心偏离任意两个相邻的焊盘102的中心连线。并使得相邻两个焊盘102中各焊盘引出的走线106朝向第二过孔104所在位置延伸至与第二过孔104电连接，走线106线宽可
以小于等于焊盘102的宽度，且每个焊盘102电连接的第二过孔104的数量小于或等于两个。这样既实现在PCB表层走线和增加过孔，达到增加过流能力的效果，也最大限度保留住阻焊槽1021的大小和完整，改善焊接时会产生的连锡虚焊等问题，提高电路板组件的可靠性。
其中，在PCB设计时，可以根据实际需求将一个或多个焊盘102与独立的焊盘105通过走线106连接，且可以在焊盘102与独立的焊盘105之间的走线106上设置第二过孔104，使得独立的焊盘105引出的走线朝向该第二过孔104、焊盘102引出的走线朝向该第二过孔104，减少了焊盘102与独立的焊盘105之间冗余的走线，减少了走线106和第二过孔104对焊盘进行侵占，从而提升了焊盘的完整性。在提升电流过流能力的同时电路板组件具有较高的可靠性。
请参阅图8，图8是本申请实施例提供的电路板组件的制备方法的流程图，用于制备上述的电路板组件，所述方法包括：
步骤801、获取第一待制备印制电路板，所述第一待制备印制电路板上间隔设置有M个焊盘，所述M个焊盘中的N个焊盘上设置有第一过孔；
该步骤中，第一待制备印制电路板可以是还未设置第二过孔的待加工的PCB板，通过在第一待制备印制电路板上设置M个焊盘，M个焊盘可以在第一待制备印制电路板阵列设置，且M个焊盘中的N个焊盘上设置有第一过孔，以便于后续可以通过焊盘与物料端进行焊接。
步骤802、在所述第一待制备印制电路板上，所述N个焊盘中任意两个相邻的焊盘之间的位置打第二过孔，且所述第二过孔的中心偏离所述任意两个相邻的焊盘的中心连线，得到印制电路板；
其中，M和N均为大于1的整数，且N小于或等于M。
该步骤中，可以通过设置过孔的方式提升电路板组件过流能力，且第二过孔位于任意两个相邻的焊盘之间，第二过孔的中心偏离任意两个相邻的焊盘的中心连线，以减少过第二孔对焊盘的侵占，改善了焊点的形态。
在本申请实施例中，在PCB的设计过程中，在第一待制备印制电路板上
设置M个焊盘，M个焊盘中的N个焊盘上设置有第一过孔，通过在第一待制备印制电路板的N个焊盘中任意两个相邻的焊盘之间的位置打第二过孔，以提升电流过流能力，且第二过孔的中心偏离任意两个相邻的焊盘的中心连线，得到印制电路板，印制电路板中，增加了第二过孔与焊盘之间的间隔距离，从而减少第二过孔对焊盘的侵占，提升了焊盘的完整性，进而增强了电路板组件的可靠性。
其中，在所述第一待制备印制电路板上，所述N个焊盘中任意两个相邻的焊盘之间的位置打第二过孔，且所述第二过孔的中心偏离所述任意两个相邻的焊盘的中心连线，得到印制电路板，包括：
在所述第一待制备印制电路板上，所述N个焊盘中任意两个相邻的焊盘之间的位置打第二过孔，且所述第二过孔的中心偏离所述任意两个相邻的焊盘的中心连线，得到第二待制备印制电路板；
在所述第二待制备印制电路板之间连线，得到印制电路板，所述印制电路板上，任意相邻两个焊盘之间的走线均朝向所述第二过孔所在位置延伸至与所述第二过孔电连接。
这样，在相邻两个焊盘之间可以设置走线，且使得相邻两个焊盘中各焊盘引出的走线朝向第二过孔所在位置延伸至与过孔电连接，以减少焊盘之间冗余的走线，避免走线和过孔分别位于焊盘的不同方向时，走线和过孔从不同方向对焊盘进行侵占的情况，从而提升了焊盘的完整性。在提升电流过流能力的同时电路板组件具有较高的可靠性。
可选地，所述在所述第一待制备印制电路板上，所述N个焊盘中任意两个相邻的焊盘之间的位置打第二过孔，且所述第二过孔的中心偏离所述任意两个相邻的焊盘的中心连线，得到印制电路板，包括：
在所述第一待制备印制电路板上的目标区域满足打过孔条件的情况下，在所述目标区域打第二过孔，得到印制电路板；
其中，所述目标区域为所述N个焊盘中任意两个相邻的焊盘之间的位置，且所述目标区域偏离所述任意两个相邻的焊盘的中心连线。
在本申请实施例中，在对第一待制备印制电路板上的目标区域进行打第二过孔时，考虑了第二过孔对N个焊盘中相邻的焊盘的干涉情况，在第二过孔对焊盘的干涉小于目标阈值，即N个焊盘中任意相邻的两个焊盘之间间距较大的情况下，可以在这两个焊盘之间设置第二过孔，相反，则不进行打孔，从而，提升了焊盘的完整性。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。此外，需要指出的是，本申请实施方式中的方法和装置的范围不限按示出或讨论的顺序来执行功能，还可包括根据所涉及的功能按基本同时的方式或按相反的顺序来执行功能，例如，可以按不同于所描述的次序来执行所描述的方法，并且还可以添加、省去、或组合各种步骤。另外，参照某些示例所描述的特征可在其他示例中被组合。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。
Claims (10)
- 一种电路板组件，包括：印制电路板和M个焊盘，所述M个焊盘间隔设置于所述印制电路板上，所述M个焊盘中的N个焊盘上设置有第一过孔，所述印制电路板上，且所述N个焊盘中任意两个相邻的焊盘之间的位置还设置有第二过孔，所述第二过孔的中心偏离所述任意两个相邻的焊盘的中心连线，M和N均为大于1的整数，且N小于或等于M。
- 根据权利要求1所述的电路板组件，其中，所述第二过孔设置于所述N个焊盘中任意相邻设置的L个焊盘的中心区域，L为大于1，且小于或等于N的整数。
- 根据权利要求2所述的电路板组件，其中，所述第二过孔的中心与所述L个焊盘中每一个焊盘的中心之间具有第一距离，所述L个焊盘中任意两个相邻的焊盘的中心之间具有第二距离，所述第一距离与所述第二距离之间的比值大于1:2。
- 根据权利要求1至3中任一项所述的电路板组件，其中，所述第一过孔与所述第二过孔之间通过走线电连接。
- 根据权利要求4所述的电路板组件，其中，所述走线的尺寸小于或等于所述焊盘的尺寸，和/或，所述走线的尺寸小于或等于所述第二过孔的尺寸。
- 根据权利要求1至3中任一项所述的电路板组件，其中，所述第二过孔与所述N个焊盘中任意两个相邻的焊盘中的一者通过第一走线连接，所述第二过孔与所述N个焊盘中任意两个相邻的焊盘中的另一者通过第二走线连接，所述第一走线和所述第二走线之间的夹角大于或等于90度。
- 根据权利要求1至3中任一项所述的电路板组件，其中，所述M个焊盘中每个焊盘为非阻焊定义焊盘。
- 根据权利要求7所述的电路板组件，其中，所述M个焊盘中每个焊盘包括焊盘本体和阻焊槽，所述阻焊槽环绕所述焊盘本体，且所述阻焊槽位于所述焊盘本体与所述第二过孔之间。
- 根据权利要求8所述的电路板组件，其中，所述印制电路板上还设有油墨，所述油墨与所述焊盘本体之间的间隙构成所述阻焊槽。
- 一种电路板组件的制备方法，所述方法包括：获取第一待制备印制电路板，所述第一待制备印制电路板上间隔设置有M个焊盘，所述M个焊盘中的N个焊盘上设置有第一过孔；在所述第一待制备印制电路板上，所述N个焊盘中任意两个相邻的焊盘之间的位置打第二过孔，且所述第二过孔的中心偏离所述任意两个相邻的焊盘的中心连线，得到印制电路板；其中，M和N均为大于1的整数，且N小于或等于M。
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