WO2024090008A1 - 積層セラミックコンデンサ - Google Patents

積層セラミックコンデンサ Download PDF

Info

Publication number
WO2024090008A1
WO2024090008A1 PCT/JP2023/030997 JP2023030997W WO2024090008A1 WO 2024090008 A1 WO2024090008 A1 WO 2024090008A1 JP 2023030997 W JP2023030997 W JP 2023030997W WO 2024090008 A1 WO2024090008 A1 WO 2024090008A1
Authority
WO
WIPO (PCT)
Prior art keywords
plating layer
layer
multilayer ceramic
ceramic capacitor
laminate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/030997
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
優 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to CN202380063734.1A priority Critical patent/CN119895516A/zh
Priority to JP2024552848A priority patent/JPWO2024090008A1/ja
Publication of WO2024090008A1 publication Critical patent/WO2024090008A1/ja
Priority to US18/800,367 priority patent/US20240404756A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
    • H01G4/1218—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
    • H01G4/1227—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates based on alkaline earth titanates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/224—Housing; Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H01G4/2325—Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/252—Terminals the terminals being coated on the capacitive element

Definitions

  • the present invention relates to a multilayer ceramic capacitor.
  • bending stress such as bending
  • the stress is transmitted to the capacitor body through the external electrodes, which can cause cracks in the capacitor body.
  • an adhesion-reducing film is disposed between the baked metal film and the plated metal film in the external electrode.
  • the adhesion-reducing film reduces the adhesion of the plated metal film to the surface on which the plated metal film is formed. This allows the plated metal film to be peeled off from the baked metal when the circuit board is deflected, thereby preventing the transmission of stress to the capacitor body.
  • the baked metal film will be exposed to the outside air, and there is concern that moisture may penetrate the baked metal film, causing deterioration of the capacitor body, etc.
  • the present invention aims to provide a multilayer ceramic capacitor that is capable of suppressing the occurrence of cracks in the multilayer ceramic capacitor and has excellent reliability.
  • the present invention provides a multilayer ceramic capacitor comprising a laminate including alternatingly stacked dielectric layers and internal electrode layers, the laminate having two main surfaces opposing each other in the stacking direction, two end faces opposing each other in a length direction perpendicular to the stacking direction, and two side surfaces opposing each other in a width direction perpendicular to both the stacking direction and the length direction, and external electrodes respectively disposed on the two end faces of the laminate, the external electrodes having a base electrode layer, a first plating layer disposed on the base electrode layer, a second plating layer disposed on the first plating layer and in contact with the first plating layer, and an adhesion relaxation layer disposed between the first plating layer and the second plating layer.
  • the present invention makes it possible to prevent the occurrence of cracks in multilayer ceramic capacitors and provide highly reliable multilayer ceramic capacitors.
  • FIG. 1 is a schematic perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention mounted on a circuit board.
  • 2A and 2B are partially enlarged cross-sectional views taken along line II-II in FIG. 1 showing a state in which a multilayer ceramic capacitor according to an embodiment of the present invention is mounted on a circuit board, in which (a) is a view showing the periphery of a first external electrode in a state in which a first plating layer and a second plating layer are bonded to each other, and (b) is a view showing the periphery of a second external electrode in a state in which the first plating layer and the second plating layer are peeled off from each other.
  • FIG. 3 is a diagram corresponding to FIG.
  • FIG. 3 is a diagram corresponding to FIG. 2( a ) and illustrating the configuration of a multilayer ceramic capacitor according to a modified example of the present invention.
  • the multilayer ceramic capacitor 1 has a substantially rectangular parallelepiped shape and includes a laminate 2 and a pair of external electrodes 3 provided on both ends of the laminate 2.
  • the multilayer ceramic capacitor 1 is mounted on a circuit board 50.
  • the terms used to indicate the orientation of the multilayer ceramic capacitor 1 are the length direction L, which is the direction in which the pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1; the stacking direction T, which is the direction in which the dielectric layers 14 and the internal electrode layers 15 are stacked; and the width direction W, which is the direction that intersects both the length direction L and the stacking direction T. Note that in this embodiment, the width direction W is perpendicular to both the length direction L and the stacking direction T.
  • a pair of outer surfaces facing the lamination direction T are referred to as two main surfaces A
  • a pair of outer surfaces facing the width direction W are referred to as two side surfaces B
  • a pair of outer surfaces facing the length direction L are referred to as two end surfaces C.
  • the two main surfaces A one is referred to as the first main surface AA
  • the other is referred to as the second main surface AB (see FIG. 2).
  • the two end surfaces C one is referred to as the first end surface CA, and the other is referred to as the second end surface CB.
  • the circuit board 50 is disposed on the second main surface AB side of the laminated ceramic capacitor 1.
  • the laminate 2 includes a laminate body portion 10 and a side margin portion 20 .
  • the laminate body main body 10 comprises an inner layer portion 11 and outer layer portions 12 arranged on both main surface A sides of the inner layer portion 11 .
  • the inner layer portion 11 is configured by laminating a plurality of dielectric layers 14 and a plurality of internal electrode layers 15 .
  • the dielectric layer 14 is made of a ceramic material.
  • a dielectric ceramic containing BaTiO3 as a main component is used as the ceramic material.
  • the ceramic material may be one in which at least one of a Mn compound, an Fe compound, a Cr compound, a Co compound, a Ni compound, or the like is added to the main component.
  • the internal electrode layer 15 includes a plurality of first internal electrode layers 15A and a plurality of second internal electrode layers 15B.
  • the first internal electrode layers 15A and the second internal electrode layers 15B are arranged alternately. Note that the first internal electrode layers 15A and the second internal electrode layers 15B will be collectively referred to as the internal electrode layers 15 unless there is a need to distinguish between them.
  • the internal electrode layer 15 is preferably formed from a metal material such as Ni, Cu, Ag, Pd, Ag-Pd alloy, Au, etc.
  • the first internal electrode layer 15A has a first opposing portion 152a that faces the second internal electrode layer 15B, and a first lead portion 151a that is led out from the first opposing portion 152a to the first end face CA side.
  • the end of the first lead portion 151a is exposed at the first end face CA and is electrically connected to the first external electrode 3A described below.
  • the second internal electrode layer 15B has a second opposing portion 152b that faces the first internal electrode layer 15A, and a second extension portion 151b that is extended from the second opposing portion 152b to the second end face CB.
  • the end of the second extension portion 151b is electrically connected to the second external electrode 3B described below.
  • the outer layer portion 12 is made of the same dielectric ceramic material as the dielectric layer 14 of the inner layer portion 11 .
  • the side margins 20 are provided on both side surfaces B of the portion where the inner layer portion 11 and the outer layer portion 12 are laminated.
  • the side margins 20 cover the ends of the internal electrode layers 15 exposed on both side surfaces of the laminate body main body 10 in the width direction W along the ends.
  • the side margins 20 are made of the same dielectric ceramic material as the dielectric layers 14.
  • the external electrode 3 includes a first external electrode 3A provided on a first end face CA of the laminate 2, and a second external electrode 3B provided on a second end face CB of the laminate 2. Note that, unless there is a particular need to distinguish between the first external electrode 3A and the second external electrode 3B, they will be collectively described as the external electrode 3.
  • the external electrode 3 covers not only the end face C, but also a portion of the main face A and the side face B on the end face C side.
  • the external electrode 3 comprises a base electrode layer 31, a first plating layer 32 arranged on the base electrode layer 31, a second plating layer 33 arranged on the first plating layer 32, and an adhesion relaxation layer 35 arranged between the first plating layer 32 and the second plating layer 33.
  • the base electrode layer 31 is formed, for example, by applying and baking a conductive paste containing a conductive metal and glass.
  • the conductive metal of the base electrode layer 31 can be, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc.
  • the first plating layer 32 is a Cu plating layer. This effectively prevents moisture from penetrating the base electrode layer 31.
  • the second plating layer 33 has an inner second plating layer 331 and an outer second plating layer 332 disposed on the inner second plating layer 331 and in contact with the inner second plating layer 331.
  • the second inner plating layer 331 is a Ni plating layer. This prevents the base electrode layer 31 and the adhesion relaxation layer 35 from being eroded by solder when the multilayer ceramic capacitor 1 is mounted on the circuit board 50.
  • the second outer plating layer 332 is a Sn plating layer. This improves the wettability of the solder when mounting the multilayer ceramic capacitor 1 on the circuit board 50, making it easier to mount the multilayer ceramic capacitor 1.
  • the adhesion relaxation layer 35 can relax the adhesion between the first plating layer 32 and the second plating layer 33 (specifically, the inner second plating layer 331). This allows the first plating layer 32 to be suitably peeled off from the second plating layer 33 in the region where the adhesion relaxation layer 35 is arranged when the circuit board 50 is bent.
  • the adhesion relaxation layer 35 contains an organosilicon compound.
  • the organosilicon compound is preferably polyfunctional alkoxysilane Si-(C n H 2n+1 ) 3. This allows the adhesion relaxation layer to be more reliably arranged on the surface of the first plating layer 32, so that the occurrence of cracks in the laminate 2 can be suitably suppressed. In addition, plating defects and removal of the multilayer ceramic capacitor 1 can be suppressed.
  • the adhesion relaxation layer 35 is disposed in the region between the first plating layer 32 and the second plating layer 33 where the first plating layer 32 and the second plating layer 33 cover the main surface A. Although not shown, the adhesion relaxation layer 35 is annular and is also disposed in the region between the first plating layer 32 and the second plating layer 33 where the first plating layer 32 and the second plating layer 33 cover the side surface B.
  • the adhesion relaxation layer 35 only needs to be disposed in the region where the first plating layer 32 and the second plating layer 33 cover the second main surface AB, and does not necessarily have to be disposed in the region where the first plating layer 32 and the second plating layer 33 cover the first main surface AA or the region where the first plating layer 32 and the second plating layer 33 cover the side surface B.
  • the adhesion relaxation layer 35 has multiple voids that penetrate the layer in the thickness direction.
  • the adhesion relaxation layer 35 can also be said to be a layer with a porous structure.
  • the first plating layer 32 and the second plating layer 33 are in contact with each other at the voids. Therefore, electricity can flow between the first plating layer 32 and the second plating layer 33 through the contact parts.
  • the surface roughness of at least the surface of the first plating layer 32 facing the adhesion relaxation layer 35 is in the range of 0.10 ⁇ m to 0.27 ⁇ m. This allows the ease of peeling when the first plating layer 32 and the second plating layer 33 are peeled off to be within an appropriate range.
  • the first plating layer 32 and the second plating layer 33 can become peeled off (hereinafter, sometimes simply referred to as "peeled off state") in the area where the adhesion relaxation layer 35 is disposed. Even in the peeled off state, the base electrode layer 31 is covered by the first plating layer 32. This makes it possible to prevent moisture from penetrating the base electrode layer 31, etc., and therefore to prevent deterioration of the multilayer ceramic capacitor 1.
  • the adhesion relaxation layer 35 is torn off, and each fragment of the adhesion relaxation layer 35 is attached to the first plating layer 32 and the second plating layer 33, respectively.
  • the state of the adhesion relaxation layer 35 in the peeled state is not particularly limited, and it is also assumed that the entire adhesion relaxation layer 35 is attached to either the first plating layer 32 or the second plating layer 33.
  • the manufacturing process for the multilayer ceramic capacitor 1 includes a laminate manufacturing step and an external electrode forming step.
  • a ceramic green sheet for lamination is prepared by forming a ceramic slurry into a sheet shape.
  • a conductive paste is placed on the ceramic green sheet for lamination, and the patterns of the internal electrode layers 15 are printed on the ceramic green sheet for lamination. In this way, a material sheet can be obtained.
  • the mother block member is then divided along cutting lines corresponding to the dimensions of the laminate. This results in a number of laminated chips. The corners and edges of the multiple laminated chips may then be rounded by barrel polishing or the like.
  • the multiple laminated chips are then fired. This results in a laminate 2 having a laminate body 10 and a side margin 20.
  • the firing temperature at this time depends on the materials of the dielectric layers 14 and the internal electrode layers 15, but is preferably 900°C or higher and 1400°C or lower.
  • a base electrode layer 31 is formed on the end face C of the laminate 2.
  • the end face C of the laminate 2 is sequentially immersed in a conductive paste, which is an electrode material for the base electrode.
  • the conductive paste is applied to each end face C of the laminate 2.
  • these conductive pastes are fired together with the laminate 2.
  • the base electrode layers 31 are formed on each end face C of the laminate 2.
  • the firing temperature is preferably 600° C. or higher and 900° C. or lower.
  • the firing of the laminate 2 and the firing of the external electrode 3 may be performed simultaneously.
  • the first plating layer 32 is formed on the base electrode layer 31.
  • the first plating layer 32 is formed so that the ends of the main surface A and side surface B of the first plating layer 32 cover the ends of the main surface A and side surface B of the base electrode layer 31.
  • the first plating layer 32 can be formed, for example, by electrolytic plating or electroless plating.
  • an adhesion relaxation layer 35 is disposed on the first plating layer 32.
  • a first organic treatment liquid and a second organic treatment liquid are used to form the adhesion relaxation layer 35.
  • the first organic treatment liquid is applied onto the first plating layer 32.
  • the first organic treatment liquid contains an organosilicon compound.
  • the organosilicon compound is a silane coupling agent.
  • the organosilicon compound (silane coupling agent) is, for example, decyltrimethoxysilane, n-propyltrimethoxysilane, octyltriethoxysilane, etc.
  • the first organic treatment liquid can be applied, for example, by a screen printing method.
  • the first organic treatment liquid is then dried at a temperature of 100°C to 200°C.
  • the second organic treatment liquid contains an organosilicon compound, and preferably contains polyfunctional alkoxysilane Si-(C n H 2n+1 ) 3.
  • the second organic treatment liquid can be applied, for example, by a screen printing method.
  • the second organic treatment liquid is then dried at a temperature of 100° C. to 200° C.
  • the dried first and second organic treatment liquids are disposed on the first plating layer 32 as an adhesion relaxation layer 35.
  • the method of applying the first and second organic treatment liquids is not limited to the screen printing method, and for example, a dip method in which the target is immersed in the organic treatment liquid may be used.
  • the adhesion relaxation layer disposed in an area where the adhesion relaxation layer is not desired to be disposed can be removed by polishing or the like.
  • the number and size of the voids in the adhesion relaxation layer 35 can be adjusted by the application amount of the first and second organic treatment liquids. When the application amounts of the first organic treatment liquid and the second organic treatment liquid are large, the number of voids is small and the size of the voids is small. When the application amounts of the first organic treatment liquid and the second organic treatment liquid are small, the number of voids is large and the size of the voids is large.
  • the inner second plating layer 331 is formed on the first plating layer 32 and the adhesion relaxation layer 35.
  • the inner second plating layer 331 is formed so that the ends of the inner second plating layer 331 on the main surface A and side surface B cover the ends of the first plating layer 32 and the adhesion relaxation layer 35 on the main surface A and side surface B.
  • the inner second plating layer 331 can be formed, for example, by electrolytic plating.
  • the outer second plating layer 332 is formed on the inner second plating layer 331.
  • the outer second plating layer 332 is formed such that the ends of the outer second plating layer 332 on the main surface A and side surface B cover the ends of the adhesion relaxation layer 35 on the main surface A and side surface B.
  • the outer second plating layer 332 can be formed, for example, by electrolytic plating. In this manner, the external electrode 3 is formed.
  • the external electrode 3 has a base electrode layer 31, a first plating layer 32 arranged on the base electrode layer 31, a second plating layer 33 arranged on the first plating layer 32 and in contact with the first plating layer 32, and an adhesion relaxation layer 35 arranged between the first plating layer 32 and the second plating layer 33.
  • the adhesion relaxation layer 35 is capable of relaxing the adhesion between the first plating layer 32 and the second plating layer 33.
  • the base electrode layer 31 remains covered by the first plating layer 32. This makes it possible to prevent moisture from penetrating the base electrode layer 31, etc., and therefore to prevent deterioration of the multilayer ceramic capacitor 1. This makes it possible to provide the multilayer ceramic capacitor 1 with excellent reliability.
  • the first plating layer 32 is a Cu plating layer. This effectively prevents moisture from penetrating the base electrode layer 31.
  • the second inner plating layer 331 is a Ni plating layer. This makes it possible to prevent the base electrode layer 31 and the adhesion relaxation layer 35 from being eroded by solder when the multilayer ceramic capacitor 1 is mounted on the circuit board 50.
  • the second outer plating layer 332 is a Sn plating layer. This improves the wettability of the solder when mounting the multilayer ceramic capacitor 1 on the circuit board 50, making it easier to mount the multilayer ceramic capacitor 1.
  • the adhesion relaxation layer 35 contains an organosilicon compound. This effectively prevents cracks from occurring in the laminate 2. It also prevents plating defects and the laminate ceramic capacitor 1 from coming off.
  • the organosilicon compound is a polyfunctional alkoxysilane. This makes it possible to more effectively suppress the occurrence of cracks in the laminate 2, as well as plating defects and detachment of the multilayer ceramic capacitor 1.
  • the surface roughness Sa of the first plating layer 32 is 0.10 ⁇ m or more and 0.27 ⁇ m or less.
  • the adhesion relaxation layer 35 is disposed in the area between the first plating layer 32 and the second plating layer 33, in the area located outside the main surface A and the area located outside the side surface B, but is not disposed in the area located outside the end surface C. This allows the adhesion between the first plating layer 32 and the second plating layer 33 to be of appropriate strength, thereby suitably preventing the multilayer ceramic capacitor 1 from coming off.
  • the adhesion relaxation layer 35 is disposed in the area between the first plating layer 32 and the second plating layer 33, in the area located outside the main surface A and the area located outside the side surface B of the laminate 2, but is not disposed in the area located outside the end surface C, but is not limited to this.
  • the multilayer ceramic capacitor 100 includes an adhesion relaxation layer 135.
  • the adhesion relaxation layer 135 is disposed so as to cover the entire area between the first plating layer 32 and the second plating layer 33.
  • the adhesion relaxation layer can be easily disposed by using, for example, a dipping method.
  • the configuration of the above embodiment is preferable in that it can suitably prevent the second plating layer from being detached from the multilayer ceramic capacitor.
  • the adhesion relaxation layer may also extend to the outside of the region between the first plating layer 32 and the second plating layer 33.
  • the multilayer ceramic capacitor 200 includes an adhesion relaxation layer 235.
  • the adhesion relaxation layer 235 is disposed so as to cover the entire outer surface of the first plating layer 32 and the entire outer surfaces of the main surface A and side surface B of the laminate 2.
  • the adhesion relaxation layer can be disposed more easily by using, for example, a dipping method.
  • the configuration of the above embodiment is preferred in terms of being able to suitably prevent the second plating layer from becoming detached from the multilayer ceramic capacitor.
  • the adhesion relaxation layer 35 contains an organosilicon compound, but is not limited to this.
  • the adhesion relaxation layer may be, for example, a metal.
  • the configuration of the above embodiment is preferred in that it can more effectively suppress the occurrence of cracks in the multilayer ceramic capacitor.
  • the first plating layer 32 has a single-layer structure, but it may have multiple layers. Furthermore, if the first plating layer has multiple layers, it is preferable that the surface roughness Sa of the outer surface of the layer located on the outermost side among the layers is 0.10 ⁇ m or more and 0.27 ⁇ m or less.
  • the second plating layer 33 has an inner second plating layer 331 and an outer second plating layer 332, but it may have a single layer structure or may have three or more layers.
  • a multilayer ceramic capacitor comprising a laminate including alternatingly stacked dielectric layers and internal electrode layers, the laminate having two main surfaces opposing each other in the stacking direction, two end faces opposing each other in a length direction perpendicular to the stacking direction, and two side surfaces opposing each other in a width direction perpendicular to both the stacking direction and the length direction, and external electrodes respectively disposed on the two end faces of the laminate, the external electrodes having a base electrode layer, a first plating layer disposed on the base electrode layer, a second plating layer disposed on the first plating layer and in contact with the first plating layer, and an adhesion relaxation layer disposed between the first plating layer and the second plating layer.
  • ⁇ 2> The multilayer ceramic capacitor described in ⁇ 1>, in which the second plating layer has an inner second plating layer and an outer second plating layer disposed on the inner second plating layer.
  • ⁇ 3> The multilayer ceramic capacitor described in ⁇ 2>, in which the first plating layer is a Cu plating layer, the inner second plating layer is a Ni plating layer, and the outer second plating layer is a Sn plating layer.
  • ⁇ 4> The multilayer ceramic capacitor according to any one of ⁇ 1> to ⁇ 3>, wherein the adhesion relaxation layer contains an organosilicon compound.
  • ⁇ 6> A multilayer ceramic capacitor according to any one of ⁇ 1> to ⁇ 5>, in which the surface roughness Sa of the first plating layer is 0.10 ⁇ m or more and 0.27 ⁇ m or less.
  • ⁇ 7> The multilayer ceramic capacitor according to any one of ⁇ 1> to ⁇ 6>, wherein the adhesion relaxation layer is disposed in the region between the first plating layer and the second plating layer that is located outside the main surface and the side surface, but is not disposed in the region that is located outside the end surface.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)
PCT/JP2023/030997 2022-10-28 2023-08-28 積層セラミックコンデンサ Ceased WO2024090008A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202380063734.1A CN119895516A (zh) 2022-10-28 2023-08-28 层叠陶瓷电容器
JP2024552848A JPWO2024090008A1 (https=) 2022-10-28 2023-08-28
US18/800,367 US20240404756A1 (en) 2022-10-28 2024-08-12 Multilayer ceramic capacitor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022-173161 2022-10-28
JP2022173161 2022-10-28

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/800,367 Continuation US20240404756A1 (en) 2022-10-28 2024-08-12 Multilayer ceramic capacitor

Publications (1)

Publication Number Publication Date
WO2024090008A1 true WO2024090008A1 (ja) 2024-05-02

Family

ID=90830597

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2023/030997 Ceased WO2024090008A1 (ja) 2022-10-28 2023-08-28 積層セラミックコンデンサ

Country Status (4)

Country Link
US (1) US20240404756A1 (https=)
JP (1) JPWO2024090008A1 (https=)
CN (1) CN119895516A (https=)
WO (1) WO2024090008A1 (https=)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07335487A (ja) * 1994-06-03 1995-12-22 Murata Mfg Co Ltd 電子部品及びその製造方法
JP2021048387A (ja) * 2019-09-18 2021-03-25 サムソン エレクトロ−メカニックス カンパニーリミテッド． 積層型電子部品
JP2021093495A (ja) * 2019-12-12 2021-06-17 株式会社村田製作所 積層セラミックコンデンサ

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018049883A (ja) * 2016-09-20 2018-03-29 株式会社村田製作所 積層セラミック電子部品
KR102760393B1 (ko) * 2019-08-23 2025-02-03 삼성전기주식회사 적층형 전자 부품
KR102762879B1 (ko) * 2019-09-18 2025-02-07 삼성전기주식회사 적층형 전자 부품
JP2021093494A (ja) * 2019-12-12 2021-06-17 株式会社村田製作所 積層セラミックコンデンサ
JP7234974B2 (ja) * 2020-02-27 2023-03-08 株式会社村田製作所 積層セラミック電子部品

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07335487A (ja) * 1994-06-03 1995-12-22 Murata Mfg Co Ltd 電子部品及びその製造方法
JP2021048387A (ja) * 2019-09-18 2021-03-25 サムソン エレクトロ−メカニックス カンパニーリミテッド． 積層型電子部品
JP2021093495A (ja) * 2019-12-12 2021-06-17 株式会社村田製作所 積層セラミックコンデンサ

Also Published As

Publication number Publication date
US20240404756A1 (en) 2024-12-05
JPWO2024090008A1 (https=) 2024-05-02
CN119895516A (zh) 2025-04-25

Similar Documents

Publication Publication Date Title
TWI450289B (zh) 電容器及其製造方法
US7944128B2 (en) Electronic component
JP2023030050A (ja) 積層セラミックコンデンサ
JP2017157805A (ja) 電子部品の実装構造及びその電子部品の製造方法
CN102157513A (zh) 薄膜表面安装部件
KR102294680B1 (ko) 적층 세라믹 전자부품
KR20170135661A (ko) 적층 세라믹 콘덴서
JP2021174829A (ja) 積層セラミックコンデンサ
JP2004296936A (ja) セラミック電子部品
JP2019114669A (ja) 電子部品
US10361032B2 (en) Ceramic capacitor including first, second, and third external electrodes wrapping around side and principal surfaces
JP2004235377A (ja) セラミック電子部品
CN100474464C (zh) 积层陶瓷电容器
JP5724262B2 (ja) 電子部品
JP2000106322A (ja) 積層セラミックコンデンサ
WO2024090008A1 (ja) 積層セラミックコンデンサ
JP2023056513A (ja) 積層型電子部品
JP7471040B2 (ja) 電子部品
JP7761990B2 (ja) 積層セラミックコンデンサ包装体
JP2012009680A (ja) セラミック電子部品
JP2006041319A (ja) 表面実装型多連コンデンサ及びその実装構造
JP2004179569A (ja) 積層セラミックコンデンサ
JP4507836B2 (ja) 積層型電子部品
JP2005217128A (ja) セラミック電子部品
WO2025046970A1 (ja) 積層セラミック電子部品

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23882223

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202380063734.1

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 2024552848

Country of ref document: JP

WWP Wipo information: published in national office

Ref document number: 202380063734.1

Country of ref document: CN

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 23882223

Country of ref document: EP

Kind code of ref document: A1