WO2024082774A1 - 半导体结构的处理方法及半导体结构 - Google Patents

半导体结构的处理方法及半导体结构 Download PDF

Info

Publication number
WO2024082774A1
WO2024082774A1 PCT/CN2023/110791 CN2023110791W WO2024082774A1 WO 2024082774 A1 WO2024082774 A1 WO 2024082774A1 CN 2023110791 W CN2023110791 W CN 2023110791W WO 2024082774 A1 WO2024082774 A1 WO 2024082774A1
Authority
WO
WIPO (PCT)
Prior art keywords
substructures
layer
semiconductor structure
support layer
substructure
Prior art date
Application number
PCT/CN2023/110791
Other languages
English (en)
French (fr)
Inventor
王南南
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Publication of WO2024082774A1 publication Critical patent/WO2024082774A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices

Definitions

  • the present disclosure relates to, but is not limited to, a processing method of a semiconductor structure and a semiconductor structure.
  • the use of high aspect ratio structures is becoming more common.
  • the high aspect ratio structures may tilt or even collapse, thereby damaging the semiconductor structure, further affecting the electrical performance of the final semiconductor product, resulting in a low product yield.
  • embodiments of the present disclosure provide a processing method for a semiconductor structure and a semiconductor structure.
  • the present disclosure provides a method for processing a semiconductor structure, including:
  • the semiconductor structure comprising a substrate and a plurality of substructures arranged on the substrate; wherein the aspect ratio of the substructure is greater than a preset ratio;
  • the support layer bridging a first region between the plurality of substructures where the critical dimension is smaller than a dimension threshold, and the support layer having at least one opening;
  • the present disclosure provides a semiconductor structure, including:
  • a plurality of substructures are arranged on the substrate, wherein the aspect ratio of the substructures is greater than a preset ratio
  • a support layer covers the top of the plurality of substructures, the support layer bridges the first regions between the plurality of substructures where the critical dimension is smaller than the dimension threshold, and the support layer has at least one opening.
  • An embodiment of the present disclosure provides a semiconductor structure, wherein the semiconductor structure is processed by using any of the above-mentioned processing methods for the semiconductor structure.
  • a semiconductor structure to be processed comprising a substrate, a plurality of substructures arranged on the substrate; wherein the aspect ratio of the substructure is greater than a preset ratio; a support layer is formed, the support layer bridges a first region between the plurality of substructures where the critical dimension is less than a size threshold, and the support layer has at least one opening; the semiconductor structure is cleaned using the opening; and the support layer on top of the plurality of substructures is removed.
  • the support layer can stabilize the substructure, reduce the damage to the substructure by the surface tension of the liquid, thereby reducing the deformation of the substructure, and further improving the electrical performance of the semiconductor product and improving the product yield; on the other hand, since the support layer has at least one The opening allows cleaning liquid to enter the gap area between the lower parts of the substructures during the cleaning process, thereby achieving a better cleaning effect of the substructures.
  • FIG1A is a schematic diagram of deformation of a high aspect ratio structure during a cleaning process
  • FIG1B is a schematic diagram showing the principle of the effect of liquid surface tension on a high aspect ratio structure
  • FIG2A is a schematic diagram of an implementation flow of a method for processing a semiconductor structure provided by an embodiment of the present disclosure
  • 2B and 2C are respectively a schematic diagram of a top view of a semiconductor structure after a support layer is formed on the semiconductor structure according to an embodiment of the present disclosure and a schematic diagram of a cross-sectional structure of the semiconductor structure along the AA' direction;
  • FIG2D is a schematic structural diagram of a hard mask layer in a semiconductor structure provided by an embodiment of the present disclosure.
  • 2E and 2F are respectively a schematic diagram of a top view of a semiconductor structure provided by an embodiment of the present disclosure and a schematic diagram of a cross-sectional structure of the semiconductor structure along the AA' direction;
  • 2G and 2H are respectively a schematic diagram of a top view of a semiconductor structure after a first filling layer is formed in a method for processing a semiconductor structure provided by an embodiment of the present disclosure and a schematic diagram of a cross-sectional structure of the semiconductor structure along the AA' direction;
  • 2I and 2J are respectively a schematic diagram of a top view of a semiconductor structure after a planarization process in a method for processing a semiconductor structure provided by an embodiment of the present disclosure and a schematic diagram of a cross-sectional structure of the semiconductor structure along the AA' direction;
  • 2K and 2L are respectively a schematic diagram of a top view of a semiconductor structure after a support layer is removed in a method for processing a semiconductor structure provided by an embodiment of the present disclosure and a schematic diagram of a cross-sectional structure of the semiconductor structure along the AA' direction;
  • 2M is a schematic cross-sectional view of a semiconductor structure after a first liner layer and a first filling layer are formed in a method for processing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 3A is a schematic structural diagram of a first liner layer formed in a method for processing a semiconductor structure provided by an embodiment of the present disclosure
  • 3B is a schematic structural diagram of a first liner layer formed in a method for processing a semiconductor structure provided by an embodiment of the present disclosure
  • 3C and 3D are respectively a schematic diagram of a top view of a semiconductor structure after a second filling layer is formed in a method for processing a semiconductor structure provided by an embodiment of the present disclosure and a schematic diagram of a cross-sectional structure of the semiconductor structure along the AA' direction;
  • 3E is a schematic cross-sectional view of a semiconductor structure after a second liner layer and a second filling layer are formed in a method for processing a semiconductor structure provided by an embodiment of the present disclosure
  • 3F is a schematic structural diagram of a second liner layer formed in a method for processing a semiconductor structure provided by an embodiment of the present disclosure
  • 3G is a schematic structural diagram of a second liner layer formed in a method for processing a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of an implementation flow of a method for forming a semiconductor structure provided in an embodiment of the present disclosure.
  • first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.
  • the high aspect ratio structure may be a structure with an aspect ratio greater than 5:1, 10:1 or 20:1, etc.
  • the surface tension of the liquid i.e., capillary force
  • the high aspect ratio structure may tilt or even collapse, thereby damaging the semiconductor structure, further affecting the electrical performance of the final semiconductor product, and resulting in a low product yield.
  • FIG1A As shown in FIG1A, during the cleaning process of a semiconductor structure 10 having a high aspect ratio structure 11, the liquid heights between the aspect ratio structures 11 are not equal. Due to the existence of the liquid surface tension, the high aspect ratio structure 11 will be deformed, thereby damaging the semiconductor structure 10, thereby affecting the electrical properties of the final semiconductor product, resulting in a low product yield.
  • a surface modifier such as hexamethylsilane, alkoxysilane, alkylsilane, fluorinated or long-chain hydrocarbons based on trichlorosilane, dichlorosilane, monochlorosilane, methoxysilane and ethoxysilane, etc.
  • a surface modifier can be added to the surface of the high aspect ratio structure to change the surface characteristics of the high aspect ratio structure through the surface modifier to reduce the static friction between two adjacent surfaces or increase the hydrophobicity of the surface of the high aspect ratio structure, thereby helping to reduce the damage of the liquid surface tension ⁇ to the high aspect ratio structure.
  • the cost of the surface modifier in this solution is relatively high, and the carbon, fluorine or chlorine in the surface modifier may remain on the high aspect ratio structure, requiring an additional dry plasma reaction ashing process to remove the residue, resulting in a high process cost.
  • a supercritical drying method is used to dry the cleaned semiconductor structure using a supercritical fluid, and the supercritical fluid is directly transformed from a supercritical state to a gas phase so that there is no gas-liquid interface, and thus there is no surface tension acting on the high aspect ratio structure, so that the high aspect ratio structure can be dried without destroying the high aspect ratio structure.
  • this solution requires the addition of an additional high-cost high-pressure supercritical drying machine, and requires additional high pressure and a large amount of supercritical fluid factory costs, and a large amount of supercritical fluid consumption costs, resulting in high process costs.
  • stimulus responsive materials such as polymer-based materials are used as sacrificial support materials to prevent structural collapse.
  • the sacrificial support material solidifies on and around the high aspect ratio structure to provide mechanical support and prevent the high aspect ratio structure from collapsing during drying.
  • a stimulus non-plasma-based stimulus such as ultraviolet light, heat and/or chemicals
  • the cost of the stimulus responsive material in this solution is relatively high, and the chemicals used for the stimulus may remain on the high aspect ratio structure, requiring an additional ashing process of dry plasma reaction to remove the residue, resulting in a higher process cost.
  • an embodiment of the present disclosure provides a method for processing a semiconductor structure. As shown in FIG. 2A , the method includes steps S101 to S104, wherein:
  • Step S101 providing a semiconductor structure to be processed, the semiconductor structure comprising a substrate and a plurality of substructures arranged on the substrate; wherein the aspect ratio of the substructure is greater than a preset ratio.
  • the substrate may be a silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate, etc.
  • the substrate may be a single-layer substrate or a multi-layer substrate, such as a single-crystalline silicon single-layer substrate, a polycrystalline silicon single-layer substrate, a polycrystalline silicon and metal multi-layer substrate, etc.
  • the substrate may also include other semiconductor elements or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys, such as gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and/or gallium indium arsenide phosphide (GaInAsP) or a combination thereof.
  • semiconductor elements or semiconductor compounds such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (
  • a plurality of substructures are provided on the substrate, and the aspect ratio of each substructure is greater than a preset ratio.
  • the material used in the substructure may be the same as that of the substrate, or may be different from that of the substrate.
  • the preset ratio may be predetermined by a person skilled in the art according to actual conditions, and the embodiments of the present disclosure do not limit this.
  • the substructure is a high aspect ratio structure, and the preset ratio may include but is not limited to 5:1, 10:1 or 20:1, etc.
  • the substructure is a nanostructure with a high aspect ratio.
  • the substructure on the substrate can be formed by any suitable process, and the process used may include but is not limited to at least one of an etching process (such as a wet etching process, a dry etching process), a deposition process (such as a selective deposition process), etc., and the embodiments of the present disclosure are not limited to this.
  • an etching process such as a wet etching process, a dry etching process
  • a deposition process such as a selective deposition process
  • a substrate may be provided first, and then a plurality of substructures having aspect ratios greater than a preset ratio may be selectively deposited on the substrate.
  • a substrate and a cover layer disposed on the substrate may be provided first, and a hard mask layer and a photoresist mask layer for defining substructures may be patterned on the surface of the cover layer through a photolithography process, and the cover layer may be etched based on the photoresist mask layer and the hard mask layer to form a plurality of substructures disposed on the substrate.
  • the cover layer may be made of the same material as the substrate, or may be made of a different material from the substrate.
  • Step S102 forming a support layer, wherein the support layer bridges a first region between a plurality of substructures where the critical dimension is smaller than a dimension threshold, and the support layer has at least one opening.
  • the support layer can cover the top of multiple substructures and bridge the first area between the multiple substructures where the critical dimension is less than the size threshold.
  • the critical dimension refers to the width of the gap between the substructures.
  • the critical dimension between each substructure can be determined according to the actual design layout of the semiconductor structure.
  • the first area where the critical dimension is less than the size threshold can be the area where the width of the gap between any two substructures is less than the size threshold. Gap area.
  • the size threshold may be determined based on the process requirements of the semiconductor structure and/or the aspect ratio of the substructure.
  • a larger size threshold may be set so that the corresponding substructure can be stabilized even when the critical dimensions between the substructures are large, thereby improving the electrical performance of the semiconductor structure; in the case where the process requirements of the semiconductor structure are low, a smaller size threshold may be set so that the area of the support layer is reduced, thereby reducing the process cost.
  • a larger size threshold may be set so that the corresponding substructure can be stabilized even when the critical dimensions between the substructures are large; in the case where the depth-to-width ratio of the substructure is small, a smaller size threshold may be set so that the area of the support layer is reduced, thereby reducing the process cost.
  • the material forming the support layer may be any suitable material having a higher etching selectivity ratio with the material forming the substructure, and the embodiments of the present disclosure are not limited thereto.
  • the material forming the substructure may be silicon, silicon germanium, etc.
  • the material forming the support layer may be nitride, etc.
  • FIG2B and FIG2C are respectively a schematic diagram of a top view structure after a support layer is formed on a semiconductor structure provided by an embodiment of the present disclosure and a schematic diagram of a cross-sectional structure of the semiconductor structure along the AA' direction.
  • the semiconductor structure 100 includes a substrate 110, and a plurality of substructures 120 disposed on the substrate 110; the formed support layer 130 covers the top of the plurality of substructures 120; the support layer 130 bridges the first region 131 between the plurality of substructures 120 where the critical dimension CD1 is less than the dimension threshold, and the support layer has at least one opening 132.
  • Step S103 using the opening to clean the semiconductor structure.
  • any appropriate cleaning process may be used to clean the semiconductor structure to clean the surface of the substructure in the semiconductor structure and the surface of the substrate.
  • the etching byproducts attached to the surface of the substructure under the supporting layer during the formation of the substructure can be removed.
  • the etching byproducts may include but are not limited to at least one of carbon, silicon oxide, fluoride, chloride, etc.
  • a wet cleaning process may be used to clean the semiconductor structure. Since the supporting layer has at least one opening, the cleaning liquid can enter the gap area between the substructures under the supporting layer through the opening to clean the substructure under the supporting layer.
  • the cleaning liquid used in the cleaning process may include but is not limited to hydrofluoric acid (such as hydrofluoric acid with a concentration of 49%, diluted hydrofluoric acid), a mixed solution of sulfuric acid and hydrogen peroxide with a molar ratio of 1:6 to 1:4 (i.e., SPM mixed solution), a mixture of ammonia, hydrogen peroxide and water (i.e., SC1 mixed solution), a mixture of hydrochloric acid, hydrogen peroxide and water (i.e., SC2 mixed solution), etc.
  • hydrofluoric acid such as hydrofluoric acid with a concentration of 49%, diluted hydrofluoric acid
  • SPM mixed solution a mixed solution of sulfuric acid and hydrogen peroxide with a molar ratio of 1:6 to 1:4
  • SC1 mixed solution mixture of ammonia, hydrogen peroxide and water
  • SC2 mixed solution a mixture of hydrochloric acid, hydrogen peroxide and water
  • the cleaned semiconductor structure may be dried, and the substructure surface and the substrate surface may be dried by the drying process.
  • any suitable drying process may be used to dry the cleaned semiconductor structure, and the embodiments of the present disclosure are not limited thereto.
  • the drying process may include, but is not limited to, at least one of a liquid phase drying process, a gas phase drying process, and the like.
  • Step S104 removing the support layer on top of the multiple substructures.
  • any suitable etching process may be used to remove the support layer, which is not limited in the embodiments of the present disclosure.
  • the support layer may be etched using an etching gas or a corrosive liquid that has a relatively large etching selectivity for the material of the support layer and the material of the substructure, thereby removing the support layer and retaining the substructure.
  • the etching selectivity of the etching gas or the corrosive liquid for the material of the support layer and the material of the substructure may be 500:1.
  • a material in order to reduce the re-contamination of the substructure surface and the substrate surface during the removal of the support layer, a material can be pre-filled between the substructures to form a gap filling layer based on the subsequent process requirements to protect the substructure surface and the substrate surface after cleaning and to support the substructure in the subsequent process.
  • a semiconductor structure to be processed comprising a substrate, a plurality of substructures arranged on the substrate; wherein the aspect ratio of the substructure is greater than a preset ratio; a support layer is formed, the support layer bridges a first region between the plurality of substructures where the critical dimension is less than a dimension threshold, and the support layer has at least one opening; and the opening is used to The semiconductor structure is cleaned; the support layer on the top of the multiple substructures is removed.
  • the support layer can stabilize the substructures during the cleaning process of the multiple substructures, reduce the damage to the substructures caused by the surface tension of the liquid, thereby reducing the deformation of the substructures, thereby improving the electrical performance of the semiconductor product and improving the product yield; on the other hand, since the support layer has at least one opening, the cleaning liquid can enter the gap area between the lower parts of the substructures through the opening during the cleaning process, thereby achieving a better cleaning effect of the substructures.
  • the support layer 130 is open in the second region to form at least one opening 132, and the second region includes a region where the critical dimension CD2 between the plurality of substructures 120 is greater than or equal to the size threshold.
  • the second region may be a gap region where the width of the gap between any two substructures is greater than or equal to the size threshold.
  • the above step S102 may include the following step S111:
  • Step S111 using a preset deposition process to deposit a first material on top of the multiple substructures to form a support layer;
  • the preset deposition process includes at least one of the following: a selective atomic layer deposition process, a plasma enhanced chemical vapor deposition process.
  • the first material may be a suitable material selected according to actual conditions, and may include but is not limited to nitride.
  • the selective atomic layer deposition process and/or the plasma enhanced chemical vapor deposition process can be used to deposit the first material only on the top of the multiple substructures to form a supporting layer covering the top of the multiple substructures.
  • a hard mask layer 140 is disposed on top of the substructure 120 .
  • the above step S111 may include the following step S121:
  • Step S121 using a preset deposition process, depositing a first material on the surface of the hard mask layer to form a support layer.
  • a photoresist mask layer and a hard mask layer may be patterned during the process of etching the substructure; then, after the substructure is etched, the patterned photoresist mask layer may be removed, and the hard mask layer on the top of the substructure may be retained.
  • the hard mask layer is not patterned during the process of etching the substructure, and the hard mask layer may be deposited on the surface of the substructure after the substructure is etched.
  • the material used to deposit the hard mask layer may include but is not limited to silicon oxide, thermal oxide, tetraethyl orthosilicate (TEOS) oxide, high density plasma oxide, atomic layer deposition oxide or spin-on dielectric oxide.
  • TEOS tetraethyl orthosilicate
  • a hard mask layer is provided on the top of the substructure before depositing the support layer.
  • the hard mask layer can be used as a protective layer to protect the top of the substructure.
  • the cleaning process of the semiconductor structure using the opening described in the above step S103 may include the following steps S131 to S132:
  • Step S131 performing ashing treatment on the semiconductor structure
  • Step S132 using the opening to clean the semiconductor structure after the ashing process.
  • the ashing process may be used to ashe the etching gas or etching liquid remaining after etching, so as to prevent the residual etching gas or etching liquid from continuing to etch the substructure or the substrate.
  • some etching byproducts 21 may be attached to the surface of the substructure under the support layer 130 and the surface of the substrate.
  • the openings 132 are used to clean the plurality of substructures 120 and the substrate 110 in the semiconductor structure after the ashing process, so that the etching byproducts 21 can be removed.
  • the semiconductor structure may be ashed using an oxygen-free ashing process, that is, the semiconductor structure may be ashed using a first mixed gas that does not contain oxygen, the first mixed gas comprising at least hydrogen and nitrogen, so as to remove the corrosive gases and polymer materials remaining on the surface after etching.
  • oxygen-free ashing since the mixed gas does not contain oxygen, the surface of the semiconductor structure will not be damaged (the surface of the substrate, substructure, and support layer will not be oxidized).
  • the use of hydrogen can effectively remove the corrosive gases and polymer materials remaining on the surface of the semiconductor structure.
  • the semiconductor structure may be ashed using an oxygen-containing ashing process, that is, the semiconductor structure may be ashed using a second mixed gas containing oxygen, the second mixed gas comprising at least hydrogen, nitrogen and oxygen.
  • the oxygen ashing process since the mixed gas contains oxygen, the ashing efficiency is higher, and the corrosive gas and polymer material remaining on the surface of the semiconductor structure after etching can be removed more quickly.
  • the semiconductor structure is ashed and the ashed semiconductor structure is cleaned by using the openings of the support layer, so that the surface of the substructure under the support layer and the surface of the substrate can be better cleaned.
  • the above step S104 may include the following steps S141 to S143:
  • Step S141 filling a second material between the plurality of substructures after the cleaning process to form a first filling layer covering the plurality of substructures and the support layer.
  • the second material includes at least one of the following: oxide, nitride.
  • the second material may include oxide (such as silicon oxide, germanium oxide, etc.), nitride (such as silicon nitride, germanium nitride, etc.), or may include an oxide-nitride combination, which is not limited in the embodiments of the present disclosure.
  • the first filling layer may be used as a dielectric layer for isolation between conductive layers.
  • FIGS. 2G and 2H are respectively a schematic diagram of a top view of a semiconductor structure after a first filling layer is formed in a processing method of a semiconductor structure provided in an embodiment of the present disclosure and a schematic diagram of a cross-sectional structure of the semiconductor structure along the AA’ direction.
  • a second material is filled between the plurality of substructures 120 after the cleaning treatment to form a first filling layer 150 covering the plurality of substructures 120 and the support layer 130.
  • Step S142 planarizing the surface of the first filling layer until the top surface of the supporting layer is exposed.
  • the planarization process may include but is not limited to an etching process and/or a polishing process, etc.
  • the etching process may be, for example, wet etching, dry etching, etc.
  • the polishing process may be, for example, chemical mechanical polishing (CMP), etc.
  • the surface of the first filling layer can be chemically reacted with an oxidant, catalyst, etc. used in the polishing process to generate a soft layer that is relatively easy to remove; the soft layer is then removed under the mechanical action of an abrasive and a polishing pad used in the polishing process; the aforementioned steps of generating and removing the soft layer are repeated, so that the surface of the first filling layer can be flattened under the combined action of chemical reaction and mechanical grinding until the top surface of the support layer is exposed.
  • the surface of the first filling layer can be etched to remove the surface layer of the first filling layer; then the residue after the etching can be removed by cleaning; the etching and cleaning processes can be repeated to make the surface of the first filling layer reach a suitable flatness, thereby achieving planarization of the surface of the first filling layer until the top surface of the support layer is exposed.
  • Figure 2I and Figure 2J are respectively a schematic diagram of the top view structure of a semiconductor structure after flattening treatment in a semiconductor structure processing method provided in an embodiment of the present disclosure and a schematic diagram of the cross-sectional structure of the semiconductor structure along the AA’ direction. As shown in Figure 2I and Figure 2J, after the surface of the first filling layer 150 is flattened, the top surface of the support layer 130 can be exposed.
  • Step S143 etching the first filling layer and the support layer after the planarization process until the support layer is removed. layer.
  • the first filling layer and the supporting layer may be etched simultaneously until the supporting layer is removed; or the first filling layer may be etched first to expose the entire supporting layer, and then the supporting layer may be etched to remove the supporting layer.
  • any suitable etching process may be used to etch the first filling layer and the supporting layer, such as a wet etching process, a dry etching process, etc., which is not limited in the embodiments of the present disclosure.
  • Figure 2K and Figure 2L are respectively a schematic diagram of the top view structure of the semiconductor structure after the support layer is removed in a semiconductor structure processing method provided in an embodiment of the present disclosure and a schematic diagram of the cross-sectional structure of the semiconductor structure along the AA’ direction.
  • the upper part of the first filling layer 150 and the support layer 130 can be etched to remove the support layer 130 and expose the top of each substructure 120.
  • the second material is filled between the multiple substructures after the cleaning process to form a first filling layer covering the multiple substructures and the support layer; the surface of the first filling layer is flattened until the top surface of the support layer is exposed; the first filling layer and the support layer after the flattening process are etched until the support layer is removed.
  • the first filling layer can stabilize the multiple substructures, the damage to the substructures during the process of removing the support layer can be reduced, and the contamination of the substructures and the substrate under the support layer can be reduced.
  • step S104 may further include the following step S151:
  • Step S151 before forming the first filling layer, forming a first lining layer on the surfaces of the plurality of substructures after the cleaning process.
  • a first cushion layer can be formed on the surface of multiple substructures after cleaning, and then the second material can be filled between the multiple substructures after the first cushion layer is formed to form a first filling layer covering the substructures, the support layer and the first cushion layer.
  • the material of the formed first liner layer may include but is not limited to at least one of thermal oxide (such as silicon dioxide, etc.), silicon, oxide, nitride, etc., and the embodiments of the present disclosure are not limited to this.
  • Figure 2M is a schematic diagram of the cross-sectional structure of a semiconductor structure after a first pad layer and a first filling layer are formed in a semiconductor structure processing method provided in an embodiment of the present disclosure.
  • a first pad layer 160 is formed on the surface of multiple substructures 120 after cleaning, and the first filling layer 150 covers the substructure 120, the support layer 130 and the first pad layer 160.
  • the first liner layer can repair the damage on the surface of the substructure caused during the etching process to form the substructure; on the other hand, the first liner layer can protect the substructure and reduce the damage to the substructure caused by device stress or etching operations in subsequent processes.
  • step S151 may include the following step S161 or step S162:
  • Step S161 performing thermal oxidation treatment on the cleaned substructures to form a first liner layer covering the surfaces of the substructures.
  • the material of the first liner layer may include thermal oxide (such as silicon dioxide).
  • thermal oxide may be generated on the surface of the substructure 120 and the surface of the substrate 110 by thermal oxidation to form a first liner layer 160 covering the surface of each substructure 120 .
  • Step S162 depositing a third material on the surfaces of the multiple substructures after the cleaning process to form a first liner layer covering the surfaces of the multiple substructures and the surface of the support layer.
  • the third material may include at least one of the following: silicon, oxide, nitride.
  • Silicon may include but is not limited to at least one of amorphous silicon, polycrystalline silicon, crystalline silicon, etc.
  • Oxide may include but is not limited to at least one of ethyl silicate oxide, atomic layer deposition oxide, etc.
  • the third material may be deposited on the surface of the substructure 120 and the surface of the support layer 130 to form a first liner layer 160 covering the surface of each substructure 120 and the surface of the support layer 130.
  • the above method may further include the following step S171:
  • Step S171 cleaning the multiple substructures after removing the support layer again;
  • some etching byproducts 22 may still be attached to the top of the substructure 120.
  • the etching byproducts 22 are covered under the support layer 130. Therefore, the multiple substructures after removing the support layer 130 may be cleaned again to remove the etching byproducts 22 attached to the top of the substructure 120.
  • the cleaning solution used for the second cleaning treatment may include but is not limited to at least one of diluted hydrofluoric acid, buffered oxide etching solution (mixed with 49% concentration of hydrofluoric acid and water, or ammonium fluoride and water), phosphoric acid, SPM mixed solution or SC1 mixed solution.
  • step S171 the method may further include the following step S172:
  • Step S172 filling a fourth material between the plurality of substructures after the second cleaning process to form a second filling layer covering the tops of the plurality of substructures and the first filling layer.
  • the fourth material includes at least one of the following: oxide, nitride.
  • the fourth material may include oxide (such as silicon oxide, germanium oxide, etc.), nitride (such as silicon nitride, germanium nitride, etc.), or may include an oxide-nitride combination, which is not limited in the embodiments of the present disclosure.
  • the second filling layer may be used as a dielectric layer for isolation between conductive layers.
  • 3C and 3D are respectively a schematic diagram of a top view of a semiconductor structure after a second filling layer is formed in a processing method of a semiconductor structure provided in an embodiment of the present disclosure and a schematic diagram of a cross-sectional structure of the semiconductor structure along the AA’ direction.
  • a fourth material is filled between the plurality of substructures 120 after a second cleaning treatment to form a second filling layer 170 covering the top of the plurality of substructures 120 and the first filling layer 150.
  • the support layer is removed after the first filling layer is formed.
  • the first filling layer can stabilize the substructure and reduce the aspect ratio of the substructure to reduce the damage to the substructure caused by the surface tension of the liquid, thereby reducing the deformation of the substructure, thereby improving the electrical performance of the semiconductor product and improving the product yield.
  • the above method may further include the following step S181:
  • Step S181 before forming the second filling layer, forming a second liner layer on top of the plurality of substructures after the second cleaning process.
  • a first cushion layer can be formed on the surface of the multiple substructures after the cleaning process again, and then the fourth material can be filled between the multiple substructures after the first cushion layer is formed to form a second filling layer covering the top of the multiple substructures, the first filling layer and the second cushion layer.
  • the material of the formed second liner layer may include but is not limited to at least one of thermal oxide (such as silicon dioxide, etc.), silicon, oxide, nitride, etc., and the embodiments of the present disclosure are not limited to this.
  • the material of the second liner layer may be the same as or different from the material of the first liner layer; the process of forming the second liner layer may be the same as or different from the process of forming the first liner layer.
  • Figure 3E is a schematic diagram of the cross-sectional structure of the semiconductor structure after a second pad layer and a second filling layer are formed in a semiconductor structure processing method provided in an embodiment of the present disclosure.
  • a second pad layer 180 is formed on the top of the multiple substructures 120 after re-cleaning, and the second filling layer 170 covers the top of the substructure 120, the first filling layer 150 and the second pad layer 180.
  • the second pad layer can repair the damage on the surface of the substructure caused in the process of removing the support layer and/or the hard mask layer arranged on the top of the substructure; on the other hand, the second pad layer can protect the substructure and reduce the damage to the substructure caused by device stress or etching operations in subsequent processes; on the other hand, the second pad layer can compensate for the critical dimensions of the upper part of the substructure, so that the critical dimensions of the upper part of the substructure after the second pad layer is formed on the surface are consistent with the critical dimensions of the lower part of the substructure after the first pad layer is formed on the surface.
  • step S181 may include the following step S191 or step S192:
  • Step S191 performing thermal oxidation treatment on the tops of the plurality of substructures after the second cleaning treatment to form a second liner layer covering the top surfaces of the plurality of substructures.
  • the material of the second liner layer may include thermal oxide (such as silicon dioxide).
  • thermal oxide may be generated on the surface of the substructure 120 by thermal oxidation to form a second liner layer 180 covering the top surface of each substructure 120 .
  • Step S192 depositing a fifth material on the surfaces of the multiple substructures after the second cleaning process to form a second liner layer covering the surfaces of the multiple substructures and the surface of the first filling layer.
  • the fifth material may include at least one of the following: silicon, oxide, nitride.
  • Silicon may include but is not limited to at least one of amorphous silicon, polycrystalline silicon, crystalline silicon, etc.
  • Oxide may include but is not limited to at least one of ethyl silicate oxide, atomic layer deposition oxide, etc.
  • the fifth material may be deposited on the surface of the substructure 120 and the surface of the first filling layer 150 to form a second liner layer 180 covering the top surface of each substructure 120 and the surface of the first filling layer 150 .
  • the semiconductor structure 100 includes:
  • a plurality of substructures 120 are disposed on the substrate 110, wherein the aspect ratio of the substructures 120 is greater than a preset ratio;
  • the support layer 130 covers the top of the plurality of substructures 120 , the support layer 130 bridges the first regions 131 between the plurality of substructures 120 where the critical dimension CD1 is smaller than the dimension threshold, and the support layer 130 has at least one opening.
  • the support layer 130 is opened in the second region to form at least one opening 132 , and the second region includes regions between the plurality of substructures 120 where the critical dimension CD2 is greater than or equal to the dimension threshold.
  • a hard mask layer 140 is disposed on top of the substructure 120 , and the support layer 130 covers the hard mask layer 140 .
  • the material used for the support layer includes nitride; and the material used for the hard mask layer includes oxide.
  • FIG4 is a schematic diagram of a process flow of a method for forming a semiconductor structure provided by the present disclosure. As shown in FIG4 , the method includes the following steps S401 to S403:
  • Step S401 providing a substrate
  • Step S402 forming a plurality of substructures on the substrate, wherein the aspect ratio of the substructures is greater than a preset ratio;
  • Step S403 forming a support layer covering the tops of the plurality of substructures, wherein the support layer bridges the first regions between the plurality of substructures where the critical dimension is smaller than the dimension threshold, and the support layer has at least one opening.
  • An embodiment of the present disclosure provides a semiconductor structure, which is obtained by processing using the semiconductor structure processing method described in any of the above processing method embodiments.
  • the above semiconductor structure embodiment has similar beneficial effects as the semiconductor structure processing method embodiment.
  • technical details not disclosed in the semiconductor structure embodiment of the present disclosure please refer to the description of the semiconductor structure processing method embodiment of the present disclosure for understanding.
  • the units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.
  • the embodiments of the present disclosure provide a method for processing and forming a semiconductor structure, and a semiconductor structure.
  • the method for processing a semiconductor structure includes: providing a semiconductor structure to be processed, the semiconductor structure including a substrate and a plurality of substructures arranged on the substrate; wherein the aspect ratio of the substructure is greater than a preset ratio; forming a support layer, the support layer bridges the areas between the plurality of substructures where the critical dimensions are less than a dimension threshold, and the support layer has at least one opening; using the opening to clean the semiconductor structure; and removing the support layer on top of the plurality of substructures.
  • the damage to the substructures caused by the surface tension of the liquid can be reduced, thereby reducing the deformation of the substructures, thereby improving the electrical performance of the semiconductor product and improving the product yield; on the other hand, the effect of better cleaning the substructures can be achieved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Weting (AREA)

Abstract

本公开实施例提供一种半导体结构的处理方法及半导体结构。其中，半导体结构的处理方法包括：提供待处理的半导体结构，半导体结构包括衬底、设置在衬底上的多个子结构；其中，子结构的深宽比大于预设比值；形成支撑层，支撑层桥接多个子结构之间关键尺寸小于尺寸阈值的第一区域，且支撑层具有至少一个开口；利用开口对半导体结构进行清洗处理；去除多个子结构顶部的支撑层。

Description

半导体结构的处理方法及半导体结构
相关申请的交叉引用
本公开基于申请号为202211290543.2、申请日为2022年10月21日、发明名称为“半导体结构的处理方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构的处理方法及半导体结构。
背景技术
随着半导体集成度的增加，高深宽比结构的使用也愈加普遍。在具有高深宽比结构的半导体产品的制程中，高深宽比结构可能倾斜甚至塌陷，从而对半导体结构造成破坏，进而影响最终形成的半导体产品的电学性能，导致产品良率较低。
发明内容
有鉴于此，本公开实施例提供一种半导体结构的处理方法及半导体结构。
本公开实施例提供一种半导体结构的处理方法，包括：
提供待处理的半导体结构，半导体结构包括衬底、设置在衬底上的多个子结构；其中，子结构的深宽比大于预设比值；
形成支撑层，支撑层桥接多个子结构之间关键尺寸小于尺寸阈值的第一区域，且支撑层具有至少一个开口；
利用开口对半导体结构进行清洗处理；
去除多个子结构顶部的支撑层。
本公开实施例提供一种半导体结构，包括：
衬底；
设置在衬底上的多个子结构，子结构的深宽比大于预设比值；
覆盖多个子结构顶部的支撑层，支撑层桥接多个子结构之间关键尺寸小于尺寸阈值的第一区域，且支撑层具有至少一个开口。
本公开实施例提供一种半导体结构，所述半导体结构是采用上述任一半导体结构的处理方法处理得到的。
在本公开实施例中，提供待处理的半导体结构，半导体结构包括衬底、设置在衬底上的多个子结构；其中，子结构的深宽比大于预设比值；形成支撑层，支撑层桥接多个子结构之间关键尺寸小于尺寸阈值的第一区域，且支撑层具有至少一个开口；利用开口对半导体结构进行清洗处理；去除多个子结构顶部的支撑层。这样，一方面，由于深宽比大于预设比值的多个子结构顶部覆盖了支撑层，且支撑层桥接多个子结构之间关键尺寸小于尺寸阈值的第一区域，因此在对多个子结构进行清洗处理的过程中，支撑层可以起到稳定子结构的作用，减少液体表面张力对子结构的破坏，从而减少子结构的变形，进而提升半导体产品的电学性能，提高产品良率；另一方面，由于支撑层具有至少一个 开口，通过该开口，可以使得清洗处理过程中清洗液可以进入子结构下部之间的间隙区域，达到更好地清洁子结构的效果。
附图说明
图1A为清洗处理过程中高深宽比结构的形变示意图；
图1B为液体表面张力对高深宽比结构进行作用的原理示意图；
图2A为本公开实施例提供的一种半导体结构的处理方法的实现流程示意图；
图2B和图2C分别为本公开实施例提供的一种半导体结构上形成支撑层后的俯视结构示意图和该半导体结构沿AA’方向的剖面结构示意图；
图2D为本公开实施例提供的一种半导体结构中硬掩模层的结构示意图；
图2E和图2F分别为本公开实施例提供的一种半导体结构的俯视结构示意图和该半导体结构沿AA’方向的剖面结构示意图；
图2G和图2H分别为本公开实施例提供的一种半导体结构的处理方法中形成第一填充层后的半导体结构的俯视结构示意图和该半导体结构沿AA’方向的剖面结构示意图；
图2I和图2J分别为本公开实施例提供的一种半导体结构的处理方法中平坦化处理后的半导体结构的俯视结构示意图和该半导体结构沿AA’方向的剖面结构示意图；
图2K和图2L分别为本公开实施例提供的一种半导体结构的处理方法中去除支撑层后的半导体结构的俯视结构示意图和该半导体结构沿AA’方向的剖面结构示意图；
图2M为本公开实施例提供的一种半导体结构的处理方法中形成第一衬垫层和第一填充层后的半导体结构的剖面结构示意图；
图3A为本公开实施例提供的一种半导体结构的处理方法中形成的第一衬垫层的结构示意图；
图3B为本公开实施例提供的一种半导体结构的处理方法中形成的第一衬垫层的结构示意图；
图3C和图3D分别为本公开实施例提供的一种半导体结构的处理方法中形成第二填充层后的半导体结构的俯视结构示意图和该半导体结构沿AA’方向的剖面结构示意图；
图3E为本公开实施例提供的一种半导体结构的处理方法中形成第二衬垫层和第二填充层后的半导体结构的剖面结构示意图；
图3F为本公开实施例提供的一种半导体结构的处理方法中形成的第二衬垫层的结构示意图；
图3G为本公开实施例提供的一种半导体结构的处理方法中形成的第二衬垫层的结构示意图；
图4为本公开实施例提供的一种半导体结构的形成方法的实现流程示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面结合附图和实施例对本公开的技术方案进一步详细阐述，所描述的实施例不应视为对本公开的限制，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本公开保护的范围。
在以下的描述中，涉及到“一些实施例”，其描述了所有可能实施例的子集，但是可以理解，“一些实施例”可以是所有可能实施例的相同子集或不同子集，并且可以在 不冲突的情况下相互结合。在以下的描述中，所涉及的术语“第一\第二\第三”仅仅是区别类似的对象，不代表针对对象的特定排序，可以理解地，“第一\第二\第三”在允许的情况下可以互换特定的顺序或先后次序，以使这里描述的本公开实施例能够以除了在这里图示或描述的以外的顺序实施。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中所使用的术语只是为了描述本公开实施例的目的，不是旨在限制本公开。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论的第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
高深宽比结构可以为具有大于5:1、10:1或20:1等的深宽比的结构。在具有高深宽比结构的半导体产品的制程中，尤其是深宽比达到10以上的高深宽比结构的半导体制程中，在清洗以及干燥处理过程中，由于液体表面张力(即毛细作用力)会造成高深宽比结构倾斜甚至塌陷，从而对半导体结构造成破坏，进而影响最终形成的半导体产品的电学性能，导致产品良率较低。
如图1A所示，在对具有高深宽比结构11的半导体结构10进行清洗处理的过程中，各深宽比结构11之间的液体高度并不相等，由于液体表面张力的存在，会导致高深宽比结构11发生变形，从而对半导体结构10造成破坏，进而影响最终形成的半导体产品的电学性能，导致产品良率较低。其原理参考图1B，如图1B所示，两个分立的高深宽比结构11之间具有间距S，此时高深宽比结构顶部的液体表面张力为γ，γ与高深宽比结构11侧面的夹角为θ，则作用在高深宽比结构11两侧的作用力F＝((2γcosθ)/S)*H*D，其中H、D分别为液体的高度和高深宽比结构11的高度。
在一些相关技术中，可以在高深宽比结构表面添加表面改性剂(如六甲基氧二硅烷，烷氧基硅烷，烷基硅烷，氟化的或基于三氯硅烷、二氯硅烷、单氯硅烷、甲氧基硅烷以及乙氧基硅烷的长链碳氢化合物等)，通过表面改性剂改变高深宽比结构的表面特性，以减少两个邻近表面之间的静摩擦力或者增加高深宽比结构表面的疏水性，从而有助于减少液体表面张力γ对高深宽比结构的破坏。但是，该方案中表面改性剂的成本较高，并且表面改性剂中的碳、氟或氯可能残留在高深宽比结构上，需要多加一道干式等离子体反应的灰化(Asher)过程来去除残留物，从而导致工艺成本较高。
在一些相关技术中，在对高深宽比结构进行清洗处理后，采用超临界干燥方法，利用超临界流体对清洗处理后的半导体结构进行干燥处理，通过将超临界流体从超临界状态到气相的直接相态转变使得不存在气-液界面，从而不存在对高深宽比结构作用的表面张力，这样可以在干燥高深宽比结构的同时不破坏该高深宽比结构。但是，该方案需要额外增加高成本的高压超临界干燥机台，并且需要额外的高压及大量超临界流体的厂务成本、大量超临界流体的消耗成本，从而导致工艺成本较高。
在一些相关技术中，在干燥高深宽比结构的过程中，将诸如聚合物基材料之类的刺激响应型材料用作防止结构塌陷的牺牲支撑材料。牺牲支撑材料凝固于高深宽比结构上和高深宽比结构周围，以提供机械支撑件并防止高深宽比结构在干燥期间塌陷。在干燥处理后，可以使用刺激(如紫外光、热和/或化学品之类的非等离子体基刺激)来去除机械支撑件。但是，该方案中刺激响应型材料的成本较高，并且刺激所使用的化学品可能残留在高深宽比结构上，需要多加一道干式等离子体反应的灰化过程来去除残留物，从而导致工艺成本较高。
有鉴于此，本公开实施例提供一种半导体结构的处理方法，如图2A所示，该方法包括步骤S101至步骤S104，其中：
步骤S101，提供待处理的半导体结构，半导体结构包括衬底、设置在衬底上的多个子结构；其中，子结构的深宽比大于预设比值。
这里，衬底可以是硅衬底、硅锗衬底、绝缘体上硅衬底等等。在一些实施方式中，衬底可以是单层衬底或多层衬底，例如单晶硅单层衬底、多晶硅单层衬底、多晶硅和金属多层衬底等。在一些实施方式中，衬底也可以包括其他半导体元素或包括半导体化合物，例如：碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)或锑化铟(InSb)，或包括其他半导体合金，例如：磷化砷镓(GaAsP)、砷化铟铝(AlInAs)、砷化镓铝(AlGaAs)、砷化铟镓(GaInAs)、磷化铟镓(GaInP)、和/或磷砷化铟镓(GaInAsP)或其组合。
在衬底上设置有多个子结构，每一子结构的深宽比大于预设比值。子结构采用的材料可以与衬底的材料相同，也可以与衬底的材料不同。在实施时，预设比值可以是本领域技术人员根据实际情况预先确定的，本公开实施例对此并不限定。在一些实施方式中，子结构为高深宽比结构，预设比值可以包括但不限于5:1、10:1或20:1等。在一些实施方式中，子结构为高深宽比的纳米结构。
在实施时，衬底上的子结构可以是通过任意合适的工艺形成的，采用的工艺可以包括但不限于刻蚀工艺(如湿法刻蚀工艺、干法刻蚀工艺)、沉积工艺(如选择性沉积工艺)等中的至少一种，本公开实施例对此并不限定。
在一些实施方式中，可以先提供衬底，然后在衬底上选择性沉积形成多个深宽比大于预设比值的子结构。
在一些实施方式中，可以先提供衬底以及设置在衬底上的覆盖层，通过光刻工艺，在覆盖层表面图案化用于定义子结构的硬掩模层和光刻胶掩模层，并基于该光刻胶掩模层和硬掩模层对覆盖层进行刻蚀，形成设置在衬底上的多个子结构。这里，覆盖层可以与衬底采用相同的材料，也可以与衬底采用不同的材料。
步骤S102，形成支撑层，支撑层桥接多个子结构之间关键尺寸小于尺寸阈值的第一区域，且支撑层具有至少一个开口。
这里，支撑层可以覆盖多个子结构的顶部，并桥接多个子结构之间关键尺寸小于尺寸阈值的第一区域。多个子结构之间具有一定的间隙，关键尺寸指的是子结构之间间隙的宽度，各子结构之间的关键尺寸可以是根据半导体结构的实际设计版图确定的。关键尺寸小于尺寸阈值的第一区域可以是任意两个子结构之间间隙的宽度小于尺寸阈值的 间隙区域。尺寸阈值可以是根据半导体结构的工艺要求和/或子结构的深宽比等确定的。例如，在半导体结构的工艺要求较高的情况下，可以设置较大的尺寸阈值，以在子结构之间关键尺寸较大的情况下也能对相应的子结构进行稳定，从而可以提高半导体结构的电学性能；在半导体结构的工艺要求较低的情况下，可以设置较小的尺寸阈值，这样减少支撑层的面积，从而可以减小工艺成本。又如，在子结构的深宽比较大的情况下，由于子结构的深宽比越大，液体表面张力导致的倾斜的情况越严重，因此可以设置较大的尺寸阈值，以在子结构之间关键尺寸较大的情况下也能对相应的子结构进行稳定；在子结构的深宽比较小的情况下，可以设置较小的尺寸阈值，这样减少支撑层的面积，从而可以减少工艺成本。
在实施时，形成支撑层的材料可以是任意合适的与形成子结构的材料之间具有较高刻蚀选择比的材料，本公开实施例对此并不限定。例如，形成子结构的材料可以是硅、硅锗等，形成支撑层的材料可以是氮化物等。
图2B和图2C分别为本公开实施例提供的一种半导体结构上形成支撑层后的俯视结构示意图和该半导体结构沿AA’方向的剖面结构示意图。如图2B和图2C所示，半导体结构100包括衬底110、设置在衬底110上的多个子结构120；形成的支撑层130覆盖多个子结构120的顶部；支撑层130桥接多个子结构120之间关键尺寸CD1小于尺寸阈值的第一区域131，且支撑层具有至少一个开口132。
步骤S103，利用开口对半导体结构进行清洗处理。
这里，可以采用任意合适的清洗工艺对半导体结构进行清洗处理，以清洁半导体结构中子结构的表面以及衬底的表面。
通过清洗处理，可以将子结构的形成过程中附着在支撑层之下的子结构表面的刻蚀副产物等去除。刻蚀副产物可以包括但不限于碳、氧化硅、氟化物、氯化物等中的至少一种。在实施时，可以采用湿法清洗工艺对半导体结构进行清洗处理。由于支撑层具有至少一个开口，通过该开口可以使得清洗液进入支撑层之下的子结构之间的间隙区域，以对支撑层之下的子结构进行清洗。清洗处理所采用的清洗液体可以包括但不限于氢氟酸(如浓度为49％的氢氟酸、稀释的氢氟酸)，摩尔比为1:6至1:4的硫酸和过氧化氢的混合溶液(即SPM混合溶液)，氨水、双氧水以及水的混合物(即SC1混合溶液)，盐酸、双氧水和水的混合物(即SC2混合溶液)等中的至少一种。
在一些实施方式中，还可以对清洗后的半导体结构进行干燥处理，通过干燥处理，可以对子结构表面和衬底表面进行干燥。在实施时，可以采用任意合适的干燥工艺对清洗后的半导体结构进行干燥处理，本公开实施例对此并不限定。干燥工艺可以包括但不限于液相干燥处理、气相干燥处理等中的至少一种。
步骤S104，去除多个子结构顶部的支撑层。
这里，可以在清洗处理后，采用任意合适的刻蚀工艺去除支撑层，本公开实施例对此并不限定。
在一些实施方式中，可以采用对支撑层的材料和子结构的材料的刻蚀选择比较大的刻蚀气体或腐蚀液等对支撑层进行刻蚀处理，去除支撑层，并保留子结构。例如，刻蚀气体或腐蚀液等对支撑层的材料和子结构的材料的刻蚀选择比可以为500：1。
在一些实施方式中，为减少去除支撑层的过程中对子结构表面和衬底表面的再次污染，可以基于后续工艺需求在子结构之间预先填充材料形成间隙填充层，以保护清洗后的子结构表面和衬底表面，并能在后续工艺中对子结构起到支撑作用。
在本公开实施例中，提供待处理的半导体结构，半导体结构包括衬底、设置在衬底上的多个子结构；其中，子结构的深宽比大于预设比值；形成支撑层，支撑层桥接多个子结构之间关键尺寸小于尺寸阈值的第一区域，且支撑层具有至少一个开口；利用开口 对半导体结构进行清洗处理；去除多个子结构顶部的支撑层。这样，一方面，由于深宽比大于预设比值的多个子结构顶部覆盖了支撑层，且支撑层桥接多个子结构之间关键尺寸小于尺寸阈值的第一区域，因此在对多个子结构进行清洗处理的过程中，支撑层可以起到稳定子结构的作用，减少液体表面张力对子结构的破坏，从而减少子结构的变形，进而提升半导体产品的电学性能，提高产品良率；另一方面，由于支撑层具有至少一个开口，通过该开口，可以使得清洗处理过程中清洗液可以进入子结构下部之间的间隙区域，达到更好地清洁子结构的效果。此外，在本公开实施例提供的半导体结构的处理方法中，无需采用高成本的表面改性剂、超临界流体及刺激响应型材料等，从而可以减少工艺成本，并且，通过在清洗处理之后将支撑层去除，可以进一步减少支撑层对半导体产品的电学性能的影响。
在一些实施例中，继续参见图2B和图2C，支撑层130在第二区域是打开的，以形成至少一个开口132，第二区域包括多个子结构120之间关键尺寸CD2大于或等于尺寸阈值的区域。这里，第二区域可以是任意两个子结构之间间隙的宽度大于或等于尺寸阈值的间隙区域。这样，由于支撑层在多个子结构之间关键尺寸大于或等于尺寸阈值的第二区域是打开的，可以使得形成的开口较大，便于后续清洗工艺中清洗液的流入和流出，并且能够进一步减少支撑层的面积，从而减少工艺成本。
在一些实施例中，上述步骤S102可以包括如下步骤S111：
步骤S111，采用预设沉积工艺，在多个子结构顶部沉积第一材料，形成支撑层；预设沉积工艺包括以下至少之一：选择性原子层沉积工艺、离子体增强化学气相沉积工艺。
这里，第一材料可以是根据实际情况选择的合适的材料，可以包括但不限于氮化物。
由于选择性原子层沉积工艺和离子体增强化学气相沉积工艺均具有较差的阶梯覆盖能力，因而采用选择性原子层沉积工艺和/或离子体增强化学气相沉积工艺，可以仅在多个子结构的顶部沉积第一材料，形成覆盖多个子结构顶部的支撑层。
在一些实施例中，参见图2D，子结构120顶部设置有硬掩模层140。
在一些实施例中，上述步骤S111可以包括如下步骤S121：
步骤S121，采用预设沉积工艺，在硬掩膜层表面沉积第一材料，形成支撑层。
这里，在一些实施方式中，可以在刻蚀子结构的过程中，图案化形成光刻胶掩模层和硬掩模层；接着，可以在刻蚀形成子结构后，去除图案化的光刻胶掩模层，保留子结构顶部的硬掩模层。
在一些实施方式中，在刻蚀子结构的过程中未图案化形成硬掩模层，可以在刻蚀形成子结构后在子结构表面沉积形成硬掩模层。
在实施时，沉积硬掩模层采用的材料可以包括但不限定于氧化硅、热氧化物、硅酸乙酯(TEOS)氧化物、高密度等离子氧化物、原子层沉积氧化物或自旋电介质氧化物等。
在上述实施例中，通过在沉积形成支撑层之前，先在子结构顶部设置硬掩模层，这样，硬掩模层可以作为保护层对子结构顶部进行保护。
在一些实施例中，上述步骤S103中所述的利用开口对半导体结构进行清洗处理，可以包括如下步骤S131至步骤S132：
步骤S131，对半导体结构进行灰化处理；
步骤S132，利用开口对灰化处理后的半导体结构进行清洗处理。
这里，灰化处理可以用于灰化刻蚀剩余的刻蚀气体或刻蚀液体，防止残留的刻蚀气体或刻蚀液体继续刻蚀子结构或者衬底。
参见图2E和图2F，在子结构120的形成过程中，可能会有一些刻蚀副产物21附着在支撑层130之下的子结构表面以及衬底表面，通过对半导体结构进行灰化处理，并 利用开口132对灰化处理后的半导体结构中的多个子结构120以及衬底110进行清洗处理，可以将刻蚀副产物21去除。
在一些实施方式中，可以采用无氧灰化处理的工艺对半导体结构进行灰化处理，即采用不含氧的第一混合气体对半导体结构进行灰化处理，第一混合气体至少包括氢气和氮气，以便清除刻蚀后残留在表面的腐蚀性气体和高分子材料。对于无氧灰化处理，由于混合气体中不含有氧气，并不会对半导体结构的表面造成损伤(不会氧化衬底、子结构及支撑层的表面)。此外，使用氢气能够有效去除残留在半导体结构表面的腐蚀性气体和高分子材料。
在一些实施方式中，可以采用有氧灰化处理的工艺对半导体结构进行灰化处理，即采用含氧的第二混合气体对半导体结构进行灰化处理，第二混合气体至少包括氢气、氮气和氧气。对于有氧灰化处理，由于混合气体中含有氧气，灰化效率更高，能更快地清除刻蚀后残留在半导体结构表面的腐蚀性气体和高分子材料。
上述实施例中，通过对半导体结构进行灰化处理，并利用支撑层的开口对灰化处理后的半导体结构进行清洗处理，这样可以更好地清洁支撑层之下的子结构表面以及衬底表面。
在一些实施例中，上述步骤S104可以包括如下步骤S141至步骤S143：
步骤S141，在清洗处理后的多个子结构之间填充第二材料，形成覆盖多个子结构和支撑层的第一填充层。
这里，第二材料包括以下至少之一：氧化物、氮化物。在实施时，第二材料可以包括氧化物(如氧化硅、氧化锗等)、氮化物(如氮化硅、氮化锗等)，也可以包括氧化物-氮化物组合物，本公开实施例对此并不限定。在一些实施方式中，第一填充层可以作为介电层，用于进行导电层之间的隔离。
图2G和图2H分别为本公开实施例提供的一种半导体结构的处理方法中形成第一填充层后的半导体结构的俯视结构示意图和该半导体结构沿AA’方向的剖面结构示意图，如图2G和图2H所示，在清洗处理后的多个子结构120之间填充第二材料，可以形成覆盖多个子结构120和支撑层130的第一填充层150。
步骤S142，对第一填充层表面进行平坦化处理，直至暴露支撑层的顶表面。
这里，平坦化处理可以包括但不限于刻蚀处理和/或抛光处理等。刻蚀处理可以例如湿法刻蚀、干法刻蚀等。抛光处理可以例如化学机械抛光(Chemical Mechanical Polishing，CMP)等。
在一些实施方式中，可以将第一填充层表面与抛光工艺中采用的氧化剂、催化剂等发生化学反应，生成一层相对容易去除的软质层；接着在抛光工艺中采用的磨料和抛光垫的机械作用下去除该软质层；重复前述生成软质层和去除软质层的步骤，这样可以在化学反应和机械研磨的共同作用下实现第一填充层表面的平坦化处理，直至暴露支撑层的顶表面。
在一些实施方式中，可以对第一填充层表面进行刻蚀处理，去除第一填充层的表层；然后通过清洗处理，将刻蚀处理后的残留物去除；重复刻蚀处理和清洗处理，可以使第一填充层表面达到合适的平整度，从而实现第一填充层表面的平坦化处理，直至暴露支撑层的顶表面。
图2I和图2J分别为本公开实施例提供的一种半导体结构的处理方法中平坦化处理后的半导体结构的俯视结构示意图和该半导体结构沿AA’方向的剖面结构示意图，如图2I和图2J所示，对第一填充层150表面进行平坦化处理后，可以暴露支撑层130的顶表面。
步骤S143，对平坦化处理后的第一填充层和支撑层进行刻蚀处理，直至去除支撑 层。
这里，可以对第一填充层和支撑层同时进行刻蚀处理，直至去除支撑层；也可以先对第一填充层进行刻蚀处理，以暴露出支撑层的全部，然后对支撑层进行刻蚀，以去除支撑层。在实施时，可以采用任意合适的刻蚀工艺对第一填充层和支撑层进行刻蚀处理，如湿法刻蚀工艺、干法刻蚀工艺等，本公开实施例对此并不限定。
图2K和图2L分别为本公开实施例提供的一种半导体结构的处理方法中去除支撑层后的半导体结构的俯视结构示意图和该半导体结构沿AA’方向的剖面结构示意图，如图2K和图2L所示，可以对第一填充层150的上部和支撑层130进行刻蚀处理，去除支撑层130，暴露出每一子结构120的顶部。
上述实施例中，在清洗处理后的多个子结构之间填充第二材料，形成覆盖多个子结构和支撑层的第一填充层；对第一填充层表面进行平坦化处理，直至暴露支撑层的顶表面；对平坦化处理后的第一填充层和支撑层进行刻蚀处理，直至去除支撑层。这样，由于第一填充层可以对多个子结构进行稳定，从而可以减少去除支撑层的过程中对子结构的破坏，并能减少对支撑层之下的子结构和衬底的污染。
在一些实施例中，上述步骤S104还可以包括如下步骤S151：
步骤S151，在形成第一填充层之前，在清洗处理后的多个子结构表面形成第一衬垫层。
这里，可以在填充第二材料形成第一填充层之前，在清洗处理后的多个子结构表面形成第一衬垫层，然后在形成第一衬垫层后的多个子结构之间填充第二材料，形成覆盖子结构、支撑层和第一衬垫层的第一填充层。
在实施时，形成的第一衬垫层的材料可以包括但不限于热氧化物(如二氧化硅等)、硅、氧化物、氮化物等中的至少一种，本公开实施例对此并不限定。
图2M为本公开实施例提供的一种半导体结构的处理方法中形成第一衬垫层和第一填充层后的半导体结构的剖面结构示意图，如图2M所示，在清洗处理后的多个子结构120表面形成了第一衬垫层160，第一填充层150覆盖子结构120、支撑层130和第一衬垫层160。
这样，一方面，第一衬垫层可以对刻蚀形成子结构的过程中在子结构表面造成的损伤进行修复；另一方面，第一衬垫层可以对子结构进行保护，减少后续工艺过程中器件应力或刻蚀等操作对子结构的损害。
在一些实施例中，上述步骤S151可以包括以下步骤S161或步骤S162：
步骤S161，对清洗处理后的多个子结构进行热氧化处理，形成覆盖多个子结构表面的第一衬垫层。
这里，在一些实施方式中，第一衬垫层的材料可以包括热氧化物(如二氧化硅等)。参见图3A，通过热氧化处理可以在子结构120表面及衬底110表面生成热氧化物，以形成覆盖每一子结构120表面的第一衬垫层160。
步骤S162，在清洗处理后的多个子结构表面沉积第三材料，形成覆盖多个子结构表面以及支撑层表面的第一衬垫层。
这里，在一些实施方式中，第三材料可以包括以下至少之一：硅、氧化物、氮化物。硅可以包括但不限于非晶硅、多晶硅、晶体硅等中的至少一种。氧化物可以包括但不限于硅酸乙酯氧化物、原子层沉积氧化物等中的至少一种。参见图3B，可以在子结构120表面及支撑层130表面沉积第三材料，形成覆盖每一子结构120表面以及支撑层130表面的第一衬垫层160。
在一些实施例中，上述方法还可以包括如下步骤S171：
步骤S171，对去除支撑层后的多个子结构进行再次清洗处理；
这里，继续参见图2E和图2F，在子结构120的形成过程中，可能还会有一些刻蚀副产物22附着在子结构120顶部，在形成支撑层130后，刻蚀副产物22被覆盖在支撑层130之下，因而，可以对去除支撑层130之后的多个子结构进行再次清洗处理，以将附着在子结构120顶部的刻蚀副产物22去除。
在实施时，再次清洗处理所采用的清洗液可以包括但不限于稀释的氢氟酸，缓冲氧化物刻蚀液(由49％浓度的氢氟酸与水、或氟化铵与水混合而成)、磷酸、SPM混合溶液或SC1混合溶液等中的至少一种。
在一些实施例中，在步骤S171之后，上述方法还可以包括如下步骤S172：
步骤S172，在再次清洗处理后的多个子结构之间填充第四材料，形成覆盖多个子结构顶部以及第一填充层的第二填充层。
这里，第四材料包括以下至少之一：氧化物、氮化物。在实施时，第四材料可以包括氧化物(如氧化硅、氧化锗等)、氮化物(如氮化硅、氮化锗等)，也可以包括氧化物-氮化物组合物，本公开实施例对此并不限定。在一些实施方式中，第二填充层可以作为介电层，用于进行导电层之间的隔离。
图3C和图3D分别为本公开实施例提供的一种半导体结构的处理方法中形成第二填充层后的半导体结构的俯视结构示意图和该半导体结构沿AA’方向的剖面结构示意图，如图3C和图3D所示，在再次清洗处理后的多个子结构120之间填充第四材料，可以形成覆盖多个子结构120顶部以及第一填充层150的第二填充层170。
在上述实施例中，支撑层是在形成第一填充层之后去除的，在对去除支撑层后的多个子结构进行再次清洗处理的过程中，第一填充层可以起到稳定子结构的作用，并能减小子结构的深宽比，以减少液体表面张力对子结构的破坏，从而减少子结构的变形，进而提升半导体产品的电学性能，提高产品良率。
在一些实施例中，在上述步骤S172之前，上述方法还可以包括如下步骤S181：
步骤S181，在形成第二填充层之前，在再次清洗处理后的多个子结构顶部形成第二衬垫层。
这里，可以在填充第四材料形成第二填充层之前，在再次清洗处理后的多个子结构表面形成第一衬垫层，然后在形成第一衬垫层后的多个子结构之间填充第四材料，形成覆盖多个子结构顶部、第一填充层和第二衬垫层的第二填充层。
在实施时，形成的第二衬垫层的材料可以包括但不限于热氧化物(如二氧化硅等)、硅、氧化物、氮化物等中的至少一种，本公开实施例对此并不限定。
需要说明的是，第二衬垫层的材料与第一衬垫层的材料可以相同，也可以不同；形成第二衬垫层的工艺与形成第一衬垫层的工艺可以相同，也可以不同。
这里，图3E为本公开实施例提供的一种半导体结构的处理方法中形成第二衬垫层和第二填充层后的半导体结构的剖面结构示意图，如图3E所示，在再次清洗处理后的多个子结构120顶部形成了第二衬垫层180，第二填充层170覆盖子结构120顶部、第一填充层150和第二衬垫层180。
这样，一方面，第二衬垫层可以对去除支撑层和/或设置在子结构顶部的硬掩模层的过程中在子结构表面造成的损伤进行修复；另一方面，第二衬垫层可以对子结构进行保护，减少后续工艺过程中器件应力或刻蚀等操作对子结构的损害；再一方面，第二衬垫层可以对子结构上部的关键尺寸进行补偿，使得表面形成第二衬垫层后的子结构上部的关键尺寸与表面形成了第一衬垫层的子结构下部之的关键尺寸保持一致。
在一些实施例中，上述步骤S181可以包括以下步骤S191或步骤S192：
步骤S191，对再次清洗处理后的多个子结构顶部进行热氧化处理，形成覆盖多个子结构顶部表面的第二衬垫层。
这里，在一些实施方式中，第二衬垫层的材料可以包括热氧化物(如二氧化硅等)。参见图3F，通过热氧化处理可以在子结构120表面生成热氧化物，以形成覆盖每一子结构120顶部表面的第二衬垫层180。
步骤S192，在再次清洗处理后的多个子结构表面沉积第五材料，形成覆盖多个子结构表面和第一填充层表面的第二衬垫层。
这里，在一些实施方式中，第五材料可以包括以下至少之一：硅、氧化物、氮化物。硅可以包括但不限于非晶硅、多晶硅、晶体硅等中的至少一种。氧化物可以包括但不限于硅酸乙酯氧化物、原子层沉积氧化物等中的至少一种。参见图3G，可以在子结构120表面及第一填充层150表面沉积第五材料，形成覆盖每一子结构120顶部表面以及第一填充层150表面的第二衬垫层180。
本公开实施例提供一种半导体结构，参见图2B和图2C，该半导体结构100包括：
衬底110；
设置在衬底110上的多个子结构120，子结构120的深宽比大于预设比值；
覆盖多个子结构120顶部的支撑层130，支撑层130桥接多个子结构120之间关键尺寸CD1小于尺寸阈值的第一区域131，且支撑层130具有至少一个开口。
在一些实施例中，继续参见图2B和图2C，支撑层130在第二区域是打开的，以形成至少一个开口132，第二区域包括多个子结构120之间关键尺寸CD2大于或等于尺寸阈值的区域。
在一些实施例中，参见图2D，子结构120顶部设置有硬掩模层140，支撑层130覆盖硬掩模层140。
在一些实施例中，支撑层采用的材料包括氮化物；硬掩模层采用的材料包括氧化物。
本公开实施例提供一种半导体结构的形成方法，图4为本公开实施例提供的一种半导体结构的形成方法的实现流程示意图。如图4所示，该方法包括如下步骤S401至步骤S403：
步骤S401，提供衬底；
步骤S402，在所述衬底上形成多个子结构，所述子结构的深宽比大于预设比值；
步骤S403，形成覆盖所述多个子结构顶部的支撑层，所述支撑层桥接所述多个子结构之间关键尺寸小于尺寸阈值的第一区域，且所述支撑层具有至少一个开口。
本公开实施例提供一种半导体结构，该半导体结构是采用上述任一处理方法实施例中所述的半导体结构的处理方法处理得到的。
上述半导体结构实施例，具有与半导体结构的处理方法实施例相似的有益效果。对于本公开半导体结构实施例中未披露的技术细节，请参照本公开半导体结构的处理方法实施例的描述而理解。
在本公开所提供的几个实施例中，应该理解到，所揭露的结构和方法，可以通过非目标的方式实现。以上所描述的结构实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元，即可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
本公开所提供的几个方法或结构实施例中所揭露的特征，在不冲突的情况下可以任意组合，得到新的方法实施例或结构实施例。
以上所述，仅为本公开实施例的一些实施方式，但本公开实施例的保护范围并不局 限于此，任何熟悉本技术领域的技术人员在本公开实施例揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开实施例的保护范围之内。
工业实用性
本公开实施例提供一种半导体结构的处理方法及形成方法、半导体结构。其中，半导体结构的处理方法包括：提供待处理的半导体结构，所述半导体结构包括衬底、设置在所述衬底上的多个子结构；其中，所述子结构的深宽比大于预设比值；形成支撑层，所述支撑层桥接所述多个子结构之间关键尺寸小于尺寸阈值的区域，且所述支撑层具有至少一个开口；利用所述开口对所述半导体结构进行清洗处理；去除所述多个子结构顶部的所述支撑层。根据本公开实施例，一方面，在对多个子结构进行清洗处理的过程中，可以减少液体表面张力对子结构的破坏，从而减少子结构的变形，进而提升半导体产品的电学性能，提高产品良率；另一方面，可以达到更好地清洁子结构的效果。

Claims (16)

  1. 一种半导体结构(100)的处理方法，所述方法包括：
    提供待处理的半导体结构(100)，所述半导体结构(100)包括衬底(110)、设置在所述衬底(110)上的多个子结构(120)；其中，所述子结构(120)的深宽比大于预设比值；
    形成支撑层(130)，所述支撑层(130)桥接所述多个子结构(120)之间关键尺寸小于尺寸阈值的第一区域(131)，且所述支撑层(130)具有至少一个开口(132)；
    利用所述开口(132)对所述半导体结构(100)进行清洗处理；
    去除所述多个子结构(120)顶部的所述支撑层(130)。
  2. 根据权利要求1所述的方法，其中，所述支撑层(130)在第二区域是打开的，以形成至少一个所述开口(132)，所述第二区域包括所述多个子结构(120)之间关键尺寸大于或等于所述尺寸阈值的区域。
  3. 根据权利要求1或2所述的方法，其中，所述形成支撑层(130)，包括：
    采用预设沉积工艺，在所述多个子结构(120)顶部沉积第一材料，形成所述支撑层(130)；所述预设沉积工艺包括以下至少之一：选择性原子层沉积工艺、离子体增强化学气相沉积工艺。
  4. 根据权利要求3所述的方法，其中，所述子结构(120)顶部设置有硬掩模层(140)。
  5. 根据权利要求1至4中任一项所述的方法，其中，所述利用所述开口(132)对所述半导体结构(100)进行清洗处理，包括：
    对所述半导体结构(100)进行灰化处理；
    利用所述开口(132)对灰化处理后的所述半导体结构(100)进行清洗处理。
  6. 根据权利要求1至5中任一项所述的方法，其中，所述去除所述多个子结构(120)顶部的所述支撑层(130)，包括：
    在清洗处理后的所述多个子结构(120)之间填充第二材料，形成覆盖所述多个子结构(120)和所述支撑层(130)的第一填充层(150)；
    对所述第一填充层(150)表面进行平坦化处理，直至暴露所述支撑层(130)的顶表面；
    对平坦化处理后的所述第一填充层(150)和所述支撑层(130)进行刻蚀处理，直至去除所述支撑层(130)。
  7. 根据权利要求6所述的方法，其中，所述去除所述多个子结构(120)顶部的所述支撑层(130)，还包括：
    在形成所述第一填充层(150)之前，在清洗处理后的所述多个子结构(120)表面形成第一衬垫层(160)。
  8. 根据权利要求7所述的方法，其中，所述在清洗处理后的所述多个子结构(120)表面形成第一衬垫层(160)，包括：
    对清洗处理后的所述多个子结构(120)进行热氧化处理，形成覆盖所述多个子结构(120)表面的第一衬垫层(160)；
    或，
    在清洗处理后的所述多个子结构(120)表面沉积第三材料，形成覆盖所述多个子结构(120)表面以及所述支撑层(130)表面的第一衬垫层(160)。
  9. 根据权利要求6至8中任一项所述的方法，所述方法还包括：
    对去除所述支撑层(130)后的所述多个子结构(120)进行再次清洗处理。
  10. 根据权利要求9所述的方法，所述方法还包括：
    在再次清洗处理后的所述多个子结构(120)之间填充第四材料，形成覆盖所述多个子结构(120)顶部以及所述第一填充层(150)的第二填充层(170)。
  11. 根据权利要求10所述的方法，所述方法还包括：
    在形成所述第二填充层(170)之前，在再次清洗处理后的所述多个子结构(120)顶部形成第二衬垫层(180)。
  12. 根据权利要求11所述的方法，其中，所述在再次清洗处理后的所述多个子结构(120)顶部形成第二衬垫层(180)，包括：
    对再次清洗处理后的所述多个子结构(120)顶部进行热氧化处理，形成覆盖所述多个子结构(120)顶部表面的第二衬垫层(180)；
    或，
    在再次清洗处理后的所述多个子结构(120)表面沉积第五材料，形成覆盖所述多个子结构(120)表面和所述第一填充层(150)表面的第二衬垫层(180)。
  13. 一种半导体结构(100)，包括：
    衬底(110)；
    设置在所述衬底(110)上的多个子结构(120)，所述子结构(120)的深宽比大于预设比值；
    覆盖所述多个子结构(120)顶部的支撑层(130)，所述支撑层(130)桥接所述多个子结构(120)之间关键尺寸小于尺寸阈值的第一区域(131)，且所述支撑层(130)具有至少一个开口。
  14. 根据权利要求13所述的半导体结构(100)，其中，所述支撑层(130)在第二区域是打开的，以形成至少一个所述开口(132)，所述第二区域包括所述多个子结构(120)之间关键尺寸大于或等于所述尺寸阈值的区域。
  15. 根据权利要求13或14所述的半导体结构(100)，其中，所述子结构(120)顶部设置有硬掩模层(140)，所述支撑层(130)覆盖所述硬掩模层(140)。
  16. 一种半导体结构(100)，所述半导体结构(100)是采用如权利要求1-12任一项处理方法处理得到的。
PCT/CN2023/110791 2022-10-21 2023-08-02 半导体结构的处理方法及半导体结构 WO2024082774A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211290543.2A CN117954306A (zh) 2022-10-21 2022-10-21 半导体结构的处理方法及半导体结构
CN202211290543.2 2022-10-21

Publications (1)

Publication Number Publication Date
WO2024082774A1 true WO2024082774A1 (zh) 2024-04-25

Family

ID=90736913

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/110791 WO2024082774A1 (zh) 2022-10-21 2023-08-02 半导体结构的处理方法及半导体结构

Country Status (2)

Country Link
CN (1) CN117954306A (zh)
WO (1) WO2024082774A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103839824A (zh) * 2012-11-21 2014-06-04 英飞凌科技德累斯顿有限责任公司 制造半导体器件的方法
US20190189501A1 (en) * 2015-12-23 2019-06-20 SK Hynix Inc. Isolation structure and method for manufacturing the same
CN113540347A (zh) * 2020-04-14 2021-10-22 中国科学院微电子研究所 电容器、半导体器件、电子设备及其制造方法
CN113889404A (zh) * 2020-07-02 2022-01-04 长鑫存储技术有限公司 半导体结构的处理方法及形成方法
CN113889405A (zh) * 2020-07-02 2022-01-04 长鑫存储技术有限公司 半导体结构的处理方法及形成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103839824A (zh) * 2012-11-21 2014-06-04 英飞凌科技德累斯顿有限责任公司 制造半导体器件的方法
US20190189501A1 (en) * 2015-12-23 2019-06-20 SK Hynix Inc. Isolation structure and method for manufacturing the same
CN113540347A (zh) * 2020-04-14 2021-10-22 中国科学院微电子研究所 电容器、半导体器件、电子设备及其制造方法
CN113889404A (zh) * 2020-07-02 2022-01-04 长鑫存储技术有限公司 半导体结构的处理方法及形成方法
CN113889405A (zh) * 2020-07-02 2022-01-04 长鑫存储技术有限公司 半导体结构的处理方法及形成方法

Also Published As

Publication number Publication date
CN117954306A (zh) 2024-04-30

Similar Documents

Publication Publication Date Title
CN110416184B (zh) 半导体结构及其形成方法
TWI235429B (en) Semiconductor device and its manufacturing method
CN106935493B (zh) 形成半导体装置的方法
US9589800B2 (en) Method for integrated circuit patterning
CN109427670B (zh) 周围包裹的外延结构和方法
JP2010109151A (ja) 使用済み半導体ウエハの再生方法
CN109585560A (zh) 半导体元件的制造方法
JP2007110005A (ja) 半導体装置の製造方法
CN107017203A (zh) 半导体元件的制造方法
US9711374B2 (en) Mechanisms for forming oxide layer over exposed polysilicon during a chemical mechanical polishing (CMP) process
TW201617283A (zh) 半導體結構及其製造方法
JP5556851B2 (ja) 半導体装置の製造方法
WO2024082774A1 (zh) 半导体结构的处理方法及半导体结构
TWI739439B (zh) 半導體裝置及其形成方法
CN108091553B (zh) 掩模图形的形成方法
TWI748496B (zh) 半導體結構及形成半導體結構的方法
KR100929731B1 (ko) 반도체 소자의 제조 방법
JP5047100B2 (ja) 使用済み半導体ウエハの再生方法
TWI838068B (zh) 半導體裝置及其形成方法
CN117976607B (zh) 半导体器件的沟槽隔离制备方法以及半导体器件
TWI786490B (zh) 半導體結構及其形成方法
CN111725137B (zh) 一种半导体器件的形成方法
CN220155548U (zh) 半导体装置
US6080677A (en) Method for preventing micromasking in shallow trench isolation process etching
TWI779607B (zh) 形成半導體結構的方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23878770

Country of ref document: EP

Kind code of ref document: A1