CN106935493B - 形成半导体装置的方法 - Google Patents
形成半导体装置的方法 Download PDFInfo
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- CN106935493B CN106935493B CN201611246910.3A CN201611246910A CN106935493B CN 106935493 B CN106935493 B CN 106935493B CN 201611246910 A CN201611246910 A CN 201611246910A CN 106935493 B CN106935493 B CN 106935493B
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Abstract
本案揭露一种形成半导体装置的方法。此方法包含提供一前驱物,其具有一基板和位于基板上的栅极堆叠,而栅极堆叠各包含一电极层、一第一硬罩(HM)层在电极层上,和一第二HM层其在第一HM层上。此方法进一步地包含沉积一介电层在基板和栅极堆叠上,且填充栅极堆叠之间的空间;并且执行一第一化学机械平坦化(CMP)程序以部分地移除介电层。此方法更进一步地包含执行一蚀刻程序以移除第二HM层且部分地移除介电层,借以暴露第一HM层。此方法更进一步地包含执行第二CMP制程直到至少部分地移除第一HM层。
Description
技术领域
本揭露内容是关于半导体装置,特别是半导体装置的栅极置换制程。
背景技术
半导体集成电路(IC)产业经历了指数级成长。在IC材料和设计技术上的进展,造就了一代又一代越发缩小和复杂电路的IC。在IC演化的历程中,功能密度(如,晶片单位面积上互连装置的数目)逐渐地增加,而几何尺寸(如:使用的制程所能创造的最小组件(或线路))则减小。这样的尺寸微缩的过程,一般有益于增加生产效率和降低相关的成本。如此的尺寸缩小亦增加了处理和制造IC上的复杂度,而且对于要实现这些进展,也需要在IC处理和制造上得到类似的发展。
在IC设计中实现的一个进展是将典型的多晶硅栅极以金属栅极取代,用以在缩小特征尺寸时改良装置的性能。一形成金属栅极电极的制程称为栅极-置换或是“栅极-后(gate-last)”制程,其是经由置换多晶硅栅极“后”,才制造金属栅极电极。这使得后续制程的数目减少,包括高温制程,其是在形成最终栅极之后执行。然而,实施这等IC制造程序具有挑战性,特别是在进阶的制程世代中,缩小IC特征,诸如20纳米(nm),16nm,和更小于此的世代。例如,IC的不同区域可能有不同的栅极长度,和/或在栅极形成和栅极以金属栅极置换之间,其经历不同的制造步骤。在IC的不同区域中,将多晶硅栅极之间维持在一致的高度是很具挑战性的。多晶硅栅极高度上的变异,会对于后续的栅极置换制程引发问题。
发明内容
在一示例的观点中,本揭露内容是针对于形成半导体装置的一方法。此方法包含提供一前驱物,其具有基板和位于基板上的栅极堆叠。栅极堆叠的各者包含一电极层、一硬罩层(HM)层在电极层上,和一第二HM层在第一HM层上。此方法更进一步地包含沉积一介电层在基板和栅极堆叠上,且填充介于栅极堆叠之间的空间。此方法更进一步地包含执行一第一化学机械平坦化(CMP)制程,以部分地移除介电层;并且执行一蚀刻制程,以移除第二HM层,和部分地移除介电层,借以暴露第一HM层。此方法更进一步地包含执行一第二CMP制程直到至少部分地移除第一HM层。
在另一示例的观点中,本揭露内容是针对于形成半导体装置的一方法。此方法包含提供一前驱物,其具有基板和位于基板上的栅极堆叠,其中栅极堆叠的各者包含一电极层、一硬罩层(HM)层在电极层上,和一第二HM层在第一HM层上。此方法更进一步地包含沉积一蚀刻停止层(ESL)在基板上并且覆盖栅极堆叠的上部和侧壁,且沉积一层间介电层(ILD)在ESL上,并且填充介于栅极堆叠之间的空间。此方法更进一步地包含执行一第一化学机械平坦化(CMP)制程,以部分地移除ILD层;执行干蚀刻制程以部分地移除ESL、ILD层,和第二HM层,借以暴露第一HM层。此方法更进一步地包含执行一第二CMP制程直到至少部分地移除第一HM层。
在另一示例的观点中,本揭露内容是针对于形成半导体装置的一方法。此方法包含提供一前驱物,其具有基板和位于基板上的栅极堆叠。栅极堆叠的各者包含一复合多层、一氮化物硬罩层(HM)层在此复合多层上,和一氧化物HM层在氮化物HM层上。此方法更进一步地包含形成一蚀刻停止层(ESL)在栅极堆叠的上部和侧壁。此ESL包含氮化物。此方法更进一步地包含沉积一层间介电层(ILD),其覆盖ESL和栅极堆叠,并且填充介于栅极堆叠之间的空间。此ILD层包含氧化物。此方法更进一步地包含执行一第一化学机械平坦化(CMP)制程,以部分地移除至少此ESL,此ILD层,和此氧化物HM层;在执行第一蚀刻制程之后,此方法更进一步地包含执行一第二蚀刻制程,以选择性调适来蚀刻此ILD层和此氧化物HM层,而此氮化物HM层维持基本上不变的,借以暴露此氮化物HM层。此方法更进一步地包含执行一第二CMP制程,以选择性地移除此氮化物HM层,而此ILD层维持基本上不变的。
附图说明
当与所附附图一起阅读时,本揭露内容可自以下详细的描述而得到最好的理解。要强调的是,根据产业的标准做法,各个特征并不按尺寸绘制,而仅用来说明目的。事实上,为了清楚地讨论,各个特征的尺寸可任意地增加或减小。
附图图1是根据本揭露内容的各不同的观点,形成半导体装置的方法的流程图;
附图图2和图3是根据一些实施例,在附图图1中的方法的一些步骤的实施例;
附图图4、5、6、7、8、9、10、13、14是根据一实施例,和根据附图图1的方法,绘示形成目标半导体装置的剖面图;
附图图11和图12是根据一实施例,和根据附图图1的方法,绘示形成目标半导体结构的俯视图。
具体实施方式
以下的揭露内容提供许多不同的实施例或示例,以实现所提供标的的不同特征。为了简化本揭露内容,成分和配置的不同示例如后描述。这些当然仅是示例,目的不在于限制。例如,在描述中提及,形成第一特征,其高于或在第二特征之上,之后可能包括实施例,其中形成第一和第二特征其为直接接触,也可能包括实施例,其中额外的特征可能形成在第一和第二特征之间,因此第一和第二特征不是直接接触。此外,在各不同的示例中,本揭露内容可能重复标号和/或字母。这样的重复目的在于简化和清楚,并不指称在所讨论的各实施例和/或配置之间有关系存在。
更进一步地,空间上的相关用语,诸如“下”、“低于”、“较低”、“高于”、“上方”,和类似者,在此使用以易于描述在所绘示的附图中,一元件或特征与另一元件或特征的关系。空间上的相关用语目的在于,除了描绘于附图中的方位以外,包含使用或操作中的装置的不同位向。这些设施可能是不同的位向(旋转90度或其他位向),而在此使用的空间上的相关用语可据此解释。
参看附图图1,其中所示是根据本揭露内容的各不同观点,形成半导体装置的方法10。如后将讨论,此装置将经历栅极置换制程,以最终(金属)栅极置换典型的多晶硅栅极。方法10的一些实施例中的一个目标,是为提供在被置换前具有一致性高度的栅极,因而消除或减少典型“栅极-后”制程的问题,诸如晶粒内栅极高度装载问题,和不完全的多-切问题。方法10是一示例,目的不在于限制本揭露内容在申请专利范围所明确列举的事项。对于此方法的额外的实施例,可提供额外的操作于方法10之前、之中、之后,而且所描述的一些操作可以取代、删除,或移位。方法10描述如后,连结以附图图4至图14,其为根据本揭露内容的各观点,装置100的剖面图和俯视图。
所示的装置100,可能是为一IC或其一部分,于制造过程中的中间物装置,其可能包含静态随机存取记忆体(SRAM)和/或其他逻辑电路,被动元件,诸如电阻、电容、诱导器,和主动元件,诸如p-型场效晶体管(PFET)、n-型FET(NFET),金属-氧化物半导体场效晶体管(MOSFET),互补式金属-氧化物半导体(CMOS)晶体管,双极型晶体管,高电压晶体管、高频率晶体管,其他记忆单元,和其组合。更进一步地,晶体管可能是多-栅极晶体管,诸如FinFETs。
在操作12,方法10(图1)提供此装置100的前驱物。为了便于讨论,此前驱物也称为装置100。参看附图图4,装置100包含基板102,和栅极堆叠104其沉积于基板102之上。在本实施例中,基板102是硅晶基板。另择地,基板102可能包含另一个元素半导体,诸如锗;化合物半导体,包含碳化硅、砷化镓、磷化镓、磷化铟、砷化铟,和/或锑化铟;合金半导体包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP,和/或GaInAsP;或其组合。在又另择者,基板102是绝缘层上覆半导体(SOI)。即使未附图,基板102可能包含由隔离特征所分隔的主动区域。例如,主动区域可能是n-型掺杂主动区域和/或p-型掺杂主动区域,且可能是平面型主动区域和/或非平面型主动区域(如:鳍式)。此隔离特征可能是浅沟槽隔离(STI)特征、场氧化物、局部硅氧化(LOCOS),和/或其他合适的结构。更进一步地,基板102可能包含磊晶特征。
在所示的实施例中,栅极堆叠104的各者包含电极层106,第一硬罩(HM)层108于电极层106之上,和第二HM层110于第一HM层108之上。在一实施例中,电极层106包含多晶硅。形成电极层106可能由合适的沉积制程,例如低压化学气相沉积(LPCVD)和等离子促进CVD(PECVD)。在一实施例中,第一HM层108包括介电材料其包含氮化物,例如氮化硅或氮氧化硅;且第二HM层110包括介电材料其包含氧化物,例如氧化硅。例如,形成氮化硅HM层108可能经由CVD,其使用化合物包括:六氯乙硅烷(HCD或Si2Cl6)、二氯硅烷(DCS或SiH2Cl2)、双第三丁基胺基硅烷(Bis(TertiaryButylAmino)Silane)(BTBAS或C8H22N2Si)和乙硅烷(DS或Si2H6)。例如,可经由热氧化,形成氧化硅HM层110。在各实施例中,第一HM层108和第二HM层110包含不同的介电材料。第一和第二HM层的各者,108和110,其形成可经由合适的沉积方法,诸如化学氧化、热氧化、原子层沉积(ALD)、化学气相沉积(CVD)、和/或其他合适的方法。栅极堆叠104可能包含其他的分层,例如介于电极层106和基板102之间的介面层。
在实施例中,栅极堆叠104的各层,可能首先沉积为基板102上的毯覆层,之后图案化,利用包含一个或多个光刻程序和一个或多个蚀刻程序的制程。典型的光刻制程包含涂覆光阻层在目标层上,软烤此光阻层,和使用遮罩(光罩)向此光阻层暴露辐射。光刻制程更进一步地包含曝光后烘烤,显影,和硬烤,借以移除光阻层的部分,且留下与遮罩元件同样的图案化光阻层。遮罩元件提供各个开口,经由这些开口,利用干蚀刻、湿蚀刻,或其他合适的蚀刻方法,蚀刻此目标层。例如,干蚀刻制程可能使用含氧气体,含氟气体(如,CF4、SF6、CH2F2、CHF3,和/或C2F6),含氯气体(如,Cl2、CHCl3、CCl4,和/或BCl3),含溴气体(如,HBr和/或CHBr3),含碘气体,其他合适的气体和/或等离子,和/或其组合。例如,湿蚀刻制程可能包含蚀刻在稀释的氢氟酸(DHF);氢氧化钾(KOH)溶液;氨;含氢氟酸(HF)的溶液,硝酸(HNO3),和/或醋酸(CH3COOH);或其他合适的湿蚀刻剂。在一实施例中,对于蚀刻第一和第二HM层,110和108,利用光阻作为遮罩元件。随后,对于蚀刻电极层106,利用第一和第二HM层,110和108,作为遮罩元件。此一个或多个蚀刻制程移除目标层的部分,使得栅极堆叠104立于基板102上。
虽然未图示,装置100可能更进一步地包含栅极间隔物在栅极堆叠104的侧壁上。例如,栅极间隔物可能包含介电材料,例如氧化硅、氮化硅,或氮氧化硅,且可能经由一个或多个沉积和反蚀刻技术形成。
栅极堆叠104可能形成在基板102的不同范围或区域。在所示的实施例中,形成栅极堆叠在基板区域102a、102b、102c,和102d。在附图图4至图14所示的在每一个区域中,基板区域的数目和栅极堆叠的数目,这是为了简化和易于理解,并不必要限制实施例于任何装置的型式、任何装置的数目、任何区域的数目,或任何结构或区域的配置。对于形成不同的装置型式,例如SRAM装置或逻辑装置,可利用不同的基板区域102a-d。在不同基板区域的栅极堆叠104可能具有沿着“x”方向的不同图案化的间距和/或不同图案化的宽度。例如在图4中所示,相较于基板区域102c的栅极堆叠,在基板区域102b的栅极堆叠104具有较窄的图案化的宽度和较小的图案化的间距。在一实施例中,基板区域102b是为了形成SRAM单元,而基板区域102c是为了形成输入/输出(IO)单元。
仍然参看附图图4,在一些实施例中,栅极堆叠104可能具有沿着“z”方向的不同高度。具体而言,HM层110的高度(或厚度)可能在不同的基板区域间有变异。例如,在基板区域102a的栅极堆叠104具有高度H1,H1小于在基板区域102b的栅极堆叠104的高度H2,H2小于在基板区域102c的栅极堆叠104的高度H3。再一次而言,在附图图4的高度H1、H2、H3,是为了说明的目的。在栅极高度的差异可能肇因于不同的因素。例如,对于蚀刻电极层106,当利用HM层110和108作为遮罩元件,蚀刻剂在装置100的表面上不平均地分布,原因在于图案化的密度、图案化的宽度、和/或图案化的间距之间的变异。因此,HM层110可能在某些区域耗蚀地较多(如,区域102a),在某些区域耗蚀地较少(如,区域102d)。其他的示例,一些基板区域,相较于其他基板区域,在形成栅极堆叠104后可能进行较多的制造过程。例如,一些基板区域,可能在其中的源极/漏极区域进行磊晶成长制程,且此磊晶成长制程可能是n-型磊晶或p-型磊晶。在这些额外的制造过程中,HM层110可能不平均地耗蚀。
在栅极置换制程,HM层110和108须要被移除,以暴露要置换的电极层106。然而,对于典型的栅极置换制程,不同的栅极高度带来了挑战。例如,在典型的栅极置换制程中,栅极层106可能在基板区域102a过度地蚀刻,和/或HM层108在基板区域102d不完全地蚀刻,留下介电质残留物在电极层106的上部。对于后续的置换制程,电极层106的过度蚀刻,和HM层108未足的蚀刻,二者皆会造成问题。本揭露内容的一个目标是完全地移除HM层110和108,和提供具有一致高度的电极层106,以让后续置换制程容易进行。
参看附图图1,在操作14,方法10形成蚀刻停止层(ESL)112在基板102和栅极堆叠104上。参看附图图5,形成ESL 112在栅极堆叠104的上部和侧壁表面,以及基板102的上表面。在一实施例中,形成ESL 112至具有保形的横截面剖面(在“x-z”平面)。在一替换性的实施例中,ESL 112不具有保形的横截面剖面。在一实施例中,ESL 112包含一氮化物,其可能相同或不同于第一HM层108的氮化物。形成ESL可能经由CVD、PECVD、ALD,或其他合适的沉积技术。在一些实施例中,ESL 112是选择性的,如:方法10,可能略过操作14,而从操作12进行至操作16。
在操作16,方法10(图1)沉积一层间介电(ILD)层在基板102、栅极堆叠104、ESL112之上。参看附图图6,ILD层114覆盖各个结构,包含栅极堆叠104和ESL 112,且填充基板102上的各结构之间的空间。在一实施例中,ILD层114包含氧化物,例如四乙基正硅酸盐氧化物,未掺杂硅酸盐玻璃、掺杂硅氧化物,诸如硼磷硅玻璃、融合硅玻璃、磷硅玻璃、硼掺杂硅玻璃,或其他合适的氧化物材料。沉积ILD层114可能经由PECVD制程,可流式CVD(FCVD)制程,或其他合适的沉积技术。例如,FCVD制程可能包含沉积一可流动的材料(例如液态化合物)在基板102上,以填充各结构之间的空间,且经由合适的技术,例如退火,将可流动的材料转变成固态的材料。ILD层114可能具有或不具有如沉积般的平坦上表面。
在操作18,方法10(图1)执行第一化学机械平坦化(CMP)制程116,以部分地移除ILD层114。参看附图图7,在此实施例中,CMP制程116部分地移除ILD层114直到暴露ESL 112的上表面,借以将装置100的上表面平坦化。在一实施例中,利用ESL 112作为CMP制程116的终止点。对于没有ESL 112包含在装置100中的实施例,可利用第二HM层110作为CMP制程116的终止点。例如,CMP制程116可能运用CMP研磨液在ILD层114上,之后研磨抛光装置100,直至原位探测到终止点(此ESL 112)。在一些实施例中,CMP研磨液可悬浮在温和的蚀刻剂中,例如氢氧化钾或氢氧化铵。CMP研磨液可能包含硝酸铁、过氧化物、碘酸钾、氨、氧化硅、氧化铝,和/或其他可用的研磨液材料。在一些实施例中,CMP研磨液可能包含有机添加剂以在CMP制程116之后,提供较好的构形。
在操作20,方法10(图1)蚀刻ILD层114,ESL 112,和第二HM层110以暴露第一HM层108。在一实施例中,操作20包含第一蚀刻118(操作26),后随第二蚀刻(操作28),如在附图图2、图8、图9所绘示。
同时参看附图图2和图8,对于ILD层114、ESL 112、第二HM层110的材料,第一蚀刻118(操作26)没有蚀刻选择性,或是低选择性。换言之,第一蚀刻118以同样的速度蚀刻(或移除)ILD层114、ESL 112、第二HM层110。因此,装置100的上表面,在第一蚀刻118过程中,仍然大约是平坦的。在此实施例中,由计时器控制第一蚀刻制程118的持续,计时器的设定是根据第二HM层110和ESL 112的厚度,且是同样的蚀刻速率,因而第一蚀刻118刚好停止在第一HM层108暴露前。如附图图8所绘示,在一实施例中,第二HM层110的薄层仍然位于第一HM层108上。在另一实施例中,第一蚀刻118完全地移除第二HM层110,且也轻微地蚀刻第一HM层108。比较在附图图7和图8中的装置100,在执行第一蚀刻118之前,即使栅极堆叠104在不同的区域a至d具有不同的高度(图7),在完成第一蚀刻118之后,现在它们具有几乎一致的高度(图8)。
同时参看附图图2和图9,完成第一蚀刻118之后,装置100进行第二蚀刻120(操作28)。第二蚀刻120使用不同于第一蚀刻118的蚀刻剂。第二蚀刻,对于ILD层114和第二HM层110,是高度选择性的。换言之,第二蚀刻120移除ILD层114和第二HM层110,以较高的速率,相较于移除ESL 112和第一HM层108。因此,第二HM层110完全地移除,ILD层114部分地移除,ESL 112和第一HM层108保持基本上不变的(虽然也可能移除一些少量的ESL 112和第一HM层108)。在一实施例中,由终止点探测控制第二蚀刻制程118的持续。“终止点探测”探测一元件,例如氮化物,其被包含入第一HM层108,但不在第二HM层110和ILD层114。当完成第二蚀刻120,暴露第一HM层108和部分的ESL 112,如附图图9所示。图9显示装置100的上表面是不平均的,ESL112和第一HM层108高于ILD 114。附图图9更进一步地显示,在此实施例中,ESL 112高于第一HM层108。在各实施例中,根据在第二蚀刻120中,蚀刻此二层面的选择性,第一HM层108可能高于或低于ESL 112,或是它们可能位于大约相同的水平面。
在一实施例中,第一蚀刻118和第二蚀刻120二者皆是干蚀刻制程。干蚀刻制程可能使用含氧气体,含氟气体(如,CF4、SF6、CH2F2、CHF3,和/或C2F6),含氯气体(如,Cl2、CHCl3、CCl4,和/或BCl3),含溴气体(如,HBr和/或CHBr3),含碘气体,其他合适的气体和/或等离子,和/或其组合。在更进一步的实施例中,执行第一蚀刻118和第二蚀刻120二者皆在同样的干蚀刻制程处理室。例如,供应制程处理室第一蚀刻气体(或气体混合物),其对于ILD层114、ESL 112、第二HM层108的材料,不具蚀刻选择性,或是具有低的蚀刻选择性。以第一蚀刻气体执行第一蚀刻118,持续时间如上述讨论。之后,第一蚀刻气体转换成第二蚀刻气体(或气体混合物),其对于ILD层114、ESL 112、第二HM层108的材料,具有高度选择性。以第二蚀刻气体执行第二蚀刻120,持续时间如上述讨论。
在一实施例中,方法10(图1)可能执行一退火制程以促进操作20后续的ILD层114的品质。
在操作22,方法10(图1)执行第二CMP制程122直到至少部分地移除第一HM层108。参看图10,在此揭露内容,CMP制程122完全地移除第一HM层108,借以暴露电极层106。CMP制程122亦部分地移除ESL 112,借以平坦化装置100的上表面。在一实施例中,CMP制程122运用CMP研磨液,其对于ESL 112和第一HM层108具有选择性。换言之,在CMP制程122的抛光或研磨期间,移除ESL 112和第一HM层108以相较于移除ILD层114高的速率。在一实施例中,后续可能执行一清洁制程,以移除任何CMV残留物。例如,清洁制程可能使用去离子水(DIW)。
参看图10,在操作18、20、22之后,所提供的装置100具有一平坦的上表面,且电极层106具有一致的高度,没有过蚀刻,且没有来自HM层108/110的残留物。这对于后续的栅极置换制程是好的基础。
在操作24,方法10(图1)执行更进一步的制程,以制造最终的IC装置。在此实施例中,操作24包含一个或多个步骤,其以最终栅极堆叠置换电极层106。操作24的一实施例显示于图3,其包含操作30,后随操作32。在操作30,方法10切割电极层106的至少一些部分,成为多个电极片段。这称为“切多”步骤,在操作32,方法10以最终栅极堆叠置换电极和电极片段。操作30和32结合附图图11至图14,简短地讨论如下。
附图图11显示操作22之后,装置100的俯视图(在“x-y”平面)。参看图11,电极层106包含多个长条型(电极106),其方向宽度在“x”方向,长度在“y”方向。电极106的各者由ESL 112围绕在它的侧壁表面上。操作30的“切多”步骤可能包含光刻和蚀刻制程。例如,光刻制程形成一遮罩元件(如:一图案化的光阻)其覆盖电极106的部分且暴露电极106的其余部分。蚀刻制程经由遮罩元件,蚀刻电极106的暴露部分,因此把电极切成片段。附图图12绘示“切多”步骤的结果。参看附图图12,在区域102a和102b内的电极106的各者,被切成由空隙124所分隔的二片段106’。在一实施例中,空隙124后续以隔离材料填充,以电性隔离这些片段。在实施例中,在任何区域102a至d的电极106可能被切成两个或多个片段。在更先进的技术节点,例如16nm或更小的节点,经由使用一个光罩形成规律的图案,并且利用另一光罩切割此规律的图案,此“切多”步骤有助于达成较高的装置密度。根据本揭露内容的实施例制备的电极106,特别适合“切多”步骤,因为它们具有一致的高度,并且不含氧化物和氮化物的残留物于它们的上表面(图10)。根据传统方法所制备的电极可能具有氧化物和氮化物的残留物在它们的上表面。结果为电极在“切多”步骤可能无法完全切割和分离。
在操作32,以最终栅极堆叠置换电极106和电极片段106’(一起称为106”)。这可能涉及一个或多个蚀刻和沉积制程。例如,一个或多个蚀刻制程移除电极106,以形成开口126(图13),并且一个或多个沉积制程,形成最终栅极堆叠128于开口126内(图14)。在一示例中,最终栅极堆叠128包含一介面层,一栅极介电层,一功函数金属层,和一金属填充层。介面层可能包含介电材料,例如氧化硅或氮氧化硅,形成可能经由化学氧化、热氧化、ALD、CVD,和/或其他合适的介电质。栅极介电层可能包含高-k介电材料,例如氧化铪、氧化锆、氧化镧、氧化钛、氧化钇、氧化锶,其他合适的金属-氧化物,或其组合。形成栅极介电层可能经由ALD和/或其他合适的方法。功函数金属层可能为p-型或n-型功函数层。P-型功函数层包含具有足够大的有效功函数的金属,例如氮化钛、氮化钽、钌、钼、钨,或其组合。n-型功函数层包含具有足够低的有效功函数的金属,例如钛、铝、碳化钽、氮碳化钽、氮硅化钽,或其组合。功函数层可能包含多个层面,且沉积可通过CVD、PVD,和/或其他合适的制程。金属填充层可能包含铝、钨、钴、铜,和/或其他合适的材料。形成金属填充层可能经由CVD、PVD、电镀,和/或其他合适的制程。
操作24可能包含更进一步的步骤,例如形成源极/漏极/栅极接触点和形成金属互连,以完成装置100的制造。
在一些实施例中,形成半导体装置的方法包含提供一前驱物,其具有基板和位于基板上的栅极堆叠。栅极堆叠的各者包含一电极层、一硬罩层(HM)层在电极层上,和一第二HM层在第一HM层上。此方法更进一步地包含沉积一介电层在基板和栅极堆叠上,且填充介于栅极堆叠之间的空间。此方法更进一步地包含执行一第一化学机械平坦化(CMP)制程,以部分地移除介电层;并且执行一蚀刻制程,以移除第二HM层,和部分地移除介电层,借以暴露第一HM层。此方法更进一步地包含执行一第二CMP制程直到至少部分地移除第一HM层。
在一些实施例中,形成半导体装置的方法还包含其中的电极层包含晶硅,第一HM层包含一氮化物,第二HM层包含一氧化物,以及第一介电层包含另一氧化物。
在一些实施例中,形成半导体装置的方法更进一步包含在沉积该第一介电层前,形成一蚀刻停止层(ESL)在该栅极堆叠的上部和侧壁,其中利用该ESL作为该第一CMP制程的终止点。
在一些实施例中,形成半导体装置的蚀刻制程包含第一蚀刻,后随第二蚀刻。对于介电层、第二HM层、ESL层的材料,第一蚀刻具有一低的蚀刻选择性。第二蚀刻选择性地移除介电层和第二HM层,而在第二蚀刻中,第一HM层维持基本上不变。
在一些实施例中,形成半导体装置的方法中的第一蚀刻和第二蚀刻二者皆是干蚀刻。
在一些实施例中,形成半导体装置的方法还包含,执行第一蚀刻和第二蚀刻于同样的制程处理室。
在一些实施例中,形成半导体装置的方法还包含,藉一计时器控制该第一蚀刻,通过探测一元件其被包在在第一HM层但不在第二HM层和介电层,以控制第二蚀刻。
在一些实施例中,形成本导体装置的方法还包含其中第二CMP制程运用研磨液其选择性地调谐,以移除第一HM层,而介电层维持基本上不变的。
在一些实施例中,形成半导体装置的方法还包含提供一前驱物,其具有基板和位于基板上的栅极堆叠,其中栅极堆叠的各者包含一电极层、一硬罩层(HM)层在电极层上,和一第二HM层在第一HM层上。此方法更进一步地包含沉积一蚀刻停止层(ESL)在基板上并且覆盖栅极堆叠的上部和侧壁,且沉积一层间介电层(ILD)在ESL上,并且填充介于栅极堆叠之间的空间。此方法更进一步地包含执行一第一化学机械平坦化(CMP)制程,以部分地移除ILD层;执行干蚀刻制程以部分地移除ESL、ILD层,和第二HM层,借以暴露第一HM层。此方法更进一步地包含执行一第二CMP制程直到至少部分地移除第一HM层。
在一些实施例中,形成半导体装置的方法更进一步包含,其中干蚀刻制程包含第一蚀刻,后随第二蚀刻。第一蚀刻以大约同样的速率,移除ILD层和第二HM层。第二蚀刻以一相较于移除第一HM层为高的速率移除ILD层和第二HM层。
在一些实施例中,形成半导体装置的方法更进一步包含,其中在第一HM层暴露之前,第一蚀刻转换至第二蚀刻。
在一些实施例中,形成半导体装置的方法,更进一步包含,其中第二CMP制程运用研磨液,其移除第一HM层以高于移除ILD层的速率。
在一些实施例中,形成本导体装置的方法更进一步地包含,在栅极堆叠的一者内,切割一电极层至多个片段。
在一些实施例中,形成半导体装置方法,包含提供一前驱物,其具有基板和位于基板上的栅极堆叠。栅极堆叠的各者包含一复合多层、一氮化物硬罩层(HM)层在此复合多层上,和一氧化物HM层在氮化物HM层上。此方法更进一步地包含形成一蚀刻停止层(ESL)在栅极堆叠的上部和侧壁。此ESL包含氮化物。此方法更进一步地包含沉积一层间介电层(ILD),其覆盖ESL和栅极堆叠,并且填充介于栅极堆叠之间的空间。此ILD层包含氧化物。此方法更进一步地包含执行一第一化学机械平坦化(CMP)制程,以部分地移除至少此ESL,此ILD层,和此氧化物HM层;在执行第一蚀刻制程之后,此方法更进一步地包含执行一第二蚀刻制程,以选择性调适来蚀刻此ILD层和此氧化物HM层,而此氮化物HM层维持基本上不变的,借以暴露此氮化物HM层。此方法更进一步地包含执行一第二CMP制程,以选择性地移除此氮化物HM层,而此ILD层维持基本上不变的。
在一些实施例中,形成半导体装置方法更进一步包含,在栅极堆叠的一者切割一合多层成为多重的复合多片段。
虽然目的不在于限制,本揭露内容的一个或多个实施例提供许多对于半导体装置和其形成的益处。本揭露内容的一实施例使用一制造流程,其包含一CMP制程、一干蚀刻制程、和另一个CMP制程,以在栅极置换前,完全地移除复合多层上的硬罩层。该等制程产生此复合多层的近乎一致的高度。这提供了对于后续栅极置换一个良好的基础。在更先进的技术节点中,本揭露内容可以容易地与现有的制造过程整合。
上述内容列出数个实施例的特征,所以本领域具通常知识者可更能理解本揭露内容的观点。本领域具通常知识者应体会他们可快速地利用本揭露内容作为设计和修改其他制程的基础,以实现与在此介绍的实施例中的相同目的,或是获得同样的优点。本领域具通常知识者亦应理解该等相应的建构并不背离本揭露内容的精神和范围,并且他们可做各式变化、取代、改造而不背离本揭露内容的精神和范围。
Claims (19)
1.一种形成半导体装置的方法,其特征在于,包含:
提供一前驱物,其具有一基板和多个栅极堆叠于该基板上,其中所述多个栅极堆叠具有不同的高度,所述多个栅极堆叠的各者包含一电极层,一第一硬罩层在该电极层上,和一第二硬罩层在该第一硬罩层上;
沉积一介电层在该基板和该栅极堆叠上,且填充所述多个栅极堆叠之间的空间;
执行一第一化学机械平坦化制程以部分地移除该介电层;
执行一蚀刻制程,其中所述蚀刻制程包含一第一蚀刻,后随一第二蚀刻,其中在所述第一蚀刻中,所述半导体装置的上表面是平坦的,在所述第一蚀刻后,所述多个栅极堆叠具有一致的高度,并且在所述第二蚀刻移除该第二硬罩层,且部分地移除所述介电层,借以暴露所述第一硬罩层;以及
执行一第二化学机械平坦化制程以至少部分地移除该第一硬罩层。
2.根据权利要求1所述的形成半导体装置的方法,其特征在于:
该电极层包含多晶硅;
该第一硬罩层包含一氮化物;
该第二硬罩层包含一氧化物;以及
该介电层包含另一氧化物。
3.根据权利要求1所述的形成半导体装置的方法,其特征在于,更进一步地包含:
在沉积该介电层前,形成一蚀刻停止层在该栅极堆叠的上部和侧壁,其中利用该蚀刻停止层作为该第一化学机械平坦化制程的终止点。
4.根据权利要求3所述的形成半导体装置的方法,其特征在于,其中:
对于该介电层、该第二硬罩层、该蚀刻停止层的材料,该第一蚀刻具有一低的蚀刻选择性;以及
该第二蚀刻选择性地移除该介电层和该第二硬罩层,而在该第二蚀刻中,该第一硬罩层维持不变。
5.根据权利要求4所述的形成半导体装置的方法,其特征在于,其中该第一蚀刻和该第二蚀刻二者皆是干蚀刻。
6.根据权利要求4所述的形成半导体装置的方法,其特征在于,执行该第一蚀刻和该第二蚀刻于同样的制程处理室。
7.根据权利要求4所述的形成半导体装置的方法,其特征在于,其中藉一计时器控制该第一蚀刻,通过探测一元件其被包含在该第一硬罩层但不在该第二硬罩层和该介电层,来控制该第二蚀刻。
8.根据权利要求1所述的形成半导体装置的方法,其特征在于,该第二化学机械平坦化制程运用研磨液其选择性地调谐,以移除该第一硬罩层,而该介电层维持不变的。
9.一种形成半导体装置的方法,其特征在于,包含:
提供一前驱物,其具有一基板和多个栅极堆叠于该基板上,其中所述多个栅极堆叠的各者包含一电极层,一第一硬罩层在该电极层上,和一第二硬罩层在该第一硬罩层上;
沉积一层间介电层在该栅极堆叠上,且填充所述多个栅极堆叠之间的空间;
执行一第一化学机械平坦化制程以部分地移除该层间介电层;
执行一干蚀刻制程,其中所述干蚀刻制程包含一第一蚀刻,后随一第二蚀刻,其中在所述第一蚀刻中,所述半导体装置的上表面是平坦的,在所述第一蚀刻后,所述多个栅极堆叠具有一致的高度,并且在所述第二蚀刻移除所述第二硬罩层,且部分地移除所述层间介电层,借以暴露所述第一硬罩层;以及
执行一第二化学机械平坦化制程以至少部分地移除该第一硬罩层。
10.根据权利要求9所述的形成半导体装置的方法,其特征在于,其中:
该第一硬罩层包含一氮化物;
该第二硬罩层包含一氧化物;以及
该层间介电层包含另一氧化物。
11.根据权利要求9所述的形成半导体装置的方法,其特征在于,其中:
该第一蚀刻以同样的速率,移除该层间介电层和该第二硬罩层;以及
该第二蚀刻以一相较于移除该第一硬罩层为高的速率移除该层间介电层和该第二硬罩层。
12.根据权利要求11所述的形成半导体装置的方法,其特征在于,在该第一硬罩层暴露之前,该第一蚀刻转换至该第二蚀刻。
13.根据权利要求11所述的形成半导体装置的方法,其特征在于,执行该第一蚀刻和该第二蚀刻于相同的制程处理室。
14.根据权利要求9所述的形成半导体装置的方法,其特征在于,该第二化学机械平坦化制程运用研磨液,其移除该第一硬罩层以高于移除该层间介电层的速率。
15.根据权利要求9所述的形成半导体装置的方法,其特征在于,更进一步包含:
在所述多个栅极堆叠的一者内,切割一电极层至多个片段。
16.一种形成半导体装置的方法,其特征在于,包含:
提供一前驱物,其具有一基板和多个栅极堆叠于该基板上,其中所述多个栅极堆叠的各者包含一复合多层,一氮化物硬罩层在该复合多层上,和一氧化物硬罩层在该氮化物硬罩层上;
形成一蚀刻停止层在栅极堆叠的顶部和侧壁,该蚀刻停止层包含一氮化物;
沉积一层间介电层覆盖该蚀刻停止层和所述多个栅极堆叠,且填充介于所述多个栅极堆叠之间的空间,该层间介电层包含一氧化物;
执行一第一化学机械平坦化制程以部分地移除该层间介电层直到暴露该蚀刻停止层;
执行一第一蚀刻制程以部分地移除至少该蚀刻停止层、该层间介电层,和该氧化物硬罩层,其中在所述第一蚀刻制程中,所述半导体装置的上表面是平坦的,在所述第一蚀刻制程后,所述多个栅极堆叠具有一致的高度;
执行完该第一蚀刻制程后,执行一第二蚀刻制程以选择性调适来蚀刻该层间介电层和该氧化物硬罩层,而该氮化物硬罩层维持不变的,借以暴露该氮化物硬罩层;以及
执行一第二化学机械平坦化制程以选择性地移除该氮化物硬罩层,而该层间介电层维持不变。
17.根据权利要求16所述的形成半导体装置的方法,其特征在于,该第一蚀刻制程和该第二蚀刻制程是干蚀刻制程,且执行于相同的制程处理室。
18.根据权利要求16所述的形成半导体装置的方法,其特征在于,对于该蚀刻停止层、该层间介电层、和该氧化物硬罩层,该第一蚀刻制程具有低的蚀刻选择性。
19.根据权利要求16所述的形成半导体装置的方法,其特征在于,更进一步包含:
在该栅极堆叠的一者切割一复合多层成为多重的复合多片段。
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US10636673B2 (en) | 2017-09-28 | 2020-04-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming semiconductor device structure |
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US10777420B1 (en) * | 2019-02-26 | 2020-09-15 | United Microelectronics Corp. | Etching back method |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200531159A (en) * | 2003-12-29 | 2005-09-16 | Intel Corp | A method for making a semiconductor device that includes a metal gate electrode |
CN103247602A (zh) * | 2012-02-08 | 2013-08-14 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
US8551843B1 (en) * | 2012-05-07 | 2013-10-08 | Globalfoundries Inc. | Methods of forming CMOS semiconductor devices |
Family Cites Families (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5505816A (en) | 1993-12-16 | 1996-04-09 | International Business Machines Corporation | Etching of silicon dioxide selectively to silicon nitride and polysilicon |
US6692903B2 (en) | 2000-12-13 | 2004-02-17 | Applied Materials, Inc | Substrate cleaning apparatus and method |
US6864164B1 (en) | 2002-12-17 | 2005-03-08 | Advanced Micro Devices, Inc. | Finfet gate formation using reverse trim of dummy gate |
US20060183055A1 (en) | 2005-02-15 | 2006-08-17 | O'neill Mark L | Method for defining a feature on a substrate |
US20060196527A1 (en) | 2005-02-23 | 2006-09-07 | Tokyo Electron Limited | Method of surface processing substrate, method of cleaning substrate, and programs for implementing the methods |
KR100801744B1 (ko) | 2006-12-28 | 2008-02-11 | 주식회사 하이닉스반도체 | 반도체소자의 금속게이트 형성방법 |
US7732346B2 (en) | 2007-02-27 | 2010-06-08 | United Mircoelectronics Corp. | Wet cleaning process and method for fabricating semiconductor device using the same |
US8350335B2 (en) | 2007-04-18 | 2013-01-08 | Sony Corporation | Semiconductor device including off-set spacers formed as a portion of the sidewall |
US8252194B2 (en) | 2008-05-02 | 2012-08-28 | Micron Technology, Inc. | Methods of removing silicon oxide |
US8153526B2 (en) * | 2008-08-20 | 2012-04-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | High planarizing method for use in a gate last process |
US8415254B2 (en) | 2008-11-20 | 2013-04-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for removing dummy poly in a gate last process |
US7871882B2 (en) | 2008-12-20 | 2011-01-18 | Power Integrations, Inc. | Method of fabricating a deep trench insulated gate bipolar transistor |
US7985690B2 (en) * | 2009-06-04 | 2011-07-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for a gate last process |
US8048733B2 (en) | 2009-10-09 | 2011-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a gate structure |
US8318568B2 (en) | 2010-04-14 | 2012-11-27 | International Business Machines Corporation | Tunnel field effect transistor |
US8404533B2 (en) * | 2010-08-23 | 2013-03-26 | United Microelectronics Corp. | Metal gate transistor and method for fabricating the same |
US8487378B2 (en) | 2011-01-21 | 2013-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Non-uniform channel junction-less transistor |
US8466502B2 (en) | 2011-03-24 | 2013-06-18 | United Microelectronics Corp. | Metal-gate CMOS device |
US9111795B2 (en) | 2011-04-29 | 2015-08-18 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with capacitor connected to memory element through oxide semiconductor film |
US9608059B2 (en) | 2011-12-20 | 2017-03-28 | Intel Corporation | Semiconductor device with isolated body portion |
US8887106B2 (en) | 2011-12-28 | 2014-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process |
US8586436B2 (en) | 2012-03-20 | 2013-11-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a variety of replacement gate types including replacement gate types on a hybrid semiconductor device |
US8729634B2 (en) | 2012-06-15 | 2014-05-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with high mobility and strain channel |
US8889022B2 (en) | 2013-03-01 | 2014-11-18 | Globalfoundries Inc. | Methods of forming asymmetric spacers on various structures on integrated circuit products |
US8815741B1 (en) | 2013-03-11 | 2014-08-26 | Globalfoundries Inc. | Method of forming a semiconductor structure including an implantation of ions into a layer of spacer material |
US8826213B1 (en) | 2013-03-11 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Parasitic capacitance extraction for FinFETs |
US8943455B2 (en) | 2013-03-12 | 2015-01-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for layout verification for polysilicon cell edge structures in FinFET standard cells |
US9401416B2 (en) * | 2014-12-04 | 2016-07-26 | Globalfoundries Inc. | Method for reducing gate height variation due to overlapping masks |
US9917017B2 (en) * | 2015-12-29 | 2018-03-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Replacement gate process for semiconductor devices |
-
2016
- 2016-08-12 US US15/236,210 patent/US9917017B2/en active Active
- 2016-12-28 TW TW105143685A patent/TWI601207B/zh active
- 2016-12-29 CN CN201611246910.3A patent/CN106935493B/zh active Active
-
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- 2018-03-08 US US15/915,272 patent/US10515860B2/en active Active
-
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- 2019-12-17 US US16/717,542 patent/US11081402B2/en active Active
-
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- 2021-07-30 US US17/390,124 patent/US11756838B2/en active Active
-
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- 2023-07-26 US US18/359,747 patent/US20230386937A1/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200531159A (en) * | 2003-12-29 | 2005-09-16 | Intel Corp | A method for making a semiconductor device that includes a metal gate electrode |
CN103247602A (zh) * | 2012-02-08 | 2013-08-14 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
US8551843B1 (en) * | 2012-05-07 | 2013-10-08 | Globalfoundries Inc. | Methods of forming CMOS semiconductor devices |
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US11081402B2 (en) | 2021-08-03 |
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US10515860B2 (en) | 2019-12-24 |
US11756838B2 (en) | 2023-09-12 |
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US9917017B2 (en) | 2018-03-13 |
US20210358816A1 (en) | 2021-11-18 |
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US20230386937A1 (en) | 2023-11-30 |
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