WO2024066247A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
WO2024066247A1
WO2024066247A1 PCT/CN2023/083452 CN2023083452W WO2024066247A1 WO 2024066247 A1 WO2024066247 A1 WO 2024066247A1 CN 2023083452 W CN2023083452 W CN 2023083452W WO 2024066247 A1 WO2024066247 A1 WO 2024066247A1
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WIPO (PCT)
Prior art keywords
steps
layer
top surface
along
initial
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PCT/CN2023/083452
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English (en)
French (fr)
Inventor
黄猛
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长鑫存储技术有限公司
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Publication of WO2024066247A1 publication Critical patent/WO2024066247A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same.
  • the memory cells are arranged in the horizontal direction. Therefore, the integration density of two-dimensional or planar semiconductor devices can be determined by the area occupied by the unit memory cell.
  • the integration density of two-dimensional or planar semiconductor devices is greatly affected by the technology of forming fine patterns, so that there is a limit to the continuous increase of the integration density of two-dimensional or planar semiconductor devices. Therefore, the development of semiconductor devices is moving towards three-dimensional semiconductor devices.
  • the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial to improving the stability of the step structure and reducing the electrical interference between adjacent steps and the electrical interference between adjacent conductive pillars.
  • an embodiment of the present disclosure provides a semiconductor structure, comprising: a substrate, the substrate having an adjacent array region and a peripheral region; a bit line extending along a first direction, a semiconductor channel extending along a second direction, and a word line extending along a third direction located on the array region, the first direction, the second direction, and the third direction intersecting each other; a stepped structure located on the peripheral region, the stepped structure comprising a plurality of steps, the steps being in one-to-one contact and connection with one of the bit line and the word line; a plurality of conductive pillars being in one-to-one contact and connection with top surfaces of the steps, the extension direction of the conductive pillars being the same as the extension direction of the other of the bit line and the word line; a supporting skeleton, located between any two adjacent conductive pillars, and being in contact and connection with each of the steps; wherein, along the extension direction of the conductive pillars, the top
  • the top surface of the support skeleton away from the base is a first top surface
  • the step farthest from the base in the stepped structure is a second top surface away from the top surface of the base, and the first top surface is not lower than the second top surface
  • the bottom surface of the support skeleton close to the base is a first bottom surface
  • the step closest to the base in the stepped structure is a second bottom surface close to the bottom surface of the base
  • the first bottom surface is not higher than the second bottom surface.
  • the steps are arranged in an array along the first direction and the second direction.
  • the top surface heights of the plurality of steps arranged at intervals along the first direction gradually decrease, and the top surface heights of the plurality of steps arranged at intervals along the second direction also gradually decrease.
  • the supporting skeleton includes multiple supporting layers, any of the supporting layers is in contact with and connected to at least two of the steps, and the multiple steps are respectively located on opposite sides of the supporting layer along the first direction and/or on opposite sides of the supporting layer along the second direction.
  • the steps are connected to the bit lines in one-to-one contact;
  • the support skeleton comprises: A first supporting layer extending in one of the first direction and the second direction, and a second supporting layer arranged at intervals along the other of the first direction and the second direction; wherein the second supporting layer is located in the interval between adjacent first supporting layers.
  • the extending direction of the first supporting layer is a reference direction, and the plurality of steps arranged at intervals along the reference direction are all in contact with and connected to the first supporting layer.
  • the extension direction of the first supporting layer is a reference direction
  • a plurality of the first supporting layers are arranged at intervals along the reference direction
  • a plurality of the steps arranged at intervals along the reference direction are respectively in contact with and connected to a plurality of the first supporting layers.
  • the steps are contacted and connected with the bit lines one by one;
  • the supporting skeleton includes: a first supporting layer extending along the first direction and the second direction, and a second supporting layer located in the interval between adjacent first supporting layers; wherein, the first supporting layer is contacted and connected with the four steps arranged in an array, the first supporting layer is arranged at intervals along the first direction and/or the second direction, and the second supporting layer is contacted and connected with the four steps arranged in an array.
  • the support frame is a grid-like structure having a plurality of spaces, and the steps are located in the spaces and correspond one-to-one with the spaces.
  • the material of the support skeleton includes at least one of silicon nitride or silicon oxynitride.
  • the peripheral region includes a spacer region between the stepped structure and the array region, the bit line or the word line is also located in the spacer region, and the semiconductor structure further includes: a peripheral protective layer, the peripheral protective layer is located on the spacer region, and surrounds the side walls of the bit line or the word line in the spacer region extending along the first direction.
  • the peripheral protection layer surrounds the sidewall of the step structure extending along the extension direction of the conductive pillar, and a portion of the peripheral protection layer is spaced from the step structure.
  • the material of the peripheral protective layer is the same as the material of the supporting skeleton.
  • an embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate having adjacent array areas and peripheral areas; forming bit lines extending along a first direction, semiconductor channels extending along a second direction, and word lines extending along a third direction on the array area, the first direction, the second direction, and the third direction intersecting each other; forming a step structure, a conductive column, and a supporting skeleton on the peripheral area, wherein the step structure comprises a plurality of steps, the steps being in one-to-one contact and connection with one of the bit lines and the word lines; the conductive columns being in one-to-one contact and connection with the steps, the extension direction of the conductive columns being the same as the extension direction of the other of the bit lines and the word lines; the supporting skeleton being located between any two adjacent conductive columns, and being in contact and connection with each of the steps; along the extension direction of the conductive columns, the top surface height of any step
  • the step of forming the stepped structure includes: forming a multilayer initial stacking structure stacked along the extension direction of the conductive pillar on the peripheral area, along the extension direction of the conductive pillar, the initial stacking structure includes a stacked first semiconductor layer and a second semiconductor layer, the initial stacking structure has a spacing area close to the array area and a step area located on the side of the spacing area away from the array area; performing a first graphical treatment on the initial stacking structure in the step area to form an initial stepped structure, the initial step structure includes a plurality of initial step structures, along the extension direction of the conductive pillar, the top surface height of any initial step structure is different from the top surface height of another initial step structure; etching the initial step structure to form a gap, and forming the step in the gap.
  • the step of forming the support skeleton includes: forming a first dielectric layer, the first dielectric layer is located on the top surface of each of the initial step structures, the top surface of the initial step structure farthest from the substrate is a reference top surface, and the top surface of the first dielectric layer farthest from the substrate is flush with the reference top surface; performing a second graphic processing on the initial step structure and the first dielectric layer to form a first groove; and forming the support skeleton that fills the first groove.
  • the first dielectric layer is also located on two opposite sides of the initial stepped structure along the second direction; after forming the initial stepped structure and before etching the initial stepped structure to form the step, it also includes: performing a third graphical treatment on the initial stacking structure and the first dielectric layer in the spacing area to form a second groove; and forming a peripheral protective layer that fills the second groove.
  • etching the initial stepped structure to form a gap includes: removing the first dielectric layer between the initial stepped structure and the peripheral protective layer to expose two opposite sides of the initial stepped structure along the second direction; etching the second semiconductor layer in the initial stepped structure along the second direction to form the gap; and forming the step that fills the gap.
  • the step after forming the step, it also includes: etching the first semiconductor layer in the initial stepped structure along the second direction to form a gap; forming a second dielectric layer, the second dielectric layer fills the gap and fills the space between the peripheral protective layer and the stepped structure.
  • 1 and 2 are two schematic diagrams of top views of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG3 is a schematic diagram of a partial three-dimensional structure of a semiconductor structure provided by an embodiment of the present disclosure.
  • FIG4 is a schematic diagram of a three-dimensional structure of a step structure in a semiconductor structure provided by an embodiment of the present disclosure
  • FIG5 is a schematic diagram of a partial cross-sectional structure of a step structure and a support skeleton in a semiconductor structure provided by an embodiment of the present disclosure
  • 6 to 10 are schematic diagrams of five partial top views of a semiconductor structure provided by an embodiment of the present disclosure.
  • 11 to 20 are schematic structural diagrams corresponding to the steps of a method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure.
  • the present disclosure provides a semiconductor structure and a manufacturing method thereof, in which a step structure is used to lead the word line or bit line of the array area to the peripheral area to connect the peripheral control circuit.
  • the steps in the step structure correspond to the word line one by one, or the steps in the step structure are connected to the bit line one by one, so as to lead the word line or bit line through the steps; further, the conductive pillars are connected to the steps one by one, so as to further lead the word line or bit line; and the support skeleton is located between any two adjacent conductive pillars and is connected to each step, so as to reduce the electrical interference between adjacent conductive pillars and the electrical interference between adjacent steps by using the support skeleton, so as to realize the independent control of each word line or bit line.
  • the support skeleton is conducive to improving the stability of the step structure, thereby improving the stability of the semiconductor structure.
  • FIGS. 1 and 2 are two schematic diagrams of top view structures of a semiconductor structure provided in an embodiment of the present disclosure
  • Figure 3 is a schematic diagram of a partial three-dimensional structure of a semiconductor structure provided in an embodiment of the present disclosure
  • Figure 4 is a schematic diagram of a three-dimensional structure of a step structure in a semiconductor structure provided in an embodiment of the present disclosure
  • Figure 5 is a schematic diagram of a partial cross-sectional structure of a step structure and a supporting skeleton in a semiconductor structure provided in an embodiment of the present disclosure
  • Figures 6 to 10 are five schematic diagrams of partial top view structures of a semiconductor structure provided in an embodiment of the present disclosure.
  • FIGS. 1 to 10 in an embodiment of the present disclosure are schematic diagrams of partial structures of the semiconductor structure.
  • the semiconductor structure includes: a substrate 100, the substrate 100 having an array region 110 and a peripheral region 120 adjacent to each other; a bit line 101 extending along a first direction X, a semiconductor channel 102 extending along a second direction Y, and a word line 103 extending along a third direction on the array region 110, wherein the first direction X, the second direction Y, and the third direction Z intersect each other; a step structure 104 located on the peripheral region 120, the step structure 104 including a plurality of steps 114, the steps 114 being connected to the bit line 101 and the word line 103;
  • the conductive pillars 105 are connected to the top surfaces of the steps 114 one by one, and the extension direction of the conductive pillars 105 is the same as the extension direction of the other one of the bit lines 101 and the word lines 103; the support frame 106 is located between any two adjacent conductive pillars 105 and is connected to each step 114; wherein, along the extension direction of the conductive pillars 105,
  • the first direction X, the second direction Y, and the third direction Z may be perpendicular to each other.
  • the angle between any two of the first direction X, the second direction Y, and the third direction Z is not 0° or 180°.
  • the first direction X, the second direction Y, and the third direction Z are perpendicular to each other as an example for detailed description.
  • a plurality of bit lines 101 may be arranged at intervals along the third direction Z, and the steps 114 are in one-to-one contact with the bit lines 101 , that is, the step structure 104 is used to lead the bit lines 101 from the array region 110 to the peripheral region 120 .
  • the semiconductor structure may further include: a capacitor structure 112 , wherein one end of the two opposite ends of the semiconductor channel 102 along the second direction Y is in contact with the bit line 101 , and the other end is in contact with the capacitor structure 112 .
  • one bit line 101 is used as an example to be in contact with four semiconductor channels 102 .
  • there is no limit on the number of semiconductor channels 102 that are in contact with the same bit line 101 there is no limit on the number of semiconductor channels 102 that are in contact with the same word line 103 .
  • the cross-sectional shape of the conductive pillar 105 in a direction perpendicular to the third direction Z may be a square, that is, the conductive pillar 105 is a square pillar.
  • the cross-sectional shape of the conductive pillar 105 in the direction perpendicular to the third direction Z may be circular, that is, the conductive pillar 105 is a cylinder.
  • a plurality of word lines 103 may be arranged at intervals along the first direction X, and the steps 114 are in contact with the word lines 103 one by one. That is, the step structure 104 is used to lead the word lines 103 from the array region 110 to the peripheral region 120 .
  • FIG. 3 eight word lines 103 are arranged at intervals along the first direction X, and four bit lines 101 are arranged at intervals along the third direction Z.
  • the support skeleton is not drawn in FIG. 3 and FIG. 4 .
  • the step structure 104 further includes: a plurality of insulating layers 144, and an insulating layer 144 at least fills a first interval.
  • the insulating layer 144 is also located between the step 114 and the base. 100 to achieve electrical insulation between the step 114 and the substrate 100.
  • the semiconductor channels 102 can be arranged at intervals along the first direction X and the third direction Z, the number of semiconductor channels 102 arranged at intervals along the first direction X is consistent with the number of word lines 103 arranged at intervals along the first direction X, and the number of semiconductor channels 102 arranged at intervals along the third direction Z is consistent with the number of bit lines 101 arranged at intervals along the third direction Z.
  • the word line 103 may include a gate dielectric layer (not shown in the figure) and a gate (not shown in the figure), the gate dielectric layer surrounds a portion of the sidewall of the semiconductor channel 102, and the gate dielectric layer corresponds to the semiconductor channel 102 one by one, and the gate extends along the third direction Z and surrounds the sidewall of the gate dielectric layer.
  • the gate dielectric layer is made of an insulating material, and the gate is made of a conductive material.
  • the step structure 104 is used to lead the bit line 101 to the peripheral area 120 as an example for detailed description.
  • the top surface of the support frame 106 away from the substrate 100 is the first top surface a
  • the top surface of the step 114 farthest from the substrate 100 in the stepped structure 104 away from the substrate 100 is the second top surface b
  • the first top surface a is not lower than the second top surface b
  • the bottom surface of the support frame 106 close to the substrate 100 is the first bottom surface c
  • the bottom surface of the step 114 closest to the substrate 100 in the stepped structure 104 close to the substrate 100 is the second bottom surface d
  • the first bottom surface c is not higher than the second bottom surface d.
  • Figure 5 may be a schematic diagram of a partial cross-sectional structure of the stepped structure 104 in Figure 1 or Figure 2, and Figure 5 is an example in which the first top surface a is flush with the second top surface b, and the first bottom surface c is flush with the second bottom surface d.
  • the support skeleton 106 is in contact and connected with the top surface of the insulating layer 144 in the stepped structure 104 that is closest to the substrate 100.
  • the support skeleton 106 may pass through the entire stepped structure 104 along the third direction Z, that is, the support skeleton 106 may be embedded in the insulating layer 144 that is closest to the substrate 100, or the first top surface a of the support skeleton 106 may be higher than the second top surface b to reduce the electrical interference between the conductive column 105 (refer to Figure 1) located on the second top surface b and other conductive columns 105.
  • the steps 114 may be arranged in an array along a first direction X and a second direction Y. As shown in FIG. 4
  • the semiconductor structure may sequentially include a first bit line, a second bit line, a third bit line, a fourth bit line, a fifth bit line, a sixth bit line, a seventh bit line, and an eighth bit line.
  • the step 114 set at the same layer as the first bit line includes 1 sub-step 154; the step 114 set at the same layer as the second bit line includes 2 sub-steps 154, and compared with the 1 sub-step 154 corresponding to the first bit line, there is one more sub-step 154 along the second direction Y, and the conductive column 105 corresponding to the second bit line is in contact with and connected to the extra sub-step 154; and so on, the step 114 set at the same layer as the fourth bit line includes 4 sub-steps 154, and compared with the 3 sub-steps 154 corresponding to the third bit line, there is one more sub-step 154 along the second direction Y, and the conductive column 105 corresponding to the fourth bit line is in contact with and connected to the extra sub-step 154.
  • the step 114 disposed on the same layer as the fifth bit line includes 5 sub-steps 154, which has one more sub-step 154 along the first direction X than the 4 sub-steps 154 corresponding to the fourth bit line, and the conductive pillar 105 corresponding to the fifth bit line is in contact with and connected to the extra sub-step 154; by analogy, the step 114 disposed on the same layer as the eighth word line includes 8 sub-steps 154, which has one more sub-step 154 along the first direction X than the 7 sub-steps 154 corresponding to the seventh bit line, and the conductive pillar 105 corresponding to the eighth bit line is in contact with and connected to the extra sub-step 154.
  • the steps 114 are arranged in an array along the first direction X and the second direction Y, and the top surface height of any step 114 is different from the top surface height of another step 114 along the extension direction of the conductive pillar 105, and adjacent steps 114 are electrically insulated.
  • FIG. 4 shows the difference in the number and arrangement of sub-steps 154 included in the steps 114 at different layers.
  • a single step 114 is The step 114 can be composed of multiple independent sub-steps 154, that is, the multiple sub-steps 154 are prepared separately, or the single step 114 itself is an integral structure, and the sub-step 154 is just a feature defined to show the difference between different steps 114, that is, the multiple sub-steps 154 that constitute the single step 114 are an integral structure.
  • the top surface heights of the plurality of steps 114 arranged at intervals along the first direction X gradually decrease, and the top surface heights of the plurality of steps 114 arranged at intervals along the second direction Y also gradually decrease.
  • the step structure 104 shown in FIG. 4 is only a specific example. In practical applications, there is no restriction on the variation trend of the top surface heights of different steps 114 in the step structure 104 along the first direction X and the second direction Y, and it is only necessary to satisfy that the top surface height of any step 114 is different from the top surface height of another step 114.
  • the top surface of a step 114 is flush with the top surface of a bit line 101, and the bottom surface of the step 114 is flush with the bottom surface of the bit line 101.
  • the top surface height of the step 114 refers to the surface of the step 114 away from the substrate 100
  • the top surface height of the bit line 101 refers to the surface of the bit line 101 away from the substrate 100
  • the bottom surface height of the step 114 refers to the surface of the step 114 close to the substrate 100
  • the bottom surface height of the bit line 101 refers to the surface of the bit line 101 close to the substrate 100.
  • the support frame 106 includes at least the following five embodiments:
  • the support skeleton 106 includes multiple support layers 116, any support layer 116 is in contact with and connected to at least two steps 114, and the multiple steps 114 are respectively located on opposite sides of the support layer 116 along the first direction X and/or on opposite sides of the support layer 116 along the second direction Y.
  • step 114 when the step 114 is located on one of two opposite sides of a support layer 116 along the first direction X, the step 114 may also be located on one of two opposite sides of another support layer 116 along the second direction Y. In this way, for any two adjacent steps 114, there is a support layer 116 between the two steps 114 to achieve electrical insulation between any two adjacent steps 114.
  • the steps 114 are in one-to-one contact with the bit lines 101 (refer to FIG. 2 );
  • the support skeleton 106 may include: a first support layer 126 extending along one of the first direction X and the second direction Y, and second support layers 136 arranged at intervals along the other of the first direction X and the second direction Y; wherein the second support layer 136 is located in the interval between adjacent first support layers 126.
  • the first supporting layer 126 extends along the first direction X and the second supporting layer 136 extends along the second direction Y as an example. In actual applications, the first supporting layer 126 may extend along the second direction Y and the second supporting layer 136 may extend along the first direction X.
  • first supporting layer 126 and the second supporting layer 136 The positional relationship between the first supporting layer 126 and the second supporting layer 136 is described in detail below through two embodiments.
  • the extension direction of the first support layer 126 is a reference direction, i.e., the first direction X, and the plurality of steps 114 arranged at intervals along the reference direction are all in contact with and connected to the first support layer 126. It is understandable that the plurality of first support layers 126 are only arranged at intervals along the second direction Y, and the second support layer 136 is in contact with and connected to two adjacent steps 114 along the first direction X.
  • the extension direction of the first support layer 126 is a reference direction, that is, a first direction X, and a plurality of first support layers 126 are arranged at intervals along the reference direction.
  • the second support layer 136 is respectively in contact with and connected to the plurality of first support layers 126. It is understood that the plurality of first support layers 126 may be arranged in intervals along the first direction X and the second direction Y, and the second support layer 136 is in contact with and connected to two adjacent steps 114 along the first direction X.
  • the step structure 104 includes 12 steps 114, and is arranged in an array in a 3*4 arrangement manner as an example.
  • there is no limit on the number of steps 114 included in the step structure 104 and there is no limit on the number of steps 114 arranged along the first direction X and the number of steps 114 arranged along the second direction Y.
  • there are two first support layers 126 along the first direction X and each first support layer 126 is in contact with and connected to four steps 114, and the four steps 114 are arranged in an array in a 2*2 arrangement manner as an example.
  • there is no limit on the number of first support layers 126 arranged along the first direction X and there is no limit on the number of steps 114 that each first support layer 126 is in contact with and connected to.
  • the steps 114 are in contact and connected one by one with the bit lines 101 (refer to FIG. 2 );
  • the supporting skeleton 106 includes: a first supporting layer 126 extending along a first direction X and a second direction Y, and a second supporting layer 136 located in the interval between adjacent first supporting layers 126 ; wherein the first supporting layer 126 is in contact and connected with four steps 114 arranged in an array, the first supporting layer 126 is arranged at intervals along the first direction X and/or the second direction Y, and the second supporting layer 136 is in contact and connected with four steps 114 arranged in an array.
  • the cross-sectional shape of the first supporting layer 126 in a plane perpendicular to the third direction Z is a cross
  • the second supporting layer 136 extends along the second direction Y
  • the adjacent first supporting layers 126 and second supporting layers 136 are in contact and connected with the same two steps 114.
  • two adjacent steps 114 along the second direction Y have relative first and second sides in the first direction X
  • the first supporting layer 126 is located on the first side
  • the second supporting layer 136 is located on the second side.
  • the steps 114 can be connected to the word lines 103 one by one.
  • the support frame 106 is suitable for the situation where the steps 114 are connected to the word lines 103 one by one.
  • the support frame 106 is a grid-like structure having a plurality of spaces, and the steps 114 are located in the spaces and correspond one to one with the spaces.
  • the specific structure of the support skeleton 106 includes but is not limited to the five examples shown in Figures 6 to 10. Any support structure located between any two adjacent conductive pillars 105 and in contact with each step 114 can serve as the support skeleton 106.
  • the material of the support frame 106 includes at least one of silicon nitride or silicon oxynitride.
  • the peripheral region 120 includes a spacer region 130 between the step structure 104 and the array region 110, the bit line 101 or the word line 103 is also located in the spacer region 130, and the semiconductor structure further includes: a peripheral protection layer 107, the peripheral protection layer 107 is located on the spacer region 130, and surrounds the sidewalls of the bit line 101 or the word line 103 of the spacer region 130 extending along the first direction X.
  • the peripheral protection layer 107 can be used to achieve electrical insulation between the step structure 104 and the storage cells in the array region 110, reduce electrical interference between the step structure 104 and the storage cells in the array region 110, and when preparing the step structure 104, it is helpful to avoid the influence of the preparation process on the array region 110.
  • bit line 101 is also located in the spacer area 130, and the peripheral protection layer 107 surrounds the side wall of the bit line 101 in the spacer area 130 extending along the first direction X.
  • word line 103 can be located in the spacer area 130, and the peripheral protection layer 107 surrounds the side wall of the word line 103 in the spacer area 130 extending along the first direction X.
  • the peripheral protection layer 107 surrounds the sidewalls of the step structure 104 extending along the extension direction of the conductive pillar 105, and a portion of the peripheral protection layer 107 is spaced apart from the step structure 104. In this way, the step structure 104 can be positioned by the peripheral protection layer 107, and the overall protection effect of the step structure 104 can be improved. In addition, when the step structure 104 is prepared, it is helpful to avoid the preparation process from affecting other areas of the array region 110 and the peripheral region 120.
  • a dielectric layer may be disposed in the space between the peripheral protection layer 107 and the stepped structure 104 .
  • an isolation layer 117 is provided between the peripheral protection layer 107 and the stepped structure 104, which is beneficial to improving the stability of the semiconductor structure as a whole.
  • the isolation layer 117 can be made of silicon oxide.
  • the staircase structure 104 is used to lead the word lines 103 or the bit lines 101 of the array area 110 to the peripheral area 120 to connect to the peripheral control circuit.
  • the steps 114 in the step structure 104 correspond to the word lines 103 one by one, or the steps 114 in the step structure 104 are in contact with and connected to the bit lines 101 one by one, so as to lead out the word lines 103 or the bit lines 101 through the steps 114; further, the conductive pillars 105 are in contact with and connected to the steps 114 one by one, so as to further lead out the word lines 103 or the bit lines 101; and the support skeleton 106 is located between any two adjacent conductive pillars 105 and is in contact with and connected to each step 114, so as to facilitate using the support skeleton 106 to reduce the electrical interference between adjacent conductive pillars 105 and the electrical interference between adjacent steps 114, so as to achieve independent control of each word line 103 or the bit line 101.
  • the support skeleton 106 is conducive to improving the stability of the step structure 104, thereby facilitating improving the stability of the semiconductor structure.
  • Another embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, which is used to prepare the semiconductor structure provided by an embodiment of the present disclosure.
  • the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure will be described in detail below in conjunction with Figures 1 to 20.
  • Figures 11 to 20 are schematic diagrams of structures corresponding to each step of the method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.
  • Figures 11 to 20 in another embodiment of the present disclosure are all schematic diagrams of partial structures of the semiconductor structure.
  • a method for manufacturing a semiconductor structure includes: providing a substrate 100, wherein the substrate 100 has an array region 110 and a peripheral region 120 adjacent to each other; forming a bit line 101 extending along a first direction X, a semiconductor channel 102 extending along a second direction Y, and a word line 103 extending along a third direction Z on the array region 110, wherein the first direction X, the second direction Y, and the third direction Z intersect each other; forming a step structure 104, a conductive column 105, and a support frame 106 on the peripheral region 120, wherein the step structure 104 includes a plurality of steps.
  • the steps 114 are in one-to-one contact with one of the bit lines 101 and the word lines 103; the conductive pillars 105 are in one-to-one contact with the steps 114, and the extension direction of the conductive pillars 105 is the same as the extension direction of the other of the bit lines 101 and the word lines 103; the support frame 106 is located between any two adjacent conductive pillars 105 and is in contact with each step 114; along the extension direction of the conductive pillars 105, the top surface height of any step 114 is different from the top surface height of another step 114, and adjacent steps 114 are electrically insulated.
  • the following detailed description will be given by taking the stepped structure 104 for leading the bit line 101 to the peripheral area 120, the steps 114 are in one-to-one contact with the bit line 101, and the extension direction of the conductive column 105 is the same as the extension direction of the word line 103 as an example.
  • forming the stepped structure 104 includes the following steps:
  • a multilayer initial stacking structure 108 stacked along the extension direction of the conductive pillar 105 is formed on the peripheral area 120.
  • the initial stacking structure 108 includes a stacked first semiconductor layer 118 and a second semiconductor layer 128.
  • the initial stacking structure 108 has a spacing area 138 close to the array area 110 (refer to Figure 1) and a step area 148 located on the side of the spacing area 138 away from the array area 110.
  • the initial stacking structure 108 of the step region 148 is subjected to a first patterning process to form an initial step structure 124, the initial step structure 124 including a plurality of initial step structures 134 extending along the conductive pillar 105. In the direction, the top surface height of any initial step structure 134 is different from the top surface height of another initial step structure 134 .
  • the remaining first semiconductor layer 118 and the remaining second semiconductor layer 128 whose orthographic projections overlap on the substrate 100 form an initial step structure 134. It is understood that the space where the first semiconductor layer 118 in the initial step structure 134 is located will be used to form the insulating layer 144 (refer to FIG. 1) later, and the space where the second semiconductor layer 128 in the initial step structure 134 is located will be used to form the step 114 (refer to FIG. 1) later, so as to form the stepped structure 104 (refer to FIG. 1).
  • the initial stepped structure 124 is etched to form a space, and the step 114 is formed in the space.
  • step 114 The steps of forming the step 114 are described in detail below.
  • forming the support skeleton 106 may include the following steps:
  • a first dielectric layer 109 is formed, and the first dielectric layer 109 is located on the top surface of each initial step structure 134, the top surface of the initial step structure 134 farthest from the substrate 100 is a reference top surface, and the top surface of the first dielectric layer 109 farthest from the substrate 100 is flush with the reference top surface.
  • the initial step structure 134 and the first dielectric layer 109 as a whole form a rectangular parallelepiped, which is conducive to the subsequent formation of a stepped structure based on a regular rectangular parallelepiped.
  • the initial stepped structure 124 and the first dielectric layer 109 are subjected to a second patterning process to form a first groove (not shown in the figure); and a support skeleton 106 that fills the first groove is formed.
  • the bottom surface of the first groove close to the substrate 100 is the third bottom surface
  • the bottom surface of the second semiconductor layer 128 in the initial step structure 124 closest to the substrate 100 close to the substrate 100 is the fourth bottom surface
  • the third bottom surface is not higher than the fourth bottom surface.
  • FIG. 14 only illustrates a method for preparing a first groove of the support skeleton 106. It is understandable that, based on the different masks used in the second patterning process, first grooves of different shapes can be prepared to form the support skeleton 106 as shown in any one of FIGS. 7 to 10.
  • the first dielectric layer 109 is also located on two opposite sides of the initial step structure 124 along the second direction Y. It is to be understood that FIG. 14 takes the example that the first dielectric layer 109 is also located on the side of the initial step structure 124 away from the spacing area 138, and FIG. 14 is located in the spacing area 138.
  • the first dielectric layer 109 includes a third dielectric layer 119 and a fourth dielectric layer 129, and the orthographic projection of the third dielectric layer 119 on the substrate 100 (refer to FIG.
  • the fourth dielectric layer 129 is located on two opposite sides of the initial step structure 124 along the second direction Y and on the side of the initial step structure 124 away from the spacing area 138.
  • the third dielectric layer 119 and the fourth dielectric layer 129 can be formed in steps, that is, the first dielectric layer 109 is a multi-layer structure; in other embodiments, the third dielectric layer 119 and the fourth dielectric layer 129 can also be integrally formed, that is, the first dielectric layer 109 is a single-layer structure.
  • the manufacturing method provided in another embodiment of the present disclosure does not limit how to form the first dielectric layer 109.
  • the manufacturing method may further include: performing a third patterning process on the initial stacked structure 108 (refer to FIG. 11 ) and the first dielectric layer 109 of the spacing region 138 (refer to FIG. 13 ) to form a second groove; and forming a peripheral protective layer 107 that fills the second groove.
  • FIG. 16 is a schematic diagram of a partial cross-sectional structure of the structure shown in FIG. 15 along the cross-sectional direction AA1.
  • the initial stacking structure 108 in contact with the step region 148 will not be removed, so that the initial stacking structure 108 formed
  • the peripheral protection layer 107 surrounds the sidewalls of the initial stepped structure 124 (refer to FIG. 12 ) extending along the first direction X.
  • only the first dielectric layer 109 may be subjected to the third patterning process to form the second groove.
  • the step of forming the second groove may further include: performing a third patterning process on the first dielectric layer 109 of the step area 148 (refer to Figure 13) to form a second groove similar to a square ring as shown in Figure 15, thereby forming a peripheral protective layer 107 similar to a square ring.
  • the second groove is a square ring as an example.
  • the second groove may be located only between the initial stacking structure 108 and the initial stepped structure 124 in the spacing region 138 (refer to FIG13). It is understandable that when the stepped structure is subsequently formed, only the initial stepped structure 124 encircled by the peripheral protection layer 107 may be etched and deposited to avoid affecting the semiconductor structure in other regions.
  • the first groove and the second groove can be formed by the same step, and the support skeleton 106 and the peripheral protective layer 107 can be formed by the same step, which is helpful to simplify the process steps of preparing the support skeleton 106 and the peripheral protective layer 107, and reduce the cost of preparing the support skeleton 106 and the peripheral protective layer 107.
  • etching the initial stepped structure 124 to form the spacer 139 includes the following steps:
  • the first dielectric layer 109 between the initial stepped structure 124 and the peripheral protection layer 107 is removed to expose two opposite sides of the initial stepped structure 124 along the second direction Y.
  • the first dielectric layer 109 is also located on a side of the initial stepped structure 124 away from the spacing region 138 (refer to FIG. 13 ). When the first dielectric layer 109 located between the initial stepped structure 124 and the peripheral protective layer 107 is removed, the side of the initial stepped structure 124 away from the spacing region 138 is also exposed.
  • the second semiconductor layer 128 in the initial stepped structure 124 is etched along the second direction Y to form a spacer 139. Since the support skeleton 106 is in contact with each of the first semiconductor layers 118, in the step of etching the second semiconductor layer 128, the support skeleton 106 is advantageously used to support the remaining first semiconductor layer 118, thereby preventing the remaining first semiconductor layer 118 from collapsing due to the etching process, thereby facilitating improving the dimensional accuracy of the formed stepped structure.
  • the manufacturing method further includes the following steps:
  • the first semiconductor layer 118 in the initial stepped structure 124 (see FIG. 14 ) is etched along the second direction Y to form a gap 149. Since the support skeleton 106 is in contact with each step 114, in the step of etching the first semiconductor layer 118, the step 114 is supported by the support skeleton 106 to prevent the step 114 from collapsing due to the etching process, thereby facilitating improving the dimensional accuracy of the formed stepped structure.
  • a second dielectric layer 159 is formed to fill the gap 149 and the space between the peripheral protection layer 107 and the stepped structure 104 .
  • the second dielectric layer 159 filling the gap 149 is the insulating layer 144 (see FIG. 5 ), and the remaining second dielectric layer 159 is located between the peripheral protection layer 107 and the stepped structure 104 , and the remaining second dielectric layer 159 is the isolation layer 117 .
  • the third dielectric layer 119 is subjected to a fourth patterning process to form a fourth groove, wherein a step 114 is exposed in the fourth groove, and a conductive pillar 105 is formed to fill the fourth groove.
  • the top surface of the conductive pillar 105 away from the substrate 100 may be higher than the highest top surface of the step structure 104 away from the substrate 100.
  • the top surface of the third dielectric layer 119 away from the substrate 100 may be higher than the highest top surface of the stepped structure 104 away from the substrate 100, that is, the third dielectric layer 119 covers the top surface of each step 114 away from the substrate 100, and each step 114 is subsequently exposed by forming a fourth groove.
  • the fourth dielectric layer 129 is drawn in a perspective manner in FIGS. 14 to 19 .
  • the support skeleton 106 in the step of forming the stepped structure 104, is conducive to avoiding the etching process from affecting the structure that does not need to be etched, and avoiding the collapse of the structure that does not need to be etched, thereby improving the dimensional accuracy of the formed stepped structure 104.
  • the peripheral protective layer 107 is conducive to avoiding the process of forming the stepped structure 104 from causing damage to other areas of the semiconductor structure. In addition.
  • the support skeleton 106 is located between any two adjacent conductive pillars 105, and is in contact with each step 114, so that it is conducive to using the support skeleton 106 to reduce the electrical interference between adjacent conductive pillars 105, and reduce the electrical interference between adjacent steps 114, so as to achieve independent control of each word line 103 or bit line 101.
  • the support skeleton 106 is conducive to improving the stability of the stepped structure 104, thereby improving the stability of the semiconductor structure.

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Abstract

公开了一种半导体结构及其制造方法。半导体结构包括：具有相邻阵列区(110)和外围区(120)的基底(100)；位于阵列区(110)上的沿第一方向(X)延伸的位线(101)、沿第二方向(Y)延伸的半导体通道(102)和沿第三方向(Z)延伸的字线(103)；位于外围区(120)上的阶梯结构(104)包括多个与位线(101和字线(103)中的一者一一接触连接的台阶(114)；与台阶(114)顶面一一接触连接的多个延伸方向与位线(101)和字线(103)中的另一者的延伸方向相同的导电柱(105)；位于任意相邻的两个导电柱(105)之间且与每一台阶(114)接触连接的支撑骨架(106)。

Description

半导体结构及其制造方法
交叉引用
本申请要求于2022年09月28日递交的名称为“半导体结构及其制造方法”、申请
号为202211193866.X的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本公开实施例涉及半导体技术领域，特别涉及一种半导体结构及其制造方法。
背景技术
二维或平面半导体器件中，存储单元均是水平方向上排列，因此，二维或平面半导体器件的集成密度可以由单位存储单元所占据的面积决定，则二维或平面半导体器件的集成密度极大地受到形成精细图案的技术影响，使得二维或平面半导体器件的集成密度的持续增大存在极限。因而，半导体器件的发展走向三维半导体器件。
然而，目前三维半导体器件中存储单元的布局，各功能器件的连线方式均需要全新的设计，例如在节省半导体器件布局面积的同时，半导体器件中的字线或位线如何引出与外围逻辑电路实现电连接是急需考虑的问题，而且，利用电连接结构将字线或位线引出的过程中，电连接结构的稳定性问题以及相邻电连接结构之间的电干扰问题均需考虑。
发明内容
本公开实施例提供一种半导体结构及其制造方法，至少有利于提高阶梯结构的稳定性，以及降低相邻台阶之间的电干扰和相邻导电柱之间的电干扰。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，包括：基底，所述基底具有相邻的阵列区和外围区；位于所述阵列区上的沿第一方向延伸的位线、沿第二方向延伸的半导体通道和沿第三方向延伸的字线，所述第一方向、所述第二方向和所述第三方向两两相交；位于所述外围区上的阶梯结构，所述阶梯结构包括多个台阶，所述台阶与所述位线和所述字线中的一者一一接触连接；与所述台阶的顶面一一接触连接的多个导电柱，所述导电柱的延伸方向与所述位线和所述字线中的另一者的延伸方向相同；支撑骨架，位于任意相邻的两个所述导电柱之间，且与每一所述台阶接触连接；其中，沿所述导电柱的延伸方向上，任一所述台阶的顶面高度与另一所述台阶的顶面高度不同，且相邻所述台阶之间电绝缘。
在一些实施例中，沿所述导电柱的延伸方向上，所述支撑骨架远离所述基底的顶面为第一顶面，所述阶梯结构中距离所述基底最远的所述台阶远离所述基底的顶面为第二顶面，所述第一顶面不低于所述第二顶面，且，所述支撑骨架靠近所述基底的底面为第一底面，所述阶梯结构中距离所述基底最近的所述台阶靠近所述基底的底面为第二底面，所述第一底面不高于所述第二底面。
在一些实施例中，所述台阶沿所述第一方向和所述第二方向阵列排布。
在一些实施例中，沿所述阵列区指向所述外围区的方向上，沿所述第一方向上间隔排布的若干所述台阶的顶面高度逐渐降低，且沿所述第二方向上间隔排布的若干所述台阶的顶面高度也逐渐降低。
在一些实施例中，所述支撑骨架包括多个支撑层，任一所述支撑层与至少两个所述台阶接触连接，且多个所述台阶分别位于所述支撑层沿所述第一方向上相对的两侧和/或所述支撑层沿所述第二方向上相对的两侧。
在一些实施例中，所述台阶与所述位线一一接触连接；所述支撑骨架包括：沿所述第 一方向和所述第二方向中的一个方向延伸的第一支撑层，沿所述第一方向和所述第二方向中的另一个方向间隔排布的第二支撑层；其中，所述第二支撑层位于相邻所述第一支撑层间的间隔中。
在一些实施例中，所述第一支撑层的延伸方向为参考方向，沿所述参考方向上间隔排布的多个所述台阶均与所述第一支撑层接触连接。
在一些实施例中，所述第一支撑层的延伸方向为参考方向，沿所述参考方向上间隔排布有多个所述第一支撑层，沿所述参考方向上间隔排布的多个所述台阶分别与多个所述第一支撑层接触连接。
在一些实施例中，所述台阶与所述位线一一接触连接；所述支撑骨架包括：沿所述第一方向和所述第二方向延伸的第一支撑层，位于相邻所述第一支撑层间的间隔中的第二支撑层；其中，所述第一支撑层与4个呈阵列排布的所述台阶接触连接，所述第一支撑层沿所述第一方向和/或所述第二方向间隔排布，所述第二支撑层与4个呈阵列排布的所述台阶接触连接。
在一些实施例中，所述支撑骨架为网格状结构，所述网格状结构具有多个空格，所述台阶位于所述空格中且与所述空格一一对应。
在一些实施例中，所述支撑骨架的材料包括氮化硅或氮氧化硅中的至少一者。
在一些实施例中，所述外围区包括位于所述阶梯结构和所述阵列区之间的间隔区，所述位线或所述字线还位于所述间隔区，所述半导体结构还包括：外围保护层，所述外围保护层位于所述间隔区上，且环绕所述间隔区的所述位线或所述字线沿所述第一方向延伸的侧壁。
在一些实施例中，所述外围保护层环绕所述阶梯结构沿所述导电柱的延伸方向延伸的侧壁，且部分所述外围保护层与所述阶梯结构之间具有间隔。
在一些实施例中，所述外围保护层的材料与所述支撑骨架的材料相同。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构的制造方法，包括：提供基底，所述基底具有相邻的阵列区和外围区；在所述阵列区上形成沿第一方向延伸的位线、沿第二方向延伸的半导体通道和沿第三方向延伸的字线，所述第一方向、所述第二方向和所述第三方向两两相交；在所述外围区上形成阶梯结构、导电柱和支撑骨架，其中，所述阶梯结构包括多个台阶，所述台阶与所述位线和所述字线中的一者一一接触连接；所述导电柱与所述台阶一一接触连接，所述导电柱的延伸方向与所述位线和所述字线中的另一者的延伸方向相同；所述支撑骨架位于任意相邻的两个所述导电柱之间，且与每一所述台阶接触连接；沿所述导电柱的延伸方向上，任一所述台阶的顶面高度与另一所述台阶的顶面高度不同，且相邻所述台阶之间电绝缘。
在一些实施例中，形成所述阶梯结构的步骤包括：在所述外围区上形成沿所述导电柱的延伸方向堆叠的多层初始堆叠结构，沿所述导电柱的延伸方向上，所述初始堆叠结构包括堆叠的第一半导体层和第二半导体层，所述初始堆叠结构具有靠近所述阵列区的间距区和位于所述间距区远离所述阵列区一侧的台阶区；对所述台阶区的所述初始堆叠结构进行第一图形化处理，以形成初始阶梯结构，所述初始阶梯结构包括多个初始台阶结构，沿所述导电柱的延伸方向上，任一所述初始台阶结构的顶面高度与另一所述初始台阶结构的顶面高度不同；对所述初始阶梯结构进行刻蚀，以形成间隔，在所述间隔中形成所述台阶。
在一些实施例中，在形成所述初始阶梯结构之后，在刻蚀所述初始阶梯结构以形成所述台阶之前，形成所述支撑骨架的步骤包括：形成第一介质层，所述第一介质层位于每一所述初始台阶结构的顶面，距离所述基底最远的所述初始台阶结构的顶面为参考顶面，所述第一介质层远离所述基底的顶面与所述参考顶面齐平；对所述初始阶梯结构和所述第一介质层进行第二图形化处理，以形成第一凹槽；形成填充满所述第一凹槽的所述支撑骨架。
在一些实施例中，所述第一介质层还位于所述初始阶梯结构沿所述第二方向上相对的两侧；在形成所述初始阶梯结构之后，在刻蚀所述初始阶梯结构以形成所述台阶之前，还包括：对所述间距区的所述初始堆叠结构和所述第一介质层进行第三图形化处理，以形成第二凹槽；形成填充满所述第二凹槽的外围保护层。
在一些实施例中，在形成所述外围保护层之后，所述对所述初始阶梯结构进行刻蚀以形成间隔，包括：去除位于所述初始阶梯结构和所述外围保护层之间的所述第一介质层，以露出所述初始阶梯结构沿所述第二方向上相对的两侧；沿所述第二方向上，刻蚀所述初始阶梯结构中的所述第二半导体层，以形成所述间隔；形成填充满所述间隔的所述台阶。
在一些实施例中，在形成所述台阶之后，还包括：沿所述第二方向上，刻蚀所述初始阶梯结构中的所述第一半导体层，以形成间隙；形成第二介质层，所述第二介质层填充满所述间隙，且填充满所述外围保护层和所述阶梯结构之间的间隔。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1和图2为本公开一实施例提供的半导体结构的两种俯视结构示意图；
图3为本公开一实施例提供的半导体结构的一种局部立体结构示意图；
图4为本公开一实施例提供的半导体结构中阶梯结构的一种立体结构示意图；
图5为本公开一实施例提供的半导体结构中阶梯结构和支撑骨架的一种局部剖视结构示意图；
图6至图10为本公开一实施例提供的半导体结构的五种局部俯视结构示意图；
图11至图20为本公开另一实施例提供的半导体结构的制造方法各步骤对应的结构示意图。
具体实施方式
由背景技术可知，利用电连接结构将字线或位线引出，以与外围逻辑电路电连接的过程中，电连接结构的稳定性有待提高，相邻电连接结构之间的电干扰有待降低。
本公开实施提供一种半导体结构及其制造方法，半导体结构中，利用阶梯结构将阵列区的字线或位线引出至外围区以连接外围控制电路。其中，阶梯结构中的台阶与字线一一对应，或者，阶梯结构中的台阶与位线一一接触连接，以通过台阶将在字线或位线引出；进一步的，导电柱与台阶一一接触连接，以进一步的将字线或位线引出；而且，支撑骨架位于任意相邻的两个导电柱之间，且与每一台阶接触连接，从而有利于利用支撑骨架降低相邻导电柱之间的电干扰，以及降低相邻台阶之间的电干扰，以实现对每一字线或位线的独立控制，此外，由于阶梯结构中各台阶之间的顶面高度均不相同，即阶梯结构自身的不规则性较高，支撑骨架有利于提高阶梯结构的稳定性，从而有利于提高半导体结构的稳定性。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
本公开一实施例提供一种半导体结构，以下将结合附图对本公开一实施例提供的半导 体结构进行详细说明。图1和图2为本公开一实施例提供的半导体结构的两种俯视结构示意图；图3为本公开一实施例提供的半导体结构的一种局部立体结构示意图；图4为本公开一实施例提供的半导体结构中阶梯结构的一种立体结构示意图；图5为本公开一实施例提供的半导体结构中阶梯结构和支撑骨架的一种局部剖视结构示意图；图6至图10为本公开一实施例提供的半导体结构的五种局部俯视结构示意图。
需要说明的是，为了便于描述以及清晰地示意出半导体结构，本公开一实施例中的图1至图10均为半导体结构的局部结构示意图。
参考图1至图10，半导体结构包括：基底100，基底100具有相邻的阵列区110和外围区120；位于阵列区110上的沿第一方向X延伸的位线101、沿第二方向Y延伸的半导体通道102和沿第三方向延伸的字线103，第一方向X、第二方向Y和第三方向Z两两相交；位于外围区120上的阶梯结构104，阶梯结构104包括多个台阶114，台阶114与位线101和字线103中的一者一一接触连接；与台阶114的顶面一一接触连接的多个导电柱105，导电柱105的延伸方向与位线101和字线103中的另一者的延伸方向相同；支撑骨架106，位于任意相邻的两个导电柱105之间，且与每一台阶114接触连接；其中，沿导电柱105的延伸方向上，任一台阶114的顶面高度与另一台阶114的顶面高度不同，且相邻台阶114之间电绝缘。
在一些实施例中，第一方向X、第二方向Y和第三方向Z可以两两垂直，实际应用中，第一方向X、第二方向Y和第三方向Z中任意两者的夹角不为0°或180°即可。便于描述，后续以第一方向X、第二方向Y和第三方向Z两两垂直为示例进行详细说明。
在一些实施例中，参考图1和图2，沿第三方向Z上可以间隔排布有多条位线101，台阶114与位线101一一接触连接，即阶梯结构104用于将位线101从阵列区110中引出至外围区120。
其中，半导体结构还可以包括：电容结构112，半导体通道102沿第二方向Y上相对的两端中的一端与位线101接触连接，另一端与电容结构112接触连接。
需要说明的是，图1和图2中以一条位线101与4个半导体通道102接触连接为示例，实际应用中，对与同一位线101接触连接的半导体通道102的数量不做限制，且对与同一字线103接触连接的半导体通道102的数量也不做限制。
导电柱的具体构造至少包括以下两种实施例：
在一些实施例中，参考图1，导电柱105在垂直于第三方向Z上的截面形状可以为方形，即导电柱105为方柱。
在另一些实施例中，参考图2，导电柱105在垂直于第三方向Z上的截面形状可以为圆形，即导电柱105为圆柱。
在另一些实施例中，参考图3和图4，沿第一方向X上可以间隔排布有多条字线103，台阶114与字线103一一接触连接。即阶梯结构104用于将字线103从阵列区110中引出至外围区120。
需要说明的是，图3中以沿第一方向X上间隔排布有8条字线103，沿第三方向Z上间隔排布有4条位线101为示例，实际应用中，对沿第一方向X上间隔排布的字线103的数量不做限制，对沿第三方向Z上间隔排布的位线101的数量也不做限制。此外，为了便于图示，充分显示出阶梯结构104中多个台阶114之间的区别，图3和图4中未绘制出支撑骨架。
在一些实施例中，参考图4和图5，沿第三方向Z上，相邻台阶114之间具有第一间隔，阶梯结构104还包括：若干绝缘层144，一绝缘层144至少填充满一第一间隔。如此，通过绝缘层144实现不同台阶114之间的电绝缘。此外，绝缘层144还位于台阶114和基底 100之间，以实现台阶114与基底100之间的电绝缘。
可以理解的是，参考图1至图3，半导体通道102可以沿第一方向X和第三方向Z间隔排布，沿第一方向X间隔排布的半导体通道102的数量与沿第一方向X间隔排布的字线103的数量一致，沿第三方向Z间隔排布的半导体通道102的数量与沿第三方向Z间隔排布的位线101的数量一致。
需要说明的是，图1至图3中，字线103可以包括栅介质层(图中未示出)和栅极(图中未示出)，栅介质层环绕部分半导体通道102的侧壁，且栅介质层与半导体通道102一一对应，栅极沿第三方向Z延伸，且环绕栅介质层侧壁。其中，栅介质层由绝缘材料构成，栅极由导电材料构成。此外，为了便于后续的描述，后续以阶梯结构104用于将位线101引出至外围区120为示例进行详细说明。
以下将结合附图对本公开实施例进行更为详细的说明。
在一些实施例中，参考图5，沿导电柱105的延伸方向上，即第三方向Z上，支撑骨架106远离基底100的顶面为第一顶面a，阶梯结构104中距离基底100最远的台阶114远离基底100的顶面为第二顶面b，第一顶面a不低于第二顶面b，且，支撑骨架106靠近基底100的底面为第一底面c，阶梯结构104中距离基底100最近的台阶114靠近基底100的底面为第二底面d，第一底面c不高于第二底面d。如此，使得支撑骨架106可以与每一台阶114接触连接，以提高阶梯结构104的稳定性，以及降低相邻台阶114之间的电干扰。
需要说明的是，图5可以为图1或图2中阶梯结构104的部分剖面结构示意图，图5中与第一顶面a与第二顶面b齐平，第一底面c和第二底面d齐平为示例，如此，支撑骨架106与阶梯结构104中距离基底100最近的绝缘层144的顶面接触连接，实际应用中，支撑骨架106可以沿第三方向Z上贯穿整个阶梯结构104，即支撑骨架106可以嵌入距离基底100最近的绝缘层144中，或者，支撑骨架106的第一顶面a可以高于第二顶面b，以降低位于第二顶面b上的导电柱105(参考图1)与其他导电柱105之间的电干扰。
在一些实施例中，参考图4，台阶114可以沿第一方向X和第二方向Y阵列排布。
可以理解的是，为示意出阶梯结构104中不同台阶114之间的区别，将部分台阶114划分为多个子台阶154。沿基底100(参考图1)指向位线101(参考图1)的方向上，半导体结构可以依次包括第一位线、第二位线、第三位线、第四位线、第五位线、第六位线、第七位线和第八位线。其中，与第一位线同层设置的台阶114包括1个子台阶154；与第二位线同层设置的台阶114包括2个子台阶154，且相较于与第一位线对应的1个子台阶154沿第二方向Y多出一个子台阶154，与第二位线对应的导电柱105与该多出的子台阶154接触连接；以此类推，与第四位线同层设置的台阶114包括4个子台阶154，且相较于与第三位线对应的3个子台阶154沿第二方向Y多出1个子台阶154，与第四位线对应的导电柱105与该多出的1个子台阶154接触连接。
此外，与第五位线同层设置的台阶114包括5个子台阶154，相较于与第四位线对应的4个子台阶154沿第一方向X多出一个子台阶154，与第五位线对应的导电柱105与该多出的子台阶154接触连接；以此类推，与第八字线同层设置的台阶114包括8个子台阶154，且相较于与第七位线对应的7个子台阶154沿第一方向X多出1个子台阶154，与第八位线对应的导电柱105与该多出的1个子台阶154接触连接。
如此，实现台阶114整体沿第一方向X和第二方向Y阵列排布的趋势，以及实现沿导电柱105的延伸方向上，任一台阶114的顶面高度与另一台阶114的顶面高度不同，且相邻台阶114之间电绝缘。
需要说明的是，为示意出阶梯结构104中不同台阶114之间的区别，图4中以位于不同层的台阶114包含的子台阶154的数量以及排布方式的不同来呈现，在实际应用中，单一 台阶114可以由多个相互独立的子台阶154构成，即多个子台阶154分别被制备，或者单一台阶114自身为一体结构，子台阶154只是为了显示出不同台阶114之间的差异而定义的特征，即组成单一台阶114中的多个子台阶154为一体结构。
在一些实施例中，沿阵列区110指向外围区120的方向上，即第一方向X上，沿第一方向X上间隔排布的若干台阶114的顶面高度逐渐降低，且沿第二方向Y上间隔排布的若干台阶114的顶面高度也逐渐降低。
如此，一方面实现台阶114沿第一方向X和第二方向Y的阵列排布，另一方面，沿第三方向Z上，有利于实现任一台阶114的顶面高度与另一台阶114的顶面高度不同。需要说明的是，图4中显示的阶梯结构104仅是一种具体的示例，在实际应用中，对阶梯结构104中不同台阶114的顶面高度沿第一方向X和第二方向Y上的变化趋势不做限制，只需满足任一台阶114的顶面高度与另一台阶114的顶面高度不同即可。
在一些实施例中，沿第三方向Z上，一台阶114的顶面高度与一位线101的顶面高度齐平，该台阶114的底面高度与该位线101的底面高度齐平。如此，一方面，有利于使得台阶114的一个端面与位线101的一个端面完全贴合，提高台阶114与位线101之间的接触面积，以降低台阶114与位线101之间的接触电阻；另一方面，有利于提高半导体结构整体的稳定性。
需要说明的是，台阶114的顶面高度指的是台阶114远离基底100一侧的表面，位线101的顶面高度指的是位线101远离基底100一侧的表面，台阶114的底面高度指的是台阶114靠近基底100一侧的表面，位线101的底面高度指的是位线101靠近基底100一侧的表面。
支撑骨架106至少包括以下五种实施例：
在一些实施例中，参考图6，支撑骨架106包括多个支撑层116，任一支撑层116与至少两个台阶114接触连接，且多个台阶114分别位于支撑层116沿第一方向X上相对的两侧和/或支撑层116沿第二方向Y上相对的两侧。
可以理解的是，对于某一台阶114而言，该台阶114在位于一支撑层116沿第一方向X上相对的两侧中的一侧时，该台阶114还可以位于另一支撑层116沿第二方向Y上相对的两侧中的一侧。如此，使得对于任意两个相邻的台阶114而言，该两个台阶114之间均具有支撑层116，以实现任意两个相邻台阶114之间的电绝缘。
在另一些实施例中，参考图7和图8，台阶114与位线101(参考图2)一一接触连接；支撑骨架106可以包括：沿第一方向X和第二方向Y中的一个方向延伸的第一支撑层126，沿第一方向X和第二方向Y中的另一个方向间隔排布的第二支撑层136；其中，第二支撑层136位于相邻第一支撑层126间的间隔中。
需要说明的是，图7和图8中以第一支撑层126沿第一方向X延伸，第二支撑层136沿第二方向Y延伸为示例，实际应用中，也可以是第一支撑层126沿第二方向Y延伸，第二支撑层136沿第一方向X延伸。
以下通过两种实施例对第一支撑层126和第二支撑层136的位置关系进行详细说明。
在一些实施例中，参考图7，第一支撑层126的延伸方向为参考方向，即第一方向X，沿参考方向上间隔排布的多个台阶114均与第一支撑层126接触连接。可以理解的是，多个第一支撑层126仅会沿第二方向Y间隔排布，第二支撑层136与沿第一方向X上相邻的2个台阶114接触连接。
在另一些实施例中，参考图8，第一支撑层126的延伸方向为参考方向，即第一方向X，沿参考方向上间隔排布有多个第一支撑层126，沿参考方向上间隔排布的多个台阶114分 别与多个第一支撑层126接触连接。可以理解的是，多个第一支撑层126可以沿第一方向X和第二方向Y间隔排布，第二支撑层136与沿第一方向X上相邻的2个台阶114接触连接。
需要说明的是，图7和图8中以阶梯结构104包括12个台阶114，且以3*4的排布方式阵列排布为示例，实际应用中，对阶梯结构104中包含的台阶114的数量不做限制，且对多个台阶114沿第一方向X上排布的数量和沿第二方向Y上排布的数量均不做限制。此外，图8中以沿第一方向X上，第一支撑层126的数量为2个，且每一第一支撑层126分别与4个台阶114接触连接，该4个台阶114呈2*2的排布方式阵列排布为示例，实际应用中，对沿第一方向X上排布的第一支撑层126的数量不做限制，且对每一第一支撑层126接触连接的台阶114的数量不做限制。
在又一些实施例中，参考图9，台阶114与位线101(参考图2)一一接触连接；支撑骨架106包括：沿第一方向X和第二方向Y延伸的第一支撑层126，位于相邻第一支撑层126间的间隔中的第二支撑层136；其中，第一支撑层126与4个呈阵列排布的台阶114接触连接，第一支撑层126沿第一方向X和/或第二方向Y间隔排布，第二支撑层136与4个呈阵列排布的台阶114接触连接。
可以理解的是，第一支撑层126沿垂直于第三方向Z的平面中截面形状为十字形，第二支撑层136沿第二方向Y延伸，相邻的第一支撑层126和第二支撑层136共同与同样的两个台阶114接触连接，例如，沿第二方向Y上相邻的2个台阶114在第一方向X上具有相对的第一侧和第二侧，第一支撑层126位于第一侧，第二支撑层136位于第二侧。
需要说明的是，实际应用中，台阶114可以与字线103一一接触连接，图6至图9中的第一方向X和第三方向Z对调后，支撑骨架106适用于台阶114与字线103一一接触连接的情形。
在再一些实施例中，参考图10，支撑骨架106为网格状结构，网格状结构具有多个空格，台阶114位于空格中且与空格一一对应。
需要说明的是，本公开一实施例提供的支撑骨架106的具体构造包括但不限于图6至图10所示的五种示例，满足位于任意相邻的两个导电柱105之间，且与每一台阶114接触连接的支撑结构均可以作为支撑骨架106。
在上述实施例中，支撑骨架106的材料包括氮化硅或氮氧化硅中的至少一者。
在一些实施例中，参考图1和图2，外围区120包括位于阶梯结构104和阵列区110之间的间隔区130，位线101或字线103还位于间隔区130，半导体结构还包括：外围保护层107，外围保护层107位于间隔区130上，且环绕间隔区130的位线101或字线103沿第一方向X延伸的侧壁。如此，可以利用外围保护层107实现阶梯结构104与阵列区110中存储单元之间的电绝缘，降低阶梯结构104与阵列区110中存储单元之间的电干扰，而且，在制备阶梯结构104时，有利于避免制备工艺对阵列区110造成影响。
需要说明的是，图1和图2中以位线101还位于间隔区130，外围保护层107环绕间隔区130的位线101沿第一方向X延伸的侧壁为示例，实际应用中，字线103可以位于间隔区130，外围保护层107环绕间隔区130的字线103沿第一方向X延伸的侧壁。
在一些实施例中，继续参考图1和图2，外围保护层107环绕阶梯结构104沿导电柱105的延伸方向延伸的侧壁，且部分外围保护层107与阶梯结构104之间具有间隔。如此，有利于通过外围保护层107对阶梯结构104进行定位，以及提高对阶梯结构104整体的保护效果，而且，在制备阶梯结构104时，有利于避免制备工艺对阵列区110以及外围区120的其他区域造成影响。
可以理解的是，外围保护层107与阶梯结构104之间的间隔中可以具有介质层。
在一些实施例中，继续参考图1和图2，外围保护层107和阶梯结构104之间具有隔离层117，有利于提高半导体结构整体的稳定性。在一个例子中，隔离层117的材料可以为氧化硅。
在一些实施例中，外围保护层107的材料与支撑骨架106的材料相同。如此，有利于共同对半导体结构起到支撑作用，以提高半导体结构整体的稳定性。
综上所述，利用阶梯结构104将阵列区110的字线103或位线101引出至外围区120以连接外围控制电路。其中，阶梯结构104中的台阶114与字线103一一对应，或者，阶梯结构104中的台阶114与位线101一一接触连接，以通过台阶114将在字线103或位线101引出；进一步的，导电柱105与台阶114一一接触连接，以进一步的将字线103或位线101引出；而且，支撑骨架106位于任意相邻的两个导电柱105之间，且与每一台阶114接触连接，从而有利于利用支撑骨架106降低相邻导电柱105之间的电干扰，以及降低相邻台阶114之间的电干扰，以实现对每一字线103或位线101的独立控制，此外，由于阶梯结构104中各台阶114之间的顶面高度均不相同，即阶梯结构104自身的不规则性较高，支撑骨架106有利于提高阶梯结构104的稳定性，从而有利于提高半导体结构的稳定性。
本公开另一实施例还提供一种半导体结构的制造方法，用于制备本公开一实施例提供的半导体结构。以下将结合图1至图20对本公开另一实施例提供的半导体结构的制造方法进行详细说明。图11至图20为本公开另一实施例提供的半导体结构的制造方法各步骤对应的结构示意图。
需要说明的是，为了便于描述以及清晰地示意出半导体结构制作方法的步骤，本公开另一实施例中的图11至图20均为半导体结构的局部结构示意图。
，与前述实施例相同或相应的部分在此不再赘述。
参考图1至图20，半导体结构的制造方法包括：提供基底100，基底100具有相邻的阵列区110和外围区120；在阵列区110上形成沿第一方向X延伸的位线101、沿第二方向Y延伸的半导体通道102和沿第三方向Z延伸的字线103，第一方向X、第二方向Y和第三方向Z两两相交；在外围区120上形成阶梯结构104、导电柱105和支撑骨架106，其中，阶梯结构104包括多个台阶114，台阶114与位线101和字线103中的一者一一接触连接；导电柱105与台阶114一一接触连接，导电柱105的延伸方向与位线101和字线103中的另一者的延伸方向相同；支撑骨架106位于任意相邻的两个导电柱105之间，且与每一台阶114接触连接；沿导电柱105的延伸方向上，任一台阶114的顶面高度与另一台阶114的顶面高度不同，且相邻台阶114之间电绝缘。
需要说明的是，为了便于后续的描述，后续以阶梯结构104用于将位线101引出至外围区120，台阶114与位线101一一接触连接，导电柱105的延伸方向与字线103的延伸方向相同为示例进行详细说明。
在一些实施例中，形成阶梯结构104包括如下步骤：
参考图11，在外围区120上形成沿导电柱105的延伸方向堆叠的多层初始堆叠结构108，沿导电柱105的延伸方向上，即第三方向Z上，初始堆叠结构108包括堆叠的第一半导体层118和第二半导体层128，初始堆叠结构108具有靠近阵列区110(参考图1)的间距区138和位于间距区138远离阵列区110一侧的台阶区148。
需要说明的是，台阶区148中部分第一半导体层118所处的空间后续会用于形成绝缘层144(参考图1)，台阶区148中部分第二半导体层128所处的空间后续会用于形成台阶114(参考图1)，以构成阶梯结构104(参考图1)。
结合参考图11和图12，对台阶区148的初始堆叠结构108进行第一图形化处理，以形成初始阶梯结构124，初始阶梯结构124包括多个初始台阶结构134，沿导电柱105的延伸 方向上，任一初始台阶结构134的顶面高度与另一初始台阶结构134的顶面高度不同。
可以理解的是，在基底100(参考图1)上正投影重合的剩余第一半导体层118和剩余第二半导体层128构成一初始台阶结构134。可以理解的是，初始台阶结构134中的第一半导体层118所处的空间后续会用于形成绝缘层144(参考图1)，初始台阶结构134中的第二半导体层128所处的空间后续会用于形成台阶114(参考图1)，以构成阶梯结构104(参考图1)。
参考图13至图17，对初始阶梯结构124进行刻蚀，以形成间隔，在间隔中形成台阶114。
以下对形成台阶114的步骤进行详细说明。
在一些实施例中，在形成初始阶梯结构124之后，在刻蚀初始阶梯结构124以形成台阶114之前，形成支撑骨架106可以包括如下步骤：
参考图13，形成第一介质层109，第一介质层109位于每一初始台阶结构134的顶面，距离基底100最远的初始台阶结构134的顶面为参考顶面，第一介质层109远离基底100的顶面与参考顶面齐平。可以理解的是，初始台阶结构134和第一介质层109整体构成一个长方体，有利于后续基于规则的长方体形成阶梯结构。
参考图14，对初始阶梯结构124和第一介质层109进行第二图形化处理，以形成第一凹槽(图中未示出)；形成填充满第一凹槽的支撑骨架106。
需要说明的是，沿导电柱105的延伸方向上，即第三方向Z上，第一凹槽靠近基底100的底面为第三底面，初始阶梯结构124中距离基底100最近的第二半导体层128靠近基底100的底面为第四底面，第三底面不高于第四底面。如此，有利于形成至少贯穿大部分初始阶梯结构124的第一凹槽，使得支撑骨架106可以与每一台阶114接触连接，以提高阶梯结构104的稳定性，以及降低相邻台阶114之间的电干扰。
此外，图14中仅示意出一种制备支撑骨架106的第一凹槽，可以理解的是，基于第二图形化处理所采用的掩膜版的不同，可以制备不同形状的第一凹槽，以形成如图7至图10中任一项所述的支撑骨架106。
在一些实施例中，继续参考图14，第一介质层109还位于初始阶梯结构124沿第二方向Y上相对的两侧。可以理解的是，图14中以第一介质层109还位于初始阶梯结构124远离间距区138的一侧，且图14位于间距区138为示例。此外，参考图14，第一介质层109包括第三介质层119和第四介质层129，第三介质层119在基底100(参考图1)上的正投影位于初始阶梯结构124在基底100上的正投影中，第四介质层129位于初始阶梯结构124沿第二方向Y上相对的两侧以及位于初始阶梯结构124远离间距区138的一侧。
需要说明的是，在一些实施例中，第三介质层119和第四介质层129可以分步形成，即第一介质层109为多膜层结构；在另一些实施例中，第三介质层119和第四介质层129也可以一体成型，即第一介质层109为单膜层结构。本公开另一实施例提供的制造方法对如何形成第一介质层109不做限制。
参考图14至图16，在形成初始阶梯结构124之后，在刻蚀初始阶梯结构124以形成台阶114之前，制造方法还可以包括：对间距区138(参考图13)的初始堆叠结构108(参考图11)和第一介质层109进行第三图形化处理，以形成第二凹槽；形成填充满第二凹槽的外围保护层107。
其中，图16是图15所示结构沿截面方向AA1的局部剖视结构示意图。
需要说明的是，参考图16，对间距区138的初始堆叠结构108进行第三图形化处理的步骤中，与台阶区148(参考图13)接触连接的初始堆叠结构108不会被去除，使得形成 的外围保护层107环绕初始阶梯结构124(参考图12)沿第一方向X延伸的侧壁。此外，在实际应用中，可以仅对第一介质层109进行第三图形化处理，以形成第二凹槽。
在一些实施例中，形成第二凹槽的步骤还可以包括：对台阶区148(参考图13)的第一介质层109进行第三图形化处理，以形成图15所示类似于方形环状的第二凹槽，从而形成类似于方形环状的外围保护层107。
需要说明的是，图15中以第二凹槽为方形环状为示例，在实际应用中，第二凹槽可以仅位于间距区138(参考图13)的初始堆叠结构108和初始阶梯结构124之间。可以理解的是，后续形成阶梯结构时，可以仅对被外围保护层107圈住的初始阶梯结构124进行刻蚀以及沉积工艺，避免对其他区域的半导体结构造成影响。
此外，在一些实施例中，可以通过同一步骤形成第一凹槽和第二凹槽，且通过同一步骤形成支撑骨架106和外围保护层107，如此有利于简化制备支撑骨架106和外围保护层107的工艺步骤，以及降低制备支撑骨架106和外围保护层107的成本。
在一些实施例中，参考图15至图17，在形成外围保护层107之后，对初始阶梯结构124进行刻蚀以形成间隔139，包括如下步骤：
参考图15，去除位于初始阶梯结构124和外围保护层107之间的第一介质层109，以露出初始阶梯结构124沿第二方向Y上相对的两侧。
在一些实施例中，第一介质层109还位于初始阶梯结构124远离间距区138(参考图13)的一侧，去除位于初始阶梯结构124和外围保护层107之间的第一介质层109时，还露出初始阶梯结构124远离间距区138的一侧。
结合参考图15至图17，沿第二方向Y上，刻蚀初始阶梯结构124中的第二半导体层128，以形成间隔139。由于支撑骨架106与每一第一半导体层118均接触连接，因而，在刻蚀第二半导体层128的步骤中，有利于通过支撑骨架106支撑剩余的第一半导体层118，避免剩余第一半导体层118受到刻蚀工艺的影响而坍塌，从而有利于提高形成的阶梯结构的尺寸精度。
参考图18，形成填充满间隔139的台阶114。
在一些实施例中，在形成台阶114之后，制造方法还包括如下步骤：
结合参考图18和图19，沿第二方向Y上，刻蚀初始阶梯结构124(参考图14)中的第一半导体层118，以形成间隙149。由于支撑骨架106与每一台阶114均接触连接，因而，在刻蚀第一半导体层118的步骤中，有利于通过支撑骨架106支撑台阶114，避免台阶114受到刻蚀工艺的影响而坍塌，从而有利于提高形成的阶梯结构的尺寸精度。
参考图19、图20和图1，形成第二介质层159，第二介质层159填充满间隙149，且填充满外围保护层107和阶梯结构104之间的间隔。
可以理解的是，填充满间隙149的第二介质层159即为绝缘层144(参考图5)，剩余第二介质层159位于外围保护层107和阶梯结构104之间，剩余第二介质层159即为隔离层117。
继续参考图20，对第三介质层119进行第四图形化处理，以形成第四凹槽，一第四凹槽露出一台阶114；形成填充满第四凹槽的导电柱105。在一些实施例中，导电柱105远离基底100的顶面可以高于阶梯结构104远离基底100的最高顶面。
此外，在实际应用中，第三介质层119可以远离基底100的顶面可以高于阶梯结构104远离基底100的最高顶面，即第三介质层119覆盖每一台阶114远离基底100的顶面，后续通过形成第四凹槽来露出每一台阶114。
需要说明的是，为示意出半导体结构中的内部结构，图14至图19中对第四介质层129采用透视的绘制方式。
综上所述，本公开另一实施例提供的制造方法中，形成阶梯结构104的步骤中，支撑骨架106有利于避免刻蚀工艺对不需要进行刻蚀的结构造成影响，避免不需要进行刻蚀的结构坍塌，从而提高形成的阶梯结构104的尺寸精度。而且，外围保护层107有利于避免形成阶梯结构104的工艺对半导体结构的其他区域造成损伤。此外。本公开另一实施例提供的制造方法形成的半导体结构中，支撑骨架106位于任意相邻的两个导电柱105之间，且与每一台阶114接触连接，从而有利于利用支撑骨架106降低相邻导电柱105之间的电干扰，以及降低相邻台阶114之间的电干扰，以实现对每一字线103或位线101的独立控制，此外，由于阶梯结构104中各台阶114之间的顶面高度均不相同，即阶梯结构104自身的不规则性较高，支撑骨架106有利于提高阶梯结构104的稳定性，从而有利于提高半导体结构的稳定性。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作各种改动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。

Claims (20)

  1. 一种半导体结构，包括：
    基底(100)，所述基底(100)具有相邻的阵列区(110)和外围区(120)；
    位于所述阵列区(110)上的沿第一方向(X)延伸的位线(101)、沿第二方向(Y)延伸的半导体通道(102)和沿第三方向(Z)延伸的字线(103)，所述第一方向(X)、所述第二方向(Y)和所述第三方向(Z)两两相交；
    位于所述外围区(120)上的阶梯结构(104)，所述阶梯结构(104)包括多个台阶(114)，所述台阶(114)与所述位线(101)和所述字线(103)中的一者一一接触连接；
    与所述台阶(114)的顶面一一接触连接的多个导电柱(105)，所述导电柱(105)的延伸方向与所述位线(101)和所述字线(103)中的另一者的延伸方向相同；
    支撑骨架(106)，位于任意相邻的两个所述导电柱(105)之间，且与每一所述台阶(114)接触连接；
    其中，沿所述导电柱(105)的延伸方向上，任一所述台阶(114)的顶面高度与另一所述台阶(114)的顶面高度不同，且相邻所述台阶(114)之间电绝缘。
  2. 根据权利要求1所述的半导体结构，其中，沿所述导电柱(105)的延伸方向上，所述支撑骨架(106)远离所述基底(100)的顶面为第一顶面(a)，所述阶梯结构(104)中距离所述基底(100)最远的所述台阶(114)远离所述基底(100)的顶面为第二顶面(b)，所述第一顶面(a)不低于所述第二顶面(b)，且，所述支撑骨架(106)靠近所述基底(100)的底面为第一底面(c)，所述阶梯结构(104)中距离所述基底(100)最近的所述台阶(114)靠近所述基底(100)的底面为第二底面(d)，所述第一底面(c)不高于所述第二底面(d)。
  3. 根据权利要求1所述的半导体结构，其中，所述台阶(114)沿所述第一方向(X)和所述第二方向(Y)阵列排布。
  4. 根据权利要求3所述的半导体结构，其中，沿所述阵列区(110)指向所述外围区(120)的方向上，沿所述第一方向(X)上间隔排布的若干所述台阶(114)的顶面高度逐渐降低，且沿所述第二方向(Y)上间隔排布的若干所述台阶(114)的顶面高度也逐渐降低。
  5. 根据权利要求1至4任一项所述的半导体结构，其中，所述支撑骨架(106)包括多个支撑层(116)，任一所述支撑层(116)与至少两个所述台阶(114)接触连接，且多个所述台阶(114)分别位于所述支撑层(116)沿所述第一方向(X)上相对的两侧和/或所述支撑层(116)沿所述第二方向(Y)上相对的两侧。
  6. 根据权利要求5所述的半导体结构，其中，所述台阶(114)与所述位线(101)一一接触连接；所述支撑骨架(106)包括：沿所述第一方向(X)和所述第二方向(Y)中的一个方向延伸的第一支撑层(126)，沿所述第一方向(X)和所述第二方向(Y)中的另一个方向间隔排布的第二支撑层(136)；其中，所述第二支撑层(136)位于相邻所述第一支撑层(126)间的间隔中。
  7. 根据权利要求6所述的半导体结构，其中，所述第一支撑层(126)的延伸方向为参考方向，沿所述参考方向上间隔排布的多个所述台阶(114)均与所述第一支撑层(126)接触连接。
  8. 根据权利要求6所述的半导体结构，其中，所述第一支撑层(126)的延伸方向为参考方向，沿所述参考方向上间隔排布有多个所述第一支撑层(126)，沿所述参考方向上间隔排布的多个所述台阶(114)分别与多个所述第一支撑层(126)接触连接。
  9. 根据权利要求5所述的半导体结构，其中，所述台阶(114)与所述位线(101)一一接触连接；所述支撑骨架(106)包括：沿所述第一方向(X)和所述第二方向(Y)延伸的第一支撑层(126)，位于相邻所述第一支撑层(126)间的间隔中的第二支撑层(136)；
    其中，所述第一支撑层(126)与4个呈阵列排布的所述台阶(114)接触连接，所述第一支撑层(126)沿所述第一方向(X)和/或所述第二方向(Y)间隔排布，所述第二支撑层(136)与4个呈阵列排布的所述台阶(114)接触连接。
  10. 根据权利要求1或2所述的半导体结构，其中，所述支撑骨架(106)为网格状结构，所述网格状结构具有多个空格，所述台阶(114)位于所述空格中且与所述空格一一对应。
  11. 根据权利要求1所述的半导体结构，其中，所述支撑骨架(106)的材料包括氮化硅或氮氧化硅中的至少一者。
  12. 根据权利要求1所述的半导体结构，其中，所述外围区(120)包括位于所述阶梯结构(104)和所述阵列区(110)之间的间隔区(130)，所述位线(101)或所述字线(103)还位于所述间隔区(130)，所述半导体结构还包括：外围保护层(107)，所述外围保护层(107)位于所述间隔区(130)上，且环绕所述间隔区(130)的所述位线(101)或所述字线(103)沿所述第一方向(X)延伸的侧壁。
  13. 根据权利要求12所述的半导体结构，其中，所述外围保护层(107)环绕所述阶梯结构(104)沿所述导电柱(105)的延伸方向延伸的侧壁，且部分所述外围保护层(107)与所述阶梯结构(104)之间具有间隔。
  14. 根据权利要求12或13所述的半导体结构，其中，所述外围保护层(107)的材料与所述支撑骨架(106)的材料相同。
  15. 一种半导体结构的制造方法，包括：
    提供基底(100)，所述基底(100)具有相邻的阵列区(110)和外围区(120)；
    在所述阵列区(110)上形成沿第一方向(X)延伸的位线(101)、沿第二方向(Y)延伸的半导体通道(102)和沿第三方向(Z)延伸的字线(103)，所述第一方向(X)、所述第二方向(Y)和所述第三方向(Z)两两相交；
    在所述外围区(120)上形成阶梯结构(104)、导电柱(105)和支撑骨架(106)，其中，所述阶梯结构(104)包括多个台阶(114)，所述台阶(114)与所述位线(101)和所述字线(103)中的一者一一接触连接；所述导电柱(105)与所述台阶(114)一一接触连接，所述导电柱(105)的延伸方向与所述位线(101)和所述字线(103)中的另一者的延伸方向相同；所述支撑骨架(106)位于任意相邻的两个所述导电柱(105)之间，且与每一所述台阶(114)接触连接；沿所述导电柱(105)的延伸方向上，任一所述台阶(114)的顶面高度与另一所述台阶(114)的顶面高度不同，且相邻所述台阶(114)之间电绝缘。
  16. 根据权利要求15所述的制造方法，其中，形成所述阶梯结构(104)的步骤包括：
    在所述外围区(120)上形成沿所述导电柱(105)的延伸方向堆叠的多层初始堆叠结构(108)，沿所述导电柱(105)的延伸方向上，所述初始堆叠结构(108)包括堆叠的第一半导体层(118)和第二半导体层(128)，所述初始堆叠结构(104)具有靠近所述阵列区(110)的间距区(138)和位于所述间距区(138)远离所述阵列区(110)一侧的台阶区(148)；
    对所述台阶区(148)的所述初始堆叠结构(108)进行第一图形化处理，以形成初始阶梯结构(124)，所述初始阶梯结构(124)包括多个初始台阶结构(134)，沿所述导电柱(105)的延伸方向上，任一所述初始台阶结构(134)的顶面高度与另一所述初始台 阶结构(134)的顶面高度不同；
    对所述初始阶梯结构(124)进行刻蚀，以形成间隔，在所述间隔中形成所述台阶(114)。
  17. 根据权利要求16所述的制造方法，其中，在形成所述初始阶梯结构(12)之后，在刻蚀所述初始阶梯结构(124)以形成所述台阶(114)之前，形成所述支撑骨架(106)的步骤包括：
    形成第一介质层(109)，所述第一介质层(109)位于每一所述初始台阶结构(134)的顶面，距离所述基底(100)最远的所述初始台阶结构(134)的顶面为参考顶面，所述第一介质层(109)远离所述基底(100)的顶面与所述参考顶面齐平；
    对所述初始阶梯结构(124)和所述第一介质层(109)进行第二图形化处理，以形成第一凹槽；
    形成填充满所述第一凹槽的所述支撑骨架(106)。
  18. 根据权利要求17所述的制造方法，其中，所述第一介质层(109)还位于所述初始阶梯结构(124)沿所述第二方向(Y)上相对的两侧；在形成所述初始阶梯结构(124)之后，在刻蚀所述初始阶梯结构(124)以形成所述台阶(114)之前，还包括：
    对所述间距区(138)的所述初始堆叠结构(108)和所述第一介质层(109)进行第三图形化处理，以形成第二凹槽；
    形成填充满所述第二凹槽的外围保护层(107)。
  19. 根据权利要求18所述的制造方法，其中，在形成所述外围保护层(107)之后，所述对所述初始阶梯结构(124)进行刻蚀以形成间隔(139)，包括：
    去除位于所述初始阶梯结构(124)和所述外围保护层(107)之间的所述第一介质层(109)，以露出所述初始阶梯结构(124)沿所述第二方向(Y)上相对的两侧；
    沿所述第二方向(Y)上，刻蚀所述初始阶梯结构(124)中的所述第二半导体层(128)，以形成所述间隔(139)；
    形成填充满所述间隔(139)的所述台阶(114)。
  20. 根据权利要求19所述的制造方法，其中，在形成所述台阶(114)之后，还包括：
    沿所述第二方向(Y)上，刻蚀所述初始阶梯结构(124)中的所述第一半导体层(118)，以形成间隙(149)；
    形成第二介质层(159)，所述第二介质层(159)填充满所述间隙(149)，且填充满所述外围保护层(107)和所述阶梯结构(104)之间的间隔。
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CN113228275A (zh) * 2019-12-24 2021-08-06 长江存储科技有限责任公司 三维nand存储器件及其形成方法
CN113540152A (zh) * 2020-07-23 2021-10-22 台湾积体电路制造股份有限公司 存储器器件、半导体器件及其制造方法

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US20190319040A1 (en) * 2018-04-11 2019-10-17 Sandisk Technologies Llc Three-dimensional memory device containing bidirectional taper staircases and methods of making the same
CN113228275A (zh) * 2019-12-24 2021-08-06 长江存储科技有限责任公司 三维nand存储器件及其形成方法
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