WO2024045870A1 - 半导体器件及其制作方法、芯片、电子设备 - Google Patents

半导体器件及其制作方法、芯片、电子设备 Download PDF

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Publication number
WO2024045870A1
WO2024045870A1 PCT/CN2023/104504 CN2023104504W WO2024045870A1 WO 2024045870 A1 WO2024045870 A1 WO 2024045870A1 CN 2023104504 W CN2023104504 W CN 2023104504W WO 2024045870 A1 WO2024045870 A1 WO 2024045870A1
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Prior art keywords
fin
substrate
oxygen barrier
barrier layer
shallow trench
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PCT/CN2023/104504
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English (en)
French (fr)
Inventor
黄敬勇
张齐飞
李洋洋
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华为技术有限公司
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Publication of WO2024045870A1 publication Critical patent/WO2024045870A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor device and its manufacturing method, chips, and electronic equipment.
  • CMOS complementary metal oxide semiconductor
  • CMOS integrated circuits due to its low cost, high integration, and low power consumption.
  • new technologies need to be continuously introduced, such as new materials, new processes, new structures, etc.
  • Ge-containing materials such as SiGe, GeSi, GeSn or Ge have high carrier mobility and good compatibility with traditional CMOS processes, so they are becoming common channel materials for field effect transistors in CMOS integrated circuits. .
  • fin field effect transistors FinFET
  • FinFET fin field effect transistors
  • the fin structure F Fin
  • the high-temperature annealing process will easily cause diffusion and migration of Ge atoms in the fin structure F, which will cause the fin structure F to become narrow or even disappear.
  • the channel interface will become rough, the mobility will decrease, and eventually the fin structure will be damaged. Problems such as structural instability and deterioration of device characteristics.
  • This application provides a semiconductor device and its manufacturing method, chip, and electronic equipment, which can improve the thermal stability of the fin structure in the field effect transistor.
  • the present application provides a semiconductor device, which includes a substrate, a shallow trench isolation layer, a fin structure, and an oxygen barrier layer provided on the substrate.
  • the fin structure includes a bottom fin and a top fin.
  • the shallow trench isolation layer is filled on the side of the bottom fin, and the top fin protrudes from the shallow trench isolation layer;
  • the oxygen barrier layer is located between the bottom fin and the shallow trench. between the isolation layers, and the oxygen barrier layer covers the surface of the bottom fin.
  • the semiconductor device provided by the embodiments of the present application covers the surface of the bottom fin with an oxygen barrier layer, and the shallow trench isolation layer is arranged outside the oxygen barrier layer.
  • the fins can be installed first.
  • An oxygen barrier layer is made on the surface of the structure, and then a shallow trench isolation layer is formed.
  • the oxygen barrier layer can block the direct contact between the fin structure and the shallow trench isolation layer.
  • This can prevent the diffusion and oxidation of Ge elements in the fin structure, improve the thermal stability of the fin structure, reduce structural damage or defects of the fin structure, and thereby improve the stability of the device structure.
  • the setting of the oxygen barrier layer can also reduce the rough interface problem of the fin structure, thereby improving the carrier mobility of the device, increasing the effective current of the device, and increasing the driving capability of the device.
  • the oxygen barrier layer extends to cover the surface of the substrate.
  • the manufacturing process based on the oxygen barrier layer (such as deposition process) will cover the surface of the substrate when making the oxygen barrier layer. There is no need to set up a separate process to remove the part of the substrate surface. Usually, the part covering the surface of the substrate will be retained. Oxygen barrier layer.
  • the oxygen barrier layer covering the surface of the substrate also helps to inhibit the diffusion and oxidation of the Ge element of the substrate.
  • the shallow trench isolation layer includes silicon dioxide.
  • the oxygen barrier layer includes at least one of SiN, SiCN, SiCO, SiNO, and SiCNO.
  • the thickness of the oxygen barrier layer is 1 nm to 10 nm.
  • the thickness of the oxygen barrier layer is 1 nm to 10 nm.
  • the semiconductor device is a fin field effect transistor; the top fin includes Ge.
  • the semiconductor device is a gate-all-around field effect transistor.
  • Embodiments of the present application also provide a method for manufacturing a semiconductor device, including: providing a substrate, and forming a fin structure on the substrate; wherein the fin structure includes a top fin and a bottom fin, and the top fin is located on the bottom fin.
  • the side of the fin away from the substrate has Ge in the top fin.
  • An oxygen barrier layer is formed on the surface of the fin structure.
  • a shallow trench isolation layer is formed by overfilling on the side of the fin structure covered with the oxygen barrier layer. Anneal the shallow trench isolation layer. The annealed shallow trench isolation layer is etched back to expose the top fin, and the oxygen barrier layer covering the surface of the top fin is removed.
  • the surface of the fin structure is first covered with an oxygen barrier layer, and the fin structure is protected by the oxygen barrier layer, and then the shallow trench isolation layer is formed, so that First, when the shallow trench isolation layer is annealed, the oxygen barrier layer blocks direct contact between the fin structure and the shallow trench isolation layer, thereby preventing the diffusion and oxidation of Ge elements in the fin structure and improving the fin structure.
  • the thermal stability of the fin structure reduces the structural damage or defects of the fin structure, thereby improving the stability of the device structure.
  • the setting of the oxygen barrier layer can also reduce the rough interface problem of the fin structure, thereby improving the carrier mobility of the device, increasing the effective current of the device, and increasing the driving capability of the device.
  • a substrate is provided above, and a fin structure is formed on the substrate; wherein the fin structure includes a top fin and a bottom fin, and the top fin is located on a side of the bottom fin away from the substrate.
  • the top fin contains Ge, including: providing a substrate, and forming a channel layer containing Ge on the substrate. The channel layer and the entire substrate are etched, the channel layer forms the top fin, and the upper part of the substrate forms the bottom fin.
  • a substrate is provided above, and a fin structure is formed on the substrate; wherein the fin structure includes a top fin and a bottom fin, and the top fin is located on a side of the bottom fin away from the substrate.
  • the top fin contains Ge, including: providing a substrate, and forming a semiconductor stack containing Ge on the substrate; wherein the semiconductor stack includes a plurality of sacrificial layers and a plurality of channel layers arranged alternately in sequence. The semiconductor stack and the entire substrate are etched, the semiconductor stack forms the top fin, and the upper portion of the substrate forms the bottom fin.
  • forming an oxygen barrier layer on the surface of the fin structure includes: using at least one of SiN, SiCN, SiCO, SiNO, SiCNO and other materials to form an oxygen barrier layer on the surface of the fin structure.
  • overfilling is used to form a shallow trench isolation layer on the side of the fin structure covering the oxygen barrier layer, including: using SiO2 on the side of the fin structure covering the oxygen barrier layer. Overfilled to form a shallow trench isolation layer.
  • An embodiment of the present application also provides a chip, which includes a controller and a semiconductor device provided in any of the above possible implementation manners, and the semiconductor device is electrically connected to the controller.
  • An embodiment of the present application also provides a chip, which includes a controller and a semiconductor device, and the semiconductor device is electrically connected to the controller.
  • the manufacturing method of the semiconductor device includes: providing a substrate and forming a fin structure on the substrate; wherein the fin structure includes a top fin and a bottom fin, and the top fin is located away from the bottom fin. side, and the top fins contain Ge.
  • a shallow trench isolation layer is formed on the side of the fin structure by overfilling, and the shallow trench isolation layer is etched back to expose the top fin.
  • An oxygen barrier layer is formed on the surface of the exposed top fin. Anneal the shallow trench isolation layer. Remove the oxygen barrier covering the top fin surface.
  • An embodiment of the present application also provides an electronic device, which includes a printed circuit board and a chip provided in any of the above possible implementation manners, and the chip is electrically connected to the printed circuit board.
  • Figure 1 is a schematic diagram of the manufacturing process of a field effect transistor in the prior art
  • Figure 2 is a schematic diagram of the fin structure of a fin field effect transistor provided by an embodiment of the present application
  • Figure 3 is a schematic diagram of the fin structure of a gate-all-around field effect transistor provided by an embodiment of the present application.
  • Figure 4 is a flow chart of a method for manufacturing a field effect transistor provided by an embodiment of the present application
  • Figure 5 is a schematic diagram of the manufacturing process of a field effect transistor provided by an embodiment of the present application.
  • Figure 6 is a schematic diagram of the manufacturing process of a field effect transistor provided by an embodiment of the present application.
  • Figure 7 is a flow chart of a method for manufacturing a field effect transistor provided by an embodiment of the present application.
  • Figure 8 is a schematic diagram of the manufacturing process of a field effect transistor provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of the manufacturing process of a field effect transistor provided by an embodiment of the present application.
  • An embodiment of the present application provides an electronic device, which includes a printed circuit board (PCB) and a chip; wherein, the chip is disposed on the surface of the printed circuit board (also called a circuit board), and the chip is connected to Printed circuit board electrical connections.
  • PCB printed circuit board
  • the chip is disposed on the surface of the printed circuit board (also called a circuit board), and the chip is connected to Printed circuit board electrical connections.
  • the chip can be a processor, a memory chip, a logic chip, etc.
  • the electronic device can be a mobile phone, a tablet computer, a notebook, a car computer, a smart watch, a smart bracelet and other electronic products.
  • the chip provided by the embodiment of the present application adopts a semiconductor device with a new structure.
  • the semiconductor device has a fin structure, and an oxygen barrier layer is provided on the surface of the fin structure.
  • the oxygen barrier layer By providing the oxygen barrier layer, the fin structure can be reduced in size. loss, thereby improving the stability of the semiconductor device structure.
  • the chip can also be provided with other devices connected to the aforementioned semiconductor device, such as a controller, etc.
  • a controller etc.
  • This application does not limit this, and can be set according to actual needs.
  • the semiconductor device can be a fin field effect transistor (FinFET), a gate all around field effect transistor (gate all around field effect transistor, GAAFET), forksheet field effect transistor, forksheet FET; among them, GAAFET can be a nanosheet (nanosheet, NS) field effect transistor (i.e. NSFET), nanowire (nanowire, NW) field effect Transistor (i.e. NWFET), complementary field effect transistor (CFET), etc.
  • FinFET fin field effect transistor
  • GAAFET gate all around field effect transistor
  • GAAFET forksheet field effect transistor
  • GAAFET can be a nanosheet (nanosheet, NS) field effect transistor (i.e. NSFET), nanowire (nanowire, NW) field effect Transistor (i.e. NWFET), complementary field effect transistor (CFET), etc.
  • FIG. 2 is a schematic diagram of a conventional FinFET fin structure.
  • Figure 3 is a schematic diagram of the fin structure of a conventional GAAFET.
  • the fin structure F is a fin-shaped structure provided on the substrate 01, and shallow holes are provided around the bottom of the fin structure F. Trench isolation layer STI to achieve electrical isolation between adjacent field effect transistors.
  • the gate of the field effect transistor (not shown in Figures 2 and 3) is laterally arranged around the middle area of the fin structure, and the two ends of the fin structure serve as the source and drain ends of the field effect transistor respectively; in the fin structure
  • the part surrounded by the gate forms a channel (channel).
  • the fin structure F is an independent complete fin structure.
  • the top of the fin structure F is usually slightly narrower than the bottom, and the sides of the fin structure F have a certain inclination angle.
  • the fin structure F includes a plurality of nanosheets NS that are parallel (or approximately parallel) to the substrate 01 .
  • the fin structure F includes a plurality of nanosheets NS that are parallel (or approximately parallel) to the substrate 01 .
  • a gate electrode arranged around the nanosheets NS is formed in the subsequent replacement metal gate process.
  • the fin structure F includes a plurality of nanowires NW that are parallel (or approximately parallel) to the substrate 01 .
  • the fin structure F includes a plurality of nanowires NW that are parallel (or approximately parallel) to the substrate 01 .
  • the fin structure F includes a plurality of nanowires NW that are parallel (or approximately parallel) to the substrate 01 .
  • Figures 2 and 3 are only for a general description of the fin structures F in different types of field effect transistors of the present application. It can be understood that Figures 2 and 3 only illustrate one type of fin structure F respectively. The partial structure of FinFET and a GAAFET, other parts are not shown in the figure.
  • the gate G is usually made using a metal gate replacement process; that is to say, during the fabrication process of the device, a dummy gate is first formed, and then In the subsequent production process, the dummy gate is removed, and the gate G is formed in the removed area of the dummy gate, such as high dielectric constant gate dielectric and metal gate (high k metal gate, HKMG), which can be referred to as high K metal.
  • HKMG high dielectric constant gate dielectric and metal gate
  • Gate the following embodiments all take HKMG as the gate G as an example for schematic explanation.
  • embodiments of the present application provide a field effect transistor with a new structure.
  • an oxygen barrier layer is first formed on the surface of the fin structure.
  • the oxygen element in the shallow trench isolation layer STI cannot react with the Ge element in the fin structure, and the fin structure will not be oxidized, that is, the fin structure will not be
  • the loss caused by high-temperature annealing improves the stability of the device structure, thereby improving the reliability of the device.
  • this embodiment provides a method for manufacturing a field effect transistor, which may include:
  • Step 11 Referring to (a) and (b) in Figure 5 or (a) and (b) in Figure 6, provide a substrate 01, and form a fin structure F on the substrate 01; wherein, the fin structure F includes a top fin F1 and a bottom fin F2.
  • the top fin F1 is located on the side of the bottom fin F2 away from the substrate 01, and the top fin F1 contains Ge.
  • the above-mentioned substrate 01 can be a bulk silicon (bulk sillicon) substrate, SOI (sillicon on isolation, silicon on an insulating substrate), a Ge substrate, a strain buffer (strained relaxed buffer, SRB) layer substrate, etc., this application is This is not a limitation and can be set as needed in practice.
  • a Ge lattice in a high Ge composition cannot be grown directly on a silicon substrate due to lattice mismatch issues. Therefore, in some embodiments, an SRB layer can be grown as a substrate (ie, a strain buffer layer substrate).
  • the above-mentioned top fin F1 containing Ge can be a single-layer or multi-layer superlattice containing SiGe, GeSi, GeSn or Ge.
  • the appropriate superlattice material, thickness, number of layers, etc. are selected according to needs.
  • the top fin F1 in a FinFET, can be a single-layer superlattice with a fixed Ge composition; in an NSFET, the top fin F1 can include a multi-layer superlattice containing a Ge composition in which the sacrificial layer and the channel layer are alternately grown. Stacked superlattice; please refer to the relevant description below for details.
  • the substrate is a part of a wafer used to prepare integrated circuits or semiconductor devices.
  • the substrate can be highly doped to suppress the formation of parasitic channels; Schematically, an ion distribution of a certain concentration and depth can be formed in the substrate through ion implantation, annealing or diffusion.
  • the above step 01 may include: referring to (a) in FIG. 5 , providing a substrate 01 and forming a channel layer 100 containing Ge on the substrate 01 . Then, referring to FIG. 5(b) , the channel layer 100 and the substrate 01 are etched as a whole to form a fin structure F; where the channel layer 100 forms the top fin F1 in the fin structure F, and the fin structure F is formed by etching the entirety of the substrate 01 . The upper part of the base 01 forms the bottom fin F2 of the fin structure F.
  • the thickness of the above-mentioned Ge-containing channel layer 100 defines the height of the top fin F1, and the channel layer 100 is used to prepare the channel of FinFET; schematically, the thickness of the channel layer 100 can be 10nm ⁇ 100nm.
  • the height of the fin structure F is the sum of the heights of the top fin F1 and the bottom fin F2.
  • the height of the bottom fin F2 determines the thickness of the subsequently formed shallow trench isolation layer STI (see below for details).
  • the height of the bottom fin F2 can be 100nm ⁇ 1000nm.
  • the above step 01 may include: referring to FIG. 6(a), providing a substrate 01, and forming a semiconductor stack 200 containing Ge on the substrate 01; wherein the semiconductor stack 200 includes A plurality of sacrificial layers 1 and a plurality of channel layers 2 are arranged alternately in sequence. Then, referring to FIG. 6(b) , the entire semiconductor stack 200 and substrate 01 are etched to form a fin structure F; wherein, the semiconductor stack 200 forms a top fin F1, and the upper part of the substrate 01 is formed. Bottom fin F2.
  • the height of the fin structure F is the sum of the heights of the top fin F1 and the bottom fin F2.
  • the thickness of the semiconductor stack 200 defines the height of the top fin F1, and the height of the bottom fin F2 determines the thickness of the subsequently formed shallow trench isolation layer STI (see below for details).
  • the height of the bottom fin F2 can be 50nm ⁇ 1000nm.
  • the width of the fin structure F determines the width of the nanosheet, and the width of the fin structure F can be 20nm to 300nm.
  • the width of the fin structure F determines the diameter of the nanowire, and the width of the fin structure F can be 10nm to 100nm.
  • a plurality of sacrificial layers 1 are respectively located below a plurality of channel layers 2, and the plurality of channel layers 2 are used to produce multiple channels of the NSFET.
  • the sacrificial layers 1 To define HKMG the sacrificial layer 1 not only plays a certain supporting role for the channel layer 2, but also needs to be selectively removed in subsequent processes to fill the HKMG. In this case, the etching of the sacrificial layer 1 requires a material with high selectivity for the channel layer 2 and also needs to provide stress for the channel layer 2 .
  • the Ge composition in the sacrificial layer 1 and the channel layer 2 may be selected to be different, and the Ge composition in the sacrificial layer 1 may be higher than the Ge composition in the channel layer 2 .
  • the shallow trench isolation layer STI needs to be annealed before the sacrificial layer 1 is removed, and during the annealing process of the shallow trench isolation layer STI
  • the middle sacrificial layer 1 is easily oxidized and easily causes structural loss. Since the structural loss of the sacrificial layer 1 will affect the profile of the channel layer 2, the sacrificial layer 1 needs to be protected by an oxygen barrier layer. For details, please refer to the following.
  • the Ge component in the sacrificial layer 1 can be set to x, and the Ge component in the channel layer 2 can be set to y, x-y is greater than or equal to 0.2, y can be 0; for example, the channel layer 2 is Si, and the sacrificial layer 1 is SiGe; for another example, the channel layer 2 is SiGe, and the sacrificial layer 1 is GeSi or Ge; for another example, the channel layer 2 is GeSn, and sacrificial layer 1 is Ge.
  • the sacrificial layer 1 and the channel layer 2 in the semiconductor stack 200 do not limit the number, thickness, materials, etc. of the sacrificial layer 1 and the channel layer 2 in the semiconductor stack 200, and they can be set as needed.
  • the sacrificial layer 1 and the channel layer 2 have the same number of layers, and their thicknesses are similar; for example, in some embodiments, the sacrificial layer 1 and the channel layer 2 may have 3 to 7 layers, with a thickness of 10 nm to 40 nm.
  • the thickness of the semiconductor stack 200 depends on the thickness and number of layers of the sacrificial layer 1 and the channel layer 2, and the thickness may be about 60 nm to 600 nm.
  • the photolithography process can use extreme ultraviolet (extreme ultra-violet) photolithography or self-aligned multiplex photolithography.
  • the photoresist pattern can be transferred to the hard mask layer through etching (such as reactive ion etching); then, the superlattice structure and the substrate are etched to form a fin structure.
  • the hard mask layer can use silicon oxide, silicon nitride, or a composite layer of silicon oxide and silicon nitride. After the fin structure F is formed, the hard mask layer on top of the fin structure F can be temporarily retained without additional removal.
  • Step 12 Referring to (c) in Figure 5 or (c) in Figure 6, form an oxygen barrier layer 10 on the surface of the fin structure F.
  • the above step 12 may include: forming an oxygen barrier layer 10 on the surface of the fin structure F using at least one of SiN, SiCN, SiCO, SiNO, SiCNO and other materials.
  • the thickness of the above-mentioned oxygen barrier layer 10 can be adjusted according to actual conditions, as long as sufficient oxygen barrier capability is ensured and no damage is caused to the narrow and thin fin structure F. In addition, it is also necessary to consider the selectivity of the subsequently formed shallow trench isolation layer STI etching or corrosion to the oxygen barrier layer 10. When the selectivity is poor, the thickness of the oxygen barrier layer 10 can be appropriately increased.
  • the thickness of the oxygen barrier layer 10 formed in the above step 12 can be 1 nm to 10 nm; by setting the thickness of the oxygen barrier layer 10 to be greater than 1 nm, the barrier effect of the oxygen barrier layer 10 is ensured; by The thickness of the oxygen barrier layer 10 is set to less than 10 nm to prevent the oxygen barrier layer 10 from being too thick and causing large stress to cause damage to the fin structure F.
  • low-temperature atomic layer deposition (ALD) or chemical vapor deposition (CVD) can be used through the above step 12.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • the oxygen barrier layer 10 formed in step 12 covers the surface of the fin structure F and can protect the fin structure F.
  • a whole-layer deposition process is used. Refer to (c in Figure 5 ) or as shown in (c) in Figure 6, the oxygen barrier layer 10 is While covering the surface of the fin structure F, it can be extended to cover the surface of the substrate 01 .
  • the surface of the substrate 01 will be covered when the oxygen barrier layer 10 is manufactured. There is no need to set up a separate process to remove part of the surface of the substrate 01, and the coverage will usually be retained.
  • the oxygen barrier layer 10 covering the surface of the substrate 01 also helps to suppress the diffusion and oxidation of the Ge element of the substrate.
  • Step 13 Referring to (d) in FIG. 5 or (d) in FIG. 6, a shallow trench isolation layer STI is formed on the side of the fin structure F covering the oxygen barrier layer 10 by overfilling.
  • the above step 13 may include: overfilling the side of the fin structure F covering the oxygen barrier layer 10 with SiO2 to form a shallow trench isolation layer STI.
  • a shallow trench isolation layer STI is formed on the side of the fin structure F covering the oxygen barrier layer 10 by overfilling.
  • the upper surface of the shallow trench isolation layer STI will be higher than that of the fin structure F.
  • the top of the fin structure F is wrapped around the top of the fin structure F; of course, the shallow trench isolation layer STI needs to be etched back to a certain depth in the subsequent process (see below for details).
  • the above-mentioned shallow trench isolation layer STI production can include multiple processes.
  • a thin and high-quality liner layer oxide layer such as SiO2 can be deposited first, and then a high aspect ratio process can be used.
  • high aspect retio process, HARP high aspect retio process
  • spin coating process spin on dielectric, SOD
  • flowable chemical vapor deposition process flowable chemical vapor deposition, FCVD
  • other overfilling thick oxide layers such as SiO2
  • processes such as argon bombardment or chemical mechanical polishing (CMP) can be used to planarize the above-mentioned overfilled oxide layer, stopping within a certain thickness above the fin structure F to reserve a certain process window to prevent fin Piece structure F damage.
  • CMP chemical mechanical polishing
  • the planarization process can also be performed after the annealing process in step 14, and this application does not limit this.
  • Step 14 Perform annealing treatment on the shallow trench isolation layer STI.
  • the oxygen barrier layer 10 can separate the Ge element in the fin structure F and the shallow trench.
  • the oxygen in the isolation layer STI is blocked, so that the oxygen in the shallow trench isolation layer STI cannot oxidize with the Ge element in the fin structure F. That is to say, the high-temperature annealing process of the shallow trench isolation layer STI will not This leads to problems such as loss and rough interface of the fin structure F containing Ge, thereby improving the thermal stability of the fin structure F.
  • Step 15 Referring to (e) and (f) in Figure 5 and (e) and (f) in Figure 6, etch back the annealed shallow trench isolation layer STI to expose the top fin F1, and remove the covering Oxygen barrier layer 10 on the surface of top fin F1.
  • the above step 15 may include: referring to Figure 5 (e) and Figure 6 (e), etching back the annealed shallow trench isolation layer STI; wherein, the etching back process may be diluted. Hydrofluoric acid or buffered oxide etch (BOE).
  • BOE Hydrofluoric acid or buffered oxide etch
  • the STI etching of the shallow trench isolation layer is stopped at the boundary of the channel layer (i.e., the junction between the top fin and the bottom fin) through the etching back process.
  • the etching of the shallow trench isolation layer STI is stopped at the boundary of the lowermost sacrificial layer 1 (i.e., the interface between the top fin and the bottom fin) through the etching back process.
  • the top fin F1 ie, the channel area covered by the oxygen barrier layer 10 is exposed.
  • the exposed oxygen barrier layer 10 that is, the oxygen barrier layer 10 covering the top fin F1
  • the oxygen barrier layer 10 covering the surface of the bottom fin F2 is embedded in the shallow trench isolation layer STI and remains without being removed.
  • wet etching or dry etching can be used, as long as the etching has a high selectivity for Ge-containing materials and SiO2, ensuring that the sides and corners are The oxygen barrier layer 10 can be removed without damaging the top fin F1 and the shallow trench isolation layer STI.
  • isotropic dry etching can be used to remove the oxygen barrier layer 10 covering the surface of the top fin F1.
  • subsequent related manufacturing processes can be performed, such as making dummy gates, gate sidewalls and inner sidewalls (for NSFET), and epitaxially growing source and drain regions.
  • Processes such as interlayer dielectric growth and planarization, dummy gate removal, channel release (for NSFET), HKMG deposition, and formation of electrical contacts are not limited in this application. In practice, corresponding fabrication can be carried out according to the type of device. .
  • the dummy gate is replaced to form a gate that laterally surrounds the top fin F1;
  • the sacrificial layer 1 is removed and a dummy gate is formed at the position of the sacrificial layer 1 , and then replace the dummy gate to form a gate that laterally surrounds multiple channel layers (nanosheets).
  • the surface of the fin structure F is first covered with the oxygen barrier layer 10, and the fin structure F is protected by the oxygen barrier layer 10. Then, the shallow trench isolation layer STI is formed. In this way, when the shallow trench isolation layer STI is annealed, the oxygen barrier layer 10 blocks the direct contact between the fin structure F and the shallow trench isolation layer STI. This can prevent the diffusion and oxidation of the Ge element in the fin structure F, improve the thermal stability of the fin structure F, reduce the structural damage or defects of the fin structure F, and thereby improve the stability of the device structure. Of course, the provision of the oxygen barrier layer 10 can also reduce the rough interface problem of the fin structure F, thereby improving the carrier mobility of the device, increasing the effective current of the device, and increasing the driving capability of the device.
  • the oxygen barrier layer 10 may cover the entire bottom fin F2.
  • the side may also be part of the side; of course, in order to reduce the structural damage or defects of the bottom fin F2 to a greater extent, the oxygen barrier layer 10 can usually be provided to cover the entire side of the bottom fin F2.
  • This embodiment also provides another method for manufacturing a field effect transistor, as shown in Figure 7.
  • the manufacturing may include:
  • Step 21 Referring to (a) and (b) in Figure 8 and (a) and (b) in Figure 9, provide a substrate 01, and form a fin structure F on the substrate 01; wherein, the fin structure F includes a top fin F1 and a bottom fin F2.
  • the top fin F1 is located on the side of the bottom fin F2 away from the substrate 01, and the top fin F1 contains Ge.
  • Step 21 is basically the same as the production of step 11 in the first embodiment.
  • step 21 please refer to the corresponding part of step 11, and will not be described again here.
  • Step 22 Referring to (c) and (d) in Figure 8 and (c) and (d) in Figure 9, use overfilling to form a shallow trench isolation layer STI on the side of the fin structure F, and The shallow trench isolation layer STI is etched back to expose the top fins.
  • the above step 11 may include: overfilling the side of the fin structure F covering the oxygen barrier layer 10 with SiO2 to form a shallow trench isolation layer STI; and then filling the shallow trench with SiO2.
  • the isolation layer STI is etched back to expose the top fin F1.
  • step 15 Regarding the overfilling method used to form the shallow trench isolation layer STI in step 22, you can refer to the corresponding instructions in the aforementioned step 13. Regarding the related content of etching back the shallow trench isolation layer STI to expose the top fin F1, you can refer to the corresponding instructions. The corresponding description in step 15 will not be repeated here.
  • Step 23 Referring to FIG. 8(e) and FIG. 9(e), form an oxygen barrier layer 10 on the surface of the exposed top fin F1.
  • the above step 23 may include: using at least one of SiN, SiCN, SiCO, SiNO, SiCNO and other materials to form the oxygen barrier layer 10 on the surface of the top fin F1.
  • the oxygen barrier layer 10 can extend to cover the surface of the shallow trench isolation layer STI.
  • Step 24 Perform annealing treatment on the shallow trench isolation layer STI.
  • the oxygen barrier layer 10 can isolate the Ge element in the top fin F1 from the shallow trench.
  • the oxygen in the shallow trench isolation layer STI is blocked, so that the oxygen in the shallow trench isolation layer STI cannot oxidize with the Ge element in the top fin F1. That is to say, the high-temperature annealing process of the shallow trench isolation layer STI will not cause
  • the top fin F1 containing Ge suffers from problems such as loss and interface roughness, thereby improving the thermal stability of the fin structure F.
  • Step 25 Refer to (f) in Figure 8 and (f) in Figure 9 to remove the oxygen barrier layer 10 covering the surface of the top fin F1.
  • the manufacturing method of the second embodiment first makes a shallow trench isolation layer STI, and etches back the shallow trench isolation layer STI to leak out the top fin F1; and then forms an oxygen layer on the surface of the top fin F1.
  • the barrier layer 10 protects the top fin F1 through the oxygen barrier layer 10, thereby preventing the diffusion and oxidation of the Ge element in the top fin F1 during the subsequent annealing process of the shallow trench isolation layer STI, reducing the The problem of structural damage and defects of the fin structure is eliminated, and the thermal stability of the fin structure is improved, thereby improving the stability of the device structure.

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Abstract

本申请提供一种半导体器件及其制作方法、芯片、电子设备，涉及半导体技术领域，能够提高场效应晶体管中鳍片结构的热稳定性。该半导体器件包括衬底以及设置于衬底上的浅沟槽隔离层、鳍片结构、氧阻隔层。其中，鳍片结构包括底部鳍片和顶部鳍片，浅沟槽隔离层填充在底部鳍片的侧面，顶部鳍片凸出于浅沟槽隔离层，顶部鳍片在长度方向上的两端分别作为半导体器件的源区和漏区；氧阻隔层位于底部鳍片与浅沟槽隔离层之间，且氧阻隔层覆盖底部鳍片的表面。

Description

半导体器件及其制作方法、芯片、电子设备
本申请要求在2022年09月01日提交中国专利局、申请号为202211062397.8、发明名称为“半导体器件及其制作方法、芯片、电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体器件及其制作方法、芯片、电子设备。
背景技术
CMOS(complementary metal oxide semiconductor，互补金属氧化物半导体)工艺以其低成本、高集成度、低功耗等特点被广泛的应用于各类芯片。为了推动CMOS集成电路的发展，需要不断引入新技术，如新材料、新工艺、新结构等。其中，SiGe，GeSi，GeSn或Ge等含Ge材料具有较高的载流子迁移率，且与传统CMOS工艺具有很好的兼容性，因此正成为CMOS集成电路中场效应晶体管的常用沟道材料。然而，由于Ge的熔点仅937℃，高温下容易扩散和迁移，且Ge容易氧化，二氧化锗不稳定，易溶于水，一氧化锗易解吸，也即含Ge材料在半导体制程中无法承受很高的热预算，因此，在制造工艺中采用高温工艺，会对在先形成含Ge材料的造成结构损伤、界面变差等不良影响，进而导致器件的电学特性波动，可靠性变差。
以采用鳍式场效应晶体管(fin field effect transistor，FinFET)的集成电路的制作为例，如图1中(a)、(b)所示，在形成鳍片结构F(Fin)之后需要先在鳍片结构F的四周填充浅沟槽隔离层STI(shallow trench isolation)；然后，需要通过高温退火对沟槽隔离层STI进行致密化，并通过回刻沟槽隔离层STI露出鳍片结构F。但是高温退火的过程会对鳍片结构F中的Ge原子容易发生扩散和迁移，会导致鳍片结构F变窄甚至消失，同时会使得沟道界面变得粗糙，迁移率下降，最终导致鳍片结构不稳定和器件特性变差等问题。
发明内容
本申请提供一种半导体器件及其制作方法、芯片、电子设备，能够提高场效应晶体管中鳍片结构的热稳定性。
本申请提供一种半导体器件，该半导体器件包括衬底以及设置于衬底上的浅沟槽隔离层、鳍片结构、氧阻隔层。其中，鳍片结构包括底部鳍片和顶部鳍片，浅沟槽隔离层填充在底部鳍片的侧面，顶部鳍片凸出于浅沟槽隔离层；氧阻隔层位于底部鳍片与浅沟槽隔离层之间，且氧阻隔层覆盖底部鳍片的表面。
本申请实施例提供的半导体器件通过在底部鳍片的表面覆盖氧阻隔层，浅沟槽隔离层设置在氧阻隔层的外侧，在此情况下，在实际的制作时，可以先在含鳍片结构的表面制作氧阻隔层，再形成浅沟槽隔离层，这样一来，在对浅沟槽隔离层进行退火处理时，氧阻隔层能够阻隔了鳍片结构与浅沟槽隔离层直接接触，从而能够防止鳍片结构中发生Ge元素的扩散和氧化，提高了鳍片结构的热稳定性，降低了鳍片结构的结构损伤或缺陷问题，进而提高了器件结构的稳定性。当然，通过氧阻隔层的设置还能够减小鳍片结构的界面粗糙问题，进而提高了器件的载流子迁移率，增大了器件的有效电流，增加了器件的驱动能力。
在一些可能实现的方式中，氧阻隔层延伸覆盖至衬底的表面。基于氧阻隔层的制作工艺(如沉积工艺)，在制作氧阻隔层时会覆盖在衬底的表面，无需设置单独工艺对衬底表面的部分进行去除，通常会保留覆盖在衬底的表面的氧阻隔层。另外，在衬底中含有Ge元素的情况下，覆盖在衬底的表面的氧阻隔层同样有助于抑制衬底的Ge元素的扩散和氧化。
在一些可能实现的方式中，浅沟槽隔离层中包括二氧化硅。
在一些可能实现的方式中，氧阻隔层中包括SiN、SiCN、SiCO、SiNO、SiCNO中的至少一种。
在一些可能实现的方式中，氧阻隔层的厚度为1nm～10nm。通过设置氧阻隔层的厚度大于1nm，来保证氧阻隔层的阻隔效果；通过设置氧阻隔层的厚度小于10nm，避免因氧阻隔层的厚度过大产生较大应力对鳍片结构造成损伤。
在一些可能实现的方式中，半导体器件为鳍式场效应晶体管；顶部鳍片中包括Ge。
在一些可能实现的方式中，半导体器件为环栅场效应晶体管。
本申请实施例还提供一种半导体器件的制作方法，包括：提供衬底，并在衬底上形成鳍片结构；其中，鳍片结构包括顶部鳍片和底部鳍片，顶部鳍片位于底部鳍片远离衬底的一侧，且顶部鳍片中含有Ge。在鳍片结构的表面形成氧阻隔层。在覆盖有氧阻隔层的鳍片结构的侧面采用过填充的方式形成浅沟槽隔离层。对浅沟槽隔离层进行退火处理。对退火后的浅沟槽隔离层进行回刻露出顶部鳍片，并去除覆盖在顶部鳍片表面的氧阻隔层。
采用本实施例提供的制作方法，在制作浅沟槽隔离层之前先在鳍片结构的表面覆盖氧阻隔层，通过氧阻隔层对鳍片结构形成保护，然后再形成浅沟槽隔离层，这样一来，在对浅沟槽隔离层进行退火处理时，氧阻隔层阻隔了鳍片结构与浅沟槽隔离层直接接触，从而能够防止鳍片结构中发生Ge元素的扩散和氧化，提高了鳍片结构的热稳定性，降低了鳍片结构的结构损伤或缺陷问题，进而提高了器件结构的稳定性。当然，通过氧阻隔层的设置还能够减小鳍片结构的界面粗糙问题，进而提高了器件的载流子迁移率，增大了器件的有效电流，增加了器件的驱动能力。
在一些可能实现的方式中，上述提供衬底，并在衬底上形成鳍片结构；其中，鳍片结构包括顶部鳍片和底部鳍片，顶部鳍片位于底部鳍片远离衬底的一侧，且顶部鳍片中含有Ge，包括：提供衬底，并在衬底上形成含有Ge的沟道层。对沟道层以及衬底整体进行刻蚀，沟道层形成顶部鳍片，衬底的上层部分形成底部鳍片。
在一些可能实现的方式中，上述提供衬底，并在衬底上形成鳍片结构；其中，鳍片结构包括顶部鳍片和底部鳍片，顶部鳍片位于底部鳍片远离衬底的一侧，且顶部鳍片中含有Ge，包括：提供衬底，并在衬底上形成含有Ge的半导体叠层；其中，半导体叠层包括依次交替设置的多个牺牲层和多个沟道层。对半导体叠层以及衬底整体进行刻蚀，半导体叠层形成顶部鳍片，衬底的上层部分形成底部鳍片。
在一些可能实现的方式中，在鳍片结构的表面形成氧阻隔层包括：在鳍片结构的表面，采用SiN、SiCN、SiCO、SiNO、SiCNO等材料中的至少一种形成氧阻隔层。
在一些可能实现的方式中，在覆盖有氧阻隔层的鳍片结构的侧面采用过填充的方式形成浅沟槽隔离层，包括：采用SiO2在覆盖有氧阻隔层的所述鳍片结构的侧面进行过填充，形成浅沟槽隔离层。
本申请实施例还提供一种芯片，该芯片包括控制器以及如前述任一种可能实现的方式中提供的半导体器件，该半导体器件与控制器电连接。
本申请实施例还提供一种芯片，该芯片包括控制器以及半导体器件，该半导体器件与控制器电连接。其中该半导体器件的制作方法，包括：提供衬底，并在衬底上形成鳍片结构；其中，鳍片结构包括顶部鳍片和底部鳍片，顶部鳍片位于底部鳍片远离衬底的一侧，且顶部鳍片中含有Ge。在鳍片结构的侧面采用过填充的方式形成浅沟槽隔离层，并对浅沟槽隔离层进行回刻露出顶部鳍片。在露出的顶部鳍片的表面形成氧阻隔层。对浅沟槽隔离层进行退火处理。去除覆盖在顶部鳍片表面的氧阻隔层。
本申请实施例还提供一种电子设备，该电子设备包括印刷线路板以及如前述任一种可能实现的方式提供的芯片，该芯片与印刷线路板电连接。
附图说明
图1为现有技术中场效应晶体管中的制作过程示意图；
图2为本申请实施例提供的一种鳍式场效应晶体管的鳍片结构示意图；
图3为本申请实施例提供的一种环栅场效应晶体管的鳍片结构示意图；
图4为本申请实施例提供的一种场效应晶体管的制作方法流程图；
图5为本申请实施例提供的一种场效应晶体管的制作过程示意图；
图6为本申请实施例提供的一种场效应晶体管的制作过程示意图；
图7为本申请实施例提供的一种场效应晶体管的制作方法流程图；
图8为本申请实施例提供的一种场效应晶体管的制作过程示意图；
图9为本申请实施例提供的一种场效应晶体管的制作过程示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书实施例和权利要求书及附图中的术语“第一”、“第二”等仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“至少一个(项)”是指一个或者多个，“多个”是指两个或两个以上。“安装”、“连接”、“相连”等应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或者一体地连接；可以是直接连接，也可以是通过中间媒介间接，也可以是两个元件内部的连通。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。“上”、“下”、“左”、“右”、“顶”、“底”等仅用于相对于附图中的部件的方位而言的，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中的部件所放置的方位的变化而相应地发生变化。
本申请实施例提供一种电子设备，该电子设备中包括印刷线路板(printed circuit board，PCB)以及芯片；其中，芯片设置在印刷线路板(也可以称为电路板)的表面，且芯片与印刷线路板电连接。
本申请对于上述芯片的设置形式不做限定。示意的，该芯片可以是处理器、存储芯片、逻辑芯片等。
本申请对于上述电子设备的设置形式不做限制。示意的，该电子设备可以为手机、平板电脑、笔记本、车载电脑、智能手表、智能手环等电子产品。
本申请实施例提供的芯片中采用一种新型结构的半导体器件，该半导体器件具有鳍片结构，并且在鳍片结构的表面设置有氧阻隔层，通过设置该氧阻隔层能够减小鳍片结构损失，进而提高半导体器件结构的稳定性。
当然，芯片中还可以设置有与前述半导体器件连接的其他器件，如控制器等，本申请对此不做限制，实际中可以根据需要进行设置。
本申请对于上述具有鳍片结构的半导体器件的具体设置形式不做限制；例如，该半导体器件可以是鳍式场效应晶体管(fin field effect transistor，FinFET)、环栅场效应晶体管(gate all around field effect transistor，GAAFET)、叉型片场效应晶体管(forksheet field effect transistor，forksheet FET)；其中，GAAFET可以是纳米片(nanosheet，NS)场效应晶体管(即NSFET)、纳米线(nanowire，NW)场效应晶体管(即NWFET)、互补式场效晶体管(complementary field effect transistor，CFET)等。
以下结合FinFET和GAAFET，对本申请实施例提供的场效应晶体管中的鳍片结构以及相关设置进行简单的说明。图2为一种常规的FinFET的鳍片结构示意图。图3为一种常规GAAFET的鳍片结构示意图。
参考图2、图3所示，本领域的技术人员可以理解的是，在场效应晶体管中，鳍片结构F为设置在衬底01上鳍状结构，并且鳍片结构F底部的四周设置有浅沟槽隔离层STI，以实现相邻的场效应晶体管之间的电性隔离。场效应晶体管的栅极(图2和图3中未示出)横向环绕设置在鳍片结构的中间区域，鳍片结构的两端分别作为场效应晶体管的源端和漏端；鳍片结构中被栅极环绕的部分形成沟道(通道)，通过控制施加在栅极上的电压大小来调整在沟道内部形成电场大小，进而实现对源端和漏端之间电流大小的调节。
当然，在不同结构的场效应晶体管中，鳍片结构F的设置也存在一定的差异。
例如，参考图2所示，在FinFET中，鳍片结构F为一个独立完整鳍状结构。当然，在实际的产品中鳍片结构F的顶部通常略窄与底部，并且鳍片结构F的侧面具有一定的倾角。
又例如，参考图3所示，在纳米片场效应晶体管(NSFET)中，鳍片结构F包括与衬底01平行(或者近似平行)的多个纳米片NS。当然，相邻的纳米片NS之间在制作初期为牺牲层，并在后续替代金属栅工艺形成环绕纳米片NS设置的栅极，具体可以参考下文的相关说明。
再例如，在纳米线场效应晶体管(NWFET)中，鳍片结构F包括与衬底01平行(或者近似平行)的多个纳米线NW。当然，相邻的纳米线NW之间在制作初期为牺牲层，并在后续替代金属栅工艺形成环绕纳米线NW设置的栅极。
需要说明的是，图2和图3仅是为了对本申请的不同类型的场效应晶体管中鳍片结构F进行大体的说明，可以理解的是，图2和图3中仅是分别示意了一种FinFET和一种GAAFET的局部结构，其他的部分并未在图中示意出。
此处可以理解的是，对于FinFET、GAAFET而言，栅极G通常是采用替代金属栅极工艺进行制作的；也就是说，在器件的制作过程中，先形成假栅(dummy gate)，在后续制作过程中将假栅(dummy gate)去除，并在假栅的去除区域形成栅极G，如高介电常数栅介质和金属栅(high k metal gate，HKMG)，可简称为高K金属栅；以下实施例均是以栅极G采用HKMG为例进行示意说明的。
参考图1所示，在现有技术中，由于对浅沟槽隔离层STI进行高温退火时，会引起鳍片结构F损失以及界面粗糙等问题，从而引起器件的载流子迁移率变差，有效电流变小，驱动能力变差；同时还会引起纳米级鳍宽的尺寸波动，进而会造成器件的电学特性波动，使得器件的可靠性变差。另外，鳍片结构严重损失的情况下，还会造成器件失效，芯片良率下降等问题。
基于此，本申请实施例提供一种新型结构的场效应晶体管，通过在对浅沟槽隔离层STI进行高温退火之前，先在鳍片结构的表面形成氧阻隔层，这样一来，在高温退火的过程中，在氧阻隔层的阻隔作用下，浅沟槽隔离层STI中的氧元素无法与鳍片结构中的Ge元素反应，鳍片结构不会发生氧化，也即鳍片结构不会因为高温退火而产生损失，使得器件结构的稳定性提高，进而能够提高器件的可靠性。
以下通过具体实施例结合FinFET、NSFET的具体制作工艺过程，对本申请实施例提供的场效应晶体管的新型结构进行说明。
实施例一
如图4所示，本实施例提供一种场效应晶体管的制作方法可以包括：
步骤11、参考图5中(a)、(b)或图6中(a)、(b)所示，提供衬底01，并在衬底01上形成鳍片结构F；其中，鳍片结构F包括顶部鳍片F1和底部鳍片F2，顶部鳍片F1位于底部鳍片F2远离衬底01的一侧，且顶部鳍片F1中含有Ge。
上述衬底01可以是体硅(bulk sillicon)衬底、SOI(sillicon on isolation，绝缘衬底上的硅)、Ge衬底、应变缓冲(strained relaxed buffer，SRB)层衬底等，本申请对此不作限制，实际中可以根据需要进行设置。例如，高Ge组分中含Ge晶格由于晶格失配问题无法直接生长在硅衬底上，因此在一些实施例中，可以选择生长SRB层作为衬底(即应变缓冲层衬底)。
上述含有Ge的顶部鳍片F1可以是含SiGe，GeSi，GeSn或Ge的单层或多层超晶格，实际中根据需要选择合适的超晶格材料、厚度、层数等。例如，在FinFET中，顶部鳍片F1可以是具有固定Ge组分的单层超晶格；在NSFET中，顶部鳍片F1可以包含牺牲层和沟道层交替生长的、含有Ge组分的多叠层超晶格；具体可以参考下文的相关描述。
可以理解的是，衬底作为用于制备集成电路或半导体器件的晶圆的部分，为防止最底层的寄生沟道导通，可以对衬底进行高掺杂，以抑制寄生沟道的形成；示意的，可以通过离子注入加退火或扩散等方式，在衬底中形成一定浓度和深度的离子分布。
在FinFET的制作工艺中，上述步骤01可以包括：参考图5中(a)所示，提供衬底01，并在衬底01上形成含有Ge的沟道层100。然后，参考图5中(b)所示，对沟道层100以及衬底01整体进行刻蚀形成鳍片结构F；其中，沟道层100形成鳍片结构F中的顶部鳍片F1，衬底01的上层部分形成鳍片结构F的底部鳍片F2。
可以理解的是，上述含有Ge的沟道层100的厚度定义顶部鳍片F1的高度，该沟道层100用于制备FinFET的沟道；示意的，该沟道层100的厚度可以为10nm～100nm。鳍片结构F高度是顶部鳍片F1和底部鳍片F2的高度之和。底部鳍片F2的高度决定了后续形成的浅沟槽隔离层STI的厚度(具体可以参考下文)。示意的，底部鳍片F2的高度可以为100nm～1000nm。
在NSFET的制作工艺中，上述步骤01可以包括：参考图6中(a)所示，提供衬底01，并在衬底01上形成含有Ge的半导体叠层200；其中，半导体叠层200包括依次交替设置的多个牺牲层1和多个沟道层2。然后，参考图6中(b)所示，对半导体叠层200以及衬底01整体进行刻蚀形成鳍片结构F；其中，半导体叠层200形成顶部鳍片F1，衬底01的上层部分形成底部鳍片F2。
可以理解的是，在NSFET的制作中，鳍片结构F的高度是顶部鳍片F1和底部鳍片F2的高度之和。半导体叠层200的厚度定义顶部鳍片F1的高度，底部鳍片F2的高度决定了后续形成的浅沟槽隔离层STI的厚度(具体可以参考下文)。示意的，底部鳍片F2的高度可以为50nm～1000nm。在NSFET中，鳍片结构F的宽度决定了纳米片的宽度，鳍片结构F的宽度可以为20nm～300nm。当然，在NWFET中，鳍片结构F的宽度决定了纳米线的直径，鳍片结构F的宽度可以为10nm～100nm。
另外，还可以理解的是，上述半导体叠层200中，多个牺牲层1分别位于多个沟道层2的下方，多个沟道层2用于制作NSFET的多个沟道，牺牲层1用来定义HKMG，牺牲层1不仅对沟道层2起一定的支撑作用，也需要在后续工艺中能够被选择性的去除以填充HKMG。在此情况下，牺牲层1的刻蚀需要对沟道层2具有高选择性的材料，同时需要为沟道层2提供应力。例如，可以选择设置牺牲层1与沟道层2中Ge的组分不同，牺牲层1中Ge组分可以高于沟道层2中的Ge组分。
此处应当理解的是，尽管牺牲层1在后续的制作工艺中被去除，但是在牺牲层1去除前，需要对浅沟槽隔离层STI进行退火，而在对浅沟槽隔离层STI退火过程中牺牲层1很容易被氧化，容易产生结构损失，由于牺牲层1的结构损失会对沟道层2轮廓产生影响，因此牺牲层1需要通过氧阻隔层进行保护，具体可以参考下文。
示意的，在一些可能实现的方式中，为了满足牺牲层1与沟道层2的刻蚀选择性，可以设置牺牲层1中Ge组分为x，沟道层2中Ge组分为y，x-y大于或等于0.2，y可以为0；例如，沟道层2为Si，牺牲层1为SiGe；又例如，沟道层2为SiGe，牺牲层1为GeSi或Ge；再例如，沟道层2为GeSn，牺牲层1为Ge。
本申请对于半导体叠层200中牺牲层1和沟道层2的层数、厚度、材料等不作限制，可以根据需要进行设置。通常牺牲层1和沟道层2的层数相同，且两者的厚度相近；例如，在一些实施例中，牺牲层1和沟道层2可以是3～7层，厚度为10nm～40nm。半导体叠层200的厚度取决于牺牲层1和沟道层2的厚度以及层数，其厚度可以约为60nm～600nm。
对于上述FinFET和NSFET中鳍片结构F的制作而言，实际中可以根据需要选择合适的工艺进行制作即可；例如，可以采用侧墙转移(spacer image transfer，SIT)，也可以采用光刻与刻蚀工艺。示意的，对于采用光刻与刻蚀工艺而言，光刻工艺可以采用极紫外(extreme ultra-violet)光刻，也可以采用自对准多重光刻。示意的，在一些实施例中，可以是通过刻蚀(如反应离子刻)把光刻胶的图形转移到硬掩膜层上；然后，再刻蚀超晶格结构及衬底形成鳍片结构F。其中，硬掩膜层可以采用氧化硅、氮化硅、氧化硅与氮化硅的复合层。在形成鳍片结构F后，鳍片结构F顶部的硬掩膜层可以暂时保留，无需额外去除。
步骤12、参考图5中(c)或图6中(c)，在鳍片结构F的表面形成氧阻隔层10。
示意的，在一些可能实现的方式中，上述步骤12可以包括：采用SiN、SiCN、SiCO、SiNO、SiCNO等材料中的至少一种，在鳍片结构F的表面形成氧阻隔层10。
上述氧阻隔层10的厚度可以根据实际情况调整，只要保证足够的氧阻隔能力且不对窄而细的鳍片结构F造成损坏即可。另外，还需要考虑后续形成的浅沟槽隔离层STI刻蚀或腐蚀对氧阻隔层10的选择性，在选择性较差时，可以适当增加氧阻隔层10的厚度。示意的，在一些可能实现的方式中，上述步骤12形成的氧阻隔层10的厚度可以为1nm～10nm；通过设置氧阻隔层10的厚度大于1nm，来保证氧阻隔层10的阻隔效果；通过设置氧阻隔层10的厚度小于10nm，避免氧阻隔层10的厚度过大而产生较大应力对鳍片结构F造成损伤。
为了保证氧阻隔层10具有较高的薄膜质量，在一些可能实现的方式中，通过上述步骤12可以采用低温的原子层沉积(atomic layer deposition，ALD)、化学气相沉积(chemical vapor deposition，CVD)、物理气相沉积(physical vapor deposition，PVD)等工艺淀积形成氧阻隔层10。
另外，步骤12中形成的氧阻隔层10覆盖鳍片结构F的表面，能够对鳍片结构F起到保护作用，在实际的制作工艺中，采用整层沉积的工艺，参考图5中(c)或图6中(c)所示，该氧阻隔层10在 覆盖鳍片结构F的表面的同时，可以延伸覆盖至衬底01的表面。
此处可以理解的是，基于氧阻隔层10的制作工艺，在制作氧阻隔层10时会覆盖在衬底01的表面，无需设置单独工艺对衬底01表面的部分进行去除，通常会保留覆盖在衬底01的表面的氧阻隔层10。另外，在衬底01中含有Ge元素的情况下，覆盖在衬底01的表面的氧阻隔层10同样有助于抑制衬底的Ge元素的扩散和氧化。
步骤13、参考图5中(d)或图6中(d)，在覆盖有氧阻隔层10的鳍片结构F的侧面采用过填充的方式形成浅沟槽隔离层STI。
示意的，在一些可能实现的方式中，上述步骤13可以包括：采用SiO2在覆盖有氧阻隔层10的鳍片结构F的侧面进行过填充，形成浅沟槽隔离层STI。
可以理解的是，步骤13采用过填充的方式在覆盖有氧阻隔层10的鳍片结构F侧面形成浅沟槽隔离层STI，浅沟槽隔离层STI的上表面会高于鳍片结构F的顶部，并包裹鳍片结构F的顶部；当然，该浅沟槽隔离层STI在后续工艺中需要进行回刻至一定深度(具体参考下文)。
上述浅沟槽隔离层STI制作可以包括多个工艺过程，例如，在一些可能实现的方式中，可以先淀积薄而质量高的衬垫层氧化层(如SiO2)，然后采用高深宽比工艺(high aspect retio precess，HARP)、旋转涂覆工艺(sprin on dielectric，SOD)或可流动式化学气相沉积工艺(flowable chemical vapor deposition，FCVD)等过填充厚的氧化层(如SiO2)，该过填充的氧化层高于鳍片结构F的顶部。然后，可以采用氩轰击或化学机械抛光(chemical mechanical polishing，CMP)等工艺对上述过填充的氧化层进行平坦化，停止在鳍片结构F的上方一定厚度内以预留一定的工艺窗口防止鳍片结构F损伤。当然，该平坦化的过程也可以在步骤14中的退火处理之后进行，本申请对此不作限制。
步骤14、对浅沟槽隔离层STI进行退火处理。
由于鳍片结构F的表面包覆有氧阻隔层10，因此在步骤14中对浅沟槽隔离层STI进行退火处理时，氧阻隔层10能够将鳍片结构F中的Ge元素与浅沟槽隔离层STI中的氧进行阻隔，使得浅沟槽隔离层STI中的氧无法与鳍片结构F中的Ge元素发生氧化反应，也就是说，对浅沟槽隔离层STI的高温退火过程不会导致含Ge的鳍片结构F发生损失和界面粗糙等问题，从而提高了鳍片结构F的热稳定性。
步骤15、参考图5中(e)、(f)以及图6中(e)、(f)所示，对退火后的浅沟槽隔离层STI进行回刻露出顶部鳍片F1，并去除覆盖在顶部鳍片F1表面的氧阻隔层10。
示意的，上述步骤15可以包括：参考图5中(e)以及图6中(e)所示，将退火后的浅沟槽隔离层STI进行回刻；其中，回刻处理可以是采用稀释的氢氟酸或缓冲氧化物刻蚀液(buffered oxide etch，BOE)。对于FinFET而言，通过回刻处理将浅沟槽隔离层STI刻蚀停止在沟道层的边界(即顶部鳍片与底部鳍片的交界位置)。对于NSFET而言，通过回刻处理将浅沟槽隔离层STI刻蚀停止在最下层的牺牲层1边界(即顶部鳍片与底部鳍片的交界位置)。这样一来，氧阻隔层10包覆的顶部鳍片F1(也即沟道区)就被暴露出来。然后，参考图5中(f)以及图6中(f)所示，对暴露的氧阻隔层10(也即包覆顶部鳍片F1的氧阻隔层10)进行刻蚀，以暴露出顶部鳍片F1；而覆盖在底部鳍片F2表面的氧阻隔层10嵌入在浅沟槽隔离层STI中，不被去除而保留下来。
当然，对于氧阻隔层10的去除而言，可以采用湿法刻蚀，也可以采用干法刻蚀，只要保证刻蚀对含Ge材料和SiO2具有较高选择比即可，保证侧面和边角的氧阻隔层10的去除，不对顶部鳍片F1和浅沟槽隔离层STI产生损伤即可。示意的，在一些可能实现的方式中，可以采用各向同性的干法刻蚀，来去除覆盖在顶部鳍片F1表面的氧阻隔层10。
当然，在去除覆盖在顶部鳍片F1表面的氧阻隔层10之后，可以进行后续相关的制作工序，如制作假栅、栅侧墙和内侧墙(对于NSFET)，外延生长源区和漏区，层间介质生长与平坦化，假栅去除，沟道释放(对于NSFET)，淀积HKMG，形成电接触等工序，本申请对此不作限制，实际中可以根据器件的类型进行对应的制作即可。示意的，对于FinFET而言，在后续制作过程中，通过替代假栅从而形成横向环绕顶部鳍片F1的栅极；对于NSFET而言，通过去除牺牲层1并在牺牲层1的位置形成假栅，然后通过替代假栅从而形成横向环绕多个沟道层(纳米片)的栅极。
综上所述，采用本实施例提供的制作方法，在制作浅沟槽隔离层STI之前先在鳍片结构F的表面覆盖氧阻隔层10，通过氧阻隔层10对鳍片结构F形成保护，然后再形成浅沟槽隔离层STI，这样一来，在对浅沟槽隔离层STI进行退火处理时，氧阻隔层10阻隔了鳍片结构F与浅沟槽隔离层STI直接接触， 从而能够防止鳍片结构F中发生Ge元素的扩散和氧化，提高了鳍片结构F的热稳定性，降低了鳍片结构F的结构损伤或缺陷问题，进而提高了器件结构的稳定性。当然，通过氧阻隔层10的设置还能够减小鳍片结构F的界面粗糙问题，进而提高了器件的载流子迁移率，增大了器件的有效电流，增加了器件的驱动能力。
此处需要说明的是，在采用本申请的制作方法形成场效应晶体管中，对于覆盖在底部鳍片F2表面的氧阻隔层10而言，该氧阻隔层10可以是覆盖底部鳍片F2的全部侧面，也可以是部分侧面；当然，为了更大程度的降低了底部鳍片F2的结构损伤或缺陷问题，通常可以设置氧阻隔层10对底部鳍片F2的整个侧面进行覆盖。
实施例二
本实施例还提供另一种场效应晶体管的制作方法，如图7所示，该制作可以包括：
步骤21、参考图8中(a)、(b)以及图9中(a)、(b)所示，提供衬底01，并在衬底01上形成鳍片结构F；其中，鳍片结构F包括顶部鳍片F1和底部鳍片F2，顶部鳍片F1位于底部鳍片F2远离衬底01的一侧，且顶部鳍片F1中含有Ge。
步骤21与前述实施例一中步骤11的制作基本相同，关于步骤21的相关说明可以参考前述步骤11中对应的部分，此处不在赘述。
步骤22、参考图8中(c)、(d)以及图9中(c)、(d)所示，在鳍片结构F的侧面采用过填充的方式形成浅沟槽隔离层STI，并对浅沟槽隔离层STI进行回刻露出顶部鳍片。
示意的，在一些可能实现的方式中，上述步骤11可以包括：采用SiO2在覆盖有氧阻隔层10的鳍片结构F的侧面进行过填充，形成浅沟槽隔离层STI；然后对浅沟槽隔离层STI进行回刻露出顶部鳍片F1。
关于步骤22中采用过填充的方式形成浅沟槽隔离层STI，可以参考前述步骤13中对应的说明，关于对浅沟槽隔离层STI进行回刻露出顶部鳍片F1的相关内容，可以对应参考前述步骤15中对应的说明，此处不再赘述。
步骤23、参考图8中(e)以及图9中(e)所示，在露出的顶部鳍片F1的表面形成氧阻隔层10。
示意的，在一些可能实现的方式中，上述步骤23可以包括：采用SiN、SiCN、SiCO、SiNO、SiCNO等材料中的至少一种，在顶部鳍片F1的表面形成氧阻隔层10。当然，氧阻隔层10可以延伸覆盖至浅沟槽隔离层STI的表面。
关于氧阻隔层10的其他设置，如厚度、制作方法等，可以参考前述步骤12中对应的说明，此处不再赘述。
步骤24、对浅沟槽隔离层STI进行退火处理。
由于顶部鳍片F1的表面包覆有氧阻隔层10，因此通过步骤24对浅沟槽隔离层STI进行退火处理时，氧阻隔层10能够将顶部鳍片F1中的Ge元素与浅沟槽隔离层STI中的氧进行阻隔，使得浅沟槽隔离层STI中的氧无法与顶部鳍片F1中的Ge元素发生氧化反应，也就是说，对浅沟槽隔离层STI的高温退火过程不会导致含Ge的顶部鳍片F1发生损失和界面粗糙等问题，从而提高了鳍片结构F的热稳定性。
步骤25、参考图8中(f)以及图9中(f)所示，去除覆盖在顶部鳍片F1表面的氧阻隔层10。
关于对氧阻隔层10的去除可以参考前述步骤15中对应的相关说明，此处不再赘述。
综上所述，该实施例二的制作方法，先制作浅沟槽隔离层STI，并通过对浅沟槽隔离层STI进行回刻漏出顶部鳍片F1；然后在顶部鳍片F1的表面形成氧阻隔层10，通过氧阻隔层10实现对顶部鳍片F1的保护，从而使得在后续对浅沟槽隔离层STI进行退火处理时，能够防止顶部鳍片F1中的Ge元素的扩散和氧化，降低了鳍片结构的结构损伤以及缺陷问题，提高了鳍片结构的热稳定性，进而提高了器件结构的稳定性。
关于上述实施例二中的其他相关说明，可以对应的参考前述实施例一对应的部分，此处不再赘述。
应理解，在本申请的各实施例中，上述各步骤序号的大小并不意味着制作顺序的先后，各制作过程的先后应以其实际的功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之 内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种半导体器件，其特征在于，包括：
    衬底；
    位于所述衬底上的浅沟槽隔离层；
    位于所述衬底上的鳍片结构，所述鳍片结构包括底部鳍片和顶部鳍片，所述浅沟槽隔离层填充在所述底部鳍片的侧面，所述顶部鳍片凸出于所述浅沟槽隔离层；
    氧阻隔层，所述氧阻隔层位于所述底部鳍片与所述浅沟槽隔离层之间，且所述氧阻隔层覆盖所述底部鳍片的表面。
  2. 根据权利要求1所述的半导体器件，其特征在于，所述氧阻隔层延伸覆盖至所述衬底的表面。
  3. 根据权利要求1或2所述的半导体器件，其特征在于，所述浅沟槽隔离层中包括二氧化硅。
  4. 根据权利要求1-3任一项所述的半导体器件，其特征在于，所述氧阻隔层中包括SiN、SiCN、SiCO、SiNO、SiCNO中的至少一种。
  5. 根据权利要求1-4任一项所述的半导体器件，其特征在于，所述氧阻隔层的厚度为1nm～10nm。
  6. 根据权利要求1-5任一项所述的半导体器件，其特征在于，
    所述半导体器件为鳍式场效应晶体管；
    所述顶部鳍片中包括Ge。
  7. 根据权利要求1-5任一项所述的半导体器件，其特征在于，
    所述半导体器件为环栅场效应晶体管。
  8. 一种半导体器件的制作方法，其特征在于，包括：
    提供衬底，并在所述衬底上形成鳍片结构；其中，所述鳍片结构包括顶部鳍片和底部鳍片，所述顶部鳍片位于底部鳍片远离所述衬底的一侧，且所述顶部鳍片中含有Ge；
    在所述鳍片结构的表面形成氧阻隔层；
    在覆盖有所述氧阻隔层的所述鳍片结构的侧面采用过填充的方式形成浅沟槽隔离层；
    对所述浅沟槽隔离层进行退火处理；
    对退火后的所述浅沟槽隔离层进行回刻露出所述顶部鳍片，并去除覆盖在所述顶部鳍片表面的所述氧阻隔层。
  9. 根据权利要求8所述的半导体器件的制作方法，其特征在于，包括：
    所述提供衬底，并在所述衬底上形成鳍片结构；其中，所述鳍片结构包括顶部鳍片和底部鳍片，所述顶部鳍片位于底部鳍片远离所述衬底的一侧，且所述顶部鳍片中含有Ge，包括：
    提供衬底，并在所述衬底上形成含有Ge的沟道层；
    对所述沟道层以及所述衬底整体进行刻蚀，所述沟道层形成所述顶部鳍片，所述衬底的上层部分形成所述底部鳍片。
  10. 根据权利要求8所述的半导体器件的制作方法，其特征在于，
    所述提供衬底，并在所述衬底上形成鳍片结构；其中，所述鳍片结构包括顶部鳍片和底部鳍片，所述顶部鳍片位于底部鳍片远离所述衬底的一侧，且所述顶部鳍片中含有Ge，包括：
    提供衬底，并在所述衬底上形成含有Ge的半导体叠层；其中，所述半导体叠层包括依次交替设置的多个牺牲层和多个沟道层；
    对所述半导体叠层以及所述衬底整体进行刻蚀，所述半导体叠层形成所述顶部鳍片，所述衬底的上层部分形成所述底部鳍片。
  11. 根据权利要求8-10任一项所述的半导体器件的制作方法，其特征在于，
    所述在所述鳍片结构的表面形成氧阻隔层包括：在所述鳍片结构的表面，采用SiN、SiCN、SiCO、SiNO、SiCNO中的至少一种材料形成氧阻隔层。
  12. 根据权利要求8-11任一项所述的半导体器件的制作方法，其特征在于，
    所述在覆盖有所述氧阻隔层的所述鳍片结构的侧面采用过填充的方式形成浅沟槽隔离层，包括：
    采用SiO2在覆盖有所述氧阻隔层的所述鳍片结构的侧面进行过填充，形成浅沟槽隔离层。
  13. 一种芯片，其特征在于，包括控制器以及如权利要求1-7任一项所述的半导体器件，所述半 导体器件与所述控制器电连接。
  14. 一种芯片，其特征在于，包括控制器以及半导体器件，所述半导体器件与所述控制器电连接；其中，所述半导体器件的制作方法包括：
    提供衬底，并在所述衬底上形成鳍片结构；其中，所述鳍片结构包括顶部鳍片和底部鳍片，所述顶部鳍片位于底部鳍片远离所述衬底的一侧，且所述顶部鳍片中含有Ge；
    在所述鳍片结构的侧面采用过填充的方式形成浅沟槽隔离层，并对所述浅沟槽隔离层进行回刻露出所述顶部鳍片；
    在露出的所述顶部鳍片的表面形成氧阻隔层；
    对所述浅沟槽隔离层进行退火处理；
    去除覆盖在所述顶部鳍片表面的所述氧阻隔层。
  15. 一种电子设备，其特征在于，包括印刷线路板以及如权利要求13或14所述的芯片，所述芯片与所述印刷线路板电连接。
PCT/CN2023/104504 2022-09-01 2023-06-30 半导体器件及其制作方法、芯片、电子设备 WO2024045870A1 (zh)

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