WO2021190295A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

Info

Publication number
WO2021190295A1
WO2021190295A1 PCT/CN2021/079667 CN2021079667W WO2021190295A1 WO 2021190295 A1 WO2021190295 A1 WO 2021190295A1 CN 2021079667 W CN2021079667 W CN 2021079667W WO 2021190295 A1 WO2021190295 A1 WO 2021190295A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
trench
source region
width
drain region
Prior art date
Application number
PCT/CN2021/079667
Other languages
English (en)
French (fr)
Inventor
尤康
白杰
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/386,474 priority Critical patent/US11869952B2/en
Publication of WO2021190295A1 publication Critical patent/WO2021190295A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Definitions

  • the present invention relates to the field of semiconductor technology, in particular to a semiconductor structure and a method of forming the same.
  • the limitation of the length of the active region causes the gate structure to become smaller and smaller, making the fabrication of transistors more difficult.
  • the trench width of the buried gate is getting narrower and the aspect ratio of the trench is getting larger and larger, which limits the material filling when forming the gate structure, and the size of the gate structure is reduced, making the gate structure
  • the resistance increases, reducing the electrical performance.
  • the technical problem to be solved by the present invention is to reduce the manufacturing difficulty of the gate structure when the size of the active area is fixed, and to improve the electrical performance of the gate structure.
  • the present invention provides a method for forming a semiconductor structure, including:
  • At least one trench is formed in the active region, and the trench at least divides the active region into a source region located on one side of the trench and a drain region located on the other side of the trench;
  • a raised source region and a raised drain region are formed on the source region and the drain region, respectively.
  • a selective epitaxy process is used to form the elevated source region and the elevated drain region.
  • the method before the step of forming the elevated source region and the elevated drain region by a selective epitaxy process, the method further includes:
  • An in-situ cleaning process is used to clean the surface of the source region and the drain region.
  • the method further includes: forming a gate structure in the trench, and the upper surface of the gate structure is flush with the upper surface of the active region.
  • the method further includes: forming a gate structure in the trench, and forming a barrier layer on the gate structure.
  • the formation process of the elevated source region and the elevated drain region includes:
  • a raised source region and a raised drain region are formed in the raised source region opening and the raised drain region opening.
  • the present invention also provides a semiconductor structure, including:
  • a substrate with an active area on the substrate A substrate with an active area on the substrate
  • At least one trench located in the active region the trench at least dividing the active region into a source region located on one side of the trench and a drain region located on the other side of the trench;
  • the width of the top of the elevated source region is greater than the width of the bottom of the elevated source region, and the width of the top of the elevated drain region is greater than the width of the bottom of the elevated drain region.
  • the opening size of the trench is larger than the width of the bottom of the raised source region or the width of the bottom of the raised drain region.
  • the width of the bottom of the elevated source region is the same as the width of the top of the source region, and the width of the bottom of the elevated drain region is the same as the width of the top of the drain region.
  • the two trenches are located in the same active area; the size range of the active area is 20nm-145nm; the width range of the trenches is 5nm-25nm, and the depth range of the trenches is 10nm- 30nm.
  • the aspect ratio of the groove is less than 3:1.
  • the thickness range of the elevated source region or the elevated drain region is 5 nm-100 nm.
  • it further includes: a gate structure located in the trench, and the upper surface of the gate structure is flush with the upper surface of the active region.
  • it further includes: a gate structure located in the trench; a barrier layer, the barrier layer is located above the gate structure, and the upper surface of the barrier layer is aligned with the upper surface of the active region flat.
  • the thickness of the barrier layer ranges from 1 nm to 10 nm, or the thickness of the barrier layer is 1/10 to 1/5 of the depth of the trench.
  • an active region is formed on the substrate; at least one trench is formed in the active region, and the trench at least divides the active area into one side of the trench
  • a source region and a drain region located on the other side of the trench are formed on the source region and the drain region, respectively.
  • an elevated source region and an elevated drain region are formed on the source region and the drain region to draw out the electrical connection points of the source region and the drain region.
  • the width of the trench can be increased, the depth is reduced, and the aspect ratio is reduced, so that when the size of the active area is constant, the difficulty of forming the gate structure in the trench is reduced. And the electrical performance of the formed gate structure is improved.
  • the width of the bottom of the elevated source region is the same as the width of the top of the source region
  • the width of the bottom of the elevated drain region is the same as the width of the top of the drain region
  • the width of the top of the elevated source region is greater than Raise the width of the bottom of the source region
  • the width of the top of the raised drain region is greater than the width of the bottom of the raised drain region, so when the size of the active region is constant, when the size of the trench formed in the active region increases
  • the size of the source region and the drain region formed in the corresponding active region is reduced, the size of the top of the raised source region and the raised drain region is increased, so by raising the source region and the drain region, it can still be guaranteed
  • the electrical connection performance when the size of the source and drain regions is reduced, while ensuring that the gate material is easily filled when the gate structure is formed in the trench, reducing the resistance of the formed gate structure, reducing the difficulty of making the gate structure and improving the gate
  • the electrical properties of the structure is reduced, while ensuring
  • the formation of the elevated source region and the elevated drain region adopts a selective epitaxy process, so that the width of the top of the elevated source region can be simply formed to be greater than the width of the bottom of the elevated source region, and the top of the elevated drain region is formed.
  • the width is greater than the width of the bottom of the raised drain region, and the accuracy of the positions and dimensions of the raised source region and the raised drain region formed are improved.
  • a barrier layer is formed on the gate structure, and the barrier layer can protect the gate structure and prevent subsequent processes from damaging the gate structure.
  • the semiconductor structure of the present invention includes: a substrate with an active area on the substrate; at least one trench located in the active area, and the trench at least divides the active area into a trench.
  • a source region on the side and a drain region on the other side of the trench; the source region and the drain region have a raised source region and a raised drain region respectively.
  • FIGS. 1-10 are structural schematic diagrams of the formation process of a semiconductor structure according to an embodiment of the present invention.
  • the present invention provides a semiconductor structure and a method for forming the same.
  • the method for forming the semiconductor structure includes: forming an active region on the substrate; forming at least one trench in the active region, and the trench The groove divides the active into at least a source region on one side of the trench and a drain region on the other side of the trench; a raised source region and a raised drain region are formed on the source region and the drain region, respectively .
  • the present invention by forming an elevated source region and an elevated drain region on the source region and the drain region, respectively, the aspect ratio of the formed trench can be reduced, and the manufacturing difficulty of the semiconductor structure can be reduced.
  • FIGS. 1-10 are structural schematic diagrams of the formation process of a semiconductor structure according to an embodiment of the present invention.
  • a substrate 201 is provided, and an active region 202 is formed on the substrate 201.
  • the material of the substrate 201 may be silicon (Si), germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI) or germanium-on-insulator (GOI); or It can also be other materials, such as group III-V compounds such as gallium arsenide.
  • the material of the substrate 201 is silicon.
  • the substrate is doped with certain impurity ions as required, and the impurity ions may be N-type impurity ions or P-type impurity ions.
  • the doping includes well region doping and/or source and drain region doping.
  • the number of the active regions 202 is several (more than or equal to 2), and adjacent active regions 202 are separated by an isolation layer 203.
  • the process of forming the active region 202 is: forming a first mask layer (not shown in the figure) on the substrate 201, and the first mask layer has a plurality of first mask layers.
  • a mask opening, the first mask opening divides the first mask layer into a plurality of strip-shaped masks;
  • a second mask is formed on the strip-shaped mask and in the first mask opening Layer, forming a second mask opening in the second mask layer on the strip mask, and using the second mask opening to divide the strip mask into a number of discrete active Area mask, using the active area mask to etch the substrate 201 to form an active area 202.
  • the active region 202 and the semiconductor substrate 201 are separated by a dotted line.
  • the active region 202 may be formed by an epitaxial process.
  • At least one trench 204 is formed in the active region 202.
  • the trench 204 at least divides the active region into a source region 205 located on one side of the trench 204 and a source region located on the other side of the trench 204.
  • the drain area 206 is formed in the active region 202.
  • the active region 202 By etching the active region 202, at least one trench is formed in the active region 202, and a gate structure is subsequently formed in the trench 204.
  • the first isolation layer between the active regions 202 may be etched at the same time, and trenches are formed in the active region 202 and the first isolation layer.
  • the number of trenches 204 in each active region 202 is one.
  • the trenches 204 divide the active region into a source region 205 located on the side of the trench 204 and a source region 205 located on the side of the trench 204.
  • the opening size (width or diameter) of the trench 204 is larger than the width of the raised bottom of the source region formed on the source region 205 or the raised bottom formed on the drain region 206 subsequently The width of the bottom of the drain area.
  • the width of the trench 204 ranges from 1 nm to 50 nm, and specifically may be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, and the depth range of the trench 204 is 1 nm. -80nm, specifically 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm.
  • the size of the active region 202 ranges from 10 nm to 70 nm
  • the width of the trench 204 ranges from 5 nm to 25 nm
  • the depth of the trench 204 ranges from 10 nm to 30 nm, so that the width of the trench can be It is as wide as possible, and the aspect ratio can be as small as possible, which can further reduce the difficulty of filling the gate material later, and further reduce the resistance of the gate structure.
  • the width of the trench 204 ranges from 5 nm to 25 nm
  • the aspect ratio of the trench 204 is less than 3:1, for example, the aspect ratio is 2.5:1, 2:1, 1.5:1, etc.
  • the size of the active region 202, the width of the trench 204, the width of the source region 205, and the width of the drain region 206 all refer to the active region 202, the trench The maximum dimensions of the trench 204, the source region 205, and the drain region 206 along the x-axis direction (as shown in FIG. 2).
  • the x-axis direction may be the extension direction of the active region 202.
  • the number of trenches 204 formed in each active region 202 is two, and the two trenches 204 divide the active region 202 into two trenches 204.
  • the source region 205 in the middle and the two drain regions 206 located on both sides of the two trenches 204 respectively, a gate structure can be formed in the two trenches 204 in each active region 202 subsequently.
  • the middle part of the active region between the two trenches 204 is the drain region, and the two ends of the active region on both sides of the two trenches are the source region.
  • the size of the active region 202 is in the range of 20nm-145nm
  • the width of the trench 204 is in the range of 5nm-25nm
  • the depth of the trench 204 is in the range of 10nm-30nm.
  • the width can be as wide as possible, and the aspect ratio can be as small as possible, which can further reduce the difficulty of filling the gate material later, and further reduce the resistance of the gate structure.
  • the subsequent formation of lift on the source and drain regions The high source region and the elevated drain region can make the electrical connection performance of the source region and the drain region not affected as much as possible.
  • the width of the trench 204 ranges from 5 nm to 20 nm
  • the aspect ratio of the trench 204 is less than 3:1, for example, the aspect ratio is 2.5:1, 2:1, 1.5:1, etc.
  • a gate structure 209 is formed in the trench.
  • FIG. 4 there is a trench in the active region 202, and a gate structure 209 is formed in the trench.
  • a gate structure 209 is formed in both trenches. .
  • the gate structure 209 includes a gate dielectric layer 207 located on the sidewall and bottom surface of the trench, and a conductive electrode 208 located on the gate dielectric layer 207 to fill the trench.
  • the gate structure 209 may include a gate dielectric layer at the bottom of the trench and the surface of the sidewall of the trench, a transition layer on the gate dielectric layer, and a transition layer on the transition layer. A conductive electrode filling the trench.
  • the material of the gate dielectric layer may be silicon oxide
  • the material of the transition layer may be TiN
  • the material of the conductive electrode 208 may be W or other suitable metal materials.
  • the conductive electrode 208 may also be a composite electrode, for example, a double-layer electrode made of W or other metal at the lower part and polysilicon at the upper part. The composite electrode can improve the device performance of the transistor.
  • the formation process of the gate structure 209 includes: forming a silicon oxide layer on the sidewall and bottom surface of the word line groove, specifically, the silicon oxide layer may be formed by a thermal oxidation process; A transition layer is formed on the silicon oxide layer; a metal layer formed on the transition layer; the metal layer and the transition layer higher than the surface of the active region 202 are removed by a planarization or etch-back process to form a gate structure 209.
  • the upper surface of the gate structure 209 is flush with the upper surface of the active region 202.
  • FIG. 6 is performed on the basis of FIG. 4. Before forming the elevated source region and the elevated drain region, a barrier layer 210 is formed on the surface (or above) of the gate structure 209.
  • the active region 202 has a trench, and a barrier layer 210 is formed on the surface of the gate structure 209 in the trench.
  • FIG. 7 is performed on the basis of FIG. 5.
  • a barrier layer 210 is formed on the surface of the gate structure.
  • the barrier layer 210 protects the gate structure 209 and prevents the gate structure 209 from being damaged by subsequent processes.
  • the material of the barrier layer 210 is different from the material of the substrate 201.
  • the material of the barrier layer 210 may be one or more of silicon nitride, silicon oxide, or silicon oxynitride.
  • the barrier layer 210 should be as thin as possible on the premise of ensuring the protection effect.
  • the thickness of the barrier layer 210 ranges from 1 nm to 10 nm, or the barrier layer The thickness of 210 is 1/10-1/5 of the depth of the groove.
  • the formation process of the barrier layer 210 may include: etching back to remove a part of the thickness of the conductive electrode 208 in the gate structure 209; forming on the surface of the remaining conductive electrode 208 and the surface of the active region 202
  • a barrier material layer, the forming process of the barrier material layer may be chemical vapor deposition; planarization removes the barrier material layer higher than the surface of the active region 202, and forms a barrier layer 210 on the surface of the remaining conductive electrode 208, and the flatness
  • the conversion can be a chemical mechanical polishing process.
  • the barrier material layer 210 may also remain on the surface of the active region 202 to protect the active region 202.
  • a raised source region 211 and a raised drain region 212 are formed on the source region 205 and the drain region 206, respectively.
  • the electrical connection point of the source region 205 and the drain region 206 is led out through the elevated source region 211 and the elevated drain region 212, and the top of the elevated source region 211 and the elevated drain region 212 are used to connect with the connection structure ( For example, a conductive plug) is electrically connected.
  • the width of the bottom of the raised source region 211 is the same as the width of the top of the source region 205
  • the width of the bottom of the raised drain region 212 is the same as the width of the drain region 206.
  • the width of the top is the same, the width of the top of the elevated source region 211 is greater than the width of the bottom of the elevated source region 211, the width of the top of the elevated drain region 212 is greater than the width of the bottom of the elevated drain region, so in the active region 202 In the case of a certain size, when the size of the trench formed in the active region 202 increases, and the size of the source region 205 and the drain region 206 formed in the corresponding active region decreases, the source region and the drain region 206 are raised.
  • the size of the top of the drain region is increased, so by raising the source region and the drain region, the electrical connection performance when the size of the source region 205 and the drain region 206 is reduced can still be ensured, and at the same time, the gate structure can be ensured when the gate structure is formed in the trench.
  • the material is easy to fill, reducing the resistance of the formed gate structure.
  • the active region 202 has a trench, a source region 205, and a drain region 206.
  • a raised source is correspondingly formed on the surface of the source region 205 and the drain region 206. Area 211 and elevated drain area 212.
  • FIG. 9 is performed on the basis of FIG. 7.
  • a raised source region 211 and a raised drain region 212 are formed on the surface of one source region 205 and two drain regions in the active region 202 correspondingly.
  • the material of the raised source region 211 and the raised drain region 212 is the same as that of the substrate 201, the width of the bottom of the raised source region 211 is the same as the width of the top of the source region 205, and the The width of the bottom of the raised drain region 212 is the same as the width of the top of the drain region 206.
  • the elevated source region 211 and the elevated drain region 212 can be formed by a selective epitaxy process, so that the width at the top of the elevated source region 211 can be simply made larger than the width at the bottom of the elevated source region 211 to form an elevated drain.
  • the width of the top of the region 212 is greater than the width of the bottom of the raised drain region, and the formed raised source region 211 and the raised drain region 212 position accuracy and dimensional accuracy are improved.
  • the material of the substrate, the elevated source region and the elevated drain region is silicon.
  • the method before the step of forming the elevated source region 211 and the elevated drain region 212 by using a selective epitaxy process, the method further includes: cleaning the source region 205 and the source region 205 and the The surface of the drain region 206 is used to remove the oxide layer or contaminants on the surface of the source region 205 and the drain region 206 to improve the quality of the raised source region 211 and the raised drain region 212 formed.
  • the thickness of the raised source region 211 or the raised drain region 212 formed is in the range of 5 nm-100 nm.
  • a selective epitaxy process is directly used to form a raised source region 211 and a raised drain region 212 on the source region 205 and the drain region 206, respectively.
  • the formation process of the raised source region 211 and the raised drain region 212 includes: forming a cover layer on the active region 211, and forming the raised source region opening and the raised area in the cover layer.
  • the drain region opening, the elevated source region opening and the elevated drain region opening expose the active region 211, and the epitaxial process or other deposition is used in the elevated source region opening and the elevated drain region opening.
  • the process forms the raised source region 211 and the raised drain region 212 to improve the formation quality of the raised source region 211 and the raised drain region 212.
  • FIG. 10 is performed on the basis of FIG.
  • the dielectric layer 213 is used to raise the isolation between the source region 211 and the drain region 212.
  • the material of the dielectric layer 213 may be silicon nitride or silicon oxide.
  • it further includes: forming a bit line connected to the elevated source region 211, and forming a capacitor connected to the elevated drain region 212.
  • the bit line and the capacitor may be connected to the elevated source region 211 and the elevated drain region 212 through corresponding conductive plugs, respectively.
  • each active region has one source region and two drain regions
  • one raised source region and two raised drain regions are formed correspondingly
  • the method further includes forming the same source region and two drain regions.
  • the bit line connected to the region and two capacitors respectively connected to the two elevated drain regions are formed.
  • FIG. 9 Another embodiment of the present invention also provides a semiconductor structure. Referring to FIG. 9, it includes:
  • the drain region 212 is raised to be located on the drain region 206.
  • the width of the top of the elevated source region 211 is greater than the width of the bottom of the elevated source region 211
  • the width of the top of the elevated drain region 212 is greater than the width of the bottom of the elevated drain region 212
  • the width of the bottom of the source region 211 is the same as the width of the top of the source region 205
  • the width of the bottom of the raised drain region 212 is the same as the width of the top of the drain region 206.
  • the elevated source region 211 and the elevated drain region 212 are formed by a selective epitaxy process.
  • the material of the raised source region 211 and the raised drain region 212 is the same as that of the substrate 201.
  • the thickness of the raised source region 211 or the raised drain region 212 ranges from 5 nm to 100 nm.
  • the number of trenches formed in each active region 202 is two, and the two trenches divide the active region 202 into a source region located between the two trenches. 205 and the two drain regions 206 on both sides of the two trenches, the source region 205 in the middle has a raised source region 211, and the two drain regions 206 have a raised drain region 212 respectively.
  • the size range of the active region 202 is 20 nm-145 nm
  • the width range of the trench 204 is 5 nm-25 nm
  • the depth range of the trench 204 is 10 nm-30 nm.
  • the aspect ratio of the trench 204 is less than 3:1, for example, the aspect ratio is 2.5:1, 2:1, 1.5:1, etc.
  • the number of trenches formed in each active region 202 is one, and one trench divides the active region 202 into a source region 205 located on the side of the trench and a source region 205 located on one side of the trench.
  • the one source region 205 has a raised source region 211
  • the one drain region 206 has a raised drain region 212.
  • the size range of the active region 202 is 10 nm-70 nm
  • the width range of the trench 204 is 5 nm-25 nm
  • the depth range of the trench 204 is 10 nm-30 nm.
  • the aspect ratio of the trench 204 is less than 3:1, for example, the aspect ratio is 2.5:1, 2:1, 1.5:1, etc.
  • It also includes a gate structure 209 located in the trench, and the upper surface of the gate structure 209 is flush with the upper surface of the active region 202.
  • the upper surface of the gate structure 209 and the upper surface of the active region 202 are absolutely flush, and there is always a process deviation, as long as the upper surface of the gate structure 209 and It is sufficient that the upper surface of the active region 202 is substantially flush.
  • the barrier layer 210 further includes a barrier layer 210, the barrier layer 210 is located above the gate structure 209, and the upper surface of the barrier layer 210 is flush with the upper surface of the active region 202.
  • the barrier layer 210 should be as thin as possible on the premise of ensuring the protection effect.
  • the thickness of the barrier layer 210 ranges from 1 nm to 10 nm, or the barrier layer The thickness of 210 is 1/10-1/5 of the depth of the groove.
  • the barrier material layer 210 may also remain on the surface of the active region 202 to protect the active region 202.
  • it further includes: a bit line connected to the elevated source region 211 and a capacitor connected to the elevated drain region 212.
  • the bit line and the capacitor may be connected to the elevated source region 211 and the elevated drain region 212 through corresponding conductive plugs, respectively.
  • each active region has one source region and two drain regions
  • one raised source region and two raised drain regions are formed correspondingly, and it also includes, and the one raised source region The connected bit line and two capacitors respectively connected to the two elevated drain regions.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种半导体结构及其形成方法，所述形成方法包括，在衬底上形成有源区；在所述有源区中形成至少一个沟槽，所述沟槽至少将所述有源区分为位于沟槽一侧的源区和位于沟槽另一侧的漏区；在所述源区和所述漏区上分别形成抬高源区和抬高漏区。因而在有源区的尺寸一定的情况下，在前述形成沟槽时，可以使得沟槽的宽度增大，深度减小，深宽比减小，从而在有源区尺寸一定的情况下，使得在沟槽中形成栅极结构时栅极材料容易填充，并且形成的栅极结构电阻较小，同时使得所述源区和漏区的电学连接性能不会受到影响。

Description

半导体结构及其形成方法
相关申请引用说明
本申请要求于2020年03月27日递交的中国专利申请号202010230470.2，申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
随着晶体管尺寸的不断减小，有源区的长度的限制导致栅极结构也变的越来越小，使得晶体管的制作变得更加困难。例如，埋伏栅极的沟槽宽度越来越窄，沟槽的深宽比越来越大，限制了形成栅极结构时的材料填充，并且栅极结构的尺寸的减小，使得栅极结构的电阻增大，降低了电学性能。
发明内容
本发明所要解决的技术问题是在有源区尺寸一定的情况下降低栅极结构的制作难度，并使形成栅极结构的电学性能得到改善。
为此，本发明提供了一种半导体结构的形成方法，包括：
提供衬底；
在所述衬底上形成有源区；
在所述有源区中形成至少一个沟槽，所述沟槽至少将所述有源区分为位于沟槽一侧的源区和位于沟槽另一侧的漏区；
在所述源区和所述漏区上分别形成抬高源区和抬高漏区。
可选的，采用选择性外延工艺形成所述抬高源区和所述抬高漏区。
可选的，所述采用选择性外延工艺形成所述抬高源区和所述抬高漏区的步骤之前，还包括：
采用原位清洁工艺清洁所述源区和所述漏区表面。
可选的，还包括：在所述沟槽中形成栅极结构，所述栅极结构的上表面和所述有源区的上表面齐平。
可选的，还包括：在所述沟槽中形成栅极结构，在所述栅极结构上形成阻挡层。
可选的，所述抬高源区和所述抬高漏区的形成过程，包括：
在所述有源区上形成覆盖层；
在所述覆盖层中形成抬高源区开口和抬高漏区开口，所述抬高源区开口和所述抬高漏区开口暴露出所述有源区；
在所述抬高源区开口和所述抬高漏区开口中形成抬高源区和抬高漏区。
本发明还提供了一种半导体结构，包括：
衬底，所述衬底上具有有源区；
位于所述有源区中的至少一个沟槽，所述沟槽至少将所述有源区分为位于沟槽一侧的源区和位于沟槽另一侧的漏区；
抬高源区，位于所述源区上；
抬高漏区，位于所述漏区上。
可选的，所述抬高源区顶部的宽度大于所述抬高源区底部的宽度，所述抬高漏区顶部的宽度大于所述抬高漏区底部的宽度。
可选的，所述沟槽的开口尺寸大于所述抬高源区底部的宽度或所述抬高漏区底部的宽度。
可选的，所述抬高源区底部的宽度与所述源区顶部的宽度相同，所述抬高漏区底部的宽度与所述漏区顶部的宽度相同。
可选的，两个沟槽位于同一有源区中；所述有源区的尺寸范围为20nm-145nm；所述沟槽的宽度范围为5nm-25nm，所述沟槽的深度范围为10nm-30nm。
可选的，所述沟槽的深宽比小于3：1。
可选的，所述抬高源区或所述抬高漏区的厚度范围为5nm-100nm。
可选的，还包括：栅极结构，位于所述沟槽中，所述栅极结构的上表面和所述有源区的上表面齐平。
可选的，还包括：栅极结构，位于所述沟槽中；阻挡层，所述阻挡层位于所述栅极结构上方，所述阻挡层的上表面与所述有源区的上表面齐平。
可选的，所述阻挡层的厚度范围为1nm-10nm，或者所述阻挡层的厚度为所述沟槽的深度的1/10-1/5。
与现有技术相比，本发明技术方案具有以下优点：
本发明的半导体结构的形成方法，在所述衬底上形成有源区；在所述有源区中形成至少一个沟槽，所述沟槽至少将所述有源区分为位于沟槽一侧的源区和位于沟槽另一侧的漏区；在所述源区和所述漏区上分别形成抬高源区和抬高漏区。本发明通过在所述源区和所述漏区上分别形成抬高源区和抬高漏区将源区和漏区的电连接点引出，因而在有源区的尺寸一定的情况下，在前述形成沟槽时，可以使得沟槽的宽度增大，深度减小，深宽比减小，从而在有源区尺寸一定的情况下，使得在沟槽中形成栅极结构的制作难度降低，并且形成的栅极结构的电学性能得到改善。
进一步，所述抬高源区底部的宽度与所述源区顶部的宽度相同，所述抬高漏区底部的宽度与所述漏区顶部的宽度相同，所述抬高源区顶部的宽度大于抬高源区底部的宽度，所述抬高漏区顶部的宽度大于抬高漏区底部的宽度，因而在有源区尺寸一定的情况下，当在有源区中形成的沟槽的尺寸增大，相应的有源区中形成的源区和漏区的尺寸减小时，由于抬高源区和抬高漏区顶部的尺寸增大，因而通过抬高源区和抬高漏区仍能保证源区和漏区尺寸减小时的电学连接性能，同时保证在沟槽中形成栅极结构时栅极材料容易填充，减小形成的栅极结构电阻，降低栅极结构的制作难度并且改善栅极结构的电学性能。
进一步，形成所述抬高源区和抬高漏区采用选择性外延工艺，从而能简便的使得形成的抬高源区顶部的宽度大于抬高源区底部的宽度，形成抬高漏区顶部的宽度大于抬高漏区底部的宽度，并且提高形成的抬高源区和抬高漏区位置的精度和尺寸的精度。
进一步，在所述栅极结构上形成阻挡层，所述阻挡层可以对所述栅极结构起保护作用，防止后续工艺对所述栅极结构造成损害。
本发明的半导体结构，包括：衬底，所述衬底上具有有源区；位于所述有源区中的至少一个沟槽，所述沟槽至少将所述有源区分为位于沟槽一侧的源区 和位于沟槽另一侧的漏区；所述源区和所述漏区上分别具有抬高源区和抬高漏区。在有源区的尺寸一定的情况下，可以减少栅极结构的制作难度，使得形成的栅极结构不存在填充缺陷，并且形成的栅极结构电阻较小，同时使得所述源区和漏区的电学连接性能不会受到影响。
附图说明
图1-10为本发明实施例半导体结构形成过程的结构示意图。
具体实施方式
本发明提供了一种半导体结构及其形成方法，所述半导体结构的形成方法，包括：在所述衬底上形成有源区；在所述有源区中形成至少一个沟槽，所述沟槽至少将所述有源区分为位于沟槽一侧的源区和位于沟槽另一侧的漏区；在所述源区和所述漏区上分别形成抬高源区和抬高漏区。本发明通过在所述源区和所述漏区上分别形成抬高源区和抬高漏区，可以使得形成的沟槽深宽比减小，降低所述半导体结构的制作难度。
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。在详述本发明实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明的保护范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
图1-10为本发明实施例半导体结构形成过程的结构示意图。
参考图1，提供衬底201，所述衬底201上形成有源区202。
所述衬底201的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。本实施例中所述衬底201材料为硅。所述衬底中根据需要掺杂一定的杂质离子，所述杂质离子可以为N型杂质离子或P型杂质离子。在一实施例中，所述掺杂包括阱区掺杂和/或源漏区掺杂。
所述有源区202的数量为若干(大于等于2个)，相邻有源区202之间通过隔离层203隔离。
在一实施例中，所述有源区202的形成过程为：在所述衬底201上形成第一掩膜层(图中未示出)，所述第一掩膜层中具有若干第一掩膜开口，所述第一掩膜开口将所述第一掩膜层分成若干长条形掩膜；在所述长条形掩膜上和所述第一掩膜开口中形成第二掩膜层，在所述长条形掩膜上的所述第二掩膜层中形成第二掩膜开口，利用所述第二掩膜开口将所述长条形掩膜分割成若干分立的有源区掩膜，利用所述有源区掩膜刻蚀所述衬底201，形成有源区202。需要说明的是，为了便于区分有源区202和半导体衬底衬底201，将有源区202和半导体衬底衬底201通过虚线分开。
在其他实施例中，所述有源区202可以通过外延工艺形成。
参考图2，在所述有源区202中形成至少一个沟槽204，所述沟槽204至少将所述有源区分为位于沟槽204一侧的源区205和位于沟槽204另一侧的漏区206。
通过刻蚀所述有源区202，在所述有源区202中形成至少一个沟槽，所述沟槽204中后续形成栅极结构。在一实施例中，在刻蚀有源区202时，同时可以刻蚀有源区202之间的第一隔离层，在所述有源区202和第一隔离层中形成沟槽。
本实施例中，参考图2，每一个有源区202中沟槽204的数量为1个，所述沟槽204将所述有源区分为位于沟槽204一侧的源区205和位于沟槽204另一侧的漏区206，所述沟槽204的开口尺寸(宽度或直径)大于后续在源区205上形成的抬高源区底部的宽度或后续在漏区206上形成的抬高漏区底部的宽度。本申请中由于后续在源区和漏区上会形成抬高源区和抬高漏区，以将源区和漏区的连接点引出，因而在有源区202尺寸一定的情况下，在形成沟槽204时，可以将形成的沟槽204宽度增大，深度减小，相应的使源区205和漏区206的宽度减小，从而后续在形成栅极结构时便于材料的填充，并能减小后续形成的栅极结构的电阻。
在一实施例中，所述沟槽204的宽度范围为1nm-50nm，具体可以为5nm、10nm、15nm、20nm、25nm、30nm、35nm、40nm、45nm，所述沟槽204的深 度范围为1nm-80nm，具体可以为10nm、20nm、30nm、40nm、50nm、60nm、70nm。
在一具体的实施例中，所述有源区202的尺寸范围为10nm-70nm，沟槽204的宽度范围为5nm-25nm，沟槽204的深度范围为10nm-30nm，使得沟槽的宽度能尽可能的宽，深宽比能尽可能的小，能更进一步减小后续填充栅极材料时的难度，进一步减小栅极结构的电阻。具体的，当沟槽204的宽度范围为5nm-25nm时，沟槽204的深宽比小于3:1，例如所述深宽比为2.5:1，2:1，1.5:1等。
需要说明的是，前述实施例中以及后续实施例中，所述有源区202的尺寸，沟槽204的宽度，源区205的宽度以及漏区206的宽度均是指有源区202、沟槽204、源区205和漏区206沿x轴方向上(如图2所示)的最大尺寸，具体的，所述x轴方向可以为有源区202的延伸方向。
在其他实施例中，参考图3，每一个有源区202中形成的沟槽204的数量为两个，两个所述沟槽204将所述有源区202分为位于两个沟槽204中间的源区205和分别位于两个沟槽204两侧的两个漏区206，后续可以在每一个有源区202中的两个沟槽204中形成栅极结构。在其他示例中，两个沟槽204中间的有源区中间部分为漏区，两个沟槽两侧的有源区两端部分为源区。
在一具体的实施例中，参考图3，有源区202的尺寸范围为20nm-145nm，沟槽204的宽度范围为5nm-25nm，沟槽204的深度范围为10nm-30nm，使得沟槽的宽度能尽可能的宽，深宽比能尽可能的小，能更进一步减小后续填充栅极材料时的难度，进一步减小栅极结构的电阻，同时源区和漏区上后续形成的抬高源区和抬高漏区可以使得源区和漏区的电学连接性能尽可能不会受到影响。具体的，当沟槽204的宽度范围为5nm-20nm时，沟槽204的深宽比小于3:1，例如，所述深宽比为2.5:1，2:1，1.5:1等。
参考图4，图4在图2的基础上进行，在所述沟槽中形成栅极结构209。
本实施例中，参考图4，所述有源区202中具有一个沟槽，在所述一个沟槽中形成栅极结构209。在其他实施例中，请参考图5，图5在图3的基础上进行，当每一个有源区202中具有两个沟槽时，在所述两个沟槽中均形成栅极结构209。
在一实施例中，所述栅极结构209包括位于沟槽侧壁和底部表面的栅介质层207，和位于栅介质层207上填充沟槽的导电电极208。在其他实施例中，所述栅极结构209可以包括位于所述沟槽底部和所述沟槽侧壁表面的栅介质层、位于所述栅介质层上的过渡层和位于所述过渡层上填充所述沟槽的导电电极。
在一实施例中，所述栅介质层的材料可以为氧化硅，所述过渡层的材料可以为TiN，所述导电电极208的材料可以为W或者其他合适的金属材料。所述导电电极208也可以为复合电极，例如下部为W或其他金属，上部为多晶硅的双层电极，所述复合电极能够改善晶体管的器件性能。
在一实施例中，所述栅极结构209的形成过程包括：在所述字线凹槽的侧壁和底部表面形成氧化硅层，具体可以通过热氧化工艺形成所述氧化硅层；在所述氧化硅层上形成过渡层；在所述过渡层上形成的金属层；通过平坦化或回刻蚀工艺去除高于有源区202表面的金属层和过渡层，形成栅极结构209。所述栅极结构209的上表面和所述有源区202的上表面齐平。具体的，在实际工艺中，很难控制制作方法使得栅极结构209的上表面和所述有源区202的上表面绝对齐平，总是存在工艺偏差，只要栅极结构209的上表面和所述有源区202的上表面大致齐平即可。
参考图6，图6在图4的基础上进行，在形成抬高源区和抬高漏区之前，在所述栅极结构209的表面(或上方)形成阻挡层210。
本实施例中，参考图6，所述有源区202中具有一个沟槽，在所述一个沟槽中的栅极结构209表面形成阻挡层210。在其他实施例中，请参考图7，图7在图5的基础上进行，当每一个有源区202中具有两个沟槽时，在所述有源区202中的两个沟槽中的栅极结构表面形成阻挡层210。所述阻挡层210对所述栅极结构209起到保护作用，防止后续工艺对栅极结构209的损害。所述阻挡层210的材料与衬底201的材料不相同，具体的，所述阻挡层210的材料可以为氮化硅、氧化硅或氮氧化硅中的一种或几种。为尽量减少对栅极结构尺寸的影响，在保证保护效果的前提下，所述阻挡层210应尽可能的薄，例如，所述阻挡层210的厚度范围为1nm-10nm，或者所述阻挡层210的厚度为所述沟槽的深度的 1/10-1/5.
在一实施例中，所述阻挡层210的形成过程可以包括：回刻蚀去除所述栅极结构209中部分厚度的导电电极208；在剩余的导电电极208表面以及有源区202表面上形成阻挡材料层，所述阻挡材料层的形成工艺可以为化学气相沉积；平坦化去除高于有源区202表面的阻挡材料层，在所述剩余的导电电极208表面形成阻挡层210，所述平坦化可以为化学机械研磨工艺。
在其他实施例中，在导电电极208表面形成阻挡层210时，有源区202表面上也可以保留阻挡材料层210，对所述有源区202进行保护。
参考图8，图8在图6的基础上进行，在所述源区205和所述漏区206上分别形成抬高源区211和抬高漏区212。
所述源区205和漏区206的电连接点通过抬高源区211和抬高漏区212引出，所述抬高源区211的顶部和抬高漏区212的顶部用于与连接结构(比如导电插塞)电连接，本实施例中，所述抬高源区211底部的宽度与所述源区205顶部的宽度相同，所述抬高漏区212底部的宽度与所述漏区206顶部的宽度相同，所述抬高源区211顶部的宽度大于抬高源区211底部的宽度，所述抬高漏区212顶部的宽度大于抬高漏区底部的宽度，因而在有源区202尺寸一定的情况下，当在有源区202中形成的沟槽的尺寸增大，相应的有源区中形成的源区205和漏区206的尺寸减小时，由于抬高源区和抬高漏区顶部的尺寸增大，因而通过抬高源区和抬高漏区仍能保证源区205和漏区206尺寸减小时的电学连接性能，同时保证在沟槽中形成栅极结构时栅极材料容易填充，减小形成的栅极结构电阻。
本实施例中，参考图8，所述有源区202中具有一个沟槽、一个源区205和一个漏区206，在所述一个源区205和一个漏区206表面上对应形成抬高源区211和抬高漏区212。在其他实施例中，请参考图9，图9在图7的基础上进行，当每一个有源区中具有两个沟槽，以及位于两个沟槽之间的源区205和位于两个沟槽两侧的两个漏区206时，在所述有源区202中的一个源区205和两个漏区表面上对应形成抬高源区211和抬高漏区212。
在一实施例中，所述抬高源区211和抬高漏区212与衬底201的材料相同，所述抬高源区211底部的宽度与所述源区205顶部的宽度相同，所述抬高漏区212底部的宽度与所述漏区206顶部的宽度相同。
形成所述抬高源区211和抬高漏区212可以采用选择性外延工艺，从而能简便的使得形成的抬高源区211顶部的宽度大于抬高源区211底部的宽度，形成抬高漏区212顶部的宽度大于抬高漏区底部的宽度，并且提高形成的抬高源区211和抬高漏区212位置的精度和尺寸的精度。在一具体的实施例中，所述衬底、抬高源区和抬高漏区的材料为硅。
在一实施例中，所述采用选择性外延工艺形成所述抬高源区211和所述抬高漏区212的步骤之前，还包括：采用原位清洁工艺清洁所述源区205和所述漏区206表面，以去除所述源区205和漏区206表面的氧化层或者污染物，以提高形成的抬高源区211和抬高漏区212的质量。
在一实施例中，所述形成的抬高源区211或所述抬高漏区212的厚度范围为5nm-100nm。
本实施例中，直接采用选择性外延工艺在所述源区205和所述漏区206上分别形成抬高源区211和抬高漏区212。
在其他实施例中，所述抬高源区211和抬高漏区212的形成过程包括：在有源区211上先形成覆盖层，在所述覆盖层中形成抬高源区开口和抬高漏区开口，所述抬高源区开口和所述抬高漏区开口暴露所述有源区211，在所述抬高源区开口和所述抬高漏区开口中利用外延工艺或其他沉积工艺形成抬高源区211和抬高漏区212，以提高抬高源区211和抬高漏区212的形成质量。
参考图10，图10在图8的基础上进行，形成覆盖所述抬高源区211、抬高漏区212、栅极结构209以及隔离层203表面的介质层213。
所述介质层213用于抬高源区211和抬高漏区212之间的隔离。所述介质层213的材料可以为氮化硅或氧化硅。
在一实施例中，还包括：形成与所述抬高源区211连接的位线，以及形成与所述抬高漏区212连接的电容器。具体的，所述位线和电容器可以分别通过 相应的导电插塞与抬高源区211和抬高漏区212连接。
在其他实施例中，每一个有源区中具有一个源区和两个漏区时，相应的形成一个抬高源区和两个抬高漏区，还包括，形成与所述一个抬高源区连接的位线和形成与所述两个抬高漏区分别连接的两个电容器。
本发明另一实施例还提供了一种半导体结构，参考图9，包括：
衬底201，所述衬底201上具有有源区202；
位于所述有源区202中的至少一个沟槽，所述沟槽至少将所述有源区分为位于沟槽一侧的源区205和位于沟槽另一侧的漏区206；
抬高源区211，位于所述源区205上；
抬高漏区212，位于所述漏区206上。
在一实施例中，所述抬高源区211顶部的宽度大于抬高源区211底部的宽度，所述抬高漏区212顶部的宽度大于抬高漏区212底部的宽度，所述抬高源区211底部的宽度与所述源区205顶部的宽度相同，所述抬高漏区212底部的宽度与所述漏区206顶部的宽度相同。
在一实施例中，所述抬高源区211和抬高漏区212通过选择性外延工艺形成。所述抬高源区211和抬高漏区212与衬底201的材料相同。所述抬高源区211或所述抬高漏区212的厚度范围为5nm-100nm。
本实施例中，参考图9，每一个有源区202中形成的沟槽的数量为两个，两个所述沟槽将所述有源区202分为位于两个沟槽中间的源区205和分别两个沟槽两侧的两个漏区206，所述位于中间的源区205上具有一个抬高源区211，所述两个漏区206上分别具有一个抬高漏区212。具体的，有源区202的尺寸范围为20nm-145nm，沟槽204的宽度范围为5nm-25nm，沟槽204的深度范围为10nm-30nm。当沟槽204的宽度范围为5nm-20nm时，沟槽204的深宽比小于3:1，例如，所述深宽比为2.5:1，2:1，1.5:1等。
其他实施例中，参考图8，每一个有源区202中形成的沟槽的数量为一个，一个所述沟槽将所述有源区202分为位于沟槽一侧的源区205和位于沟槽另一侧的漏区206，所述一个源区205上具有一个抬高源区211，所述一个漏区206 上具有一个抬高漏区212。具体的，有源区202的尺寸范围为10nm-70nm，沟槽204的宽度范围为5nm-25nm，沟槽204的深度范围为10nm-30nm。当沟槽204的宽度范围为5nm-25nm时，沟槽204的深宽比小于3:1，例如所述深宽比为2.5:1，2:1，1.5:1等。
还包括：栅极结构209，位于所述沟槽中，所述栅极结构209的上表面和所述有源区202的上表面齐平。具体的，在实际工艺中，很难控制制作方法使得栅极结构209的上表面和所述有源区202的上表面绝对齐平，总是存在工艺偏差，只要栅极结构209的上表面和所述有源区202的上表面大致齐平即可。
在一实施例中，还包括：阻挡层210，所述阻挡层210位于所述栅极结构209上方，所述阻挡层210的上表面与所述有源区202的上表面齐平。为尽量减少对栅极结构尺寸的影响，在保证保护效果的前提下，所述阻挡层210应尽可能的薄，例如，所述阻挡层210的厚度范围为1nm-10nm，或者所述阻挡层210的厚度为所述沟槽的深度的1/10-1/5.
在其他实施例中，有源区202表面上也可以保留阻挡材料层210，对所述有源区202进行保护。
在一实施例中，还包括：与所述抬高源区211连接的位线，以及与所述抬高漏区212连接的电容器。具体的，所述位线和电容器可以分别通过相应的导电插塞与抬高源区211和抬高漏区212连接。
在其他实施例中，每一个有源区中具有一个源区和两个漏区时，相应的形成一个抬高源区和两个抬高漏区，还包括，与所述一个抬高源区连接的位线和与所述两个抬高漏区分别连接的两个电容器。
需要说明的是，本实施例中关于半导体结构其他限定或描述在本实施例中不再赘述，具体请参考前述半导体结构形成过程实施例中的相应限定或描述。
本发明虽然已以较佳实施例公开如上，但其并不是用来限定本发明，任何本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改，因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、 等同变化及修饰，均属于本发明技术方案的保护范围。

Claims (16)

  1. 一种半导体结构的形成方法，其特征在于，包括：
    提供衬底；
    在所述衬底上形成有源区；
    在所述有源区中形成至少一个沟槽，所述沟槽至少将所述有源区分为位于沟槽一侧的源区和位于沟槽另一侧的漏区；
    在所述源区和所述漏区上分别形成抬高源区和抬高漏区。
  2. 如权利要求1所述的半导体结构的形成方法，其特征在于，采用选择性外延工艺形成所述抬高源区和所述抬高漏区。
  3. 如权利要求2所述的半导体结构的形成方法，其特征在于，所述采用选择性外延工艺形成所述抬高源区和所述抬高漏区的步骤之前，还包括：
    采用原位清洁工艺清洁所述源区和所述漏区表面。
  4. 如权利要求1所述的半导体结构的形成方法，其特征在于，还包括：在所述沟槽中形成栅极结构，所述栅极结构的上表面和所述有源区的上表面齐平。
  5. 如权利要求1所述的半导体结构的形成方法，其特征在于，还包括：在所述沟槽中形成栅极结构，在所述栅极结构上形成阻挡层。
  6. 如权利要求1所述的半导体结构的形成方法，其特征在于，所述抬高源区和所述抬高漏区的形成过程，包括：
    在所述有源区上形成覆盖层；
    在所述覆盖层中形成抬高源区开口和抬高漏区开口，所述抬高源区开口和所述抬高漏区开口暴露出所述有源区；
    在所述抬高源区开口和所述抬高漏区开口中形成抬高源区和抬高漏区。
  7. 一种半导体结构，其特征在于，包括：
    衬底，所述衬底上具有有源区；
    位于所述有源区中的至少一个沟槽，所述沟槽至少将所述有源区分为位于沟槽一侧的源区和位于沟槽另一侧的漏区；
    抬高源区，位于所述源区上；
    抬高漏区，位于所述漏区上。
  8. 如权利要求7所述的半导体结构，其特征在于，所述抬高源区顶部的宽度大于所述抬高源区底部的宽度，所述抬高漏区顶部的宽度大于所述抬高漏区底部的宽度。
  9. 如权利要求7所述的半导体结构，其特征在于，所述沟槽的开口尺寸大于所述抬高源区底部的宽度或所述抬高漏区底部的宽度。
  10. 如权利要求7所述的半导体结构，其特征在于，所述抬高源区底部的宽度与所述源区顶部的宽度相同，所述抬高漏区底部的宽度与所述漏区顶部的宽度相同。
  11. 如权利要求7所述的半导体结构，其特征在于，两个沟槽位于同一有源区中；所述有源区的尺寸范围为20nm-145nm；所述沟槽的宽度范围为5nm-25nm，所述沟槽的深度范围为10nm-30nm。
  12. 如权利要求11所述的半导体结构，其特征在于，所述沟槽的深宽比小于3：1。
  13. 如权利要求7所述的半导体结构，其特征在于，所述抬高源区或所述抬高漏区的厚度范围为5-100nm。
  14. 如权利要求7所述的半导体结构，其特征在于，还包括：栅极结构，位于所述沟槽中，所述栅极结构的上表面和所述有源区的上表面齐平。
  15. 如权利要求7所述的半导体结构，其特征在于，还包括：栅极结构，位于所述沟槽中；阻挡层，所述阻挡层位于所述栅极结构上方，所述阻挡层的上表面与所述有源区的上表面齐平。
  16. 如权利要求15所述的半导体结构，其特征在于，所述阻挡层的厚度范围为1nm-10nm，或者所述阻挡层的厚度为所述沟槽的深度的1/10-1/5。
PCT/CN2021/079667 2020-03-27 2021-03-09 半导体结构及其形成方法 WO2021190295A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/386,474 US11869952B2 (en) 2020-03-27 2021-07-27 Semiconductor structure and method for forming same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010230470.2 2020-03-27
CN202010230470.2A CN113451395B (zh) 2020-03-27 2020-03-27 半导体结构及其形成方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/386,474 Continuation US11869952B2 (en) 2020-03-27 2021-07-27 Semiconductor structure and method for forming same

Publications (1)

Publication Number Publication Date
WO2021190295A1 true WO2021190295A1 (zh) 2021-09-30

Family

ID=77808112

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/079667 WO2021190295A1 (zh) 2020-03-27 2021-03-09 半导体结构及其形成方法

Country Status (3)

Country Link
US (1) US11869952B2 (zh)
CN (1) CN113451395B (zh)
WO (1) WO2021190295A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11862697B2 (en) 2020-04-30 2024-01-02 Changxin Memory Technologies, Inc. Method for manufacturing buried gate and method for manufacturing semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6252277B1 (en) * 1999-09-09 2001-06-26 Chartered Semiconductor Manufacturing Ltd. Embedded polysilicon gate MOSFET
CN103094121A (zh) * 2011-01-13 2013-05-08 英飞凌科技奥地利有限公司 一种用于制造半导体器件的方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089872A (en) * 1990-04-27 1992-02-18 North Carolina State University Selective germanium deposition on silicon and resulting structures
KR100714900B1 (ko) * 2006-06-09 2007-05-04 삼성전자주식회사 매몰 게이트 전극을 갖는 반도체 소자 및 그 제조방법
US9059212B2 (en) * 2012-10-31 2015-06-16 International Business Machines Corporation Back-end transistors with highly doped low-temperature contacts

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6252277B1 (en) * 1999-09-09 2001-06-26 Chartered Semiconductor Manufacturing Ltd. Embedded polysilicon gate MOSFET
CN103094121A (zh) * 2011-01-13 2013-05-08 英飞凌科技奥地利有限公司 一种用于制造半导体器件的方法

Also Published As

Publication number Publication date
US20210359094A1 (en) 2021-11-18
US11869952B2 (en) 2024-01-09
CN113451395A (zh) 2021-09-28
CN113451395B (zh) 2023-01-24

Similar Documents

Publication Publication Date Title
US10672796B2 (en) Mechanisms for forming FINFET device
TWI737391B (zh) 具有強健內間隔件之環繞式閘極場效電晶體及方法
CN108122846B (zh) 包括鳍式场效应晶体管的半导体器件及其形成方法
US10566331B1 (en) Semiconductor devices
US11430878B2 (en) Method for fabricating semiconductor device
US20130292776A1 (en) Semiconductor device employing fin-type gate and method for manufacturing the same
US20140042548A1 (en) Dram structure with buried word lines and fabrication thereof, and ic structure and fabrication thereof
CN112563266A (zh) 半导体装置
TWI749363B (zh) 在閘極與源極/汲極接觸之間具有絕緣層的ｆｉｎｆｅｔ
KR20200059137A (ko) 리세싱된 실리콘 캡이 있는 트랜지스터 및 그 형성 방법
US20180277645A1 (en) Gate cuts after metal gate formation
CN109755290B (zh) 纳米线晶体管及其制备方法
WO2021190295A1 (zh) 半导体结构及其形成方法
CN111081546B (zh) 半导体结构及其形成方法
US10347629B2 (en) FinFET device
CN109755312B (zh) 纳米线晶体管及其制备方法
US10325811B2 (en) Field-effect transistors with fins having independently-dimensioned sections
TWI769797B (zh) 動態隨機存取記憶體及其製造法方法
WO2023108784A1 (zh) 一种半导体器件及其制造方法
WO2022041896A1 (zh) 一种半导体结构及其制备方法
TWI604569B (zh) 半導體裝置及其形成方法
TW202228273A (zh) 半導體記憶體結構及其形成方法
CN105826200A (zh) 晶体管及其形成方法
WO2024045870A1 (zh) 半导体器件及其制作方法、芯片、电子设备
CN117374076A (zh) 3ds fet及其制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21774450

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21774450

Country of ref document: EP

Kind code of ref document: A1