CN113451395B - 半导体结构及其形成方法 - Google Patents
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Abstract
一种半导体结构及其形成方法,所述形成方法包括,在衬底上形成有源区;在所述有源区中形成至少一个沟槽,所述沟槽至少将所述有源区分为位于沟槽一侧的源区和位于沟槽另一侧的漏区;在所述源区和所述漏区上分别形成抬高源区和抬高漏区。因而在有源区的尺寸一定的情况下,在前述形成沟槽时,可以使得沟槽的宽度增大,深度减小,深宽比减小,从而在有源区尺寸一定的情况下,使得在沟槽中形成栅极结构时栅极材料容易填充,并且形成的栅极结构电阻较小,同时使得所述源区和漏区的电学连接性能不会受到影响。
Description
技术领域
本发明涉及半导体技术领域,尤其涉及一种半导体结构及其形成方法。
背景技术
随着晶体管尺寸的不断减小,有源区的长度的限制导致栅极结构也变的越来越小,使得晶体管的制作变得更加困难。例如,埋伏栅极的沟槽宽度越来越窄,沟槽的深宽比越来越大,限制了形成栅极结构时的材料填充,并且栅极结构的尺寸的减小,使得栅极结构的电阻增大,降低了电学性能。
发明内容
本发明所要解决的技术问题是在有源区尺寸一定的情况下降低栅极结构的制作难度,并使形成栅极结构的电学性能得到改善。
为此,本发明提供了一种半导体结构的形成方法,包括:
提供衬底;
在所述衬底上形成有源区;
在所述有源区中形成至少一个沟槽,所述沟槽至少将所述有源区分为位于沟槽一侧的源区和位于沟槽另一侧的漏区;
在所述源区和所述漏区上分别形成抬高源区和抬高漏区。
可选的,采用选择性外延工艺形成所述抬高源区和所述抬高漏区。
可选的,所述采用选择性外延工艺形成所述抬高源区和所述抬高漏区的步骤之前,还包括:
采用原位清洁工艺清洁所述源区和所述漏区表面。
可选的,还包括:在所述沟槽中形成栅极结构,所述栅极结构的上表面和所述有源区的上表面齐平。
可选的,还包括:在所述沟槽中形成栅极结构,在所述栅极结构上形成阻挡层。
可选的,所述抬高源区和所述抬高漏区的形成过程,包括:
在所述有源区上形成覆盖层;
在所述覆盖层中形成抬高源区开口和抬高漏区开口,所述抬高源区开口和所述抬高漏区开口暴露出所述有源区;
在所述抬高源区开口和所述抬高漏区开口中形成抬高源区和抬高漏区。
本发明还提供了一种半导体结构,包括:
衬底,所述衬底上具有有源区;
位于所述有源区中的至少一个沟槽,所述沟槽至少将所述有源区分为位于沟槽一侧的源区和位于沟槽另一侧的漏区;
抬高源区,位于所述源区上;
抬高漏区,位于所述漏区上。
可选的,所述抬高源区顶部的宽度大于所述抬高源区底部的宽度,所述抬高漏区顶部的宽度大于所述抬高漏区底部的宽度。
可选的,所述沟槽的开口尺寸大于所述抬高源区底部的宽度或所述抬高漏区底部的宽度。
可选的,所述抬高源区底部的宽度与所述源区顶部的宽度相同,所述抬高漏区底部的宽度与所述漏区顶部的宽度相同。
可选的,两个沟槽位于同一有源区中;所述有源区的尺寸范围为20nm-145nm;所述沟槽的宽度范围为5nm-25nm,所述沟槽的深度范围为10nm-30nm。
可选的,所述沟槽的深宽比小于3:1。
可选的,所述抬高源区或所述抬高漏区的厚度范围为5nm-100nm。
可选的,还包括:栅极结构,位于所述沟槽中,所述栅极结构的上表面和所述有源区的上表面齐平。
可选的,还包括:栅极结构,位于所述沟槽中;阻挡层,所述阻挡层位于所述栅极结构上方,所述阻挡层的上表面与所述有源区的上表面齐平。
可选的,所述阻挡层的厚度范围为1nm-10nm,或者所述阻挡层的厚度为所述沟槽的深度的1/10-1/5。
与现有技术相比,本发明技术方案具有以下优点:
本发明的半导体结构的形成方法,在所述衬底上形成有源区;在所述有源区中形成至少一个沟槽,所述沟槽至少将所述有源区分为位于沟槽一侧的源区和位于沟槽另一侧的漏区;在所述源区和所述漏区上分别形成抬高源区和抬高漏区。本发明通过在所述源区和所述漏区上分别形成抬高源区和抬高漏区将源区和漏区的电连接点引出,因而在有源区的尺寸一定的情况下,在前述形成沟槽时,可以使得沟槽的宽度增大,深度减小,深宽比减小,从而在有源区尺寸一定的情况下,使得在沟槽中形成栅极结构的制作难度降低,并且形成的栅极结构的电学性能得到改善。
进一步,所述抬高源区底部的宽度与所述源区顶部的宽度相同,所述抬高漏区底部的宽度与所述漏区顶部的宽度相同,所述抬高源区顶部的宽度大于抬高源区底部的宽度,所述抬高漏区顶部的宽度大于抬高漏区底部的宽度,因而在有源区尺寸一定的情况下,当在有源区中形成的沟槽的尺寸增大,相应的有源区中形成的源区和漏区的尺寸减小时,由于抬高源区和抬高漏区顶部的尺寸增大,因而通过抬高源区和抬高漏区仍能保证源区和漏区尺寸减小时的电学连接性能,同时保证在沟槽中形成栅极结构时栅极材料容易填充,减小形成的栅极结构电阻,降低栅极结构的制作难度并且改善栅极结构的电学性能。
进一步,形成所述抬高源区和抬高漏区采用选择性外延工艺,从而能简便的使得形成的抬高源区顶部的宽度大于抬高源区底部的宽度,形成抬高漏区顶部的宽度大于抬高漏区底部的宽度,并且提高形成的抬高源区和抬高漏区位置的精度和尺寸的精度。
进一步,在所述栅极结构上形成阻挡层,所述阻挡层可以对所述栅极结构起保护作用,防止后续工艺对所述栅极结构造成损害。
本发明的半导体结构,包括:衬底,所述衬底上具有有源区;位于所述有源区中的至少一个沟槽,所述沟槽至少将所述有源区分为位于沟槽一侧的源区和位于沟槽另一侧的漏区;所述源区和所述漏区上分别具有抬高源区和抬高漏区。在有源区的尺寸一定的情况下,可以减少栅极结构的制作难度,使得形成的栅极结构不存在填充缺陷,并且形成的栅极结构电阻较小,同时使得所述源区和漏区的电学连接性能不会受到影响。
附图说明
图1-10为本发明实施例半导体结构形成过程的结构示意图。
具体实施方式
本发明提供了一种半导体结构及其形成方法,所述半导体结构的形成方法,包括:在所述衬底上形成有源区;在所述有源区中形成至少一个沟槽,所述沟槽至少将所述有源区分为位于沟槽一侧的源区和位于沟槽另一侧的漏区;在所述源区和所述漏区上分别形成抬高源区和抬高漏区。本发明通过在所述源区和所述漏区上分别形成抬高源区和抬高漏区,可以使得形成的沟槽深宽比减小,降低所述半导体结构的制作难度。
为使本发明的上述目的、特征和优点能够更加明显易懂,下面结合附图对本发明的具体实施方式做详细的说明。在详述本发明实施例时,为便于说明,示意图会不依一般比例作局部放大,而且所述示意图只是示例,其在此不应限制本发明的保护范围。此外,在实际制作中应包含长度、宽度及深度的三维空间尺寸。
图1-10为本发明实施例半导体结构形成过程的结构示意图。
参考图1,提供衬底201,所述衬底201上形成有源区202。
所述衬底201的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC);也可以是绝缘体上硅(SOI),绝缘体上锗(GOI);或者还可以为其它的材料,例如砷化镓等Ⅲ-Ⅴ族化合物。本实施例中所述衬底201材料为硅。所述衬底中根据需要掺杂一定的杂质离子,所述杂质离子可以为N型杂质离子或P型杂质离子。在一实施例中,所述掺杂包括阱区掺杂和/或源漏区掺杂。
所述有源区202的数量为若干(大于等于2个),相邻有源区202之间通过隔离层203隔离。
在一实施例中,所述有源区202的形成过程为:在所述衬底201上形成第一掩膜层(图中未示出),所述第一掩膜层中具有若干第一掩膜开口,所述第一掩膜开口将所述第一掩膜层分成若干长条形掩膜;在所述长条形掩膜上和所述第一掩膜开口中形成第二掩膜层,在所述长条形掩膜上的所述第二掩膜层中形成第二掩膜开口,利用所述第二掩膜开口将所述长条形掩膜分割成若干分立的有源区掩膜,利用所述有源区掩膜刻蚀所述衬底201,形成有源区202。需要说明的是,为了便于区分有源区202和半导体衬底衬底201,将有源区202和半导体衬底衬底201通过虚线分开。
在其他实施例中,所述有源区202可以通过外延工艺形成。
参考图2,在所述有源区202中形成至少一个沟槽204,所述沟槽204至少将所述有源区分为位于沟槽204一侧的源区205和位于沟槽204另一侧的漏区206。
通过刻蚀所述有源区202,在所述有源区202中形成至少一个沟槽,所述沟槽204中后续形成栅极结构。在一实施例中,在刻蚀有源区202时,同时可以刻蚀有源区202之间的第一隔离层,在所述有源区202和第一隔离层中形成沟槽。
本实施例中,参考图2,每一个有源区202中沟槽204的数量为1个,所述沟槽204将所述有源区分为位于沟槽204一侧的源区205和位于沟槽204另一侧的漏区206,所述沟槽204的开口尺寸(宽度或直径)大于后续在源区205上形成的抬高源区底部的宽度或后续在漏区206上形成的抬高漏区底部的宽度。本申请中由于后续在源区和漏区上会形成抬高源区和抬高漏区,以将源区和漏区的连接点引出,因而在有源区202尺寸一定的情况下,在形成沟槽204时,可以将形成的沟槽204宽度增大,深度减小,相应的使源区205和漏区206的宽度减小,从而后续在形成栅极结构时便于材料的填充,并能减小后续形成的栅极结构的电阻。
在一实施例中,所述沟槽204的宽度范围为1nm-50nm,具体可以为5nm、10nm、15nm、20nm、25nm、30nm、35nm、40nm、45nm,所述沟槽204的深度范围为1nm-80nm,具体可以为10nm、20nm、30nm、40nm、50nm、60nm、70nm。
在一具体的实施例中,所述有源区202的尺寸范围为10nm-70nm,沟槽204的宽度范围为5nm-25nm,沟槽204的深度范围为10nm-30nm,使得沟槽的宽度能尽可能的宽,深宽比能尽可能的小,能更进一步减小后续填充栅极材料时的难度,进一步减小栅极结构的电阻。具体的,当沟槽204的宽度范围为5nm-25nm时,沟槽204的深宽比小于3:1,例如所述深宽比为2.5:1,2:1,1.5:1等。
需要说明的是,前述实施例中以及后续实施例中,所述有源区202的尺寸,沟槽204的宽度,源区205的宽度以及漏区206的宽度均是指有源区202、沟槽204、源区205和漏区206沿x轴方向上(如图2所示)的最大尺寸,具体的,所述x轴方向可以为有源区202的延伸方向。
在其他实施例中,参考图3,每一个有源区202中形成的沟槽204的数量为两个,两个所述沟槽204将所述有源区202分为位于两个沟槽204中间的源区205和分别位于两个沟槽204两侧的两个漏区206,后续可以在每一个有源区202中的两个沟槽204中形成栅极结构。在其他示例中,两个沟槽204中间的有源区中间部分为漏区,两个沟槽两侧的有源区两端部分为源区。
在一具体的实施例中,参考图3,有源区202的尺寸范围为20nm-145nm,沟槽204的宽度范围为5nm-25nm,沟槽204的深度范围为10nm-30nm,使得沟槽的宽度能尽可能的宽,深宽比能尽可能的小,能更进一步减小后续填充栅极材料时的难度,进一步减小栅极结构的电阻,同时源区和漏区上后续形成的抬高源区和抬高漏区可以使得源区和漏区的电学连接性能尽可能不会受到影响。具体的,当沟槽204的宽度范围为5nm-20nm时,沟槽204的深宽比小于3:1,例如,所述深宽比为2.5:1,2:1,1.5:1等。
参考图4,图4在图2的基础上进行,在所述沟槽中形成栅极结构209。
本实施例中,参考图4,所述有源区202中具有一个沟槽,在所述一个沟槽中形成栅极结构209。在其他实施例中,请参考图5,图5在图3的基础上进行,当每一个有源区202中具有两个沟槽时,在所述两个沟槽中均形成栅极结构209。
在一实施例中,所述栅极结构209包括位于沟槽侧壁和底部表面的栅介质层207,和位于栅介质层207上填充沟槽的导电电极208。在其他实施例中,所述栅极结构209可以包括位于所述沟槽底部和所述沟槽侧壁表面的栅介质层、位于所述栅介质层上的过渡层和位于所述过渡层上填充所述沟槽的导电电极。
在一实施例中,所述栅介质层的材料可以为氧化硅,所述过渡层的材料可以为TiN,所述导电电极208的材料可以为W或者其他合适的金属材料。所述导电电极208也可以为复合电极,例如下部为W或其他金属,上部为多晶硅的双层电极,所述复合电极能够改善晶体管的器件性能。
在一实施例中,所述栅极结构209的形成过程包括:在所述字线凹槽的侧壁和底部表面形成氧化硅层,具体可以通过热氧化工艺形成所述氧化硅层;在所述氧化硅层上形成过渡层;在所述过渡层上形成的金属层;通过平坦化或回刻蚀工艺去除高于有源区202表面的金属层和过渡层,形成栅极结构209。所述栅极结构209的上表面和所述有源区202的上表面齐平。具体的,在实际工艺中,很难控制制作方法使得栅极结构209的上表面和所述有源区202的上表面绝对齐平,总是存在工艺偏差,只要栅极结构209的上表面和所述有源区202的上表面大致齐平即可。
参考图6,图6在图4的基础上进行,在形成抬高源区和抬高漏区之前,在所述栅极结构209的表面(或上方)形成阻挡层210。
本实施例中,参考图6,所述有源区202中具有一个沟槽,在所述一个沟槽中的栅极结构209表面形成阻挡层210。在其他实施例中,请参考图7,图7在图5的基础上进行,当每一个有源区202中具有两个沟槽时,在所述有源区202中的两个沟槽中的栅极结构表面形成阻挡层210。所述阻挡层210对所述栅极结构209起到保护作用,防止后续工艺对栅极结构209的损害。所述阻挡层210的材料与衬底201的材料不相同,具体的,所述阻挡层210的材料可以为氮化硅、氧化硅或氮氧化硅中的一种或几种。为尽量减少对栅极结构尺寸的影响,在保证保护效果的前提下,所述阻挡层210应尽可能的薄,例如,所述阻挡层210的厚度范围为1nm-10nm,或者所述阻挡层210的厚度为所述沟槽的深度的1/10-1/5.
在一实施例中,所述阻挡层210的形成过程可以包括:回刻蚀去除所述栅极结构209中部分厚度的导电电极208;在剩余的导电电极208表面以及有源区202表面上形成阻挡材料层,所述阻挡材料层的形成工艺可以为化学气相沉积;平坦化去除高于有源区202表面的阻挡材料层,在所述剩余的导电电极208表面形成阻挡层210,所述平坦化可以为化学机械研磨工艺。
在其他实施例中,在导电电极208表面形成阻挡层210时,有源区202表面上也可以保留阻挡材料层210,对所述有源区202进行保护。
参考图8,图8在图6的基础上进行,在所述源区205和所述漏区206上分别形成抬高源区211和抬高漏区212。
所述源区205和漏区206的电连接点通过抬高源区211和抬高漏区212引出,所述抬高源区211的顶部和抬高漏区212的顶部用于与连接结构(比如导电插塞)电连接,本实施例中,所述抬高源区211底部的宽度与所述源区205顶部的宽度相同,所述抬高漏区212底部的宽度与所述漏区206顶部的宽度相同,所述抬高源区211顶部的宽度大于抬高源区211底部的宽度,所述抬高漏区212顶部的宽度大于抬高漏区底部的宽度,因而在有源区202尺寸一定的情况下,当在有源区202中形成的沟槽的尺寸增大,相应的有源区中形成的源区205和漏区206的尺寸减小时,由于抬高源区和抬高漏区顶部的尺寸增大,因而通过抬高源区和抬高漏区仍能保证源区205和漏区206尺寸减小时的电学连接性能,同时保证在沟槽中形成栅极结构时栅极材料容易填充,减小形成的栅极结构电阻。
本实施例中,参考图8,所述有源区202中具有一个沟槽、一个源区205和一个漏区206,在所述一个源区205和一个漏区206表面上对应形成抬高源区211和抬高漏区212。在其他实施例中,请参考图9,图9在图7的基础上进行,当每一个有源区中具有两个沟槽,以及位于两个沟槽之间的源区205和位于两个沟槽两侧的两个漏区206时,在所述有源区202中的一个源区205和两个漏区表面上对应形成抬高源区211和抬高漏区212。
在一实施例中,所述抬高源区211和抬高漏区212与衬底201的材料相同,所述抬高源区211底部的宽度与所述源区205顶部的宽度相同,所述抬高漏区212底部的宽度与所述漏区206顶部的宽度相同。
形成所述抬高源区211和抬高漏区212可以采用选择性外延工艺,从而能简便的使得形成的抬高源区211顶部的宽度大于抬高源区211底部的宽度,形成抬高漏区212顶部的宽度大于抬高漏区底部的宽度,并且提高形成的抬高源区211和抬高漏区212位置的精度和尺寸的精度。在一具体的实施例中,所述衬底、抬高源区和抬高漏区的材料为硅。
在一实施例中,所述采用选择性外延工艺形成所述抬高源区211和所述抬高漏区212的步骤之前,还包括:采用原位清洁工艺清洁所述源区205和所述漏区206表面,以去除所述源区205和漏区206表面的氧化层或者污染物,以提高形成的抬高源区211和抬高漏区212的质量。
在一实施例中,所述形成的抬高源区211或所述抬高漏区212的厚度范围为5nm-100nm。
本实施例中,直接采用选择性外延工艺在所述源区205和所述漏区206上分别形成抬高源区211和抬高漏区212。
在其他实施例中,所述抬高源区211和抬高漏区212的形成过程包括:在有源区211上先形成覆盖层,在所述覆盖层中形成抬高源区开口和抬高漏区开口,所述抬高源区开口和所述抬高漏区开口暴露所述有源区211,在所述抬高源区开口和所述抬高漏区开口中利用外延工艺或其他沉积工艺形成抬高源区211和抬高漏区212,以提高抬高源区211和抬高漏区212的形成质量。
参考图10,图10在图8的基础上进行,形成覆盖所述抬高源区211、抬高漏区212、栅极结构209以及隔离层203表面的介质层213。
所述介质层213用于抬高源区211和抬高漏区212之间的隔离。所述介质层213的材料可以为氮化硅或氧化硅。
在一实施例中,还包括:形成与所述抬高源区211连接的位线,以及形成与所述抬高漏区212连接的电容器。具体的,所述位线和电容器可以分别通过相应的导电插塞与抬高源区211和抬高漏区212连接。
在其他实施例中,每一个有源区中具有一个源区和两个漏区时,相应的形成一个抬高源区和两个抬高漏区,还包括,形成与所述一个抬高源区连接的位线和形成与所述两个抬高漏区分别连接的两个电容器。
本发明另一实施例还提供了一种半导体结构,参考图9,包括:
衬底201,所述衬底201上具有有源区202;
位于所述有源区202中的至少一个沟槽,所述沟槽至少将所述有源区分为位于沟槽一侧的源区205和位于沟槽另一侧的漏区206;
抬高源区211,位于所述源区205上;
抬高漏区212,位于所述漏区206上。
在一实施例中,所述抬高源区211顶部的宽度大于抬高源区211底部的宽度,所述抬高漏区212顶部的宽度大于抬高漏区212底部的宽度,所述抬高源区211底部的宽度与所述源区205顶部的宽度相同,所述抬高漏区212底部的宽度与所述漏区206顶部的宽度相同。
在一实施例中,所述抬高源区211和抬高漏区212通过选择性外延工艺形成。所述抬高源区211和抬高漏区212与衬底201的材料相同。所述抬高源区211或所述抬高漏区212的厚度范围为5nm-100nm。
本实施例中,参考图9,每一个有源区202中形成的沟槽的数量为两个,两个所述沟槽将所述有源区202分为位于两个沟槽中间的源区205和分别两个沟槽两侧的两个漏区206,所述位于中间的源区205上具有一个抬高源区211,所述两个漏区206上分别具有一个抬高漏区212。具体的,有源区202的尺寸范围为20nm-145nm,沟槽204的宽度范围为5nm-25nm,沟槽204的深度范围为10nm-30nm。当沟槽204的宽度范围为5nm-20nm时,沟槽204的深宽比小于3:1,例如,所述深宽比为2.5:1,2:1,1.5:1等。
其他实施例中,参考图8,每一个有源区202中形成的沟槽的数量为一个,一个所述沟槽将所述有源区202分为位于沟槽一侧的源区205和位于沟槽另一侧的漏区206,所述一个源区205上具有一个抬高源区211,所述一个漏区206上具有一个抬高漏区212。具体的,有源区202的尺寸范围为10nm-70nm,沟槽204的宽度范围为5nm-25nm,沟槽204的深度范围为10nm-30nm。当沟槽204的宽度范围为5nm-25nm时,沟槽204的深宽比小于3:1,例如所述深宽比为2.5:1,2:1,1.5:1等。
还包括:栅极结构209,位于所述沟槽中,所述栅极结构209的上表面和所述有源区202的上表面齐平。具体的,在实际工艺中,很难控制制作方法使得栅极结构209的上表面和所述有源区202的上表面绝对齐平,总是存在工艺偏差,只要栅极结构209的上表面和所述有源区202的上表面大致齐平即可。
在一实施例中,还包括:阻挡层210,所述阻挡层210位于所述栅极结构209上方,所述阻挡层210的上表面与所述有源区202的上表面齐平。为尽量减少对栅极结构尺寸的影响,在保证保护效果的前提下,所述阻挡层210应尽可能的薄,例如,所述阻挡层210的厚度范围为1nm-10nm,或者所述阻挡层210的厚度为所述沟槽的深度的1/10-1/5.
在其他实施例中,有源区202表面上也可以保留阻挡材料层210,对所述有源区202进行保护。
在一实施例中,还包括:与所述抬高源区211连接的位线,以及与所述抬高漏区212连接的电容器。具体的,所述位线和电容器可以分别通过相应的导电插塞与抬高源区211和抬高漏区212连接。
在其他实施例中,每一个有源区中具有一个源区和两个漏区时,相应的形成一个抬高源区和两个抬高漏区,还包括,与所述一个抬高源区连接的位线和与所述两个抬高漏区分别连接的两个电容器。
需要说明的是,本实施例中关于半导体结构其他限定或描述在本实施例中不再赘述,具体请参考前述半导体结构形成过程实施例中的相应限定或描述。
本发明虽然已以较佳实施例公开如上,但其并不是用来限定本发明,任何本领域技术人员在不脱离本发明的精神和范围内,都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改,因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰,均属于本发明技术方案的保护范围。
Claims (13)
1.一种半导体结构的形成方法,其特征在于,包括:
提供衬底;
在所述衬底上形成有源区;
在所述有源区中形成至少一个沟槽,所述沟槽至少将所述有源区分为位于沟槽一侧的源区和位于沟槽另一侧的漏区,所述沟槽的开口尺寸大于后续形成的抬高源区底部的宽度或抬高漏区底部的宽度;
在所述沟槽中形成栅极结构;
在所述源区和所述漏区上分别形成抬高源区和抬高漏区,所述抬高源区底部的宽度与所述源区顶部的宽度相同,所述抬高漏区底部的宽度与所述漏区顶部的宽度相同,所述抬高源区顶部的宽度大于所述抬高源区底部的宽度,所述抬高漏区顶部的宽度大于所述抬高漏区底部的宽度。
2.如权利要求1所述的半导体结构的形成方法,其特征在于,采用选择性外延工艺形成所述抬高源区和所述抬高漏区。
3.如权利要求2所述的半导体结构的形成方法,其特征在于,所述采用选择性外延工艺形成所述抬高源区和所述抬高漏区的步骤之前,还包括:
采用原位清洁工艺清洁所述源区和所述漏区表面。
4.如权利要求1所述的半导体结构的形成方法,其特征在于,还包括:在所述沟槽中形成栅极结构,所述栅极结构的上表面和所述有源区的上表面齐平。
5.如权利要求1所述的半导体结构的形成方法,其特征在于,还包括:在所述栅极结构上形成阻挡层。
6.如权利要求1所述的半导体结构的形成方法,其特征在于,所述抬高源区和所述抬高漏区的形成过程,包括:
在所述有源区上形成覆盖层;
在所述覆盖层中形成抬高源区开口和抬高漏区开口,所述抬高源区开口和所述抬高漏区开口暴露出所述有源区;
在所述抬高源区开口和所述抬高漏区开口中形成抬高源区和抬高漏区。
7.一种半导体结构,其特征在于,包括:
衬底,所述衬底上具有有源区;
位于所述有源区中的至少一个沟槽,所述沟槽至少将所述有源区分为位于沟槽一侧的源区和位于沟槽另一侧的漏区;
栅极结构,位于所述沟槽中;
抬高源区,位于所述源区上;
抬高漏区,位于所述漏区上,所述抬高源区底部的宽度与所述源区顶部的宽度相同,所述抬高漏区底部的宽度与所述漏区顶部的宽度相同,所述抬高源区顶部的宽度大于所述抬高源区底部的宽度,所述抬高漏区顶部的宽度大于所述抬高漏区底部的宽度,所述沟槽的开口尺寸大于所述抬高源区底部的宽度或所述抬高漏区底部的宽度。
8.如权利要求7所述的半导体结构,其特征在于,两个沟槽位于同一有源区中;所述有源区的尺寸范围为20nm-145nm;所述沟槽的宽度范围为5nm-25nm,所述沟槽的深度范围为10nm-30nm。
9.如权利要求8所述的半导体结构,其特征在于,所述沟槽的深宽比小于3:1。
10.如权利要求7所述的半导体结构,其特征在于,所述抬高源区或所述抬高漏区的厚度范围为5-100nm。
11.如权利要求7所述的半导体结构,其特征在于,所述栅极结构的上表面和所述有源区的上表面齐平。
12.如权利要求7所述的半导体结构,其特征在于,阻挡层,所述阻挡层位于所述栅极结构上方,所述阻挡层的上表面与所述有源区的上表面齐平。
13.如权利要求12所述的半导体结构,其特征在于,所述阻挡层的厚度范围为1nm-10nm,或者所述阻挡层的厚度为所述沟槽的深度的1/10-1/5。
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