WO2024036828A1 - 存储器及其制造方法、读写控制方法 - Google Patents

存储器及其制造方法、读写控制方法 Download PDF

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Publication number
WO2024036828A1
WO2024036828A1 PCT/CN2022/137314 CN2022137314W WO2024036828A1 WO 2024036828 A1 WO2024036828 A1 WO 2024036828A1 CN 2022137314 W CN2022137314 W CN 2022137314W WO 2024036828 A1 WO2024036828 A1 WO 2024036828A1
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source
semiconductor layer
transistor
layer
memory
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PCT/CN2022/137314
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English (en)
French (fr)
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李辉辉
张云森
王桂磊
赵超
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北京超弦存储器研究院
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Publication of WO2024036828A1 publication Critical patent/WO2024036828A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • the present application relates to the field of semiconductor technology. Specifically, the present application relates to a memory, a manufacturing method thereof, and a read-write control method.
  • MRAM Magneticoresistive Random Access Memory
  • MRAM memory cells in MRAM have a problem of low on-state current, which results in slow reading and writing speeds of the memory cells and affects the performance of MRAM.
  • This application proposes a memory, a manufacturing method thereof, a memory control method, and an electronic device, at least to improve the deficiencies in the background technology.
  • Some embodiments of the present application provide a memory, including:
  • the memory unit includes a transistor and a magnetic tunnel junction, one end of the magnetic tunnel junction is electrically connected to the transistor;
  • the transistor is a dual-channel transistor, including a first channel and a second channel;
  • one word line being electrically connected to each gate of the transistor in the same row of memory cells;
  • bit lines one bit line being electrically connected to the other end of each magnetic tunnel junction in the same column of memory cells;
  • the sources of each transistor in a column of memory cells are electrically connected to two adjacent source lines at the same time.
  • the two adjacent source lines are electrically connected to the first channel and the second channel respectively through the source electrodes.
  • Some embodiments of the present application provide a memory read and write control method, including:
  • the word line controls the transistor in the memory cell to be read to be in the on state, and the read signal is transmitted to the magnetic tunnel junction of the memory cell to be read through one of the bit lines or a source line, so that the bit line or another sensing magnetic tunnel junction in one source line to store data;
  • the word line is used to control the transistor in the memory cell to be written to be in the on state
  • the bit line and two source lines are used to control the direction of the storage signal flowing through the magnetic tunnel junction in the memory cell to be written to turn the bit line Or the storage signal transmitted by the source line is written into the magnetic tunnel junction.
  • Some embodiments of the present application provide a memory manufacturing method, including:
  • each first trench is flanked by stacked source rows, first sacrificial structure rows and drain rows;
  • the first sacrificial structure row exposed on the side of the first trench is etched back to form a sacrificial structure row, and the sidewalls of the source row, sacrificial structure row and drain row form a U-shaped trench;
  • a semiconductor material layer is formed in the U-shaped trench
  • Patterning the transistor row area forming a plurality of second trenches perpendicular to the first trench to distinguish a plurality of transistor areas, each transistor area including a source electrode formed by stacked source electrode rows, and a semiconductor layer formed by a semiconductor material layer and a drain electrode formed by the drain electrode row; the sacrificial structure formed by the sacrificial structure row is arranged in the same layer as the semiconductor layer and is located between the first semiconductor layer and the second semiconductor layer included in the semiconductor layer;
  • a magnetic tunnel junction and a bit line are formed in sequence on the side of the drain away from the substrate.
  • the transistor of the memory unit by configuring the transistor of the memory unit to be a dual-channel transistor, the on-state current of the transistor can be increased, the read and write speed of the memory unit can be increased, and the performance of the memory can be improved.
  • each memory cell is configured with two source lines, and the two adjacent source lines are electrically connected to the first channel and the second channel of the transistor through the source electrodes, thereby reducing the current of each source line, thus It can reduce the impact of current flowing through the source line on other components of the memory.
  • Figure 1 is a schematic circuit diagram of a memory provided by an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of a memory provided by an embodiment of the present application.
  • Figure 3 is a schematic structural diagram of the AA-direction cross-section of the memory shown in Figure 1 provided by an embodiment of the present application;
  • Figure 4 is a schematic flow chart of a memory manufacturing method provided by an embodiment of the present application.
  • Figure 5 is a schematic structural diagram of the first photoresist structure and the first mask structure obtained in the memory manufacturing method according to the embodiment of the present application;
  • Figure 6 is a schematic structural diagram after obtaining the initial stacked structure in the manufacturing method of the memory provided by the embodiment of the present application;
  • Figure 7 is a schematic structural diagram after obtaining the first arc-shaped groove in the manufacturing method of the memory provided in the embodiment of the present application;
  • Figure 8 is a schematic structural diagram after obtaining a metal layer in the manufacturing method of a memory according to an embodiment of the present application.
  • Figure 9 is a schematic structural diagram after bit lines are obtained in the manufacturing method of a memory according to an embodiment of the present application.
  • Figure 10 is a schematic structural diagram after obtaining the first flat layer in the manufacturing method of the memory provided in the embodiment of the present application;
  • Figure 11 is a schematic structural diagram of the memory manufacturing method after removing the first mask structure according to the embodiment of the present application.
  • Figure 12 is a schematic structural diagram of a stacked structure obtained in a memory manufacturing method according to an embodiment of the present application.
  • Figure 13 is a schematic structural diagram after obtaining the semiconductor material layer in the manufacturing method of the memory provided in the embodiment of the present application;
  • Figure 14 is a schematic structural diagram after obtaining the second flat layer in the manufacturing method of the memory provided in the embodiment of the present application;
  • Figure 15 is a BB-direction cross-sectional structural schematic diagram after the mask structure is produced from the structure shown in Figure 14 in the memory manufacturing method provided in the embodiment of the present application;
  • Figure 16 is a schematic structural diagram of a semiconductor layer produced based on the structure shown in Figure 15 in a memory manufacturing method according to an embodiment of the present application;
  • Figure 17 is a schematic structural diagram after word lines are formed in the manufacturing method of a memory according to an embodiment of the present application.
  • Figure 18 is a schematic structural diagram after forming a connection structure in a memory manufacturing method according to an embodiment of the present application.
  • FIG. 19 is a schematic structural diagram after forming an encapsulation layer in a memory manufacturing method according to an embodiment of the present application.
  • 200-memory cell 201-word line; 2011-first sub-segment; 2012-second sub-segment; 202-bit line; 203-source line; 2031-first source line; 2032-second source line; 2033- Metal silicide sub-layer; 2034-metal sub-layer;
  • MRAM is a non-volatile magnetic random access memory.
  • the data stored in MRAM is stored in a magnetic state instead of charges.
  • the polarity of the magnetic field does not change with the charge like charges. leaks over time, so information is retained even in the event of a power outage.
  • MRAM often includes multiple memory cells arranged in an array, and each memory cell needs to be provided with bit lines, word lines and bit lines.
  • the size of the transistors in the memory unit is getting smaller and smaller.
  • the on-state current of the transistor is smaller, which in turn leads to lower driving performance and slower turn-on speed of the transistor, affecting the read and write speed of the memory unit, thereby affecting the performance of the memory.
  • the manufacturing precision of the semiconductor structure and gate of the vertical transistor in the MRAM memory unit is low, which leads to differences in the performance of the VGAA transistors in the memory and affects the performance of the memory.
  • vertical transistors face the bottleneck of further increasing the driving current. For example, as the size of the vertical transistor decreases, the on-state current of the vertical transistor decreases, which in turn reduces the driving performance of the transistor and causes a slower turn-on speed, which in turn affects the performance of the memory.
  • the memory, its manufacturing method, and the read and write control method provided by this application are intended to solve the above technical problems of the prior art.
  • FIG. 1 An embodiment of the present application provides a memory.
  • the schematic circuit diagram of the memory is shown in Figure 1.
  • the memory includes: multiple memory cells 200, multiple word lines 201, multiple bit lines 202, and multiple source lines 203.
  • the memory unit 200 includes a transistor 10 and a magnetic tunnel junction 20. One end of the magnetic tunnel junction 20 is electrically connected to the transistor 10.
  • the transistor 10 is a dual-channel transistor, including a first channel and a second channel.
  • One word line 201 is electrically connected to each gate 13 of the transistor 10 in the same row of memory cells 200; one bit line 202 is electrically connected to the other end of each magnetic tunnel junction 20 in the same column of memory cells 200; each transistor in one column of memory cells 200
  • the source electrode 11 of 10 is electrically connected to two adjacent source lines 203 at the same time, and the two adjacent source lines 203 are electrically connected to the first channel and the second channel respectively through the source electrode 11.
  • the transistor 10 of the memory unit 200 by configuring the transistor 10 of the memory unit 200 to be a dual-channel transistor, the on-state current of the transistor 10 can be increased, the read and write speed of the memory unit 200 can be increased, and the performance of the memory can be improved.
  • each memory cell 200 is configured with a word line 201, a bit line 202 and two source lines 203.
  • the two adjacent source lines 203 are respectively connected to the first channel and the second channel of the transistor 10 through the source electrode 11. Therefore, the current of each source line 203 can be reduced, thereby reducing the impact of the current flowing through the source line 203 on other components of the memory.
  • the plurality of memory cells 200 are arranged in an array, that is, the transistors 10 of each memory unit 200 are arranged in an array. It is defined herein that the direction extending parallel to the word line 201 is a row, and the direction parallel to the source line 203 is a column. As shown in Figure 1, the direction from left to right is a row, and the direction from top to bottom is a column. Figure 1 exemplarily shows two memory cells in the same row, that is, two memory cells are shown respectively. One memory unit 200 for each of the column memory units 200 .
  • each memory cell 200 includes a transistor 10 and a magnetic tunnel junction 20 , and the transistor 10 and the magnetic tunnel junction 20 are electrically connected.
  • one end of the magnetic tunnel junction 20 is electrically connected to the drain 14 of the transistor 10 .
  • the transistor 10 is a dual-channel vertical transistor 10. Compared with a single-channel transistor, the on-state current of the transistor 10 can be significantly increased, and the driving capability and driving ability of the transistor 10 can be improved.
  • the opening speed can increase the speed of data writing and data reading of the storage unit 100, thereby improving the performance of the memory.
  • two adjacent source lines 203 are electrically connected to the first channel and the second channel of the transistor 10 respectively through the source electrode 11, which is equivalent to each transistor 10 including two parallel-connected sub-transistors. Therefore, while increasing the on-state current of the transistor 10, the current passing through each sub-transistor can be reduced, thereby reducing the loss rate of the transistor 10 and extending the service life of the transistor 10.
  • the other end of the magnetic tunnel junction 20 is electrically connected to the bit line 202
  • the gate electrode 13 of the transistor 10 in each memory cell 200 in the same row is electrically connected to the word line 201 .
  • the word line 201 is used to control the transistor 10 to turn on
  • the data reading of a column of memory cells 200 can be controlled through a source line 203 and a bit line 202
  • a column of storage can be controlled through two source lines 203 and a bit line 202.
  • Unit 200 data is written.
  • the magnetic tunnel junction 20 includes a MTJ (Magnetic Tunnel Junctions), and the MRAM determines whether the stored data is "0" or "1” by detecting the resistance of the MTJ.
  • MTJ Magnetic Tunnel Junctions
  • the MTJ includes a free layer, a tunneling layer and a fixed layer stacked in sequence.
  • the direction of the magnetic field of the free layer can be changed, while the direction of the magnetic field of the fixed layer is fixed. Under the action of the electric field, electrons will pass through the tunnel layer barrier and pass through the device vertically.
  • the MTJ presents a low resistance state "0".
  • the magnetic field direction of the free layer is opposite to that of the fixed layer, the MTJ presents a high resistance state "1".
  • the source lines 203 electrically connected to the same column of memory cells 200 along the first direction of the parallel substrate 100 are respectively the first source line 2031 and the first source line 2031 .
  • An isolation structure 51 is provided between 2031.
  • the source lines 203 electrically connected to the memory cells 200 in the same column are the first source line 2031 and the second source line 2032 respectively.
  • an isolation structure 51 is provided between the second source line 2032 connected to each source 11 of one column of memory cells 200 and the first source line 2031 connected to each source 11 of another column of memory cells 200, so that the The source lines 203 connected to each column of memory cells 200 are insulated from each other.
  • the isolation structure 51 is used as a part of the media structure 50 .
  • the transistor 10 is a vertical transistor 10 , and the transistor 10 and the magnetic tunnel junction 20 are stacked in a direction vertical to the substrate 100 .
  • FIG. 2 it is a schematic structural diagram of a memory provided by the embodiment of the present application.
  • four complete source lines 203 are shown, and the storage unit 200 is disposed on the source lines 203.
  • each memory cell 200 is configured with one word line 201, one bit line 202 and two source lines 203.
  • the transistor 10 and the magnetic tunnel junction 20 of each memory cell 200 in the memory are stacked in a direction vertical to the substrate 100 .
  • the transistor 10 is a vertical transistor 10. As shown in FIG. 2, the source electrode 11, the semiconductor structure 12 and the drain electrode 14 are stacked in sequence along the direction perpendicular to the substrate 100.
  • the gate electrode 13 is also located between the source electrode 11 and the drain electrode 14 , that is, the gate electrode 13 and the semiconductor structure 12 are arranged in the same layer.
  • the transistor 10 includes a source electrode 11 , a semiconductor layer 12 and a drain electrode 14 which are sequentially stacked on the substrate 100 ;
  • the semiconductor layer 12 includes a first The semiconductor layer 121 and the second semiconductor layer 122, the first semiconductor layer 121 and the second semiconductor layer 122 are spaced apart on the same side of the source electrode 11 and are in contact with the source electrode 11 respectively;
  • the first semiconductor layer 121 includes a first channel, and the second semiconductor layer 122 is in contact with the source electrode 11.
  • the semiconductor layer 122 includes a second channel; at least part of the gate 13 is located in a spaced area between the first semiconductor layer 121 and the second semiconductor layer 122 .
  • the source electrode 11 , the semiconductor layer 12 and the drain electrode 14 are stacked in sequence.
  • the gate electrode 13 is also located between the source electrode 11 and the drain electrode 14 , that is, the gate electrode 13 and the semiconductor layer 12 are arranged in the same layer.
  • the first semiconductor layer 121 and the second semiconductor layer 122 are spaced apart on the same side of the source electrode 11 and are respectively in contact with the source electrode 11 .
  • the first semiconductor layer 121 includes a first channel when turned on, and the second semiconductor layer 122 includes a second channel when turned on. That is, the transistor 10 is a dual-channel vertical transistor.
  • the gate 13 includes a first gate 13 and a second gate 13 connected to each other; the first gate 131 is located on the first semiconductor layer 121
  • the second gate electrode 132 is disposed on the outer side walls of the first semiconductor layer 121 and the second semiconductor layer 122 and is connected to the first semiconductor layer 121 and the second semiconductor layer 122 .
  • the source electrode 11 and the drain electrode 14 are insulated.
  • the gate 13 includes a first gate 13 and a second gate 13; the first gate 13 is disposed between the two first semiconductor layers 121 and the second semiconductor layer 122, and is in contact with the first semiconductor layer 121. , the second semiconductor layer 122, the source electrode 11 and the drain electrode 14 are insulated; the second gate electrode 13 is disposed on the outer wall of the semiconductor layer 12 and is insulated from the semiconductor layer 12, the source electrode 11 and the drain electrode 14.
  • the transistor 11 further includes a gate insulating layer 15 .
  • the gate insulating layer 15 is made of a high-k value dielectric material.
  • the gate insulating layer 15 includes a first gate insulating layer 151 and two second gate insulating layers 152 .
  • the first gate insulating layer 151 conforms to the inner walls of the source 11 , the first semiconductor layer 121 and the second semiconductor layer 122 , and the peripheral wall of the cavity formed by the drain electrode 14 ;
  • the second gate insulating layer 152 conforms to the source 11
  • the electrode 11, the outer side walls of the first semiconductor layer 121 and the second semiconductor layer 122, and the peripheral wall of the groove formed by the drain electrode 14 conform to the shape.
  • the first gate 131 of the gate 13 is located between two spaced apart semiconductor layers 12 .
  • the first gate 131 is provided on the first gate insulating layer. 151 encloses the formed cavity, so that the first gate electrode 131 is insulated from the semiconductor layer 12 , the source electrode 11 and the drain electrode 14 .
  • the second gate 132 of the gate 13 is located on the outer wall of the semiconductor layer 12 .
  • the second gate 132 is disposed in a groove formed by the second gate insulating layer 152 .
  • the second gate electrode 132 is insulated from the semiconductor layer 12 , the source electrode 11 and the drain electrode 14 .
  • both the first gate 13 and the second gate 13 are connected to the word line 201 .
  • the word line 201 extends along a first direction parallel to the substrate 100 .
  • the source line 203 extends along a second direction parallel to the substrate 100 . The direction is perpendicular to the second direction.
  • the extension direction of the bit line 202 is parallel to the extension direction of the source line 203 .
  • the first gate 131 and the second gate 132 of the gate 13 are both connected to the word line 201, so that the first gate 131 and the second gate 132 can be connected to the first gate 131 and the second gate 132 through the word line 201.
  • Applying a voltage level to the second gate 132 at the same time can further enhance the electric field strength of the gate 13, which can help to increase the on-state current of the transistor 10, thereby helping to improve the driving capability and turn-on speed of the transistor 10, which can help Improving the reading and writing speed of the storage unit 200 helps to improve the performance of the memory.
  • the word line 201 extends along a first direction parallel to the substrate 100 .
  • the source line 203 extends along a second direction parallel to the substrate 100 . The direction is perpendicular to the second direction.
  • the extension direction of the bit line 202 is parallel to the extension direction of the source line 203 .
  • the first gate 131 and the second gate 132 of the gate 13 are both connected to the word line 201, so that the first gate 131 and the second gate 132 can be connected to the first gate 131 and the second gate 132 through the word line 201.
  • Applying a voltage level to the second gate 132 at the same time can further enhance the electric field strength of the gate 13, thereby helping to increase the on-state current of the transistor 10, thereby helping to improve the driving capability and turn-on speed of the transistor 10, which helps Improving the reading and writing speed of the storage unit 200 helps to improve the performance of the memory.
  • the source electrode 11 is based on silicon doping, and the conductivity of the source electrode 11 is smaller than the conductivity of the source line 203 .
  • the source line 203 includes a metal silicide sub-layer 2033 and a metal sub-layer 2034.
  • the metal silicide sub-layer 2033 is connected to the source electrode 11; the cross-section of the metal silicide sub-layer 2033 is an arc shape, and the arc-shaped metal silicide sub-layer 2033 is connected to the source electrode 11.
  • the material sub-layer 2033 surrounds part of the metal sub-layer 2034.
  • the source line 203 includes a metal silicide sub-layer 2033 and a metal sub-layer 2034.
  • the material of the metal silicide sub-layer 2033 is metal silicide, and the material of the metal sub-layer 2034 is metal. Therefore, the size of the source line 203 can be increased, the resistance of the source line 203 can be reduced, the conductivity of the source line 203 can be improved, the transmission efficiency of electrical signals can be ensured, and the power consumption of the memory can be reduced.
  • the metal silicide sub-layer 2033 and the metal sub-layer 2034 include the same metal element.
  • the metal silicide sub-layer 2033 has an arc-shaped cross section, and the arc-shaped metal silicide sub-layer 2033 surrounds part of the metal sub-layer 2034 to prevent the metal sub-layer 2034 from being directly connected to the source electrode 11 .
  • the word line 201 includes a plurality of first sub-segments 2011 and second sub-segments 2012 connected alternately in sequence; the first sub-segments 2011 surround the first gate 13 and the second gate 13, and The first gate 13 and the second gate 13 are both connected; one end of the second sub-section 2012 is connected to one first sub-section 2011, and the other end is connected to another first sub-section 2011.
  • the first sub-segments 2011 and the second sub-segments 2012 are connected alternately in sequence.
  • the first sub-section 2011 is arranged around the first gate 131 and the second gate 132, that is, the first sub-section 2011 wraps the two end surfaces of the first gate 131 and both end surfaces of the second gate 132, thereby being connected to both the first gate 131 and the second gate 132.
  • the upper surface of the first sub-section 2011 is flush with the upper surface of the first gate 131 , thereby preventing the first sub-section 2011 from contacting the drain 14 of the transistor 10 .
  • the second subsection 2012 is located between two adjacent transistors 10 and is used to connect the first subsection 2011 surrounding the first gate 131 and the second gate 132 .
  • the upper surface of the second sub-segment 2012 is flush with the upper surface of the first sub-segment 2011, which can reduce the probability of the second sub-segment 2012 contacting the drain 14 of the transistor 10, and can reduce the probability of parasitic capacitance between the two, and thus Able to ensure memory performance.
  • first sub-segment 2011 and the second sub-segment 2012 are shown with dotted lines in FIGS. 2 and 3
  • the first sub-segment 2011, the second sub-segment 2012 and the gate 13 are made of the same material. Formed, there is no dashed line as shown in Figures 2 and 3.
  • the projection of the outer contours of the source electrode 11 and the drain electrode 14 on the substrate, the outer contour surrounding the first semiconductor layer 121, the second semiconductor layer 122 and the first gate electrode 13 are projected on the substrate.
  • the projection on the bottom causes the source electrode 11 and the drain electrode 14 to protrude outward relative to the semiconductor structure and the first gate electrode 13 .
  • the orthographic projection of the outer contour of the drain 14 of the source 11 on the substrate 100 surrounds the first semiconductor layer 121 , the second semiconductor layer 122 and the first gate.
  • the orthographic projection of the outer contour of the electrode 131 on the substrate 100 causes the source electrode 11 and the drain electrode 14 to protrude outward relative to the semiconductor structure 12 and the first gate electrode 131 .
  • the cross-sectional pattern formed by the combination of the source electrode 11 , the first semiconductor layer 121 , the second semiconductor layer 122 , the first gate electrode 131 and the drain electrode 14 is an I-shape.
  • the projection of the outer contours of the source electrode 11 and the drain electrode 14 on the substrate overlaps with the projection of the outer contour of the second gate electrode 13 on the substrate.
  • the orthographic projection of the outer contours of the electrode 11 and the drain electrode 14 on the substrate 100 overlaps with the orthographic projection of the outer contour of the second gate electrode 132 on the substrate 100 , so that the source The outer side walls of the electrode 11 and the drain electrode 14 are flush with the outer side walls of the second gate electrode 132 .
  • the memory unit 200 further includes: a connection structure 40 disposed on the side of the drain 14 of the transistor 10 away from the source 11 ; a magnetic tunnel junction 20 is disposed on the side of the connection structure away from the drain 14 .
  • the transistor 10 and the connection structure 40 are stacked in a direction perpendicular to the substrate 100 , and the connection structure 40 is provided on the side of the drain electrode 14 of the transistor 10 away from the source electrode 11 .
  • connection structure 40 is used to realize the electrical connection between the transistor 10 and the magnetic tunnel junction 20 .
  • This facilitates the separate production of the transistor 10 and the magnetic tunnel junction 20.
  • first use a production line to sequentially form the source line 203, the transistor 10, the word line 201 and the connection structure 40 on one side of the substrate 100, and then use another production line.
  • the wires form a magnetic tunnel junction 20, thereby enabling memory production efficiency to be improved.
  • connection structure 40 includes a suicide structure 41 and a metal structure 42. Since the drain electrode 14 is mostly made of doped semiconductor materials, there is a significant difference in conductivity between the drain electrode 14 and the metal structure 42 . By providing the silicide structure 41 , the interface resistance between the metal structure 42 and the drain electrode 14 can be reduced. The performance of the storage unit 200 can be guaranteed.
  • the memory also includes a dielectric structure 50 , which can be made of the same dielectric material as the insulating layer 15 .
  • the connection structure 40 is disposed in the opening of the media structure 50 .
  • a hard mask structure 30 is provided on the side of the magnetic tunnel junction 20 away from the substrate 100 .
  • the hard mask structure 30 can protect the magnetic tunnel.
  • the hard mask structure 30 includes metal and dielectric materials. Therefore, the hard mask structure 30 has certain electrical conductivity.
  • the hard mask structure 30 is connected to the bit line 202 to realize the connection between the bit line 202 and the magnetic tunnel junction 20 . Electrical connection.
  • the hardness of the hard mask structure 30 is relative to the hardness of the photoresist, and the materials of the hard mask structure 30 include silicon oxide, silicon nitride, etc.
  • an encapsulation layer 60 is provided on the side of the hard mask structure 30 away from the substrate 100 .
  • the encapsulation layer 60 covers the side walls of the magnetic tunnel junction 20 to avoid external water, oxygen, etc. Eroding the magnetic tunnel junction20.
  • the material of the encapsulation layer 60 includes dense materials such as silicon nitride, aluminum oxide, and magnesium oxide.
  • the cross-sectional shape of the source line 203 is arc-shaped, and one side of the source electrode 11 of each transistor 10 in a column of memory cells 200 is connected to a The arc-shaped source line 203 is connected, and the other side of the source electrode 11 of each transistor 10 in the same column of memory cells 200 is connected to another arc-shaped source line 203, so that each column of memory cells 200 is connected to two source lines 203.
  • a source line 203 with an arc-shaped cross-section can avoid right-angled portions of the source line 203, thereby avoiding the tip effect. Able to ensure memory performance.
  • embodiments of the present application provide an electronic device, including any memory as provided in the above embodiments.
  • the electronic device includes a smartphone, computer, tablet, artificial intelligence device, wearable device or power bank.
  • electronic devices are not limited to the above-mentioned types. Persons skilled in the art can install any of the memories provided by the above embodiments of the present application in different devices according to actual application requirements, thereby obtaining the results of the present application.
  • the electronic device provided by the embodiment provided by the embodiment.
  • embodiments of the present application provide a memory control method, which includes: during the reading phase, controlling the transistor in the memory cell to be read to be in a conductive state through a word line, and controlling the transistor in the memory cell to be read through a bit line or a source line.
  • the transistor in the unit is in a conductive state, and the direction of the storage signal flowing through the magnetic tunnel junction in the memory unit to be written is controlled through the bit line and the two source lines, so that the storage signal transmitted by the bit line or the source line is written into the magnetic tunnel junction.
  • the memory control method provided by the embodiment of the present application can be used for any memory provided by the above-mentioned embodiments.
  • the first level is input to the gate 13 of the transistor 10 in the memory cell 200 to be read through the word line 201, so that the transistor 10 is in a conductive state, and the first level is input through a bit line 202 or
  • a source line 203 senses changes in current or voltage and the extent of the changes to realize reading of data stored in the magnetic tunnel junction 20 .
  • the following takes sensing current changes through the source line 203 as an example to illustrate how to realize data storage and reading in the magnetic tunnel junction 20 .
  • the MTJ presents a high resistance state at this time.
  • the read signal is transmitted to the magnetic tunnel junction 20 through a bit line 202, that is, to the magnetic tunnel through the bit line 202
  • a second level is applied to the junction 20, and a source line 203 remains at the reference level.
  • the reference level is less than the second level. Since the MTJ presents a high resistance state, the current is difficult to pass through the magnetic tunnel junction 20, that is, the source line 203 is difficult to measure. There is an obvious current.
  • the read data is judged to be "1”, that is, the data stored in the magnetic tunnel junction 205 of the memory cell 200 to be read can be sensed as "1" through a source line 203.
  • the MTJ When the data stored in the magnetic tunnel junction 20 is "0", the MTJ presents a low resistance state at this time.
  • a read signal is transmitted to the magnetic tunnel junction 20 through a bit line 202, that is, a read signal is applied to the magnetic tunnel junction 20 through the bit line 202.
  • a source line 203 At the second level, a source line 203 remains at the reference level. The reference level is lower than the second level. Since the MTJ presents a low resistance state, the current can pass through the magnetic tunnel junction 20, that is, a relatively obvious current can be measured by the source line 203. , in this case, it is determined that the read data is “0”, that is, through a source line 203, it can be sensed that the data stored in the magnetic tunnel junction 20 of the memory unit 200 to be read is “0”.
  • the first level is input to the gate 13 of the transistor 10 in the memory cell 200 to be read through the word line 201, so that the transistor 10 is in a conductive state, and the first level is input through the bit line 202 and the two
  • the source lines 203 control the direction of the storage signal flowing through the magnetic tunnel junction 20 in the memory cell 200 to be written, so that the storage signal transmitted by the bit line 202 or the source line 203 is written into the magnetic tunnel junction 20 .
  • the following takes the transmission of a storage signal to the memory unit 200 to be written through the source line 203 as an example to illustrate how to implement data storage in the magnetic tunnel junction 20 .
  • the third level is applied to the source 11 of the transistor 10 of the memory cell 200 to be written through the source line 203, the bit line 202 is maintained at the reference level, and the third level is greater than Reference level, since the third level is applied to both source lines 203, the potential difference between the two ends of the magnetic tunnel junction 20 is large enough, and the current including the storage signal flows from the source line 203 to the bit line 202, and when the current flows through the magnetic tunnel During the process of junction 20, the magnetic field direction of the free layer of the magnetic tunnel junction 20 will change and be opposite to the magnetic field direction of the fixed layer, so that the magnetic tunnel junction 20 assumes a high-resistance state "1", thereby realizing the storage of data "1".
  • the magnetic tunnel junction 20 exhibits a low-resistance state of "0", thereby realizing the storage of data "0".
  • the write current in MRAM is usually more than ten times the read current. If a single-channel transistor is used, the current flowing through the transistor during the write phase is larger. As the frequency of use increases, It will greatly accelerate the loss rate of single-channel transistors and reduce the service life of single-channel transistors. Therefore, in the embodiment of the present application, by arranging the dual-channel vertical transistor 10, the current passing through each sub-transistor can be reduced, thereby reducing the loss rate of the transistor 10 and extending the service life of the transistor 10.
  • each memory cell 200 is electrically connected to two source lines 203, and the transistor 10 is a dual-channel transistor.
  • the two source lines 203 are respectively located on both sides of the transistor 10. side, which is equivalent to each source line 203 being electrically connected to a sub-transistor of the transistor 10.
  • a source line 203 senses changes in current or voltage and the degree of change, which is equivalent to only one sub-transistor in the transistor 10 being in working status.
  • both source lines 203 apply a third level to the source 11 of the transistor 10 of the memory cell 200 to be written, that is, both sub-transistors in the transistor 10 are in the working state, thereby increasing the transistor size. While reducing the on-state current of 10, the current passing through each sub-transistor can be reduced, thereby reducing the loss speed of the transistor 10 and extending the service life of the transistor 10.
  • the current of each source line 203 can be reduced, thereby reducing the impact of the current flowing in the source line 203 on other components of the memory.
  • FIG. 4 A schematic flow chart of the method is shown in Figure 4. The method includes the following steps S401-S403:
  • S401 Form a plurality of first trenches on the substrate through a patterning process to distinguish multiple transistor row areas.
  • the sides of each first trench are stacked source rows, first sacrificial structure rows and drain rows. .
  • S402 Form two mutually insulated source lines in the first trench through an annealing process and a patterning process, at least part of the source lines being located below the source row.
  • the first sacrificial structure row exposed on the side of the first trench is etched back to form a sacrificial structure row, and the side walls of the source row, sacrificial structure row and drain row form a U-shaped trench.
  • Each transistor area includes a source formed by a stacked source row and a semiconductor material layer.
  • the drain electrode formed by the semiconductor layer and the drain electrode row; the sacrificial structure formed by the sacrificial structure row is arranged on the same layer as the semiconductor layer and is located between the first semiconductor layer and the second semiconductor layer included in the semiconductor layer.
  • S407 Fill the hole and the sidewalls of the first semiconductor layer and the second semiconductor layer with conductive material through a plating process, and pattern the conductive material to form a gate electrode and a word line connected to the gate electrode.
  • S408 Form a magnetic tunnel junction and a bit line in sequence on the side of the drain away from the substrate.
  • At least one memory provided in the above embodiments can be manufactured by using the memory manufacturing method provided in the embodiments of the present application.
  • two mutually insulated source lines are formed before the transistor, which can prevent the annealing process from affecting subsequent transistors and ensure the manufacturing yield of the transistor; at the same time, during the manufacturing process, through Setting up the first sacrificial structure row and intermediate structures such as the sacrificial structure facilitates precise control of the dimensions of the semiconductor layer and gate in the subsequently manufactured transistor, thereby ensuring the manufacturing accuracy of the transistor and thus ensuring the transistor performance of each memory unit in the memory. Uniformity, thereby ensuring memory performance.
  • a plurality of first trenches 117 are formed on the substrate 100 through a patterning process to distinguish multiple transistor row regions, and each first trench 117
  • the side surface of The semiconductor layer 102 and the second silicon-doped conductive layer 103; the source row 1011, the first sacrificial structure row 1021 and the drain row 1031 are respectively based on the first silicon-doped conductive layer 101, the sacrificial semiconductor layer 102 and the second silicon-doped Conductive layer 103 is formed.
  • the first silicon-doped conductive layer 101, the sacrificial semiconductor layer 102, and the second silicon-doped conductive layer 103 are sequentially formed on one side of the substrate 100 through an epitaxial growth process, as shown in FIG. 5 .
  • the first silicon-doped conductive layer 101 and the second silicon-doped conductive layer 103 are made of doped semiconductor materials.
  • both the first silicon-doped conductive layer 101 and the second silicon-doped conductive layer 103 are N-type doped, and the doping degree can be determined according to the specific manufacturing process or requirements;
  • the sacrificial semiconductor layer 102 is GeSi (silicon). germanium).
  • the thickness of each film layer can be accurately controlled, especially the thickness of the sacrificial semiconductor layer 102 can be accurately controlled. Controlling the dimensions of the subsequently manufactured semiconductor structure 12 and gate 13 can ensure the manufacturing accuracy of the transistor, thereby ensuring the uniformity of transistor performance of each memory unit in the memory, and thus ensuring the performance of the memory.
  • deposition processes such as CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), and ALD (Atomic Layer Deposition) can also be used to manufacture each film layer structure.
  • CVD Chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • ALD Atomic Layer Deposition
  • the second silicon-doped conductive layer 103 may also include: forming a first photoresist structure 104 on a side of the second silicon-doped conductive layer 103 away from the substrate 100, and performing the first photolithography step.
  • the two side walls of the glue structure 104 form a first mask structure 105, as shown in FIG. 5 .
  • the first mask structure 105 may be made of silicon oxide.
  • a plurality of first trenches 117 are formed on the substrate 100 through a patterning process to distinguish multiple transistor row regions, and each first trench 117
  • the side is the stacked source row 1011, the first sacrificial structure row 1021 and the drain row 1031, including: removing the first photoresist structure 104, etching the second silicon doped conductive layer 103 with the first mask structure 105 , the sacrificial semiconductor layer 102, the first silicon-doped conductive layer 101 and part of the substrate 100, forming a plurality of initial stacked structure rows 106 spaced apart from each other.
  • the initial stacked structure rows 106 are the transistor row regions, and the first trench 117 is used to separate two any adjacent initial stacked structure rows 106 .
  • the first mask structure 105 By setting the first mask structure 105 as a hard mask, self-aligned etching can be achieved during etching of the second silicon-doped conductive layer 103, the sacrificial semiconductor layer 102, and the first silicon-doped conductive layer 101. function to ensure the accuracy of etching.
  • the row of initial stacked structures 106 extends along a second direction.
  • the second direction is parallel to the substrate 100 and perpendicular to the first direction.
  • the first direction is the extension direction of the source line 203 .
  • a plurality of initial stacked structures The rows 106 are spaced apart along the first direction; the initial stacked structure row 106 includes a stacked source row 1011 , an initial sacrificial structure row 1021 and a drain row 1031 .
  • step S401 after the above step S401, it further includes: forming a protective layer covering the top wall and side wall of the initial stacked structure row 106.
  • the protective layer can protect the initial stacked structure rows 106 and prevent the initial stacked structure rows 106 from being etched or doped.
  • the protective layer is made of silicon oxide.
  • two mutually insulated source lines 203 are formed in the first trench 117 through an annealing process and a patterning process, and at least part of the source lines 203 is located in the source row.
  • it includes: etching the substrate 100 along the bottom of the first trench 117 to form a first arc-shaped trench 108 connected to the first trench 117; 117 is filled with metal material, and an annealing process is used to process the metal material to form a source line structure with part of the surface conforming to the first arc-shaped groove 108; the source line structure is patterned to form two source lines 203 that are separated from each other. details as follows:
  • a portion of the substrate 100 is etched along the bottom of the first trench 117 to form a first arc-shaped trench 108 connected to the first trench 117 .
  • the first arc-shaped groove 108 partially extends below two adjacent stacked structure rows 106 .
  • a protective structure 1071 is formed.
  • metal materials such as titanium, cobalt and other metal materials, are filled in the first arc-shaped groove 108 and part of the first trench 117 to form a metal layer 109, as shown in FIG. 8 .
  • the metal layer 109 completely fills the first arc-shaped groove 108 and partially fills the first trench 117.
  • the upper surface of the metal layer 109 is planar with the upper surface of the initial sacrificial structure row 1021 of the initial stacked structure row 106. aligned, so that the subsequently formed source line 203 can contact the source row 1011.
  • an annealing process is used to process the metal layer 109, so that the metal layer 109 reacts with part of the substrate 100 and part of the source rows 1011 to form a source line structure including a metal silicide sublayer, and part of the surface of the source line structure is in contact with the first arc.
  • the shaped groove 108 follows the shape.
  • the source line structure is patterned to form two source lines 203 that are separated from each other.
  • a portion of the substrate 100 is etched so that the two source lines 203 formed with the same source line structure can be insulated from each other.
  • the unreacted portion of the metal layer 109 surrounded by the arc-shaped metal silicide sub-layer in the source line 203 is then retained to form a metal sub-layer 2034, thereby ensuring the conductivity of the source line 203.
  • At least part of the source line 203 is located below the source row 1011 .
  • the method further includes: filling the first arc-shaped groove 108 with dielectric material, forming a Barrier structure 51 between source lines 203 .
  • a deposition process is used to deposit a dielectric material, such as silicon oxide, and a CMP (Chemical Mechanical Polishing) process is used to form the first flat layer 111, as shown in Figure 10.
  • a CMP (Chemical Mechanical Polishing) process is used to form the first flat layer 111, as shown in Figure 10.
  • the protective structure 1071 and the first flat layer 111 are made of the same material, so in FIG. 10 the first flat layer 111 is used to represent both, and the protective structure 1071 is not marked.
  • first flat structure 1111 is used to form the barrier structure 51.
  • the specific process of forming the barrier structure 51 by the first flat structure 1111 will be described in detail later and will not be described again here.
  • the first sacrificial structure row 1021 exposed on the side of the first trench 117 is etched back to form a sacrificial structure row 1121, source
  • the sidewalls of the pole row 1011, the sacrificial structure row 1121 and the drain row 1031 form a U-shaped trench.
  • a selective etching process is used to laterally etch the initial sacrificial structure row 1021 to form the sacrificial structure row 1121, so that both side walls of the sacrificial structure row 1121 are indented relative to the source row 1011 and the drain row 1031, A stacked structure row 112 is obtained.
  • the stacked structure row 112 includes a stacked source row 1011 , a sacrificial structure row 1121 and a drain row 1031 .
  • forming the semiconductor material layer 113 in the U-shaped trench in each transistor row region in step S404 includes: using an epitaxial growth process to grow the semiconductor material in the U-shaped trench. , forming a U-shaped trench semiconductor material layer 113 with a cross-section consistent with the U-shaped trench cross-sectional shape, or a semiconductor material layer 113 with a columnar cross-section. Specifically, it includes the following steps:
  • an epitaxial process is used to form a semiconductor material layer 113 on the exposed surfaces of the source row 1011 , the sacrificial structure row 1121 and the drain row 1031 .
  • the epitaxial process can continue to be used to form the exposed outer surfaces of the source row 1011, the sacrificial structure row 1121 and the drain row 1031.
  • layer 113 of semiconductor material Since the source row 1011, the sacrificial structure row 1121 and the drain row 1031 are all formed based on the epitaxial process, the epitaxial process can continue to be used to form the exposed outer surfaces of the source row 1011, the sacrificial structure row 1121 and the drain row 1031.
  • a semiconductor material layer 113 with a columnar cross-section may be formed by etching, as shown in FIG. 13 .
  • the transistor row area is patterned to form a plurality of second trenches 119 perpendicular to the first trench 117 to distinguish multiple transistor areas, each transistor area It includes the source 11 formed by the stacked source row 1011, the semiconductor layer 12 formed by the semiconductor material layer 113, and the drain 14 formed by the drain row 1031; the sacrificial structure formed by the sacrificial structure row 1121 is arranged in the same layer as the semiconductor layer 12, and is located between the first semiconductor layer 121 and the second semiconductor layer 122 included in the semiconductor layer 12 .
  • the process etches the stacked structure rows 112 and the semiconductor material layer 113 to form the stacked structure 116 and the semiconductor layer 12 .
  • a deposition process is used to deposit a dielectric material such as silicon oxide, and a CMO process is used to form the second planar layer 114 .
  • the mask structure includes first sub-mask structures 1151 arranged at intervals. As shown in FIG. 15, an extension of the first sub-mask structure 1151 is The direction is perpendicular to the extension direction of the stacked structure row 112 .
  • Figures 5 to 14 are schematic cross-sectional structural views along the first direction, and the second direction is perpendicular to the first direction.
  • Figure 15 is the AA-direction cross-section after the mask structure is prepared from the structure shown in Figure 14 Structural diagram, used in Figure 15 Indicates that the first direction is the inward direction perpendicular to the paper surface.
  • a self-aligned etching process is used to etch the stacked structure rows 112 and the semiconductor material layer 113 to form the stacked structure 116 and the semiconductor layer 12.
  • the stacked structures 116 are arranged in an array.
  • the unetched second flat layer 114 is removed.
  • the second trench 119 is used to separate adjacent stacked structures 116 .
  • the first sub-mask structure 1151 is a hard mask made of silicon oxide, which can play a role in self-aligned etching during the etching of the stacked structure rows 112 and the semiconductor material layer 113. function to ensure the accuracy of etching.
  • the stacked structure 116 includes a source electrode 11 and a drain electrode 14.
  • the sacrificial structure row 1121 is etched to form a sacrificial structure.
  • the semiconductor material layer 113 is etched to form the semiconductor layer 12.
  • the sacrificial structure is blocked by the semiconductor layer 12. Not visible, the source 11 is connected to the bit line 20 .
  • Figure 16 is a schematic cross-sectional structural view along the second direction. In Figure 16, Indicates that the first direction is the inward direction perpendicular to the paper surface.
  • removing the sacrificial structure to form a hole in the above step S406 includes: using a selective etching process to remove the sacrificial structure, so that the source 11, the first semiconductor layer 121, the second semiconductor layer 122 and the drain electrode 14 are enclosed to form a hole.
  • the axial direction of the hole is parallel to the second direction and perpendicular to the first direction.
  • conductive material is filled in the hole and the sidewalls of the first semiconductor layer 121 and the second semiconductor layer 122 through a plating process, and the conductive material is patterned to form the gate 13
  • the word line 201 connected to the gate 13 it also includes: forming an insulating layer 15 in the hole and on the sidewalls of the first semiconductor layer 121 and the second semiconductor layer 122 through a plating process and a patterning process.
  • the insulating layer 15 includes The hole wall conforms to the first insulating layer 151 and the second insulating layer 152 conforms to the first semiconductor layer 121 and the second semiconductor layer 122 .
  • a deposition process is used to form a first insulating layer conforming to the inner walls of the source electrode 11, the first semiconductor layer 121 and the second semiconductor layer 122 of the semiconductor layer 12, and the peripheral wall of the cavity formed by the drain electrode 14. 151, and a second insulating layer 152 conforming to the outer walls of the source electrode 11, the first semiconductor layer 121 and the second semiconductor layer 122, and the peripheral wall of the groove formed by the drain electrode 14, to obtain the insulating layer 15, to The subsequently prepared gate electrode 13 is insulated from the source electrode 11 , the drain electrode 14 and the first semiconductor layer 121 and the second semiconductor layer 122 , as shown in FIG. 17 .
  • conductive material is filled in the hole and the sidewalls of the first semiconductor layer 121 and the second semiconductor layer 122 through a plating process, and the conductive material is patterned to form the gate 13 and word line 201 connected to gate 13 .
  • it includes the following steps:
  • an atomic layer deposition process is used to deposit a metal material, so that the metal material fills the cavity formed by the first insulating layer 151 and fills the groove formed by the second insulating layer 152 to form an initial word line. layer.
  • Figure 17 is a schematic cross-sectional structural diagram along the first direction.
  • ⁇ is used to indicate that the second direction is the direction perpendicular to the outward direction of the paper.
  • the SOH (Spin On Hard mask) process can be used to form a self-leveling flat layer on one side of the initial word line layer, and then form a self-leveling flat layer on one side of the flat layer.
  • a photoresist structure is formed on the side, and the initial word line layer is etched using the photoresist structure as a mask.
  • the first gate 131 is disposed in a cavity surrounded by the first insulating layer 151 , so that the first gate 131 is connected with the first semiconductor layer 121 , the second semiconductor layer 122 , the source 11 and the drain Pole 14 phase insulation.
  • the second gate electrode 132 is disposed in the groove formed by the second insulating layer 152 so that the second gate electrode 132 is insulated from the first semiconductor layer 121 , the second semiconductor layer 122 , the source electrode 11 and the drain electrode 14 .
  • both the first semiconductor layer 121 and the second semiconductor layer 122 are laterally indented relative to the outer contours of the source electrode 11 and the drain electrode 14 because the source electrode 11 and the drain electrode 14 are prepared based on an epitaxial growth process.
  • the distance between the source electrode 11 and the drain electrode 14 can be accurately controlled along the direction perpendicular to the substrate 100.
  • the insulating layer 15 is formed through the ALD process, and the thickness of the insulating layer 15 can also be accurately controlled, so that The size of the cavity formed by the first insulating layer 151 and the size of the groove formed by the second insulating layer 152 can be accurately controlled, so that the formed first gate 131 and the second gate 132 can be precisely controlled.
  • the size, especially the length of the first gate 131 and the second gate 132 can be precisely controlled, thereby improving the preparation accuracy of the gate 13, ensuring the preparation accuracy of the memory cells, and thus ensuring the performance of each memory cell in the memory. Uniformity, thereby ensuring memory performance.
  • the magnetic tunnel junction 20 and the bit line 202 are sequentially formed on the side of the drain electrode 14 away from the substrate 100, including: on the side of the drain electrode 14 away from the substrate 100 A connection structure 40 is formed on one side; a magnetic tunnel junction 20 connected to the connection structure 40 is formed on one side of the connection structure 40; an encapsulation layer 60 covering the magnetic tunnel junction 20 is formed; the encapsulation layer 60 is patterned and connected to the magnetic tunnel junction 20 bit line 202.
  • a deposition process is used to deposit a dielectric material, such as silicon oxide, and after smoothing and patterning, a dielectric structure 50 including an opening is formed, and the opening exposes part of the drain electrode 14 .
  • a dielectric material such as silicon oxide
  • a metal material such as titanium, cobalt and other metal materials, is deposited in the opening, and an annealing process is used to form a silicide structure 41; the thickness of the silicide structure 41 is smaller than the depth of the opening.
  • a metal material is deposited on the side of the silicide structure 41 away from the substrate 100 to cover the silicide structure 41 and fill the opening to form a metal structure 42 flush with the upper surface of the dielectric structure 50 to obtain a connection structure 40, as shown in FIG. 18 Show.
  • an initial magnetic tunnel junction layer, a hard mask layer and a second photoresist structure are sequentially formed on the side of the dielectric structure 50 and the metal structure 42 away from the substrate 100 .
  • the hard mask layer is patterned using the second photoresist structure as a mask to form the hard mask structure 30
  • the initial magnetic tunnel junction layer is patterned using the hard mask structure 30 as a mask to form the magnetic tunnel junction 20 .
  • the hard mask structure 30 can play a role in protecting the magnetic tunnel junction 20.
  • an encapsulation layer 60 is deposited on the side of the hard mask structure 30 away from the substrate 100 , and the encapsulation layer 60 covers the sidewalls of the magnetic tunnel junction 20 , as shown in FIG. 19 .
  • an isolation layer 70 including an opening is formed on the side of the packaging layer 60 away from the substrate 100.
  • the opening of the isolation layer 70 exposes part of the hard mask structure 30, and a metal material is deposited in the opening of the isolation layer 70 to form the bit line 202. , forming a memory as shown in Figure 2.
  • the transistor 10 of the memory unit 200 by configuring the transistor 10 of the memory unit 200 to be a dual-channel transistor, the on-state current of the transistor 10 can be increased, the read and write speed of the memory unit 200 can be increased, and the performance of the memory can be improved.
  • each memory cell 200 is configured with a word line 201, a bit line 202 and two source lines 203.
  • the two adjacent source lines 203 are respectively connected to the first channel and the second channel of the transistor 10 through the source electrode 11. Therefore, the current of each source line 203 can be reduced, thereby reducing the impact of the current flowing through the source line 203 on other components of the memory.

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Abstract

申请实施例提供了一种存储器及其制造方法、读写控制方法。在本申请实施例提供的存储器中，通过设置存储单元的晶体管为双沟道晶体管，从而能够提高晶体管的开态电流，能够提高存储单元的读写速度，能够提高存储器的性能。每个存储单元配置有两条源线，两条相邻的源线通过源极分别与晶体管的第一沟道和第二沟道电连接，从而能够降低每条源线的电流，从而能够降低源线流经电流对存储器其它部件的影响。

Description

存储器及其制造方法、读写控制方法 技术领域
本申请涉及半导体技术领域，具体而言，本申请涉及一种存储器及其制造方法、读写控制方法。
背景技术
随着半导体器件集成化技术的发展，存储器的种类越来越多，MRAM(Magnetoresistive Random Access Memory，磁性随机存储器)作为一种非易失性存储器是行业的重要的研究方向之一。
目前，MRAM中存储单元存在开态电流较小的问题，导致存储单元的读写速度较慢，影响MRAM的性能。
发明内容
本申请提出一种存储器及其制造方法、存储器的控制方法、电子设备，至少用以改善背景技术中的不足。
本申请一些实施例提供了一种存储器，包括：
多个存储单元，存储单元包括晶体管和磁性隧道结，磁性隧道结的一端与晶体管电连接；晶体管为双沟道晶体管，包含第一沟道和第二沟道；
多条字线，一条字线与同一行存储单元中晶体管的各栅极电连接；
多条位线，一条位线与同一列存储单元中各磁性隧道结的另一端电连接；
多条源线，一列存储单元中各晶体管的源极同时与两条相邻的源线电连接，两条相邻的源线通过源极分别与第一沟道和第二沟道电连接。
本申请一些实施例提供了一种存储器的读写控制方法，包括：
在读取阶段，通过字线控制待读取存储单元中晶体管处于导通状态， 通过位线或一条源线中的一个向待读取存储单元的磁性隧道结传输读取信号，以使得位线或一条源线中的另一个感测磁性隧道结的存储数据；
在写入阶段，通过字线控制待写入存储单元中晶体管处于导通状态，通过位线和两条源线控制存储信号流经待写入存储单元中磁性隧道结的方向，以将位线或源线传输的存储信号写入磁性隧道结。
本申请一些实施例提供了一种存储器的制造方法，包括：
通过图案化工艺在衬底上形成多个第一沟槽以区分多个晶体管行区域，每个第一沟槽的侧面为叠置的源极行、第一牺牲结构行和漏极行；
通过退火工艺和图案化工艺在第一沟槽内形成相互绝缘的两条源线，至少部分源线位于源极行的下方；
每个晶体管行区域，对露出在第一沟槽侧面的第一牺牲结构行进行回刻处理形成牺牲结构行，源极行、牺牲结构行和漏极行的侧壁形成U型沟槽；
每个晶体管行区域，在U型沟槽内形成半导体材料层；
图案化晶体管行区域，形成多个垂直于第一沟槽的第二沟槽以区分多个晶体管区域，每个晶体管区域包括叠置的源极行形成的源极、半导体材料层形成的半导体层和漏极行形成的漏极；牺牲结构行形成的牺牲结构与半导体层同层设置，并位于半导体层包括的第一半导体层和第二半导体层之间；
去除牺牲结构形成孔；
通过镀膜工艺在孔内、第一半导体层和第二半导体层的侧壁填充导电材料，图案化导电材料形成栅极和与栅极连接的字线；
在漏极远离衬底的一侧依次形成磁性隧道结和位线。
本申请实施例提供的技术方案带来的有益技术效果包括：
在本申请实施例提供的存储器中，通过设置存储单元的晶体管为双沟道晶体管，从而能够提高晶体管的开态电流，能够提高存储单元的读写速度，能够提高存储器的性能。
同时，每个存储单元配置有两条源线，两条相邻的源线通过源极分别 与晶体管的第一沟道和第二沟道电连接，从而能够降低每条源线的电流，从而能够降低源线流经电流对存储器其它部件的影响。
本申请附加的方面和优点将在下面的描述中部分给出，这些将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为本申请实施例提供的一种存储器的电路原理示意图；
图2为本申请实施例提供的一种存储器的结构示意图；
图3为本申请实施例提供的图1所示存储器的AA向剖视结构示意图；
图4为本申请实施例提供的一种存储器的制造方法的流程示意图；
图5为本申请实施例提供存储器的制造方法中得到第一光刻胶结构和第一掩膜结构后的结构示意图；
图6为本申请实施例提供存储器的制造方法中得到初始叠置结构行后的结构示意图；
图7为本申请实施例提供存储器的制造方法中得到第一弧形槽后的结构示意图；
图8为本申请实施例提供存储器的制造方法中得到金属层后的结构示意图；
图9为本申请实施例提供存储器的制造方法中得到位线后的结构示意图；
图10为本申请实施例提供存储器的制造方法中得到第一平坦层后的结构示意图；
图11为本申请实施例提供存储器的制造方法中去除第一掩膜结构后的结构示意图；
图12为本申请实施例提供存储器的制造方法中得到叠置结构行后的结构示意图；
图13为本申请实施例提供存储器的制造方法中得到半导体材料层后 的结构示意图；
图14为本申请实施例提供存储器的制造方法中得到第二平坦层后的结构示意图；
图15为本申请实施例提供存储器的制造方法中在图14所示结构制作得到掩膜结构后的BB向剖面结构示意图；
图16为本申请实施例提供存储器的制造方法中基于图15所示结构制作得到半导体层后的结构示意图；
图17为本申请实施例提供存储器的制造方法中形成字线后的结构示意图；
图18为本申请实施例提供存储器的制造方法中形成连接结构后的结构示意图；
图19为本申请实施例提供存储器的制造方法中形成封装层后的结构示意图。
附图标记说明：
100-衬底；
200-存储单元；201-字线；2011-第一子段；2012-第二子段；202-位线；203-源线；2031-第一源线；2032-第二源线；2033-金属硅化物子层；2034-金属子层；
10-晶体管；
11-源极；12-半导体层；121-第一半导体层；122-第二半导体层；13-栅极；131-第一栅极；132-第二栅极；14-漏极；15-介质层绝缘层；151-第一绝缘层；152-第二绝缘层；
20-磁性隧道结；30-硬掩膜结构；40-连接结构；41-硅化物结构；42-金属结构；50-介质结构；51-隔离结构；60-封装层；70-隔离层；
101-第一硅掺杂导电层；102-牺牲半导体层；103-第二硅掺杂导电层；104-第一光刻胶结构；105-第一掩膜结构；
106-初始叠置结构行；1011-源极行；1021-初始半导体材料层牺牲结构行；1031-漏极行；1071-保护结构；
108-第一弧形槽；109-金属层；111-第一平坦层；1111-第一平坦结构； 112-叠置结构行；1121-半导体材料层牺牲结构行；113-半导体材料层；114-第二平坦层；1151-第一子掩膜结构；116-叠置结构；117-第一沟槽；118-第二沟槽。
具体实施方式
下面结合本申请中的附图描述本申请的实施例。应理解，下面结合附图所阐述的实施方式，是用于解释本申请实施例的技术方案的示例性描述，对本申请实施例的技术方案不构成限制。
本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。应该进一步理解的是，本申请的说明书中使用的措辞“包括”是指存在所述特征、整数、步骤、操作、元件和/或组件，但不排除实现为本技术领域所支持其他特征、信息、数据、步骤、操作、元件、组件和/或它们的组合等。
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
本申请实施例涉及的存储器可以为MRAM，MRAM是一种非易失性的磁性随机存储器，MRAM中存储的数据以一种磁性状态存储，而不是电荷，磁场极性不像电荷那样会随着时间而泄漏，因此即使在断电的情况下，也能保持信息。
目前，MRAM往往包括多个呈阵列排布的存储单元，每个存储单元需设置位线、字线和位线。目前，由于MRAM的集成化程度越来越高，从而导致存储单元中晶体管的尺寸越来越小。随着晶体管尺寸的减小，导致晶体管的开态电流较小，进而导致晶体管的驱动性能较低、开启速度较慢，影响存储单元的读写速度，进而影响存储器的性能。
而且，MRAM存储单元中垂直晶体管的半导体结构、栅极的制造精度较低，从而导致存储器中VGAA晶体管的性能存在差异，影响存储器的性能。
而且，垂直晶体管面临驱动电流进一步提升的瓶颈。比如，随着垂直晶体管尺寸的减小，垂直晶体管的开态电流减小，进而晶体管的驱动性能 降低、开启速度较慢，进而影响存储器的性能。
本申请提供的存储器及其制造方法、读写控制方法，旨在解决现有技术的如上技术问题。
下面以具体地实施例对本申请的技术方案进行详细说明。
本申请实施例提供了一种存储器，该存储器的电路原理示意图如图1所示，存储器包括：多个存储单元200、多条字线201、多条位线202和多条源线203。
存储单元200，存储单元200包括晶体管10和磁性隧道结20，磁性隧道结20的一端与晶体管10电连接，晶体管10为双沟道晶体管，包含第一沟道和第二沟道。一条字线201与同一行存储单元200中晶体管10的各栅极13电连接；一条位线202与同一列存储单元200中各磁性隧道结20的另一端电连接；一列存储单元200中各晶体管10的源极11同时与两条相邻的源线203电连接，两条相邻的源线203通过源极11分别与第一沟道和第二沟道电连接。
在本申请实施例提供的存储器中，通过设置存储单元200的晶体管10为双沟道晶体管，从而能够提高晶体管10的开态电流，能够提高存储单元200的读写速度，能够提高存储器的性能。
同时，每个存储单元200配置有一条字线201、一条位线202和两条源线203，两条相邻的源线203通过源极11分别与晶体管10的第一沟道和第二沟道电连接，从而能够降低每条源线203的电流，从而能够降低源线203流经电流对存储器其它部件的影响。
可选地，多个存储单元200呈阵列排布，也即各个存储单元200的晶体管10呈阵列排布。本文中定义，平行于字线201延伸的方向为行，平行于源线203延伸的方向为列。如图1所示，沿自左向右的方向为行，沿自上而下的方向为列，图1中示例性的示出了同一行的两个存储单元，也即分别示出了两列存储单元200中每一列存储单元的一个存储单元200。
本申请实施例中，如图1所示，每个存储单元200均包括一个晶体管10和一个磁性隧道结20，晶体管10和磁性隧道结20电连接。可选地， 磁性隧道结20的一端与晶体管10的漏极14电连接。
本申请实施例中，如图1所示，晶体管10为双沟道垂直晶体管10，相较于单沟道晶体管而言，能够显著提高晶体管10的开态电流，能够提升晶体管10的驱动能力和开启速度，能够提高存储单元100的数据写入和数据读取的速度，进而能够提升存储器的性能。
如图1所示，两条相邻的源线203通过源极11分别与晶体管10的第一沟道和第二沟道电连接，相当于每个晶体管10包括两个并联连接的子晶体管，从而在增大晶体管10的开态电流的同时，能够降低通过每个子晶体管的电流，从而能够降低晶体管10的损耗速度，能够延长晶体管10的使用寿命。
本申请实施例中，如图1所示，磁性隧道结20的另一端与位线202电连接，同一行的各存储单元200中晶体管10的栅极13与字线201电连接。当通过字线201控制晶体管10开启后，通过一条源线203和一条位线202，就可以控制一列存储单元200的数据读取，通过两条源线203和一条位线202就可以控制一列存储单元200的数据写入。
可选地，本申请实施例中，磁性隧道结20包括MTJ(Magnetic Tunnel Junctions，磁性隧道结)，MRAM通过检测MTJ电阻的高低来判断所存储的数据是“0”还是“1”
具体的，MTJ包括依次叠置的自由层、隧穿层和固定层。自由层的磁场方向是可以改变的，而固定层的磁场方向是固定不变的，在电场作用下电子会通过隧穿层势垒而垂直穿过器件，当自由层的磁场方向与固定层的磁场方向相同时，MTJ呈现低阻态“0”，当自由层的磁场方向与固定层的磁场方向相反时，MTJ呈现高阻态“1”。
可选地，如图2所示，在本申请的一个实施例中，沿平行衬底100的第一方向，与同一列存储单元200电连接的源线203分别为第一源线2031和第二源线2032；两列相邻的存储单元200中，与一列存储单元200的各源极11连接的第二源线2032，和另一列存储单元200的各源极11连接的第一源线2031之间设置有隔离结构51。
本申请实施例中，如图2所示，沿第一方向，与同一列存储单元200电连接的源线203分别为第一源线2031和第二源线2032，两列相邻的存储单元200中，与一列存储单元200的各源极11连接的第二源线2032，和另一列存储单元200的各源极11连接的第一源线2031之间设置有隔离结构51，从而使得与每列存储单元200连接的源线203之间相互绝缘。
可选地，本申请实施例中，隔离结构51作为介质结构50的部分。
可选地，如图2所示，在本申请的一个实施例中，晶体管10为垂直晶体管10，晶体管10和磁性隧道结20沿垂直衬底100的方向叠层设置。
本申请实施例中，如图2所示，为本申请实施例提供的一种存储器的结构示意图，如图2所示，示意出了四条完整的源线203，存储单元200设置于源线203远离衬底100的一侧，每个存储单元200配置有一条字线201、一条位线202和两条源线203。存储器中每个存储单元200的晶体管10和磁性隧道结20沿垂直衬底100的方向叠层设置。
本申请实施例中，晶体管10为垂直晶体管10，如图2所示，沿垂直于衬底100的方向，源极11、半导体结构12和漏极14依次叠层设置。栅极13也位于源极11和漏极14之间，即栅极13与半导体结构12同层设置。
可选地，如图2所示，在本申请的一个实施例中，晶体管10包括在衬底100上依次叠层设置的源极11、半导体层12和漏极14；半导体层12包括第一半导体层121和第二半导体层122，第一半导体层121和第二半导体层122间隔设置于源极11的同一侧分别与源极11接触；第一半导体层121包括第一沟道，第二半导体层122包括第二沟道；至少部分栅极13位于第一半导体层121和第二半导体层122的间隔的区域。
本申请实施例中，如图2所示，沿垂直于衬底100的方向，源极11、半导体层12和漏极14依次叠层设置。栅极13也位于源极11和漏极14之间，即栅极13与半导体层12同层设置。
如图2所示，第一半导体层121和第二半导体层122间隔设置于源极11的同一侧分别与源极11接触。第一半导体层121在导通的情况下包括 第一沟道，第二半导体层122在导通的情况下包括第二沟道，即晶体管10为双沟道垂直晶体管。
可选地，如图2所示，在本申请的一个实施例中，栅极13包括相互连接的第一栅极13和第二栅极13；第一栅极131为位于第一半导体层121和第二半导体层122的间隔的区域之间的栅极；第二栅极132设置于第一半导体层121和第二半导体层122的外侧壁，且与第一半导体层121、第二半导体层122、源极11和漏极14相绝缘。
可选地，栅极13包括第一栅极13和第二栅极13；第一栅极13设置于两个第一半导体层121和第二半导体层122之间，且与第一半导体层121、第二半导体层122、源极11和漏极14相绝缘；第二栅极13设置于半导体层12的外侧壁，且与半导体层12、源极11和漏极14相绝缘。
本申请实施例中，如图2所示，晶体管11还包括栅极绝缘层15，可选地，本申请实施例中，栅极绝缘层15采用高k值介质材料制成。
可选地，如图2所示，栅极绝缘层15包括一个第一栅极绝缘层151和两个第二栅极绝缘层152。第一栅极绝缘层151与源极11、第一半导体层121和第二半导体层122的内侧壁以及漏极14围合形成的腔室的周壁随形；第二栅极绝缘层152与源极11、第一半导体层121和第二半导体层122的外侧壁以及漏极14围合形成的凹槽的周壁随形。
本申请实施例中，如图2所示，栅极13的第一栅极131位于两个间隔设置的半导体层12之间，可选地，第一栅极131设置于第一栅极绝缘层151围合形成的腔室内，以使得第一栅极131与半导体层12、源极11和漏极14相绝缘。
如图2所示，栅极13的第二栅极132位于半导体层12的外侧壁，可选地，第二栅极132设置于第二栅极绝缘层152围合形成的凹槽内，以使得第二栅极132与半导体层12、源极11和漏极14相绝缘。
在本申请的一个实施例中，第一栅极13和第二栅极13均与字线201连接。
本申请实施例中，如图2所示，字线201沿平行于衬底100的第一方 向延伸，如图3所示，源线203沿平行于衬底100的第二方向延伸，第一方向垂直于第二方向。可选地，位线202的延伸方向平行于源线203的延伸方向。
本申请实施例中，结合图3和图4可知，栅极13的第一栅极131和第二栅极132，均与字线201连接，从而通过字线201能够向第一栅极131和第二栅极132同时施加电平，能够进一步增强栅极13的电场强度，从而能够有助于提高晶体管10的开态电流，进而有助于提升晶体管10的驱动能力和开启速度，有助于提升存储单元200的读写速度，有助于提升存储器的性能。
本申请实施例中，如图2所示，字线201沿平行于衬底100的第一方向延伸，如图3所示，源线203沿平行于衬底100的第二方向延伸，第一方向垂直于第二方向。可选地，位线202的延伸方向平行于源线203的延伸方向。
本申请实施例中，结合图3和图4可知，栅极13的第一栅极131和第二栅极132，均与字线201连接，从而通过字线201能够向第一栅极131和第二栅极132同时施加电平，能够进一步增强栅极13的电场强度，从而能够有助于提高晶体管10的开态电流，进而有助于提升晶体管10的驱动能力和开启速度，有助于提升存储单元200的读写速度，有助于提升存储器的性能。
可选地，在本申请的一个实施例中，源极11是基于硅掺杂得到的，且源极11的导电率小于源线203的导电率。
可选地，源线203包括金属硅化物子层2033和金属子层2034，金属硅化物子层2033与源极11连接；金属硅化物子层2033的横截面为弧形状，弧形状的金属硅化物子层2033包围部分金属子层2034。
本申请实施例中，如图2所示，源线203包括金属硅化物子层2033和金属子层2034，金属硅化物子层2033的材料为金属硅化物，金属子层2034的材料为金属，从而能够增大源线203的尺寸，降低源线203的电阻，能够提高源线203的导电率，能够保障电信号的传输效率，能够降低 存储器的功耗。可选地，金属硅化物子层2033和金属子层2034包括同一中金属元素。
如图2所示，金属硅化物子层2033的横截面为弧形状，弧形状的金属硅化物子层2033包围部分金属子层2034，以避免金属子层2034直接与源极11连接。
在本申请的一个实施例中，字线201包括多个依次交替连接的第一子段2011和第二子段2012；第一子段2011环绕第一栅极13和第二栅极13，与第一栅极13和第二栅极13均连接；第二子段2012的一端与一个第一子段2011连接，另一端与另一个第一子段2011连接。
本申请实施例中，如图2和图3所示，沿第一方向，也即字线201的延伸方向，第一子段2011和第二子段2012依次交替连接。
本申请实施例中，结合图2和图3可知，第一子段2011环绕第一栅极131和第二栅极132设置，即第一子段2011包裹了第一栅极131的两个端面和第二栅极132的两个端面，从而与第一栅极131和第二栅极132均连接。
可选地，如图3所示，第一子段2011的上表面与第一栅极131的上表面平齐，从而能够避免第一子段2011与晶体管10的漏极14接触。
本申请实施例中，如图2所示，第二子段2012位于相邻两个晶体管10之间，用于连接环绕第一栅极131和第二栅极132的第一子段2011。第二子段2012的上表面与第一子段2011的上表面平齐，能够降低第二子段2012与晶体管10漏极14接触的几率，能够降低两者之间产生寄生电容的几率，进而能够保障存储器的性能。
应该说明的是，为了便于清楚示意出字线201中第一子段2011和第二子段2012的结构，图2和图3中用虚线表示出了第一子段2011与第二子段2012之间的界面分界线、第一子段2011与第一栅极131之间的界面分界线，实际产品中，第一子段2011、第二子段2012和栅极13是采用同种材料制作形成的，并不存在如图2和图3中所展示的虚线。
在本申请的一个实施例中，源极11和漏极14的外轮廓在衬底上的投 影、围设第一半导体层121、第二半导体层122和第一栅极13的外轮廓在衬底上的投影，使得源极11、漏极14相对于半导体结构和第一栅极13向外凸出。
可选地，如图2所示，晶体管10中，源极11的漏极14的外轮廓在衬底100上的正投影，围设第一半导体层121、第二半导体层122和第一栅极131的外轮廓在衬底100上的正投影，使得源极11、漏极14相对于半导体结构12和第一栅极131向外凸出。如图1所示，源极11、第一半导体层121、第二半导体层122、第一栅极131和漏极14组合形成的剖面图形为工字形。
在本申请的一个实施例中，源极11和漏极14的外轮廓在衬底上的投影，与第二栅极13的外轮廓在衬底上的投影相重叠。可选地，如图2所示，极11和漏极14的外轮廓在衬底100上的正投影，与第二栅极132的外轮廓在衬底100上的正投影相重叠，使得源极11、漏极14的外侧壁与第二栅极132的外侧壁相平齐。
应该说明的是，本申请实施例中，所提及的外和内，均是相对于存储器的中心而言，相对靠近存储器的中心为内，相对远离存储器的中心为外。
在本申请的一个实施例中，存储单元200还包括：连接结构40，设置于晶体管10的漏极14远离源极11的一侧；磁性隧道结20设置于连接结构远离漏极14的一侧。
可选地，如图2所示，沿垂直于衬底100的方向，晶体管10和连接结构40叠层设置，连接结构40设置于晶体管10的漏极14远离源极11的一侧。
本申请实施例中，连接结构40用于实现晶体管10与磁性隧道结20的电连接。从而便于晶体管10和磁性隧道结20的分别制作，例如，先采用一条产线在衬底100的一侧依次形成源线203、晶体管10、字线201以及连接结构40后，再采用另一条产线形成磁性隧道结20，从而能够提高存储器的生产效率。
可选地，如图3所示，连接结构40包括硅化物结构41和金属结构 42。由于漏极14多采用掺杂的半导体材料制成，其与金属结构42的导电率存在明显的差异，通过设置硅化物结构41，能够降低金属结构42与漏极14之间的界面电阻，从而能够保障存储单元200的性能。
本申请实施例中，如图2-图3所示，存储器还包括介质结构50，介质结构50可以与绝缘层15采用同种介质材料制成。可选的，如图2所示，连接结构40设置于介质结构50的开口内。
可选地，如图2所示，磁性隧道结20远离衬底100的一侧设置有硬掩膜结构30，在形成磁性隧道结20的过程中，硬掩膜结构30可以起到保护磁性隧道结20的作用。可选地，硬掩膜结构30包括金属和介质材料，因此，硬掩膜结构30具有一定的导电性，硬掩膜结构30与位线202连接，从而实现位线202与磁性隧道结20的电连接。
应该说明的是，硬掩膜结构30的硬度是相对于光刻胶的硬度而言的，硬掩膜结构30的材料包括氧化硅、氮化硅等。
本申请实施例中，如图2所示，硬掩膜结构30远离衬底100的一侧设置有的封装层60，封装层60覆盖磁性隧道结20的侧壁，以避免外界水、氧等侵蚀磁性隧道结20。可选地，封装层60的材料包括氮化硅、氧化铝、氧化镁等致密材料。
本申请实施例中，如图2所示，在源线203的径向平面内，源线203的截面形状为弧形，一列存储单元200中各晶体管10的源极11的一侧均与一条弧形源线203连接，同一列存储单元200中各晶体管10的源极11的另一侧均与另一条弧形源线203连接，从而使得每列存储单元200连接有两条源线203。
本领域技术人员了解的是，相较于截面形状均为直线段的源线而言，采用截面形状为弧形的源线203，能够避免源线203出现直角的部分，从而能够避免尖端效应，能够保障存储器的性能。
基于同一发明构思，本申请实施例提供了一种电子设备，包括：如上述各个实施例所提供的任一种存储器。
本申请实施例中，由于电子设备采用了前述各实施例提供的任一种存 储器，其原理和技术效果请参阅前述各实施例，在此不再赘述。
可选地，电子设备包括智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
应该说明的是，电子设备并不局限于上述几种，本领域技术人员可以根据实际的应用需求，在不同的设备中设置本申请上述各个实施例所提供的任一种存储器，从而得到本申请实施例所提供的电子设备。
基于同一发明构思，本申请实施例提供了一种存储器的控制方法，包括：在读取阶段，通过字线控制待读取存储单元中晶体管处于导通状态，通过位线或一条源线中的一个向待读取存储单元的磁性隧道结传输读取信号，以使得位线或一条源线中的另一个感测磁性隧道结的存储数据；在写入阶段，通过字线控制待写入存储单元中晶体管处于导通状态，通过位线和两条源线控制存储信号流经待写入存储单元中磁性隧道结的方向，以将位线或源线传输的存储信号写入磁性隧道结。
本申请实施例提供了的存储器的控制方法，用于上述各个实施例所提供的任一存储器。
可选地，在存储器的读取阶段，通过字线201向待读取存储单元200中晶体管10的栅极13输入第一电平，使得该晶体管10处于导通状态，通过一条位线202或一条源线203感测电流或电压的变化以及变化程度，实现磁性隧道结20存储数据的读取。下面以通过源线203感测电流变化为例，来说明是如何实现磁性隧道结20存储数据读取的。
具体的，当磁性隧道结20存储的数据是“1”时，此时MTJ呈现高阻态，当通过一条位线202向磁性隧道结20传输读取信号，也即通过位线202向磁性隧道结20施加第二电平，一条源线203保持在参考电平，参考电平小于第二电平，由于MTJ呈现高阻态，电流难以通过磁性隧道结20，即源线203难以测得较为明显的电流，此种情况判断读取的数据为“1”，也即通过一条源线203即可感测待读取存储单元200的磁性隧道结205存储的数据为“1”。
当磁性隧道结20存储的数据是“0”时，此时MTJ呈现低阻态，当通 过一条位线202向磁性隧道结20传输读取信号，也即通过位线202向磁性隧道结20施加第二电平，一条源线203保持在参考电平，参考电平小于第二电平，由于MTJ呈现低阻态，电流能够通过磁性隧道结20，即源线203可以测得较为明显的电流，此种情况判断读取的数据为“0”，也即通过一条源线203即可感测待读取存储单元200的磁性隧道结20存储的数据为“0”。
本领域技术人员理解的是，通过控制位线202和源线203之间的电位差，能够控制电流的流向，进而实现待读取存储单元200中磁性隧道结20存储数据的读取。
可选地，在存储器的写入阶段，通过字线201向待读取存储单元200中晶体管10的栅极13输入第一电平，使得该晶体管10处于导通状态，通过位线202和两条源线203控制存储信号流经待写入存储单元200中磁性隧道结20的方向，以将位线202或源线203传输的存储信号写入磁性隧道结20。下面以通过源线203向待写入存储单元200传输存储信号为例，来说明是如何实现磁性隧道结20数据存储的。
具体的，当存储信号为“1”时，通过源线203向待写入存储单元200的晶体管10的源极11施加第三电平，位线202保持在参考电平，第三电平大于参考电平，由于两条源线203均施加第三电平，使得磁性隧道结20两端的电位差足够大，包括存储信号的电流从源线203流向位线202，且在电流流经磁性隧道结20的过程中，磁性隧道结20的自由层的磁场方向会改变并与固定层的磁场方向相反，使得磁性隧道结20呈现高阻态“1”，从而实现数据“1”的存储。
反之，通过控制磁性隧道结20的自由层的磁场方向改变并与固定层的磁场方向相同，使得磁性隧道结20呈现低阻态“0”，从而实现数据“0”的存储。
本领域技术人员了解的是，MRAM中写入电流通常是读取电流的十几倍，如果采用单沟道晶体管，在写入阶段，流经晶体管的电流较大，随着使用频率的增多，会大大加快单沟道晶体管的损耗速度，降低单沟道晶 体管的使用寿命。因此，本申请实施例中，通过设置双沟道垂直晶体管10，能够降低通过每个子晶体管的电流，从而能够降低晶体管10的损耗速度，能够延长晶体管10的使用寿命。
结合图1和图2可知，每个存储单元200的晶体管10电连接有两条源线203，且晶体管10为双沟道晶体管，从图2可知，两条源线203分别位于晶体管10的两侧，相当于每条源线203电连接一个晶体管10的子晶体管，在存储器的读取阶段，一条源线203感测电流或电压的变化以及变化程度，相当于晶体管10中只有一个子晶体管处于工作状态。
在存储器的写入阶段，两条源线203均向待写入存储单元200的晶体管10的源极11施加第三电平，即晶体管10中两个子晶体管均处于工作状态，从而在增大晶体管10的开态电流的同时，能够降低通过每个子晶体管的电流，从而能够降低晶体管10的损耗速度，能够延长晶体管10的使用寿命。
而且，在存储器的写入阶段，在增大晶体管10的开态电流的同时，能够降低每条源线203的电流，从而能够降低源线203流经电流对存储器其它部件的影响。
基于同一发明构思，本申请实施例提供了一种存储器的制造方法，该方法的流程示意图如图4所示，该方法包括如下步骤S401-S403：
S401，通过图案化工艺在衬底上形成多个第一沟槽以区分多个晶体管行区域，每个第一沟槽的侧面为叠置的源极行、第一牺牲结构行和漏极行。
S402，通过退火工艺和图案化工艺在第一沟槽内形成相互绝缘的两条源线，至少部分源线位于源极行的下方。
S403，每个晶体管行区域，对露出在第一沟槽侧面的第一牺牲结构行进行回刻处理形成牺牲结构行，源极行、牺牲结构行和漏极行的侧壁形成U型沟槽。
S404，每个晶体管行区域，在U型沟槽内形成半导体材料层。
S405，图案化晶体管行区域，形成多个垂直于第一沟槽的第二沟槽以区分多个晶体管区域，每个晶体管区域包括叠置的源极行形成的源极、半 导体材料层形成的半导体层和漏极行形成的漏极；牺牲结构行形成的牺牲结构与半导体层同层设置，并位于半导体层包括的第一半导体层和第二半导体层之间。
S406，去除牺牲结构形成孔。
S407，通过镀膜工艺在孔内、第一半导体层和第二半导体层的侧壁填充导电材料，图案化导电材料形成栅极和与栅极连接的字线。
S408，在漏极远离衬底的一侧依次形成磁性隧道结和位线。
采用本申请实施例所提供的存储器的制造方法能够制造得到上述实施例中所提供的至少一种存储器。
在本申请实施例所提供的存储器的制造方法中，先于晶体管形成相互绝缘的两条源线，能够避免退火工艺影响后续晶体管，能够保障晶体管的制造良率；同时，在制造过程中，通过设置第一牺牲结构行以及牺牲结构等中间结构，便于精准控制后续制造得到的晶体管中半导体层和栅极的尺寸，从而能够保障晶体管的制造精度，进而能够保障存储器中各个存储单元的晶体管性能的均一性，进而能够保障存储器的性能。
为了便于读者直观了解本申请实施例所提供的存储器的制造方法以及采用该方法制备得到的存储器的优点，下面将结合图5-图19进行具体说明。
可选地，在本申请的一个实施例中，在上述步骤S401中通过图案化工艺在衬底100上形成多个第一沟槽117以区分多个晶体管行区域，每个第一沟槽117的侧面为叠置的源极行1011、第一牺牲结构行1021和漏极行1031，之前还包括：通过外延生长工艺在衬底100的一侧依次形成第一硅掺杂导电层101、牺牲半导体层102和第二硅掺杂导电层103；源极行1011、第一牺牲结构行1021和漏极行1031分别基于第一硅掺杂导电层101、牺牲半导体层102和第二硅掺杂导电层103形成。
可选地，通过外延生长工艺在衬底100的一侧依次形成第一硅掺杂导电层101、牺牲半导体层102和第二硅掺杂导电层103，如图5所示。
可选地，第一硅掺杂导电层101和第二硅掺杂导电层103为掺杂的半 导体材料制成。可选地，第一硅掺杂导电层101和第二硅掺杂导电层103均为N型掺杂，掺杂程度可以根据具体的制造工艺或需求来确定；牺牲半导体层102为GeSi(硅锗)。
通过采用外延生长工艺形成第一硅掺杂导电层101、牺牲半导体层102和第二硅掺杂导电层103，便于精准控制各个膜层的厚度，特别是精准控制牺牲半导体层102厚度，便于精准控制后续制造得到的半导体结构12和栅极13的尺寸，从而能够保障晶体管的制造精度，进而能够保障存储器中各个存储单元的晶体管性能的均一性，进而能够保障存储器的性能。
可选地，也可以采用CVD(Chemical Vapor Deposition，化学气相沉积)、PVD(Physical Vapor Deposition，物理气相沉积)以及ALD(Atomic Layer Deposition，原子层沉积)等沉积工艺制造各个膜层结构。
可选地，在形成第二硅掺杂导电层103后，还可以包括：在第二硅掺杂导电层103远离衬底100的一侧形成第一光刻胶结构104，在第一光刻胶结构104的两侧壁形成第一掩膜结构105，如图5所示。
可选地，第一掩膜结构105的制备材料可以是氧化硅。
可选地，在本申请的一个实施例中，上述步骤S401中通过图案化工艺在衬底100上形成多个第一沟槽117以区分多个晶体管行区域，每个第一沟槽117的侧面为叠置的源极行1011、第一牺牲结构行1021和漏极行1031，包括：去除第一光刻胶结构104，以第一掩膜结构105刻蚀第二硅掺杂导电层103、牺牲半导体层102、第一硅掺杂导电层101以及部分衬底100，形成多个相互间隔设置的初始叠置结构行106。
可选地，如图6所示，初始叠置结构行106即为晶体管行区域，第一沟槽117用于间隔两个任意相邻的初始叠置结构行106。
通过设置第一掩膜结构105为硬掩膜，在刻蚀第二硅掺杂导电层103、牺牲半导体层102以及第一硅掺杂导电层101的过程中，能够起到自对准刻蚀的作用，从而保障刻蚀的精度。
如图6所示，初始叠置结构行106沿第二方向延伸，第二方向平行于衬底100且垂直于第一方向，第一方向为源线203的延伸方向，多个初始 叠置结构行106沿第一方向间隔设置；初始叠置结构行106包括叠层设置的源极行1011、初始牺牲结构行1021和漏极行1031。
可选地，在本申请的一个实施例中，在上述步骤S401之后还包括：形成覆盖初始叠置结构行106的顶壁和侧壁的保护层。
在后续制造过程中，保护层能够起到保护初始叠置结构行106的作用，防止初始叠置结构行106被刻蚀或被掺杂。可选地，保护层的制备材料包括氧化硅。
可选地，在本申请的一个实施例中，上述步骤S402中通过退火工艺和图案化工艺在第一沟槽117内形成相互绝缘的两条源线203，至少部分源线203位于源极行1011的下方，包括：沿第一沟槽117的底部刻蚀处理衬底100，形成与第一沟槽117连通的第一弧形槽108；在第一弧形槽108和部分第一沟槽117内填充金属材料，采用退火工艺处理金属材料，形成部分表面与第一弧形槽108随形的源线结构；图案化源线结构，形成相互分离的两条源线203。具体如下：
可选地，如图7所示，沿第一沟槽117的底部刻蚀处理部分衬底100，形成与第一沟槽117连通的第一弧形槽108。如图7所示，第一弧形槽108部分延伸至相邻两个叠置结构行106的下方。可选地，如图7所示，保护层经过刻蚀后，形成保护结构1071。
接着，在第一弧形槽108和部分第一沟槽117内填充金属材料，例如钛、钴等金属材料，形成金属层109，如图8所示。金属层109完全填充第一弧形槽108，并填充部分第一沟槽117，如图8所示，金属层109的上表面与初始叠置结构行106的初始牺牲结构行1021的上表面平齐，以使得后续形成的源线203能够与源极行1011接触。
然后，采用退火工艺处理金属层109，使得金属层109与部分衬底100和部分源极行1011发生反应，形成包括金属硅化物子层的源线结构，源线结构的部分表面与第一弧形槽108随形。
接着，图案化源线结构，形成相互分离的两条源线203，如图9所示，刻蚀部分衬底100以使得同一源线结构形成的两条源线203能够相互绝缘。 可选地，如图9所示，然后保留被源线203中弧形金属硅化物子层包围的未反应的部分金属层109，形成金属子层2034，从而能够保障源线203的导电性。
可选地，如图9所示，至少部分源线203位于源极行1011的下方。
可选地，在本申请的一个实施例中，在上述步骤图案化源线结构，形成相互隔离的两条源线之后还包括：在第一弧形槽108内填充介质材料，形成位于两条源线203之间的阻隔结构51。
可选地，采用沉积工艺沉积介质材料，如氧化硅，并采用CMP(Chemical Mechanical Polishing，化学机械抛光)工艺处理，形成第一平坦层111，如图10所示。可选地，保护结构1071和第一平坦层111的制造材料相同，因此图10中用第一平坦层111来表示两者，没有标示出保护结构1071。
然后，通过刻蚀工艺去除部分第一平坦层111和第一掩膜结构105，剩余的第一平坦层111形成第一平坦结构1111，如图11所示。可选地，第一平坦结构1111用于形成阻隔结构51，第一平坦结构1111形成阻隔结构51具体工艺会在后续中详细描述，此处不再赘述。
可选地，在本申请的一个实施例中，上述步骤S403中每个晶体管行区域，对露出在第一沟槽117侧面的第一牺牲结构行1021进行回刻处理形成牺牲结构行1121，源极行1011、牺牲结构行1121和漏极行1031的侧壁形成U型沟槽。
可选地，采用选择性刻蚀工艺侧向刻蚀初始牺牲结构行1021，形成牺牲结构行1121，使得牺牲结构行1121的两侧壁均相对于源极行1011和漏极行1031缩进，得到叠置结构行112，如图12所示，叠置结构行112包括叠层设置源极行1011、牺牲结构行1121和漏极行1031。
可选地，在本申请的一个实施例中，上述步骤S404中每个晶体管行区域，在U型沟槽内形成半导体材料层113，包括：采用外延生长工艺在U型沟槽内生长半导体材料，形成截面与U型沟槽截面形状相一致的U型沟槽半导体材料层113、或者截面为柱状的半导体材料层113。具体包 括以下步骤：
首先，采用外延工艺在源极行1011、牺牲结构行1121和漏极行1031的露出面形成半导体材料层113。
由于源极行1011、牺牲结构行1121和漏极行1031均是基于外延工艺形成，因此可以继续采用外延工艺形成与源极行1011、牺牲结构行1121和漏极行1031露出的外表面随形的半导体材料层113。
可选地，对于截面与U型沟槽截面形状相一致的U型沟槽半导体材料层113通过刻蚀可以形成截面为柱状的半导体材料层113，如图13所示。
可选地，在本申请的一个实施例中，上述步骤S405中图案化晶体管行区域，形成多个垂直于第一沟槽117的第二沟槽119以区分多个晶体管区域，每个晶体管区域包括叠置的源极行1011形成的源极11、半导体材料层113形成的半导体层12和漏极行1031形成的漏极14；牺牲结构行1121形成的牺牲结构与半导体层12同层设置，并位于半导体层12包括的第一半导体层121和第二半导体层122之间。具体包括以下步骤：在叠置结构行112远离衬底100的一侧形成掩膜结构；掩膜结构的延伸方向垂直于叠置结构行的延伸方向；基于掩膜结构，采用自对准刻蚀工艺刻蚀叠置结构行112和半导体材料层113，形成叠置结构116和半导体层12。
可选地，如图14所示，首先，采用沉积工艺沉积如氧化硅的介质材料，并采用CMO工艺处理，形成第二平坦层114。
然后，在第二平坦层114远离衬底100的一侧形成掩膜结构，掩膜结构包括间隔设置的第一子掩膜结构1151，如图15所示，第一子掩膜结构1151的延伸方向垂直于叠置结构行112的延伸方向。
本申请实施例中，图5-图14为沿第一方向的剖视结构示意图，第二方向垂直于第一方向，图15为在图14所示结构制备得到掩膜结构后的AA向剖面结构示意图，图15中用
Figure PCTCN2022137314-appb-000001
表示第一方向为垂直纸面向内的方向。
接着，基于第一子掩膜结构1151，采用自对准刻蚀工艺刻蚀叠置结构行112和半导体材料层113，形成叠置结构116和半导体层12，叠置结 构116呈阵列排布，并去除未被刻蚀的第二平坦层114，如图16所示，第二沟槽119用于间隔相邻的叠置结构116。
本申请实施例中，第一子掩膜结构1151为硬掩膜，制作材料包括氧化硅，在刻蚀叠置结构行112和半导体材料层113的过程中，能够起到自对准刻蚀的作用，从而保障刻蚀的精度。
如图16所示，叠置结构116包括源极11、漏极14，牺牲结构行1121刻蚀后形成牺牲结构，半导体材料层113刻蚀后形成半导体层12，牺牲结构由于半导体层12的遮挡而不可见，源极11与位线20连接。图16为沿第二方向的剖视结构示意图，图16中用
Figure PCTCN2022137314-appb-000002
表示第一方向为垂直纸面向内的方向。
可选地，在本申请的一个实施例中，上述步骤S406中去除牺牲结构形成孔，包括：采用选择性刻蚀工艺去除牺牲结构，使得源极11、第一半导体层121、第二半导体层122和漏极14围合形成孔。可选地，孔的轴向平行于第二方向、垂直于第一方向。
可选地，在本申请的一个实施例中，上述步骤S407中通过镀膜工艺在孔内、第一半导体层121和第二半导体层122的侧壁填充导电材料，图案化导电材料形成栅极13和与栅极13连接的字线201之前，还包括：通过镀膜工艺和图案化工艺在孔内、第一半导体层121和第二半导体层122的侧壁形成绝缘层15，绝缘层15包括与孔的孔壁随形的第一绝缘层151和与第一半导体层121以及第二半导体层122随形的第二绝缘层152。
可选地，采用沉积工艺形成与源极11、半导体层12的第一半导体层121和第二半导体层122的内侧壁以及漏极14围合形成的腔室的周壁随形的第一绝缘层151，以及形成与源极11、第一半导体层121和第二半导体层122的外侧壁以及漏极14围合形成的凹槽的周壁随形的第二绝缘层152，得到绝缘层15，以使得后续制备栅极13与源极11、漏极14以及第一半导体层121、第二半导体层122相绝缘，如图17所示。
可选地，在本申请的一个实施例中，上述步骤S407中通过镀膜工艺在孔内、第一半导体层121和第二半导体层122的侧壁填充导电材料，图 案化导电材料形成栅极13和与栅极13连接的字线201。具体包括以下步骤：
可选地，首先，采用原子层沉积工艺沉积金属材料，使得金属材料填充第一绝缘层151围合形成的腔室内，填充于第二绝缘层152围合形成的凹槽内，形成初始字线层。
接着，图案化初始字线层，形成字线201、第一栅极131和第二栅极132，如图17所示。图17为沿第一方向的剖视结构示意图，图17中用⊙表示第二方向为垂直纸面向外的方向。
可选地，图案化初始字线层，可以采用SOH(Spin On Hard mask，旋涂于硬掩膜)工艺，在初始字线层的一侧形成自流平的平坦层，然后在平坦层的一侧之形成光刻胶结构，以光刻胶结构为掩膜刻蚀初始字线层。
本申请实施例中，第一栅极131设置于第一绝缘层151围合形成的腔室内，以使得第一栅极131与第一半导体层121、第二半导体层122、源极11和漏极14相绝缘。第二栅极132设置于第二绝缘层152围合形成的凹槽内，以使得第二栅极132与第一半导体层121、第二半导体层122、源极11和漏极14相绝缘。
本申请实施例中，第一半导体层121和第二半导体层122均相对于源极11和漏极14的外轮廓侧向缩进，由于源极11和漏极14是基于外延生长工艺制备得到的，沿垂直于衬底100的方向，源极11和漏极14之间的距离是能够精准控制的，绝缘层15是通过ALD工艺形成的，绝缘层15的厚度也是能够精准控制的，从而使得第一绝缘层151围合形成的腔室的尺寸，以及第二绝缘层152围合形成的凹槽的尺寸能够精准控制，从而能够精准控制形成的第一栅极131和第二栅极132的尺寸，特别是能够精准控制第一栅极131和第二栅极132的长度，从而能够提高栅极13的制备精度，能够保障存储单元的制备精度，进而能够保障存储器中各个存储单元性能的均一性，进而能够保障存储器的性能。
可选地，在本申请的一个实施例中，上述步骤S408中在漏极14远离衬底100的一侧依次形成磁性隧道结20和位线202，包括：在漏极14远 离衬底100的一侧形成连接结构40；在连接结构40的一侧形成与连接结构连接40的磁性隧道结20；形成覆盖磁性隧道结20的封装层60；图案化封装层60并形成与磁性隧道结20连接的位线202。
可选地，采用沉积工艺沉积介质材料，如氧化硅，磨平处理并图案化后形成包括开口的介质结构50，开口使得部分漏极14露出。
然后，在开口内沉积金属材料，例如钛、钴等金属材料，并采用退火工艺处理形成硅化物结构41；硅化物结构41的厚度小于开口的深度。
接着，在硅化物结构41远离衬底100的一侧积金属材料，覆盖硅化物结构41并填充开口，形成与介质结构50上表面齐平的金属结构42，得到连接结构40，如图18所示。
然后，在介质结构50和金属结构42远离衬底100的一侧依次形成初始磁性隧道结层、硬掩膜层和第二光刻胶结构。
接着，以第二光刻胶结构为掩膜图案化硬掩膜层，形成硬掩膜结构30，继续以硬掩膜结构30为掩膜图案化初始磁性隧道结层，形成磁性隧道结20。在形成磁性隧道结20的过程中，硬掩膜结构30可以起到保护磁性隧道结20的作用。
然后，在硬掩膜结构30远离衬底100的一侧沉积形成封装层60，封装层60覆盖磁性隧道结20的侧壁，如图19所示。
接着，在封装层60远离衬底100的一侧形成包括开口的隔离层70，隔离层70的开口使得部分硬掩膜结构30露出，在隔离层70的开口内沉积金属材料，形成位线202，形成如图2所示的存储器。
应用本申请实施例，至少能够实现如下有益效果：
在本申请实施例提供的存储器中，通过设置存储单元200的晶体管10为双沟道晶体管，从而能够提高晶体管10的开态电流，能够提高存储单元200的读写速度，能够提高存储器的性能。
同时，每个存储单元200配置有一条字线201、一条位线202和两条源线203，两条相邻的源线203通过源极11分别与晶体管10的第一沟道和第二沟道电连接，从而能够降低每条源线203的电流，从而能够降低源 线203流经电流对存储器其它部件的影响。
在本申请的描述中，词语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方向或位置关系，为基于附图所示的示例性的方向或位置关系，是为了便于描述或简化描述本申请的实施例，而不是指示或暗示所指的装置或部件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
以上所述仅是本申请的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请的方案技术构思的前提下，采用基于本申请技术思想的其他类似实施手段，同样属于本申请实施例的保护范畴。

Claims (14)

  1. 一种存储器，其特征在于，包括：
    多个存储单元，所述存储单元包括晶体管和磁性隧道结，所述磁性隧道结的一端与所述晶体管电连接；所述晶体管为双沟道晶体管，包含第一沟道和第二沟道；
    多条字线，一条所述字线与同一行所述存储单元中所述晶体管的各栅极电连接；
    多条位线，一条所述位线与同一列所述存储单元中各所述磁性隧道结的另一端电连接；
    多条源线，一列所述存储单元中各所述晶体管的源极同时与两条相邻的所述源线电连接，所述两条相邻的源线通过所述源极分别与所述第一沟道和第二沟道电连接。
  2. 根据权利要求1所述的存储器，其特征在于，沿平行衬底的第一方向，与同一列所述存储单元电连接的所述源线分别为第一源线和第二源线；
    两列相邻的所述存储单元中，与一列所述存储单元的各所述源极连接的所述第二源线，和另一列所述存储单元的各所述源极连接的所述第一源线之间设置有隔离结构。
  3. 根据权利要求1所述的存储器，其特征在于，所述晶体管为垂直晶体管，所述晶体管和所述磁性隧道结沿垂直衬底的方向叠层设置。
  4. 根据权利要求3所述的存储器，其特征在于，所述晶体管包括在衬底上依次叠层设置的源极、半导体层和漏极；
    所述半导体层包括第一半导体层和第二半导体层，所述第一半导体层和所述第二半导体层间隔设置于所述源极的同一侧分别与所述源极接触； 所述第一半导体层包括第一沟道，所述第二半导体层包括第二沟道；
    至少部分所述栅极位于所述第一半导体层和所述第二半导体层之间的间隔区域。
  5. 根据权利要求4所述的存储器，其特征在于，所述栅极包括相互连接的第一栅极和第二栅极；
    所述第一栅极为位于所述第一半导体层和所述第二半导体层之间的间隔区域的部分所述栅极；
    所述第二栅极设置于所述第一半导体层和所述第二半导体层的外侧壁，且与所述第一半导体层、所述第二半导体层、所述源极和所述漏极相绝缘。
  6. 根据权利要求1所述的存储器，其特征在于，所述源极是基于硅掺杂得到的，且所述源极的导电率小于所述源线的导电率。
  7. 一种存储器的读写控制方法，其特征在于，包括：
    在读取阶段，通过字线控制待读取存储单元中晶体管处于导通状态，通过位线或一条源线中的一个向所述待读取存储单元的磁性隧道结传输读取信号，以使得位线或一条源线中的另一个感测所述磁性隧道结的存储数据；
    在写入阶段，通过字线控制待写入存储单元中晶体管处于导通状态，通过位线和两条源线控制存储信号流经待写入存储单元中磁性隧道结的方向，以将所述位线或所述源线传输的所述存储信号写入所述磁性隧道结。
  8. 一种存储器的制造方法，其特征在于，包括：
    通过图案化工艺在衬底上形成多个第一沟槽以区分多个晶体管行区域，每个所述第一沟槽的侧面为叠置的源极行、第一牺牲结构行和漏极行；
    通过退火工艺和图案化工艺在所述第一沟槽内形成相互绝缘的两条 源线，至少部分所述源线位于所述源极行的下方；
    每个所述晶体管行区域，对露出在所述第一沟槽侧面的所述第一牺牲结构行进行回刻处理形成牺牲结构行，所述源极行、所述牺牲结构行和所述漏极行的侧壁形成U型沟槽；
    每个所述晶体管行区域，在所述U型沟槽内形成半导体材料层；
    图案化所述晶体管行区域，形成多个垂直于所述第一沟槽的第二沟槽以区分多个晶体管区域，每个所述晶体管区域包括叠置的所述源极行形成的源极、所述半导体材料层形成的半导体层和所述漏极行形成的漏极；所述牺牲结构行形成的牺牲结构与所述半导体层同层设置，并位于所述半导体层包括的第一半导体层和第二半导体层之间；
    去除所述牺牲结构形成孔；
    通过镀膜工艺在所述孔内、所述第一半导体层和所述第二半导体层的侧壁填充导电材料，图案化所述导电材料形成栅极和与栅极连接的字线；
    在所述漏极远离所述衬底的一侧依次形成磁性隧道结和位线。
  9. 根据权利要求8所述的存储器的制造方法，其特征在于，所述通过退火工艺和图案化工艺在所述第一沟槽内形成相互绝缘的两条源线，至少部分所述源线位于所述源极行的下方，包括：
    沿所述第一沟槽的底部刻蚀处理所述衬底，形成与所述第一沟槽连通的第一弧形槽；
    在所述第一弧形槽和部分所述第一沟槽内填充金属材料，采用退火工艺处理所述金属材料，形成部分表面与所述第一弧形槽随形的源线结构；
    图案化所述源线结构，形成相互分离的两条所述源线。
  10. 根据权利要求9所述的存储器的制造方法，其特征在于，所述图案化所述源线结构，形成相互隔离的两条所述源线之后还包括：
    在所述第一弧形槽内填充介质材料，形成位于两条所述源线之间的阻隔结构。
  11. 根据权利要求8所述的存储器的制造方法，其特征在于，所述在所述U型沟槽内形成半导体材料层，包括：
    采用外延生长工艺在所述U型沟槽内生长半导体材料，形成截面与所述U型沟槽截面形状相一致的U型沟槽半导体材料层、或者截面为柱状的半导体材料层。
  12. 根据权利要求8所述的存储器的制造方法，其特征在于，所述通过图案化工艺在衬底上形成多个第一沟槽以区分多个晶体管行区域，每个所述第一沟槽的侧面为叠置的源极行、第一牺牲结构行和漏极行，之前还包括：
    通过外延生长工艺在所述衬底的一侧依次形成第一硅掺杂导电层、牺牲半导体层和第二硅掺杂导电层；所述源极行、所述第一牺牲结构行和所述漏极行分别基于所述第一硅掺杂导电层、所述牺牲半导体层和所述第二硅掺杂导电层形成。
  13. 根据权利要求8所述的存储器的制造方法，其特征在于，所述通过镀膜工艺在所述孔内、所述第一半导体层和所述第二半导体层的侧壁填充导电材料，图案化所述导电材料形成栅极和与栅极连接的字线，之前还包括：
    通过镀膜工艺和图案化工艺在所述孔内、所述第一半导体层和所述第二半导体层的侧壁形成绝缘层，所述绝缘层包括与所述孔的孔壁随形的第一绝缘层和与所述第一半导体层以及所述第二半导体层随形的第二绝缘层。
  14. 根据权利要求8所述的存储器的制造方法，其特征在于，所述在所述漏极远离所述衬底的一侧依次形成磁性隧道结和位线，包括：
    在所述漏极远离所述衬底的一侧形成连接结构；
    在所述连接结构的一侧形成与所述连接结构连接的磁性隧道结；
    形成覆盖所述磁性隧道结的封装层；
    图案化所述封装层并形成与所述磁性隧道结连接的位线。
PCT/CN2022/137314 2022-08-18 2022-12-07 存储器及其制造方法、读写控制方法 WO2024036828A1 (zh)

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