WO2024036827A1 - 存储器及其制造方法、读写控制方法 - Google Patents

存储器及其制造方法、读写控制方法 Download PDF

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Publication number
WO2024036827A1
WO2024036827A1 PCT/CN2022/137312 CN2022137312W WO2024036827A1 WO 2024036827 A1 WO2024036827 A1 WO 2024036827A1 CN 2022137312 W CN2022137312 W CN 2022137312W WO 2024036827 A1 WO2024036827 A1 WO 2024036827A1
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semiconductor layer
source
memory
substrate
gate
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PCT/CN2022/137312
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English (en)
French (fr)
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李辉辉
张云森
王桂磊
赵超
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北京超弦存储器研究院
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Publication of WO2024036827A1 publication Critical patent/WO2024036827A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • the present application relates to the field of semiconductor technology. Specifically, the present application relates to a memory, a manufacturing method thereof, and a read-write control method.
  • MRAM Magneticoresistive Random Access Memory
  • each memory cell in MRAM needs to be provided with bit lines, word lines, and source lines, which results in a lot of wiring in MRAM and increases the design and manufacturing costs of MRAM.
  • This application proposes a memory, a manufacturing method thereof, and a read/write control method, which are at least used to improve the deficiencies in the background technology.
  • Some embodiments of the present application provide a memory, including: multiple rows and multiple columns of memory cells, multiple rows of word lines, multiple column bit lines, and multiple column source lines;
  • the memory unit includes: a transistor and a magnetic tunnel junction; the transistor includes a first channel and a second channel;
  • One end of the magnetic tunnel junction is electrically connected to the drain of the transistor, and the other end is electrically connected to the bit line; the gate of the transistor in each memory cell in the same row is electrically connected to the word line; the source of each transistor in a column of memory cells is simultaneously connected to both The source lines are electrically connected.
  • one source line is electrically connected to the first channel of each transistor in the same column of memory cells, and the other source line is electrically connected to the second channel of each transistor in the same column of memory cells. ;
  • one end of a source line is electrically connected to the source of each transistor in one column of memory cells, and the other end of the source line is electrically connected to the source of each transistor in the other column of memory cells.
  • Some embodiments of the present application provide a memory read and write control method, including:
  • the word line controls the transistor in the memory cell to be read to be in the on state, and the read signal is transmitted to the magnetic tunnel junction of the memory cell to be read through one of the bit lines or a source line, so that the bit line or another sensing magnetic tunnel junction in one source line to store data;
  • the word line is used to control the transistor in the memory cell to be written to be in the on state
  • the bit line and two source lines are used to control the direction of the storage signal flowing through the magnetic tunnel junction in the memory cell to be written to turn the bit line Or the storage signal transmitted by the source line is written into the magnetic tunnel junction.
  • Some embodiments of the present application provide a memory manufacturing method, including:
  • a stacked structure of multiple source lines and multiple arrays is formed on one side of the substrate;
  • the stacked structure includes a stacked source electrode, a sacrificial semiconductor structure and a drain electrode, and the two outer sides of the sacrificial semiconductor structure
  • the walls are respectively provided with a first semiconductor layer and a second semiconductor layer, and the sources of any two stacked structures adjacent in the row direction are connected to the same source line;
  • connection structure and a magnetic tunnel junction are formed in sequence on the side of the source of the transistor away from the substrate;
  • a bit line is formed on the side of the magnetic tunnel junction away from the substrate.
  • one end of a source line is electrically connected to the source of each transistor in one column of memory cells, and the other end of the source line is electrically connected to the source of each transistor in another column of memory cells. Therefore, two columns of memory cells can be controlled simultaneously through one source line, thereby reducing the number of source lines in the memory, reducing the difficulty of wiring layout in the memory, and reducing the design cost and manufacturing cost of the memory.
  • Figure 1 is a schematic circuit diagram of a memory provided by some embodiments of the present application.
  • Figure 2 is a schematic structural diagram of a memory provided by some embodiments of the present application.
  • Figure 3 is a schematic cross-sectional structural diagram along the direction AA of the memory shown in Figure 1 provided by some embodiments of the present application;
  • Figure 4 is a schematic structural diagram of another memory provided by some embodiments of the present application.
  • Figure 5 is a schematic structural diagram of another memory provided by some embodiments of the present application.
  • Figure 6 is a BB-direction cross-sectional structural diagram of the vertical transistor in the memory shown in Figure 5;
  • Figure 7 is a schematic flow chart of a memory manufacturing method provided by some embodiments of the present application.
  • Figure 8 is a schematic structural diagram of the first photoresist structure and the first mask structure obtained in the memory manufacturing method according to some embodiments of the present application;
  • Figure 9 is a schematic structural diagram after obtaining the initial stacked structure row in the manufacturing method of a memory provided by some embodiments of the present application.
  • Figure 10 is a schematic structural diagram after obtaining the first arc-shaped groove in a memory manufacturing method according to some embodiments of the present application.
  • Figure 11 is a schematic structural diagram of a metal layer obtained in a memory manufacturing method according to some embodiments of the present application.
  • Figure 12 is a schematic structural diagram after bit lines are obtained in a memory manufacturing method according to some embodiments of the present application.
  • Figure 13 is a schematic structural diagram after obtaining the first flat layer in a memory manufacturing method according to some embodiments of the present application.
  • Figure 14 is a schematic structural diagram of a first flat structure obtained in a memory manufacturing method according to some embodiments of the present application.
  • Figure 15 is a schematic structural diagram of a stacked structure obtained in a memory manufacturing method according to some embodiments of the present application.
  • Figure 16 is a schematic structural diagram of semiconductor lines obtained in a memory manufacturing method according to some embodiments of the present application.
  • Figure 17 is a schematic structural diagram after obtaining the second flat layer in the manufacturing method of the memory provided by some embodiments of the present application.
  • Figure 18 is a schematic diagram of the CC cross-sectional structure after the mask structure is produced from the structure shown in Figure 16 in the manufacturing method of the memory provided in some embodiments of the present application;
  • Figure 19 is a schematic structural diagram of a semiconductor layer produced based on the structure shown in Figure 17 in a memory manufacturing method according to some embodiments of the present application;
  • Figure 20 is a schematic structural diagram after forming word lines in a memory manufacturing method according to some embodiments of the present application.
  • Figure 21 is a schematic structural diagram after forming a connection structure in a memory manufacturing method according to some embodiments of the present application.
  • Figure 22 is a schematic structural diagram after forming an encapsulation layer in a memory manufacturing method according to some embodiments of the present application.
  • 200-memory cell 201-word line; 2011-first sub-segment; 2012-second sub-segment; 202-bit line; 203-source line; 2031-the first part of source line 203; 2032-the third part of source line 203 Part Two;
  • 112-Stacked structure row 1121-Sacrificial semiconductor row; 113-Semiconductor row; 114-Second planarization layer; 1151-First sub-mask structure; 116-Stacked structure.
  • MRAM is a non-volatile magnetic random access memory.
  • the data stored in MRAM is stored in a magnetic state instead of charges.
  • the polarity of the magnetic field does not change with the charge like charges. leaks over time, so information is retained even in the event of a power outage.
  • MRAM often includes multiple memory cells arranged in an array. Each memory unit needs to be provided with bit lines, word lines and bit lines. The memory cells are often arranged in an array, which results in more wiring in the MRAM and leads to the Increased design costs and manufacturing costs.
  • the manufacturing precision of the semiconductor structure and gate of the vertical transistor in the MRAM memory unit is low, which leads to differences in the performance of the VGAA transistors in the memory and affects the performance of the memory.
  • vertical transistors face the bottleneck of further increasing the driving current. For example, as the size of vertical transistors decreases, the on-state current of the vertical transistors decreases, resulting in reduced driving performance and slower turn-on speed of the transistors, which in turn affects the performance of the memory.
  • the memory, its manufacturing method, and the read and write control method provided by this application are intended to solve the above technical problems of the prior art.
  • the memory includes: multiple rows and multiple columns of memory cells 200, multiple rows of word lines 201, multiple column bit lines 202, and multiple column source lines 203. ;
  • the memory unit 200 includes: a transistor 10 and a magnetic tunnel junction 20; the transistor 10 includes a first channel and a second channel.
  • One end of the magnetic tunnel junction 20 is electrically connected to the drain 14 of the transistor 10, and the other end is electrically connected to the bit line 202; the source 11 of the transistor 10 in any two adjacent memory cells 200 along the row direction is connected to the same source line 203. Electrically connected, the gate 13 of the transistor 10 in each memory cell 200 in the same row is electrically connected to the word line 201.
  • One end of the magnetic tunnel junction 20 is electrically connected to the drain 14 of the transistor 10, and the other end is electrically connected to the bit line 202; the gate 13 of the transistor 10 and the word line 201 of each memory cell 200 in the same row are electrically connected; one column of memory cells 200
  • the source 11 of each transistor 10 is electrically connected to two source lines 203 at the same time.
  • one source line 203 is electrically connected to the first channel of each transistor 10 in the same column of memory cells 200
  • the other source line 203 is electrically connected to the first channel of each transistor 10 in the same column of memory cells 200.
  • the line 203 is electrically connected to the second channel of each transistor 10 in the same column of memory cells 200; in any two adjacent columns of memory cells 200, one end of a source line 203 is connected to the source 11 of each transistor 10 in a column of memory cells 200. The other end of the source line 203 is electrically connected to the source 11 of each transistor 10 in another column of memory cells 200 .
  • one end of a source line 203 is electrically connected to the source 11 of each transistor 10 in one column of memory cells 200, and the other end of the source line 203 is electrically connected to each transistor in another column of memory cells 200.
  • the source 11 of 10 is electrically connected, so that two columns of memory cells 200 can be controlled simultaneously through one source line 203, thereby reducing the number of source lines 203 in the memory, reducing the difficulty of wiring wiring in the memory, and reducing the memory cost. Design costs and manufacturing costs.
  • multiple memory cells 200 are arranged in an array, that is, the transistors 10 of each memory unit 200 are arranged in an array. It is defined herein that the direction extending parallel to the word line 201 is a row, and the direction parallel to the source line 203 is a column. As shown in Figure 1, the direction from left to right is a row, and the direction from top to bottom is a column. Figure 1 exemplarily shows the transistors 10 of two memory cells in the same row, that is, they are shown respectively. One memory cell 200 for each column of two columns of memory cells 200 is shown.
  • one end and the other end of the source line 203 do not refer to the two free ends of a source line 203, but refer to a certain part of the source line 203. Alternatively, they may refer to The portion of the source line 203 along the radial direction is shown in FIG. 2 .
  • each memory cell 200 includes a transistor 10 and a magnetic tunnel junction 20 , and the transistor 10 and the magnetic tunnel junction 20 are electrically connected.
  • one end of the magnetic tunnel junction 20 is electrically connected to the drain electrode 14 of the transistor 10 .
  • the sources 11 of the transistors 10 in any two adjacent memory cells 200 in the row direction are electrically connected to the same source line 203 , so that the memory cells 200 in any two adjacent rows are configured with three source lines 203 That is, compared with the memory of the related art, the number of source lines 203 in the memory can be greatly reduced, thereby reducing the difficulty of wiring arrangement in the memory and reducing the design cost and manufacturing cost of the memory.
  • the other end of the magnetic tunnel junction 20 is electrically connected to the bit line 202 , and the gate electrode 13 of the transistor 10 in each memory cell 200 in the same row is electrically connected to the word line 201 .
  • the transistor 10 is controlled to turn on through the word line 201, the data reading of the two columns of memory cells 200 can be controlled through the same source line 203 electrically connected to the two columns of memory cells 200, thereby improving the data reading speed of the memory.
  • Data writing of two columns of memory cells 200 can be controlled through three source lines 203 .
  • the magnetic tunnel junction 20 includes a MTJ (Magnetic Tunnel Junctions), and the MRAM determines whether the stored data is "0" or "1” by detecting the resistance of the MTJ.
  • MTJ Magnetic Tunnel Junctions
  • the MTJ includes a free layer, a tunneling layer and a fixed layer stacked in sequence.
  • the direction of the magnetic field of the free layer can be changed, while the direction of the magnetic field of the fixed layer is fixed. Under the action of the electric field, electrons will pass through the tunnel layer barrier and pass through the device vertically.
  • the MTJ presents a low resistance state "0".
  • the magnetic field direction of the free layer is opposite to that of the fixed layer, the MTJ presents a high resistance state "1".
  • the transistor 10 by arranging the transistor 10 to include a first channel and a second channel, compared with a single-channel transistor, the on-state current of the transistor 10 can be significantly increased, and the driving capability and turn-on of the transistor 10 can be improved. speed, thereby improving memory performance.
  • the transistor 10 is a vertical transistor 10 , and the transistor 10 and the magnetic tunnel junction 20 are stacked in a direction vertical to the substrate 100 .
  • FIG. 2 it is a schematic structural diagram of a memory provided by the embodiment of the present application.
  • the memory unit 200 is disposed on the side of the source line 203 away from the substrate 100.
  • the transistor 10 and the magnetic tunnel junction 20 of each memory cell 200 are stacked in the direction vertical to the substrate 100.
  • the transistor 10 in any two adjacent memory cells 200 along the row direction (ie, the first direction in FIG. 2)
  • the source 11 is electrically connected to the same source line 203 .
  • FIG. 2 is a schematic partial cross-sectional structural diagram of the storage device. Therefore, the source lines 203 on both sides of the first direction are only partially shown. The unshown parts of the two source lines 203 can be found in Middle source line 203.
  • the transistor 10 includes a source electrode 11, a semiconductor layer 12 and a drain electrode 14 which are stacked in sequence on the substrate 100;
  • the semiconductor layer 12 includes a first semiconductor layer 121 and a second semiconductor layer 122,
  • the first semiconductor layer 121 and the second semiconductor layer 122 are spaced apart on the same side of the source electrode 11 and are in contact with the source electrode 11 respectively;
  • the first semiconductor layer 121 includes a first channel, and the second semiconductor layer 122 includes a second channel; at least Part of the gate electrode 13 is located in the spacing area 122 between the first semiconductor layer 121 and the second semiconductor layer.
  • the source electrode 11 , the semiconductor layer 12 and the drain electrode 14 are stacked in sequence.
  • the gate electrode 13 is also located between the source electrode 11 and the drain electrode 14 , that is, the gate electrode 13 and the semiconductor layer 12 are arranged in the same layer.
  • the first semiconductor layer 121 and the second semiconductor layer 122 are spaced apart on the same side of the source electrode 11 and are respectively in contact with the source electrode 11 .
  • the first semiconductor layer 121 includes a first channel when turned on
  • the second semiconductor layer 122 includes a second channel when turned on.
  • the first semiconductor layer 121 and the second semiconductor layer 122 are spaced apart along the row direction; the cross section of the source line 203 is an arc shape with a gap at the top.
  • the same source line In 203, one end close to the gap is the first part 2031 of the source line 203, and the other end close to the gap is the second part 2032 of the source line 203; the first part 2031 and the first semiconductor in at least part of the memory cells 200 in a column of memory cells 200
  • the layer 121 is connected and the second portion 2032 is connected to the second semiconductor layer 122 in at least part of the memory cells 200 in another column of memory cells 200 .
  • the first semiconductor layer 121 and the second semiconductor layer 122 in the transistor 10 are spaced apart along the row direction, that is, spaced apart along the first direction parallel to the substrate 100.
  • the cross section of the source line 203 is an arc shape with a gap at the top, and in the same source line 203, one end close to the gap is the first part 2031, and the other end close to the gap is the first part 2031.
  • the source electrode 11 is made of lightly doped semiconductor material, so that the conductivity of the source electrode 11 is smaller than the conductivity of the source line 203 .
  • the semiconductor layer 12 in the transistor 10 includes a first semiconductor layer 121 and a second semiconductor layer 122 arranged at intervals. In the conductive state, the first semiconductor layer 121 includes a first channel, and the second semiconductor layer 122 includes a first channel, a first channel, and a second semiconductor layer 122 .
  • the semiconductor layer 122 includes a second channel, which is equivalent to each transistor 10 including two parallel-connected sub-transistors, thereby increasing the on-state current of the transistor 10 while reducing the current passing through each sub-transistor, thereby reducing the transistor cost.
  • a loss rate of 10 can extend the service life of the transistor 10.
  • the orthographic projection of the first part 2031 on the substrate 100 overlaps with the projection of the first semiconductor layer 121 on the substrate 100 , and overlaps with the projection of the second semiconductor layer 121 on the substrate 100 .
  • the projection of the layer 122 on the substrate 100 has no overlap; the orthographic projection of the second part 2032 on the substrate 100 overlaps with the projection of the second semiconductor layer 122 on the substrate 100 and overlaps with the projection of the first semiconductor layer 121 on the substrate
  • the projections on 100 have no overlap.
  • each source line 203 by setting each source line 203 to include a second part 2032 of the first part 2031, for the same source line 203, the first part 2031 can control each transistor 10 in a column of memory cells 200, and the second part 2031 can control the transistors 10 in a column of memory cells 200.
  • the part 2032 can control each transistor 10 in another column of memory cells 200, so that two columns of memory cells 200 can be controlled simultaneously through one source line 203, thereby reducing the number of source lines 203 in the memory and reducing the wiring arrangement in the memory. Difficulty, can reduce the design cost and manufacturing cost of memory.
  • the orthographic projection of the first part 2031 of the source line 203 on the substrate 100 only overlaps with the projection of the first semiconductor layer 121 on the substrate 100 , and the second part 2032 on the substrate 100
  • the orthographic projection only overlaps with the projection of the second semiconductor layer 122 on the substrate 100 , and the difference is that the thickness of the source electrode 11 is different.
  • Those skilled in the art can set the source electrode 11 with corresponding thickness according to different selections of materials for making the source electrode 11, so that the first part 2031 can control the first semiconductor layer 121 and the second part 2032 can control the second semiconductor layer 122.
  • the first part 2031 and the second part 2032 of the source line 203 are divided by dividing lines in Figures 4 and 5. 2032 boundary, in actual products, the first part 2031 and the second part 2032 of the source line 203 are manufactured at the same time, and there is no dividing line between the first part 2031 and the second part 2032 as shown in Figures 4 and 5.
  • the first part 2031 is in contact with the lower surface of the source electrode 11 and close to the area of the first semiconductor layer 121
  • the second part 2032 is in contact with the source electrode 11 .
  • the lower surface of the source electrode 11 and the area close to the second semiconductor layer 122 are in contact, and the projections of the first part 1031 and the second part 2032 within the projection of the source electrode 11 do not overlap.
  • the first part 2031 of a source line 203 is located on the side of a source electrode 11 away from the first semiconductor layer 121 , and the second part 2032 of the same source line 203 Located on the side of the other source electrode 11 away from the second semiconductor layer 122 .
  • the projection of the first part 1031 of one source line 203 on the source 11 does not overlap with the projection of the second part 2032 of another adjacent source line 203 on the same source 11, so that through the first part 2031 and the The second part 2032 is able to control the transistor 10 independently.
  • the memory includes a substrate 100 disposed below the source electrode 11 , and the source electrodes 11 of the transistors 10 in any two adjacent columns of memory cells 200 A trench is opened in the substrate 100 between them; the bottom of the trench and the two sidewalls are made of metal silicide; the two sidewalls of the trench are respectively recessed below the source electrodes 11 of the two adjacent columns. ; The two adjacent sidewalls of two adjacent trenches located below the source electrode 11 belong to the first part 2031 and the second part 2032 respectively; the material of the portion of the substrate 100 located between the two adjacent sidewalls for silicon.
  • the side of the source 11 away from the semiconductor layer is the substrate 100 of the memory.
  • the substrate 100 is a silicon substrate.
  • a trench is opened in the substrate 100 between any two adjacent columns of source electrodes 11, and the opening of the trench faces the word line 201.
  • the silicon substrate is opened from the inside of the trench.
  • the material within a certain radial thickness starting from the peripheral surface is metal silicide.
  • the trench includes a bottom and two sidewalls connected to the bottom.
  • the bottom and sidewalls of the trench are jointly formed.
  • the cross-sectional shape of the groove is arc-shaped.
  • the two side walls of the trench are respectively recessed below the source electrodes 11 in two adjacent columns, so that part of the side walls are located below the source electrodes 11 , and the adjacent side walls are located below the source electrodes 11 .
  • Two adjacent side walls of the two trenches belong to the first part 2031 and the second part 2032 respectively, that is, the materials of the first part 2031 and the second part 2032 are both metal silicide.
  • the portion of the substrate 100 located between the first part 2031 and the second part 2032 is made of silicon, thereby preventing the adjacent first part 2031 and the second part 2032 from being electrically connected.
  • the metal silicide of the bottom of the trench and the two sidewalls are formed simultaneously through a metal silicide process.
  • the source electrode 11 is based on silicon doping, and the conductivity of the source electrode 11 is less than the conductivity of the first part 2031 and the second part 2032 .
  • the source electrode 11 is made of lightly doped semiconductor material, and the size of the source electrode 11 in the direction perpendicular to the substrate 100 can be appropriately reduced, so that part of the first part 2031 and part of the second part 2032 can function. to the source 11 to ensure the performance of the vertical transistor 10 .
  • each vertical transistor 10 is equivalent to two parallel sub-transistors. This can avoid physically isolating the source of the sub-transistor, simplify the preparation process of the thin film transistor, and reduce the manufacturing cost of the thin film transistor.
  • the projection of the source 11 on the substrate 100 covers part of the projection of the source line 203 on the substrate; in the radial plane of the source line 203, the cross-sectional shape of the source line 203 is an arc.
  • One side of the shaped source line 203 is connected to the source electrode 11 of each transistor 10 of one column of memory cells 200, and the other side is connected to the source electrode 11 of each transistor 10 of another column of memory cells.
  • the source line 203 is located between the substrate 100 and the transistor 10 .
  • the projection of the source 11 of the transistor 10 on the substrate 100 covers part of the projection of the source line 203 on the substrate 100 , that is, The source electrode 11 covers part of the source line 203 .
  • the cross-sectional shape of the source line 203 is arc-shaped, and one side of the arc-shaped source line 203 is in contact with the transistor 10 of a column of memory cells 200 .
  • the source electrode 11 is connected, and the other side is connected to the source electrode 11 of each transistor 10 of another column of memory cells 200, so that the memory cells 200 of the two columns can be connected through one source line 203.
  • a source line 203 with an arc-shaped cross-section can avoid right-angled portions of the source line 203, thereby avoiding the tip effect. Able to ensure memory performance.
  • the gate 13 includes a first gate 13 and a second gate 13 connected to each other; the first gate 131 is located between the spacing area of the first semiconductor layer 121 and the second semiconductor layer 122 .
  • the second gate electrode 132 is disposed on the outer side walls of the first semiconductor layer 121 and the second semiconductor layer 122 and is insulated from the first semiconductor layer 121, the second semiconductor layer 122, the source electrode 11 and the drain electrode 14 .
  • the gate 13 includes a first gate 13 and a second gate 13; the first gate 13 is disposed between the two first semiconductor layers 121 and the second semiconductor layer 122, and is connected to The first semiconductor layer 121, the second semiconductor layer 122, the source electrode 11 and the drain electrode 14 are insulated from each other; the second gate electrode 13 is disposed on the outer wall of the semiconductor layer 12 and is in contact with the semiconductor layer 12, the source electrode 11 and the drain electrode 14. insulation.
  • the transistor 10 further includes a gate insulating layer 15 .
  • the gate insulating layer 15 is made of a high-k value dielectric material.
  • the gate insulating layer 15 includes a first gate insulating layer 151 and two second gate insulating layers 152 .
  • the first gate insulating layer 151 conforms to the inner walls of the source 11 , the first semiconductor layer 121 and the second semiconductor layer 122 , and the peripheral wall of the cavity formed by the drain electrode 14 ;
  • the second gate insulating layer 152 conforms to the source 11
  • the electrode 11, the outer side walls of the first semiconductor layer 121 and the second semiconductor layer 122, and the peripheral wall of the groove formed by the drain electrode 14 conform to the shape.
  • the first gate 131 of the gate 13 is located between two spaced apart semiconductor layers 12 .
  • the first gate 131 is disposed on the first gate insulating layer.
  • 151 encloses the formed cavity, so that the first gate electrode 131 is insulated from the semiconductor layer 12 , the source electrode 11 and the drain electrode 14 .
  • the second gate 132 of the gate 13 is located on the outer wall of the semiconductor layer 12 .
  • the second gate 132 is disposed in a groove formed by the second gate insulating layer 152 .
  • the second gate electrode 132 is insulated from the semiconductor layer 12 , the source electrode 11 and the drain electrode 14 .
  • both the first gate 13 and the second gate 13 are connected to the word line 201 .
  • the word line 201 extends along a first direction parallel to the substrate 100 .
  • the source line 203 extends along a second direction parallel to the substrate 100 . The direction is perpendicular to the second direction.
  • the extension direction of the bit line 202 is parallel to the extension direction of the source line 203 .
  • the first gate 131 and the second gate 132 of the gate 13 are both connected to the word line 201, so that the first gate 131 and the second gate 132 can be connected to the first gate 131 and the second gate 132 through the word line 201.
  • Applying a voltage level to the second gate 132 at the same time can further enhance the electric field strength of the gate 13, which can help to increase the on-state current of the transistor 10, thereby helping to improve the driving capability and turn-on speed of the transistor 10, which can help Improving the reading and writing speed of the storage unit 200 helps to improve the performance of the memory.
  • the word line 201 includes a plurality of first sub-segments 2011 and second sub-segments 2012 connected alternately in sequence; the first sub-segments 2011 surround the first gate 13 and the second gate 13, and The first gate 13 and the second gate 13 are both connected; one end of the second sub-section 2012 is connected to one first sub-section 2011, and the other end is connected to another first sub-section 2011.
  • the first sub-segments 2011 and the second sub-segments 2012 are connected alternately in sequence.
  • the first sub-section 2011 is arranged around the first gate 131 and the second gate 132, that is, the first sub-section 2011 wraps the two end surfaces of the first gate 131. and both end surfaces of the second gate 132, thereby being connected to both the first gate 131 and the second gate 132.
  • the upper surface of the first sub-section 2011 is flush with the upper surface of the first gate 131 , thereby preventing the first sub-section 2011 from contacting the drain 14 of the transistor 10 .
  • the second subsection 2012 is located between two adjacent transistors 10 and is used to connect the first subsection 2011 surrounding the first gate 131 and the second gate 132 .
  • the upper surface of the second sub-segment 2012 is flush with the upper surface of the first sub-segment 2011, which can reduce the probability of the second sub-segment 2012 contacting the drain 14 of the transistor 10, and can reduce the probability of parasitic capacitance between the two, and thus Able to ensure memory performance.
  • the first sub-segment 2011 and the second sub-segment 2012 are shown with dotted lines in FIGS. 2, 3 and 4.
  • the first sub-segment 2011, the second sub-segment 2012 and the gate 13 use the same Made of this kind of material, there are no dotted lines as shown in Figures 2, 3 and 4.
  • the projection of the outer contours of the source electrode 11 and the drain electrode 14 on the substrate, the outer contour surrounding the first semiconductor layer 121, the second semiconductor layer 122 and the first gate electrode 131 are projected on the substrate.
  • the projection on the bottom causes the source electrode 11 and the drain electrode 14 to protrude outward relative to the first semiconductor layer 121 , the second semiconductor layer 122 and the first gate electrode 131 .
  • the orthographic projection of the outer contour of the drain 14 of the source 11 on the substrate 100 surrounds the first semiconductor layer 121 , the second semiconductor layer 122 and the first gate.
  • the orthographic projection of the outer contour of the pole 131 on the substrate 100 As shown in FIG. 1 , the cross-sectional pattern formed by the combination of the source electrode 11 , the semiconductor layer 12 , the first gate electrode 131 and the drain electrode 14 is an I-shape.
  • the projection of the outer contours of the source electrode 11 and the drain electrode 14 on the substrate overlaps with the projection of the outer contour of the second gate electrode 13 on the substrate.
  • the orthographic projection of the outer contours of the electrode 11 and the drain electrode 14 on the substrate 100 overlaps with the orthographic projection of the outer contour of the second gate electrode 132 on the substrate 100 , so that the source The outer side walls of the electrode 11 and the drain electrode 14 are flush with the outer side walls of the second gate electrode 132 .
  • the gate 13 includes a first gate 131 and a second gate 132 connected to each other; the gate 13 is columnar as a whole, and the gate 13 Different areas on the upper surface of 131 have two mutually independent openings extending to the lower surface respectively; the two openings are filled with the first semiconductor layer 121 and the second semiconductor layer 122 respectively, and the first semiconductor layer 121 and the second semiconductor layer 122 is insulated from the gate 13 in the opening by the gate insulating layer 15 .
  • the first gate 131 and the second gate 132 of the gate 13 form an overall structure.
  • the gate 13 is provided with two independent openings.
  • the structure located between the two openings in the gate 13 is the first gate 131 , and the structure located outside the opening is the second gate 132 .
  • One of the two openings is filled with the first semiconductor layer 121 and the other is filled with the second semiconductor layer 122 .
  • both openings are filled with a gate insulating layer 15.
  • the gate insulating layer 15 includes a first gate insulating layer 151 and a second gate insulating layer 152.
  • the first gate insulating layer 151 is located on the sidewall of the opening close to the first gate 131
  • the second gate insulating layer 152 is located on the sidewall of the opening close to the second gate 132 .
  • the first semiconductor layer 121 and the second semiconductor layer 122 are located in the corresponding openings and are insulated from the gate electrode 13 by the first gate insulating layer 151 and the second gate insulating layer 152 .
  • the memory unit 200 further includes: a connection structure 40 disposed on a side of the drain electrode 14 away from the source electrode 11 ; and a magnetic tunnel junction 20 disposed on a side of the connection structure away from the drain electrode 14 .
  • the transistor 10 and the connection structure 40 are stacked in a direction perpendicular to the substrate 100 , and the connection structure 40 is provided on the side of the drain electrode 14 of the transistor 10 away from the source electrode 11 .
  • connection structure 40 is used to realize the electrical connection between the transistor 10 and the magnetic tunnel junction 20 .
  • This facilitates the separate production of the transistor 10 and the magnetic tunnel junction 20.
  • first use a production line to sequentially form the source line 203, the transistor 10, the word line 201 and the connection structure 40 on one side of the substrate 100, and then use another production line.
  • the wires form a magnetic tunnel junction 20, thereby enabling memory production efficiency to be improved.
  • the connection structure 40 includes a suicide structure 41 and a metal structure 42 .
  • the drain electrode 14 is mostly made of doped semiconductor materials, there is a significant difference in conductivity between the drain electrode 14 and the metal structure 42 .
  • the silicide structure 41 By providing the silicide structure 41 , the interface resistance between the metal structure 42 and the drain electrode 14 can be reduced. The performance of the storage unit 200 can be guaranteed.
  • the memory also includes a dielectric structure 50 .
  • the dielectric structure 50 can be made of the same dielectric material as the gate insulating layer 15 .
  • the connection structure 40 is disposed in the opening of the media structure 50 .
  • a hard mask structure 30 is provided on the side of the magnetic tunnel junction 20 away from the substrate 100 .
  • the hard mask structure 30 can protect the magnetic tunnel.
  • the hard mask structure 30 includes metal and dielectric materials. Therefore, the hard mask structure 30 has certain electrical conductivity.
  • the hard mask structure 30 is connected to the bit line 202 , thereby realizing the connection between the bit line 202 and the magnetic tunnel junction 20 . Electrical connection.
  • the hardness of the hard mask structure 30 is relative to the hardness of the photoresist, and the materials of the hard mask structure 30 include silicon oxide, silicon nitride, etc.
  • an encapsulation layer 60 is provided on the side of the hard mask structure 30 away from the substrate 100 .
  • the encapsulation layer 60 covers the side walls of the magnetic tunnel junction 20 to avoid external water, oxygen, etc. Eroding the magnetic tunnel junction20.
  • the material of the encapsulation layer 60 includes dense materials such as silicon nitride, aluminum oxide, and magnesium oxide.
  • embodiments of the present application provide an electronic device, including any memory as provided in the above embodiments.
  • the electronic device includes a smartphone, computer, tablet, artificial intelligence device, wearable device or power bank.
  • the electronic equipment is not limited to the above-mentioned types. Persons skilled in the art can install any of the memories provided by the above embodiments of the present application in different devices according to actual application requirements, thereby obtaining the results of the present application.
  • the electronic device provided by the embodiment provided by the embodiment.
  • embodiments of the present application provide a memory read and write control method, including:
  • the transistor 10 in the memory cell 200 to be read is controlled to be in a conductive state through the word line 201, and the read is transmitted to the magnetic tunnel junction 20 of the memory cell 200 to be read through one of the bit lines 202 or a source line 203.
  • a signal is taken such that the other of the bit line 202 or one of the source lines 203 senses the stored data of the magnetic tunnel junction 20 .
  • the word line 201 is used to control the transistor 10 in the memory cell 200 to be written to be in a conductive state
  • the bit line 202 and the two source lines 203 are used to control the storage signal to flow through the magnetic tunnel junction 20 in the memory cell 200 to be written. direction to write the storage signal transmitted by the bit line 202 or the source line 203 into the magnetic tunnel junction 20 .
  • the memory read and write control method provided by the embodiment of the present application can be used for any memory provided by the above-mentioned embodiments.
  • the first level is input to the gate 13 of the transistor 10 in the memory cell 200 to be read through the word line 201, so that the transistor 10 is in a conductive state, and the first level is input through a bit line 202 or A source line 203 senses the change in current or voltage and the degree of change to realize the reading of the data stored in the magnetic tunnel junction 20 .
  • the following takes sensing current changes through the source line 203 as an example to illustrate how to realize data storage and reading in the magnetic tunnel junction 20 .
  • the MTJ presents a high resistance state at this time.
  • the read signal is transmitted to the magnetic tunnel junction 20 through a bit line 202, that is, to the magnetic tunnel through the bit line 202
  • a second level is applied to the junction 20, and a source line 203 remains at the reference level.
  • the reference level is less than the second level. Since the MTJ presents a high resistance state, the current is difficult to pass through the magnetic tunnel junction 20, that is, the source line 203 is difficult to measure. There is an obvious current.
  • the read data is judged to be "1”, that is, the data stored in the magnetic tunnel junction 205 of the memory cell 200 to be read can be sensed as "1" through a source line 203.
  • the MTJ When the data stored in the magnetic tunnel junction 20 is "0", the MTJ presents a low resistance state at this time.
  • a read signal is transmitted to the magnetic tunnel junction 20 through a bit line 202, that is, a read signal is applied to the magnetic tunnel junction 20 through the bit line 202.
  • a source line 203 At the second level, a source line 203 remains at the reference level. The reference level is lower than the second level. Since the MTJ presents a low resistance state, the current can pass through the magnetic tunnel junction 20, that is, a relatively obvious current can be measured by the source line 203. , in this case, it is determined that the read data is “0”, that is, through a source line 203, it can be sensed that the data stored in the magnetic tunnel junction 20 of the memory unit 200 to be read is “0”.
  • the first level is input to the gate 13 of the transistor 10 in the memory cell 200 to be read through the word line 201, so that the transistor 10 is in a conductive state, and the first level is input through the bit line 202 and the two
  • the source lines 203 control the direction of the storage signal flowing through the magnetic tunnel junction 20 in the memory cell 200 to be written, so that the storage signal transmitted by the bit line 202 or the source line 203 is written into the magnetic tunnel junction 20 .
  • the following takes the transmission of a storage signal to the memory unit 200 to be written through the source line 203 as an example to illustrate how to implement data storage in the magnetic tunnel junction 20 .
  • the third level is applied to the source 11 of the transistor 10 of the memory cell 200 to be written through the source line 203, the bit line 202 is maintained at the reference level, and the third level is greater than Reference level, since the third level is applied to both source lines 203, the potential difference between the two ends of the magnetic tunnel junction 20 is large enough, and the current including the storage signal flows from the source line 203 to the bit line 202, and when the current flows through the magnetic tunnel During the process of junction 20, the magnetic field direction of the free layer of the magnetic tunnel junction 20 will change and be opposite to the magnetic field direction of the fixed layer, so that the magnetic tunnel junction 20 assumes a high-resistance state "1", thereby realizing the storage of data "1".
  • the magnetic tunnel junction 20 presents a low resistance state of "0", thereby realizing the storage of data "0".
  • the write current in MRAM is usually more than ten times the read current. If a single-channel transistor is used, the current flowing through the transistor during the write phase is larger. As the frequency of use increases, It will greatly accelerate the loss rate of single-channel transistors and reduce the service life of single-channel transistors. Therefore, in the embodiment of the present application, by arranging the dual-channel vertical transistor 10, the current passing through each sub-transistor can be reduced, thereby reducing the loss rate of the transistor 10 and extending the service life of the transistor 10.
  • FIG. 7 A schematic flow chart of the method is shown in Figure 7. The method includes the following steps S701-S705:
  • a stacked structure of multiple source lines and multiple arrays is formed on one side of the substrate;
  • the stacked structure includes a stacked source electrode, a sacrificial semiconductor structure and a drain electrode, and the sacrificial semiconductor structure
  • a first semiconductor layer and a second semiconductor layer are provided on both outer side walls respectively, and the sources of any two stacked structures adjacent in the row direction are connected to the same source line.
  • S703 Form a word line and a gate electrode located at least partially between the first semiconductor layer and the second semiconductor layer to obtain an array of transistors; the gate electrodes of each transistor located in the same row are connected to the same word line.
  • S704 Form a connection structure and a magnetic tunnel junction in sequence on the side of the source of the transistor away from the substrate.
  • multiple source lines and multiple array-arranged stacked structures are formed on one side of the substrate based on a patterning process, including: forming multiple source lines and multiple arrays on the substrate.
  • the stacked structure rows 112 include stacked source rows 1011, sacrificial Semiconductor row 1121 and drain row 1031; using an epitaxial process to form semiconductor rows 113 on both outer walls of the sacrificial semiconductor row 1121; in a direction parallel to the substrate and perpendicular to the source line, that is, perpendicular to the stacked structure row 112 direction, the stacked structure rows 112 and the semiconductor rows 113 are patterned to form the stacked structures 116 and the first semiconductor layer 121 and the second semiconductor layer 122 arranged in an array.
  • forming multiple source lines and multiple mutually spaced stacked structure rows on the substrate in the above steps includes: sequentially forming a first conductor layer, a sacrificial layer, and a sacrificial sacrificial layer on one side of the substrate based on an epitaxial process.
  • the initial stacked structure row includes a stacked source row, an initial sacrificial semiconductor row and a drain row; forming a source line conforming to the first arc-shaped groove in the first arc-shaped groove; etching back the initial sacrificial electrode
  • Semiconductor rows form sacrificial semiconductor rows, resulting in stacked structure rows.
  • the first conductor layer 101, the sacrificial semiconductor layer 102 and the second conductor layer 103 are sequentially formed on one side of the substrate 100 based on an epitaxial growth process, and the first light conductor layer 103 is formed on the side of the second conductor layer 103 away from the substrate 100.
  • the resist structure 104 forms a first mask structure 105 on both side walls of the first photoresist structure 104, as shown in FIG. 8 .
  • the first conductor layer 101 and the second conductor layer 103 are made of doped semiconductor materials.
  • the first conductor layer 101 and the second conductor layer 103 are both N-type doped, and the doping level can be It is determined according to the specific manufacturing process or requirements;
  • the sacrificial semiconductor layer 102 is GeSi (silicon germanium);
  • the preparation material of the first mask structure 105 can be silicon oxide.
  • the first conductor layer 101, the sacrificial semiconductor layer 102 and the second conductor layer 103 are formed using an epitaxial growth process, thereby facilitating precise control of the thickness of each film layer, especially the precise control of the sacrificial semiconductor layer 102
  • the thickness facilitates precise control of the dimensions of the subsequently manufactured semiconductor layer 12 and gate 13, thereby ensuring the manufacturing accuracy of the transistor, thereby ensuring the uniformity of transistor performance of each memory unit in the memory, and thereby ensuring the performance of the memory.
  • deposition processes such as CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), and ALD (Atomic Layer Deposition) can be used to manufacture each film. layer structure.
  • CVD Chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • ALD Atomic Layer Deposition
  • the first photoresist structure 104 After removing the first photoresist structure 104, the second conductor layer 103, the sacrificial semiconductor layer 102, the first conductor layer 101 and part of the substrate 100 are etched using the first mask structure 105 as a mask to form a plurality of third An initial row 106 of stacked structures with arcuate grooves 108 spaced apart from each other, as shown in FIGS. 9 and 10 .
  • the first mask structure 105 is a hard mask, which can play a role in etching the second conductor layer 103, the sacrificial semiconductor layer 102, and part of the first conductor layer 101. Align the etching function to ensure the accuracy of etching.
  • trenches for isolating the initial stacked structure rows 106 may be formed first, and then the first arc-shaped grooves 108 are formed based on the trenches.
  • a protective layer covering the top and side walls of the initial stacked structure row 106 is formed based on the structure described in FIG. 9 .
  • the protective layer can protect the initial stacked structure rows 106 and prevent the initial stacked structure rows 106 from being etched or doped.
  • the protective layer has a whole-layer structure and also covers the unetched first conductor layer 101 between two adjacent initial stacked structure rows 106 .
  • the protective layer is made of silicon oxide. Etch part of the substrate 100 and part of the source row 1011 between two adjacent stacked structure rows 106 to form a first arc-shaped groove 108 that partially extends below the two stacked structure rows 106, as shown in Figure 10 .
  • the initial stacked structure row 106 extends along a second direction.
  • the second direction is parallel to the substrate 100 and perpendicular to the first direction.
  • the first direction is the extension direction of the source line 203 .
  • a plurality of initial stacked structures The rows 106 are spaced apart along the first direction.
  • the initial stacked structure row 106 includes a stacked source row 1011 , an initial sacrificial semiconductor row 1021 and a drain row 1031 .
  • there is a portion of the first conductor layer 101 that has not been etched between two adjacent initial stacked structure rows 106 to prevent over-etching during the subsequent formation of the source lines 203 .
  • a protective structure 1071 is formed.
  • forming a source line 203 conforming to the first arc-shaped groove 108 in the first arc-shaped groove 108 includes: filling metal material between the first arc-shaped groove 108 and two adjacent initial stacked structure rows 106 , such as titanium, cobalt and other metal materials, to form a metal layer 109. As shown in FIG. 11, the metal layer 109 completely fills the first arc-shaped groove 108, and the upper surface of the metal layer 109 is in contact with the initial sacrificial semiconductor of the initial stacked structure row 106.
  • the upper surface of the row 1021 is flush; an annealing process is used to process the metal layer 109 so that the metal layer 109 reacts with part of the substrate 100 and part of the source row 1011 to form a source line 203 including metal silicide, and then the unreacted metal is removed Layer 109, as shown in Figure 12.
  • the source line 203 conforms to the surface of the first arc-shaped groove 108 .
  • One source line 203 is connected to the source rows 1011 of two adjacent initial stacked structure rows 106 .
  • a deposition process is used to deposit a dielectric material, such as silicon oxide, and a CMP (Chemical Mechanical Polishing) process is used to form a first flat layer 111, as shown in Figure 13.
  • a CMP Chemical Mechanical Polishing
  • the protective structure 1071 and the first flat layer 111 are made of the same material, so the first flat layer 111 is used to represent both of them in FIG. 13 , and the protective structure 1071 is not shown in FIG. 13 .
  • part of the first flat layer 111 and the first mask structure 105 is removed through an etching process to form a first flat structure 1111.
  • the upper surface of the first flat structure 1111 is flush with the upper surface of the source row 1021, so that the initial sacrifice Both sidewalls of the semiconductor row 1021 are exposed, as shown in FIG. 14 .
  • etching back the initial sacrificial semiconductor row 1021 to form the sacrificial semiconductor row 1121 to obtain the stacked structure row 112 includes: using a selective etching process to laterally etch the initial sacrificial semiconductor row 1021 to form the sacrificial semiconductor row 1121, so that the sacrificial semiconductor row 1121 is formed. Both side walls of 1121 are indented relative to the source row 1011 and the drain row 1031, resulting in a stacked structure row 112. As shown in Figure 15, the stacked structure row 112 includes a stacked source row 1011 and a sacrificial semiconductor row. 1121 and drain row 1031.
  • an epitaxial process is used to form the semiconductor rows 113 on both outer walls of the sacrificial semiconductor row 1121, which specifically includes the following steps:
  • an epitaxial process is used to form a semiconductor layer on the exposed surfaces of the source row 1011, the sacrificial semiconductor row 1121, and the drain row 1031.
  • the epitaxial process can be continued to be used to form the exposed outer surfaces of the source row 1011, the sacrificial semiconductor row 1121 and the drain row 1031. semiconductor layer.
  • patterning the stacked structure rows 112 and the semiconductor rows 113 in the above steps to form an array-arranged stacked structure 116 specifically includes the following steps: Patterning the stacked structure rows on the side away from the substrate A mask structure is formed; the extension direction of the mask structure is perpendicular to the extension direction of the stacked structure rows; based on the mask structure, a self-aligned etching process is used to etch the stacked structure rows and semiconductor rows to form a stacked structure and a semiconductor layer .
  • a mask structure is formed on the side of the second flat layer 114 away from the substrate 100.
  • the mask structure includes first sub-mask structures 1151 arranged at intervals. As shown in FIG. 18, an extension of the first sub-mask structure 1151 is The direction is perpendicular to the extension direction of the stacked structure row 112 .
  • Figures 7 to 17 are schematic cross-sectional structural views along the first direction, and the second direction is perpendicular to the first direction.
  • Figure 18 is the AA-direction cross-section after the mask structure is prepared from the structure shown in Figure 17 Structural diagram, used in Figure 18 Indicates that the first direction is the inward direction perpendicular to the paper surface.
  • a self-aligned etching process is used to etch the stacked structure rows 112 and the semiconductor rows 113 to form the stacked structures 116 and the semiconductor layer 12.
  • the stacked structures 116 are arranged in an array, and The unetched second flat layer 114 is removed, as shown in FIG. 19 .
  • the first sub-mask structure 1151 is a hard mask made of silicon oxide, which can play a role in self-aligned etching during the etching of the stacked structure row 112 and the semiconductor row 113. , thereby ensuring the accuracy of etching.
  • the stacked structure 116 includes a source electrode 11 and a drain electrode 14.
  • the sacrificial semiconductor row 1121 is etched to form a sacrificial semiconductor structure.
  • the semiconductor row 113 is etched to form the semiconductor layer 12.
  • the sacrificial semiconductor structure is due to the Shielded and not visible, the source 11 is connected to the bit line 202 .
  • Figure 19 is a schematic cross-sectional structural diagram along the second direction. In Figure 19, Indicates that the first direction is the inward direction perpendicular to the paper surface.
  • removing the sacrificial semiconductor structure in the above step S702 specifically includes: using a selective etching process to remove the sacrificial semiconductor structure.
  • forming a word line and a gate at least partially located between the first semiconductor layer and the second semiconductor layer in the semiconductor layer in step S703 above to obtain transistors arranged in an array specifically includes the following steps:
  • a deposition process is used to form a first gate insulating layer 151 conforming to the source electrode 11, the inner walls of the two semiconductor layers 12, and the peripheral wall of the cavity formed by the drain electrode 14, and to form a first gate insulating layer 151 conforming to the source electrode 11 and the two semiconductor layers 12.
  • the second gate insulating layer 152 is formed along the outer walls of the groove formed by the semiconductor layer 12 and the drain electrode 14 to form the gate insulating layer 15, so that the gate electrode 13, the source electrode 11, and the drain electrode 14 can be subsequently prepared.
  • the pole 14 and the semiconductor layer 12 are insulated from each other.
  • a metal material is deposited using an atomic layer deposition process, so that the metal material fills the cavity formed by the first gate insulating layer 151 and fills the groove formed by the second gate insulating layer 152 to form an initial word line. layer.
  • Figure 20 is a schematic cross-sectional structural diagram along the first direction.
  • ⁇ is used to indicate that the second direction is the direction perpendicular to the outward direction of the paper.
  • the SOH (Spin On Hard mask) process can be used to form a self-leveling flat layer on one side of the initial word line layer, and then form a self-leveling flat layer on one side of the flat layer.
  • a photoresist structure is formed on the side, and the initial word line layer is etched using the photoresist structure as a mask.
  • the first gate 131 is disposed in a cavity surrounded by the first gate insulating layer 151 , so that the first gate 131 is insulated from the semiconductor layer 12 , the source electrode 11 and the drain electrode 14 .
  • the second gate electrode 132 is disposed in the groove formed by the second gate insulating layer 152 so that the second gate electrode 132 is insulated from the semiconductor layer 12 , the source electrode 11 and the drain electrode 14 .
  • the two semiconductor layers 12 are laterally indented relative to the outer contours of the source electrode 11 and the drain electrode 14. Since the source electrode 11 and the drain electrode 14 are prepared based on the epitaxial growth process, the two semiconductor layers 12 are formed vertically to the substrate. In the direction of the bottom 100, the distance between the source electrode 11 and the drain electrode 14 can be accurately controlled.
  • the gate insulating layer 15 is formed through the ALD process, and the thickness of the gate insulating layer 15 can also be accurately controlled, so that the third The size of the cavity formed by the gate insulating layer 151 and the groove formed by the second gate insulating layer 152 can be precisely controlled, so that the formation of the first gate 131 and the second gate can be precisely controlled.
  • the size of the electrode 132 can be accurately controlled, thereby improving the preparation accuracy of the gate 13, ensuring the preparation accuracy of the memory unit, and thus ensuring the accuracy of each memory unit in the memory. Performance uniformity, thereby ensuring memory performance.
  • connection structure and a magnetic tunnel junction are sequentially formed on the side of the source of the transistor away from the substrate, which specifically includes the following steps:
  • a dielectric material such as silicon oxide
  • a dielectric structure 50 including an opening is formed. The opening exposes part of the drain electrode 14 .
  • a metal material such as titanium, cobalt and other metal materials, is deposited in the opening, and an annealing process is used to form a silicide structure 41; the thickness of the silicide structure 41 is smaller than the depth of the opening.
  • a metal material is deposited on the side of the silicide structure 41 away from the substrate 100 to cover the silicide structure 41 and fill the opening to form a metal structure 42 flush with the upper surface of the dielectric structure 50 to obtain a connection structure 40, as shown in FIG. 21 Show.
  • an initial magnetic tunnel junction layer, a hard mask layer and a second photoresist structure are sequentially formed on the side of the dielectric structure 50 and the metal structure 42 away from the substrate 100 .
  • the hard mask layer is patterned using the second photoresist structure as a mask to form the hard mask structure 30, and the initial magnetic tunnel junction layer is patterned using the hard mask structure 30 as a mask to form the magnetic tunnel junction 20.
  • the hard mask structure 30 can play a role in protecting the magnetic tunnel junction 20.
  • an encapsulation layer 60 is deposited on the side of the hard mask structure 30 away from the substrate 100 , and the encapsulation layer 60 covers the sidewalls of the magnetic tunnel junction 20 , as shown in FIG. 22 .
  • forming a bit line on the side of the magnetic tunnel junction away from the substrate in the above step S405 specifically includes the following steps:
  • an isolation layer 70 including an opening is formed on a side of the encapsulation layer 60 away from the substrate 100 , and the opening of the isolation layer 70 exposes part of the hard mask structure 30 .
  • a metal material is deposited in the opening of the isolation layer 70 to form the bit line 202 .
  • one end of a source line 203 is electrically connected to the source 11 of each transistor 10 in one column of memory cells 200, and the other end of the source line 203 is electrically connected to each transistor in another column of memory cells 200.
  • the source 11 of 10 is electrically connected, so that two columns of memory cells 200 can be controlled simultaneously through one source line 203, thereby reducing the number of source lines 203 in the memory, reducing the difficulty of wiring wiring in the memory, and reducing the memory cost. Design costs and manufacturing costs.
  • steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can be alternated, changed, combined, or deleted.
  • steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can also be alternated, changed, rearranged, decomposed, combined, or deleted.
  • steps, measures, and solutions in the prior art with various operations, methods, and processes disclosed in this application can also be replaced, changed, rearranged, decomposed, combined, or deleted.

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Abstract

本申请实施例提供了一种存储器及其制造方法、读写控制方法。在本申请实施例提供的存储器中，通过设置一条源线电连接沿行方向任意相邻的两个存储单元中晶体管，从而通过一条源线能够同时控制两列存储单元，从而能够减小存储器中源线的数量，能够降低存储器中走线的排布难度，能够降低存储器的设计成本和制造成本。

Description

存储器及其制造方法、读写控制方法 技术领域
本申请涉及半导体技术领域，具体而言，本申请涉及一种存储器及其制造方法、读写控制方法。
背景技术
随着半导体器件集成化技术的发展，存储器的种类越来越多，MRAM(Magnetoresistive Random Access Memory，磁性随机存储器)作为一种非易失性存储器是行业的重要的研究方向之一。
目前，MRAM中每个存储单元需设置位线、字线以及源线，导致MRAM中的布线较多，导致MRAM的设计成本和制造成本的增加。
发明内容
本申请提出一种存储器及其制造方法、读写控制方法，至少用以改善背景技术中的不足。
本申请一些实施例提供了一种存储器，包括：多行多列存储单元、多行字线、多列位线和多列源线；
存储单元包括：晶体管和磁性隧道结；晶体管包括第一沟道和第二沟道；
磁性隧道结的一端与晶体管的漏极电连接，另一端与位线电连接；同一行的各存储单元中晶体管的栅极与字线电连接；一列存储单元中各晶体管的源极同时与两条源线电连接，两条源线中，一条源线与同一列存储单元中各晶体管的第一沟道电连接，另一源线与同一列存储单元中各晶体管的第二沟道电连接；任意两列相邻的存储单元中，一条源线的一端与一列存储单元中各晶体管的源极电连接，该条源线的另一端与另一列存储单元 中各晶体管的源极电连接。
本申请一些实施例提供了一种存储器的读写控制方法，包括：
在读取阶段，通过字线控制待读取存储单元中晶体管处于导通状态，通过位线或一条源线中的一个向待读取存储单元的磁性隧道结传输读取信号，以使得位线或一条源线中的另一个感测磁性隧道结的存储数据；
在写入阶段，通过字线控制待写入存储单元中晶体管处于导通状态，通过位线和两条源线控制存储信号流经待写入存储单元中磁性隧道结的方向，以将位线或源线传输的存储信号写入磁性隧道结。
本申请一些实施例提供了一种存储器的制造方法，包括：
基于图案化工艺在衬底的一侧形成多条源线和多个阵列排布的叠置结构；叠置结构包括叠层设置的源极、牺牲半导体结构和漏极，牺牲半导体结构的两外侧壁分别设置有第一半导体层和第二半导体层，沿行方向任意相邻的两个叠置结构的源极与同一条源线连接；
去除牺牲半导体结构；
形成字线和至少部分位于第一半导体层和第二半导体层之间的栅极，得到阵列排布的晶体管；位于同一行的各晶体管的栅极与同一条字线连接；
在晶体管的源极远离衬底的一侧依次形成连接结构和磁性隧道结；
在磁性隧道结远离衬底的一侧形成位线。
本申请实施例提供的技术方案带来的有益技术效果包括：
在本申请实施例所提供的存储器中，通过设置一条源线的一端与一列存储单元中各晶体管的源极电连接，源线的另一端与另一列存储单元中各晶体管的源极电连接，从而通过一条源线能够同时控制两列存储单元，从而能够减小存储器中源线的数量，能够降低存储器中走线的排布难度，能够降低存储器的设计成本和制造成本。
本申请附加的方面和优点将在下面的描述中部分给出，这些将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为本申请一些实施例提供的一种存储器的电路原理示意图；
图2为本申请一些实施例提供的一种存储器的结构示意图；
图3为本申请一些实施例提供的图1所示存储器的AA向剖视结构示意图；
图4为本申请一些实施例提供的另一种存储器的结构示意图；
图5为本申请一些实施例提供的又一种存储器的结构示意图；
图6为图5所示存储器中垂直晶体管的BB向剖面结构示意图；
图7为本申请一些实施例提供的一种存储器的制造方法的流程示意图；
图8为本申请一些实施例提供存储器的制造方法中得到第一光刻胶结构和第一掩膜结构后的结构示意图；
图9为本申请一些实施例提供存储器的制造方法中得到初始叠置结构行后的结构示意图；
图10为本申请一些实施例提供存储器的制造方法中得到第一弧形槽后的结构示意图；
图11为本申请一些实施例提供存储器的制造方法中得到金属层后的结构示意图；
图12为本申请一些实施例提供存储器的制造方法中得到位线后的结构示意图；
图13为本申请一些实施例提供存储器的制造方法中得到第一平坦层后的结构示意图；
图14为本申请一些实施例提供存储器的制造方法中得到第一平坦结构后的结构示意图；
图15为本申请一些实施例提供存储器的制造方法中得到叠置结构行后的结构示意图；
图16为本申请一些实施例提供存储器的制造方法中得到半导体行后的结构示意图；
图17为本申请一些实施例提供存储器的制造方法中得到第二平坦层 后的结构示意图；
图18为本申请一些实施例提供存储器的制造方法中在图16所示结构制作得到掩膜结构后的CC向剖面结构示意图；
图19为本申请一些实施例提供存储器的制造方法中基于图17所示结构制作得到半导体层后的结构示意图；
图20为本申请一些实施例提供存储器的制造方法中形成字线后的结构示意图；
图21为本申请一些实施例提供存储器的制造方法中形成连接结构后的结构示意图；
图22为本申请一些实施例提供存储器的制造方法中形成封装层后的结构示意图。
附图标记说明：
100-衬底；
200-存储单元；201-字线；2011-第一子段；2012-第二子段；202-位线；203-源线；2031-源线203的第一部分；2032-源线203的第二部分；
10-晶体管；
11-源极；12-半导体层；121-第一半导体层；122-第二半导体层；13-栅极；131-第一栅极；132-第二栅极；14-漏极；15-栅极绝缘层；151-第一栅极绝缘层；152-第二栅极绝缘层；
20-磁性隧道结；30-硬掩膜结构；40-连接结构；41-硅化物结构；42-金属结构；50-介质结构；60-封装层；70-隔离层；
101-第一导体层；102-牺牲半导体层；103-第二导体层；104-第一光刻胶结构；105-第一掩膜结构；
106-初始叠置结构行；1011-源极行；1021-初始牺牲半导体行；1031-漏极行；1071-保护结构；
108-第一弧形槽；109-金属层；111-第一平坦层；1111-第一平坦结构；
112-叠置结构行；1121-牺牲半导体行；113-半导体行；114-第二平坦层；1151-第一子掩膜结构；116-叠置结构。
具体实施方式
下面结合本申请中的附图描述本申请的实施例。应理解，下面结合附图所阐述的实施方式，是用于解释本申请实施例的技术方案的示例性描述，对本申请实施例的技术方案不构成限制。
本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。应该进一步理解的是，本申请的说明书中使用的措辞“包括”是指存在所述特征、整数、步骤、操作、元件和/或组件，但不排除实现为本技术领域所支持其他特征、信息、数据、步骤、操作、元件、组件和/或它们的组合等。
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
本申请实施例涉及的存储器可以为MRAM，MRAM是一种非易失性的磁性随机存储器，MRAM中存储的数据以一种磁性状态存储，而不是电荷，磁场极性不像电荷那样会随着时间而泄漏，因此即使在断电的情况下，也能保持信息。
目前，MRAM往往包括多个呈阵列排布的存储单元，每个存储单元需设置位线、字线和位线，存储单元往往呈阵列排布，这导致MRAM中的布线较多，导致MRAM的设计成本和制造成本的增加。
而且，MRAM存储单元中垂直晶体管的半导体结构、栅极的制造精度较低，从而导致存储器中VGAA晶体管的性能存在差异，影响存储器的性能。
而且，垂直晶体管面临驱动电流进一步提升的瓶颈。比如，随着垂直晶体管尺寸的减小，垂直晶体管的开态电流减小，进而晶体管的驱动性能降低、开启速度较慢，进而影响存储器的性能。
本申请提供的存储器及其制造方法、读写控制方法，旨在解决现有技术的如上技术问题。
下面以具体地实施例对本申请的技术方案进行详细说明。
本申请实施例提供了一种存储器，该存储器的电路原理示意图如图1所示，存储器包括：多行多列存储单元200、多行字线201、多列位线202 和多列源线203；存储单元200包括：晶体管10和磁性隧道结20；晶体管10包括第一沟道和第二沟道。
磁性隧道结20的一端与晶体管10的漏极14电连接，另一端与位线202电连接；沿行方向任意相邻的两个存储单元200中晶体管10的源极11与同一条源线203电连接，同一行的各存储单元200中晶体管10的栅极13与字线201电连接。
磁性隧道结20的一端与晶体管10的漏极14电连接，另一端与位线202电连接；同一行的各存储单元200中晶体管10的栅极13与字线201电连接；一列存储单元200中各晶体管10的源极11同时与两条源线203电连接，两条源线203中，一条源线203与同一列存储单元200中各晶体管10的第一沟道电连接，另一源线203与同一列存储单元200中各晶体管10的第二沟道电连接；任意两列相邻的存储单元200中，一条源线203的一端与一列存储单元200中各晶体管10的源极11电连接，该条源线203的另一端与另一列存储单元200中各晶体管10的源极11电连接。
在本申请实施例所提供的存储器中，通过设置一条源线203的一端与一列存储单元200中各晶体管10的源极11电连接，源线203的另一端与另一列存储单元200中各晶体管10的源极11电连接，从而通过一条源线203能够同时控制两列存储单元200，从而能够减小存储器中源线203的数量，能够降低存储器中走线的排布难度，能够降低存储器的设计成本和制造成本。
本申请实施例中，多个存储单元200呈阵列排布，也即各个存储单元200的晶体管10呈阵列排布。本文中定义，平行于字线201延伸的方向为行，平行于源线203延伸的方向为列。如图1所示，沿自左向右的方向为行，沿自上而下的方向为列，图1中示例性的示出了同一行的两个存储单元的晶体管10，也即分别示出了两列存储单元200中每一列存储单元的一个存储单元200。
应该说明的是，本申请实施例中，源线203的一端和另一端并不是指一条源线203的两个自由端，而是指源线203的某一部分，可选地，可以 指的是源线203沿径向方向的部分，如图2所示。
本申请实施例中，如图1所示，每个存储单元200均包括一个晶体管10和一个磁性隧道结20，晶体管10和磁性隧道结20电连接。可选地，磁性隧道结20的一端与晶体管10的漏极14电连接。
如图1所示，沿行方向任意相邻的两个存储单元200中晶体管10的源极11与同一条源线203电连接，从而使得任意相邻两行的存储单元200配置三条源线203即可，相较于相关技术的存储器，能够大大减小存储器中源线203的数量，从而能够降低存储器中走线的排布难度，能够降低存储器的设计成本和制造成本。
本申请实施例中，如图1所示，磁性隧道结20的另一端与位线202电连接，同一行的各存储单元200中晶体管10的栅极13与字线201电连接。当通过字线201控制晶体管10开启后，通过与两列存储单元200电连接的同一条源线203，就可以控制两列存储单元200的数据读取，从而能够提高存储器的数据读取速度。通过三条源线203就可以控制两列存储单元200的数据写入。
可选地，本申请实施例中，磁性隧道结20包括MTJ(Magnetic Tunnel Junctions，磁性隧道结)，MRAM通过检测MTJ电阻的高低来判断所存储的数据是“0”还是“1”
具体的，MTJ包括依次叠置的自由层、隧穿层和固定层。自由层的磁场方向是可以改变的，而固定层的磁场方向是固定不变的，在电场作用下电子会通过隧穿层势垒而垂直穿过器件，当自由层的磁场方向与固定层的磁场方向相同时，MTJ呈现低阻态“0”，当自由层的磁场方向与固定层的磁场方向相反时，MTJ呈现高阻态“1”。
本申请实施例中，通过设置晶体管10包括第一沟道和第二沟道，相较于单沟道晶体管而言，能够显著提高晶体管10的开态电流，能够提升晶体管10的驱动能力和开启速度，进而能够提升存储器的性能。
在本申请的一个实施例中，晶体管10为垂直晶体管10，晶体管10和磁性隧道结20沿垂直衬底100的方向叠层设置。
本申请实施例中，如图2所示，为本申请实施例提供的一种存储器的结构示意图，如图2所示，存储单元200设置于源线203远离衬底100的一侧，存储器中每个存储单元200的晶体管10和磁性隧道结20沿垂直衬底100的方向叠层设置，沿行方向(即图2中的第一方向)任意相邻的两个存储单元200中晶体管10的源极11与同一条源线203电连接。
应该说明的是，图2为储存器的局部剖视结构示意图，因此，沿第一方向两侧的源线203均只是示意出了部分，这两条源线203未示出的部分可以参见位于中间的源线203。
在本申请的一个实施例中，晶体管10包括在衬底100上依次叠层设置的源极11、半导体层12和漏极14；半导体层12包括第一半导体层121和第二半导体层122，第一半导体层121和第二半导体层122间隔设置于源极11的同一侧分别与源极11接触；第一半导体层121包括第一沟道，第二半导体层122包括第二沟道；至少部分栅极13位于第一半导体层121和第二半导体层之间122的间隔区域。
本申请实施例中，如图2所示，沿垂直于衬底100的方向，源极11、半导体层12和漏极14依次叠层设置。栅极13也位于源极11和漏极14之间，即栅极13与半导体层12同层设置。
如图2所示，第一半导体层121和第二半导体层122间隔设置于源极11的同一侧分别与源极11接触。可选地，第一半导体层121在导通的情况下包括第一沟道，第二半导体层122在导通的情况下包括第二沟道。
在本申请的一个实施例中，如图2所示，第一半导体层121和第二半导体层122沿行方向间隔设置；源线203的横截面为顶部具有豁口的弧形状，同一条源线203中，靠近豁口的一端为源线203的第一部分2031，靠近豁口的另一端为源线203的第二部分2032；第一部分2031与一列存储单元200中至少部分存储单元200中的第一半导体层121连接，第二部分2032与另一列存储单元200中至少部分存储单元200中的第二半导体层122连接。
本申请实施例，如图2所示，晶体管10中第一半导体层121和第二 半导体层122沿行方向间隔设置，即沿平行于衬底100的第一方向间隔设置。
可选地，如图2和4所示，源线203的横截面为顶部具有豁口的弧形状，且同一条源线203中，靠近豁口的一端为第一部分2031，靠近豁口的另一端为第二部分2032；第一部分2031与一列存储单元200中至少部分存储单元200中的第一半导体层121连接，第二部分2032与另一列存储单元200中至少部分存储单元200中的第二半导体层122连接。
可选地，本申请实施例中，源极11采用轻掺杂的半导体材料，使得源极11的导电率小于源线203的导电率。结合图1和图2所示，晶体管10中半导体层12包括间隔设置的第一半导体层121和第二半导体层122，在导通状态下，第一半导体层121包括第一沟道，第二半导体层122包括第二沟道，相当于每个晶体管10包括两个并联连接的子晶体管，从而在增大晶体管10的开态电流的同时，能够降低通过每个子晶体管的电流，从而能够降低晶体管10的损耗速度，能够延长晶体管10的使用寿命。
同时，能够避免在物理上隔绝子晶体管的源极11，能够简化晶体管的制备工艺，降低晶体管的制造成本。
可选地，如图4所示，在本申请的一个实施例中，第一部分2031在衬底100的正投影与第一半导体层121在衬底100上的投影有交叠，与第二半导体层122在衬底100上的投影无交叠；第二部分2032在衬底100的正投影与第二半导体层122在衬底100上的投影有交叠，与第一半导体层121在衬底100上的投影无交叠。
本申请实施例中，通过设置源线203的第一部分2031在衬底100的正投影只与第一半导体层121在衬底100上的投影有交叠，能够避免第一部分2031与第二半导体层122电连接；通过设置第二部分2032在衬底100的正投影只与第二半导体层122在衬底100上的投影有交叠，能够避免第二部分2032与第一半导体层121电连接，从而使得通过第一部分2031和第二部分2032能够单独控制晶体管10，使得每个晶体管10实际上包括两个并联连接的子晶体管。从而在通过一条源线203的第一部分2031 和另一条源线203的第二部分2032同时控制一个晶体管10的情况下，能够成倍增大施加于垂直晶体管10的电场，进而能够提高数据读取和写入的速度。
同时，本申请实施例中，通过设置每条源线203包括第一部分2031的第二部分2032，对于同一条源线203而言，第一部分2031能够控制一列存储单元200中各晶体管10，第二部分2032能够控制另一列存储单元200中各晶体管10，从而通过一条源线203能够同时控制两列存储单元200，从而能够减小存储器中源线203的数量，能够降低存储器中走线的排布难度，能够降低存储器的设计成本和制造成本。
可选地，如图5所示，源线203的第一部分2031在衬底100的正投影只与第一半导体层121在衬底100上的投影有交叠，第二部分2032在衬底100的正投影只与第二半导体层122在衬底100上的投影有交叠，区别在于源极11的厚度存在不同。本领域技术人员可以根据源极11制造材料的不同选择设置对应厚度的源极11，使得第一部分2031能够控制第一半导体层121、第二部分2032能够控制第二半导体层122。
应该说明的是，如图4和图5所示，为了便于读者直观了解源线203的第一部分2031和第二部分2032，图4和图5中用分割线划分了第一部分2031和第二部分2032边界，实际产品中，源线203的第一部分2031和第二部分2032为同时制造得到的，第一部分2031和第二部分2032之间并不存在图4和图5所示的分割线。
可选地，如图4和图5所示，在本申请的一个实施例中，第一部分2031与源极11的下表面且靠近第一半导体层121的区域接触，第二部分2032与源极11的下表面且靠近第二半导体层122的区域接触，第一部分1031和第二部分2032在源极11的投影内的投影无交叠。
本申请实施例中，如图4和图5所示，一条源线203的部分第一部分2031位于一源极11远离第一半导体层121的一侧，同一条源线203的部分第二部分2032位于另一源极11远离第二半导体层122的一侧。且一条源线203的第一部分1031在源极11的投影，与相邻的另一条源线203的 第二部分2032在同一源极11上的投影无交叠，从而使得通过第一部分2031和第二部分2032能够单独控制晶体管10。
可选地，如图4和图5所示，在本申请的一个实施例中，存储器包括设置于源极11下方的衬底100，任意相邻两列存储单元200中晶体管10的源极11之间的衬底100处开设有沟槽；沟槽的底部和两个侧壁的材料均为金属硅化物；沟槽的两个侧壁，分别凹于相邻的两列的源极11下方；位于源极11下方的、相邻两个沟槽的相邻两个侧壁，分别属于第一部分2031和第二部分2032；衬底100中位于相邻两个侧壁之间的部分的材料为硅。
本申请实施例中，如图4和图5所示，源极11远离半导体层的一侧为存储器的衬底100，可选地，衬底100为硅衬底。
如图4和图5所示，任意相邻两列源极11之间的衬底100处开设有沟槽，沟槽的开口朝向字线201，可选地，硅衬底从沟槽的内周表面开始一定径向厚度内的材料为金属硅化物，沟槽包括底部和与底部连接两个侧壁，可选地，如图4和图5所示，沟槽的底部和侧壁联合形成的沟槽的截面形状为弧形。
如图4和图5所示，沟槽的两个侧壁分别凹于相邻的两列的源极11下方，使得部分侧壁位于源极11的下方，位于源极11下方的、相邻两个沟槽的相邻两个侧壁，分别属于第一部分2031和第二部分2032，也即第一部分2031和第二部分2032的材料均为金属硅化物。
可选地，如图4和图5所示，衬底100中位于第一部分2031和第二部分2032之间部分为硅，从而能够避免相邻的第一部分2031和第二部分2032电连接。
可选地，本申请实施例中，在存储器的制造过程中，沟槽的底部和两个侧壁的金属硅化物为通过金属硅化物工艺同时形成。
可选地，在本申请的一个实施例中，源极11是基于硅掺杂得到的，且源极11的导电率小于第一部分2031和第二部分2032的导电率。
本申请实施例中，源极11采用轻度掺杂的半导体材料制成，源极11 沿垂直于衬底100方向的尺寸可以适当减小，使得部分第一部分2031和部分第二部分2032能够起到源极11的作用，以保障垂直晶体管10的性能。
本申请实施例中，如图4和图5所示，位于垂直晶体管10下方的部分第一部分2031和部分第二部分2032均与源极11直接连接并靠近第一半导体层121或第二半导体层122，源极11的导电率小于第一部分2031和第二部分2032的导电率，从而在垂直晶体管10处于导通状态下，第一半导体层121和第二半导体层122的电流会直接流向最近的第一位线201或第二位线202，能够降低流经第一半导体层121和第二半导体层122的电流相互影响，此时，每个垂直晶体管10相当于两个并联的子晶体管。从而能够避免在物理上隔绝子晶体管的源极，能够简化薄膜晶体管的制备工艺，降低薄膜晶体管的制造成本。
在本申请的一个实施例中，源极11在衬底100的投影覆盖部分源线203在衬底的投影；在源线203的径向平面内，源线203的截面形状为弧形，弧形源线203的一侧与一列存储单元200的各晶体管10的源极11连接，另一侧与另一列存储单元的各晶体管10的源极11连接。
本申请实施例中，如图2所示，源线203位于衬底100和晶体管10之间，晶体管10的源极11在衬底100的投影覆盖部分源线203在衬底100的投影，即源极11覆盖部分源线203。
本申请实施例中，如图2所示，在源线203的径向平面内，源线203的截面形状为弧形，弧形源线203的一侧与一列存储单元200的各晶体管10的源极11连接，另一侧与另一列存储单元200的各晶体管10的源极11连接，从而通过一条源线203能够连接两列的存储单元200。
本领域技术人员了解的是，相较于截面形状均为直线段的源线而言，采用截面形状为弧形的源线203，能够避免源线203出现直角的部分，从而能够避免尖端效应，能够保障存储器的性能。
在本申请的一个实施例中，栅极13包括相互连接的第一栅极13和第二栅极13；第一栅极131为位于第一半导体层121和第二半导体层122 的间隔区域之间的栅极；第二栅极132设置于第一半导体层121和第二半导体层122的外侧壁，且与第一半导体层121、第二半导体层122、源极11和漏极14相绝缘。
在本申请的一个实施例中，栅极13包括第一栅极13和第二栅极13；第一栅极13设置于两个第一半导体层121和第二半导体层122之间，且与第一半导体层121、第二半导体层122、源极11和漏极14相绝缘；第二栅极13设置于半导体层12的外侧壁，且与半导体层12、源极11和漏极14相绝缘。
本申请实施例中，如图2所示，晶体管10还包括栅极绝缘层15，可选地，本申请实施例中，栅极绝缘层15采用高k值介质材料制成。
可选地，如图2所示，栅极绝缘层15包括一个第一栅极绝缘层151和两个第二栅极绝缘层152。第一栅极绝缘层151与源极11、第一半导体层121和第二半导体层122的内侧壁以及漏极14围合形成的腔室的周壁随形；第二栅极绝缘层152与源极11、第一半导体层121和第二半导体层122的外侧壁以及漏极14围合形成的凹槽的周壁随形。
本申请实施例中，如图2所示，栅极13的第一栅极131位于两个间隔设置的半导体层12之间，可选地，第一栅极131设置于第一栅极绝缘层151围合形成的腔室内，以使得第一栅极131与半导体层12、源极11和漏极14相绝缘。
如图2所示，栅极13的第二栅极132位于半导体层12的外侧壁，可选地，第二栅极132设置于第二栅极绝缘层152围合形成的凹槽内，以使得第二栅极132与半导体层12、源极11和漏极14相绝缘。
在本申请的一个实施例中，第一栅极13和第二栅极13均与字线201连接。
本申请实施例中，如图2所示，字线201沿平行于衬底100的第一方向延伸，如图3所示，源线203沿平行于衬底100的第二方向延伸，第一方向垂直于第二方向。可选地，位线202的延伸方向平行于源线203的延伸方向。
本申请实施例中，结合图3和图4可知，栅极13的第一栅极131和第二栅极132，均与字线201连接，从而通过字线201能够向第一栅极131和第二栅极132同时施加电平，能够进一步增强栅极13的电场强度，从而能够有助于提高晶体管10的开态电流，进而有助于提升晶体管10的驱动能力和开启速度，有助于提升存储单元200的读写速度，有助于提升存储器的性能。
在本申请的一个实施例中，字线201包括多个依次交替连接的第一子段2011和第二子段2012；第一子段2011环绕第一栅极13和第二栅极13，与第一栅极13和第二栅极13均连接；第二子段2012的一端与一个第一子段2011连接，另一端与另一个第一子段2011连接。
本申请实施例中，如图2和图3所示，沿第一方向，也即字线201的延伸方向，第一子段2011和第二子段2012依次交替连接。
本申请实施例中，结合图2和图3可知，第一子段2011环绕第一栅极131和第二栅极132设置，即第一子段2011包裹了第一栅极131的两个端面和第二栅极132的两个端面，从而与第一栅极131和第二栅极132均连接。
可选地，如图3所示，第一子段2011的上表面与第一栅极131的上表面平齐，从而能够避免第一子段2011与晶体管10的漏极14接触。
本申请实施例中，如图2所示，第二子段2012位于相邻两个晶体管10之间，用于连接环绕第一栅极131和第二栅极132的第一子段2011。第二子段2012的上表面与第一子段2011的上表面平齐，能够降低第二子段2012与晶体管10漏极14接触的几率，能够降低两者之间产生寄生电容的几率，进而能够保障存储器的性能。
应该说明的是，为了便于清楚示意出字线201中第一子段2011和第二子段2012的结构，图2、图3和图4中用虚线表示出了第一子段2011与第二子段2012之间的界面分界线、第一子段2011与第一栅极131之间的界面分界线，实际产品中，第一子段2011、第二子段2012和栅极13是采用同种材料制作形成的，并不存在如图2、图3和图4中所展示的虚 线。
在本申请的一个实施例中，源极11和漏极14的外轮廓在衬底上的投影、围设第一半导体层121、第二半导体层122和第一栅极131的外轮廓在衬底上的投影，使得源极11、漏极14相对于第一半导体层121、第二半导体层122和第一栅极131向外凸出。
可选地，如图2所示，晶体管10中，源极11的漏极14的外轮廓在衬底100上的正投影，围设第一半导体层121、第二半导体层122和第一栅极131的外轮廓在衬底100上的正投影。如图1所示，源极11、半导体层12、第一栅极131和漏极14组合形成的剖面图形为工字形。
在本申请的一个实施例中，源极11和漏极14的外轮廓在衬底上的投影，与第二栅极13的外轮廓在衬底上的投影相重叠。
可选地，如图2所示，极11和漏极14的外轮廓在衬底100上的正投影，与第二栅极132的外轮廓在衬底100上的正投影相重叠，使得源极11、漏极14的外侧壁与第二栅极132的外侧壁相平齐。
应该说明的是，本申请实施例中，所提及的外和内，均是相对于存储器的中心而言，相对靠近存储器的中心为内，相对远离存储器的中心为外。
可选地，如图5和图6所示，在本申请的一个实施例中，栅极13包括相互连接的第一栅极131和第二栅极132；栅极13整体呈柱状，栅极131的上表面的不同区域具有分别延伸到下表面的两个相互独立的开口；两个开口中分别填充有第一半导体层121和第二半导体层122，第一半导体层121和第二半导体层122与所在的开口中的栅极13之间通过栅极绝缘层15相绝缘。
本申请实施例中，结合图5和图6所示，栅极13的第一栅极131和第二栅极132构成的整体结构。
如图6所示，栅极13中开设有两个相互独立的开口，栅极13中位于两个开口之间的结构为第一栅极131，位于开口外侧的结构为第二栅极132。两个开口中一个填充有第一半导体层121，另一个填充有第二半导体层122。
本申请实施例中，如图5和图6所示，两个开口内均填充有栅极绝缘层15，栅极绝缘层15包括第一栅极绝缘层151和第二栅极绝缘层152，第一栅极绝缘层151位于开口靠近第一栅极131的侧壁，第二栅极绝缘层152位于开口靠近第二栅极132的侧壁。第一半导体层121和第二半导体层122位于对应开口内，并通过第一栅极绝缘层151和第二栅极绝缘层152与栅极13相绝缘。
在本申请的一个实施例中，存储单元200还包括：连接结构40，设置于漏极14远离源极11的一侧；磁性隧道结20设置于连接结构远离漏极14的一侧。
可选地，如图2所示，沿垂直于衬底100的方向，晶体管10和连接结构40叠层设置，连接结构40设置于晶体管10的漏极14远离源极11的一侧。
本申请实施例中，连接结构40用于实现晶体管10与磁性隧道结20的电连接。从而便于晶体管10和磁性隧道结20的分别制作，例如，先采用一条产线在衬底100的一侧依次形成源线203、晶体管10、字线201以及连接结构40后，再采用另一条产线形成磁性隧道结20，从而能够提高存储器的生产效率。
可选地，如图3所示，连接结构40包括硅化物结构41和金属结构42。由于漏极14多采用掺杂的半导体材料制成，其与金属结构42的导电率存在明显的差异，通过设置硅化物结构41，能够降低金属结构42与漏极14之间的界面电阻，从而能够保障存储单元200的性能。
本申请实施例中，如图2-图3所示，存储器还包括介质结构50，介质结构50可以与栅极绝缘层15采用同种介质材料制成。可选的，如图2所示，连接结构40设置于介质结构50的开口内。
可选地，如图2所示，磁性隧道结20远离衬底100的一侧设置有硬掩膜结构30，在形成磁性隧道结20的过程中，硬掩膜结构30可以起到保护磁性隧道结20的作用。可选地，硬掩膜结构30包括金属和介质材料，因此，硬掩膜结构30具有一定的导电性，硬掩膜结构30与位线202连接， 从而实现位线202与磁性隧道结20的电连接。
应该说明的是，硬掩膜结构30的硬度是相对于光刻胶的硬度而言的，硬掩膜结构30的材料包括氧化硅、氮化硅等。
本申请实施例中，如图2所示，硬掩膜结构30远离衬底100的一侧设置有的封装层60，封装层60覆盖磁性隧道结20的侧壁，以避免外界水、氧等侵蚀磁性隧道结20。
可选地，封装层60的材料包括氮化硅、氧化铝、氧化镁等致密材料。
基于同一发明构思，本申请实施例提供了一种电子设备，包括：如上述各个实施例所提供的任一种存储器。
本申请实施例中，由于电子设备采用了前述各实施例提供的任一种存储器，其原理和技术效果请参阅前述各实施例，在此不再赘述。
可选地，电子设备包括智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
应该说明的是，电子设备并不局限于上述几种，本领域技术人员可以根据实际的应用需求，在不同的设备中设置本申请上述各个实施例所提供的任一种存储器，从而得到本申请实施例所提供的电子设备。
基于同一发明构思，本申请实施例提供了一种存储器的读写控制方法，包括：
在读取阶段，通过字线201控制待读取存储单元200中晶体管10处于导通状态，通过位线202或一条源线203中的一个向待读取存储单元200的磁性隧道结20传输读取信号，以使得位线202或一条源线203中的另一个感测磁性隧道结20的存储数据。
在写入阶段，通过字线201控制待写入存储单元200中晶体管10处于导通状态，通过位线202和两条源线203控制存储信号流经待写入存储单元200中磁性隧道结20的方向，以将位线202或源线203传输的存储信号写入磁性隧道结20。
本申请实施例提供了的存储器的读写控制方法，用于上述各个实施例所提供的任一存储器。
可选地，在存储器的读取阶段，通过字线201向待读取存储单元200中晶体管10的栅极13输入第一电平，使得该晶体管10处于导通状态，通过一条位线202或一条源线203感测电流或电压的变化以及变化程度，实现磁性隧道结20存储数据的读取。下面以通过源线203感测电流变化为例，来说明是如何实现磁性隧道结20存储数据读取的。
具体的，当磁性隧道结20存储的数据是“1”时，此时MTJ呈现高阻态，当通过一条位线202向磁性隧道结20传输读取信号，也即通过位线202向磁性隧道结20施加第二电平，一条源线203保持在参考电平，参考电平小于第二电平，由于MTJ呈现高阻态，电流难以通过磁性隧道结20，即源线203难以测得较为明显的电流，此种情况判断读取的数据为“1”，也即通过一条源线203即可感测待读取存储单元200的磁性隧道结205存储的数据为“1”。
当磁性隧道结20存储的数据是“0”时，此时MTJ呈现低阻态，当通过一条位线202向磁性隧道结20传输读取信号，也即通过位线202向磁性隧道结20施加第二电平，一条源线203保持在参考电平，参考电平小于第二电平，由于MTJ呈现低阻态，电流能够通过磁性隧道结20，即源线203可以测得较为明显的电流，此种情况判断读取的数据为“0”，也即通过一条源线203即可感测待读取存储单元200的磁性隧道结20存储的数据为“0”。
本领域技术人员理解的是，通过控制位线202和源线203之间的电位差，能够控制电流的流向，进而实现待读取存储单元200中磁性隧道结20存储数据的读取。
可选地，在存储器的写入阶段，通过字线201向待读取存储单元200中晶体管10的栅极13输入第一电平，使得该晶体管10处于导通状态，通过位线202和两条源线203控制存储信号流经待写入存储单元200中磁性隧道结20的方向，以将位线202或源线203传输的存储信号写入磁性隧道结20。下面以通过源线203向待写入存储单元200传输存储信号为例，来说明是如何实现磁性隧道结20数据存储的。
具体的，当存储信号为“1”时，通过源线203向待写入存储单元200的晶体管10的源极11施加第三电平，位线202保持在参考电平，第三电平大于参考电平，由于两条源线203均施加第三电平，使得磁性隧道结20两端的电位差足够大，包含存储信号的电流从源线203流向位线202，且在电流流经磁性隧道结20的过程中，磁性隧道结20的自由层的磁场方向会改变并与固定层的磁场方向相反，使得磁性隧道结20呈现高阻态“1”，从而实现数据“1”的存储。
反之，通过控制磁性隧道结20的自由层的磁场方向改变并与固定层的磁场方向相同，使得磁性隧道结20呈现低阻态“0”，从而实现数据“0”的存储。
本领域技术人员了解的是，MRAM中写入电流通常是读取电流的十几倍，如果采用单沟道晶体管，在写入阶段，流经晶体管的电流较大，随着使用频率的增多，会大大加快单沟道晶体管的损耗速度，降低单沟道晶体管的使用寿命。因此，本申请实施例中，通过设置双沟道垂直晶体管10，能够降低通过每个子晶体管的电流，从而能够降低晶体管10的损耗速度，能够延长晶体管10的使用寿命。
基于同一发明构思，本申请实施例提供了一种存储器的制造方法，该方法的流程示意图如图7所示，该方法包括如下步骤S701-S705：
S701，基于图案化工艺在衬底的一侧形成多条源线和多个阵列排布的叠置结构；叠置结构包括叠层设置的源极、牺牲半导体结构和漏极，牺牲半导体结构的两外侧壁分别设置有第一半导体层和第二半导体层，沿行方向任意相邻的两个叠置结构的源极与同一条源线连接。
S702，去除牺牲半导体结构。
S703，形成字线和至少部分位于第一半导体层和第二半导体层之间的栅极，得到阵列排布的晶体管；位于同一行的各晶体管的栅极与同一条字线连接。
S704，在晶体管的源极远离衬底的一侧依次形成连接结构和磁性隧道结。
S705，在磁性隧道结远离衬底的一侧形成位线。
为了便于读者直观了解本申请实施例所提供的存储器的制造方法以及采用该方法制备得到的存储器的优点，下面将结合图8-图22进行具体说明。
在本申请的一个实施例中，上述步骤S701中基于图案化工艺在衬底的一侧形成多条源线和多个阵列排布的叠置结构，包括：在衬底形成多条源线和多个相互间隔设置的叠置结构行；叠置结构行包括叠层设置的源极行、牺牲半导体行和漏极行；通过外延工艺在牺牲半导体行的两侧壁形成半导体行；沿平行于衬底且垂直于源线的方向，图案化叠置结构行和半导体行，分别形成多个叠置结构以及第一半导体层和第二半导体层。
可选地，基于图案化工艺在衬底100的一侧依次形成多源线203和多个相互间隔设置的叠置结构行112，叠置结构行112包括叠层设置的源极行1011、牺牲半导体行1121和漏极行1031；采用外延工艺在牺牲半导体行1121的两外侧壁形成半导体行113；沿平行于衬底且垂直于源线的方向，也即沿垂直于叠置结构行112走向的方向，图案化叠置结构行112和半导体行113，形成阵列排布的叠置结构116以及第一半导体层121和第二半导体层122。
在本申请的一个实施例中，上述步骤中在衬底形成多条源线和多个相互间隔设置的叠置结构行，包括：基于外延工艺在衬底一侧依次形成第一导体层、牺牲半导体层和第二导体层；图案化第一导体层、牺牲半导体层、第二导体层和部分衬底，形成多个第一弧形槽和多个被第一弧形槽间隔的初始叠置结构行；初始叠置结构行包括叠层设置的源极行、初始牺牲半导体行和漏极行；在第一弧形槽内形成与第一弧形槽随形的源线；回刻初始牺牲半导体行形成牺牲半导体行，得到叠置结构行。可选地，具体包括以下步骤：
首先，基于外延生长工艺在衬底100的一侧依次形成第一导体层101、牺牲半导体层102和第二导体层103，并在第二导体层103远离衬底100的一侧形成第一光刻胶结构104，在第一光刻胶结构104的两侧壁形成第 一掩膜结构105，如图8所示。
可选地，第一导体层101和第二导体层103为掺杂的半导体材料制成，可选地，第一导体层101和第二导体层103均为N型掺杂，掺杂程度可以根据具体的制造工艺或需求来确定；牺牲半导体层102为GeSi(硅锗)；第一掩膜结构105的制备材料可以是氧化硅。
可选地，本申请实施例中，第一导体层101、牺牲半导体层102和第二导体层103采用外延生长工艺形成，从而便于精准控制各个膜层的厚度，特别是精准控制牺牲半导体层102厚度，便于精准控制后续制造得到的半导体层12和栅极13的尺寸，从而能够保障晶体管的制造精度，进而能够保障存储器中各个存储单元的晶体管性能的均一性，进而能够保障存储器的性能。
可选地，本申请实施例中，可以采用CVD(Chemical Vapor Deposition，化学气相沉积)、PVD(Physical Vapor Deposition，物理气相沉积)以及ALD(Atomic Layer Deposition，原子层沉积)等沉积工艺制造各个膜层结构。
然后，去除第一光刻胶结构104后，以第一掩膜结构105为掩膜刻蚀第二导体层103、牺牲半导体层102、第一导体层101以及部分衬底100，形成多个第一弧形槽108相互间隔设置的初始叠置结构行106，如图9和10所示。
可选地，本申请实施例中，第一掩膜结构105为硬掩膜，在刻蚀第二导体层103、牺牲半导体层102、以及部分第一导体层101的过程中，能够起到自对准刻蚀的作用，从而保障刻蚀的精度。
可选地，本申请实施例中，如图9和图10所示，可以先形成用于隔离初始叠置结构行106的沟槽，然后基于沟槽形成第一弧形槽108。可选地，基于图9所述的结构形成覆盖初始叠置结构行106的顶壁和侧壁的保护层。在后续制造过程中，保护层能够起到保护初始叠置结构行106的作用，防止初始叠置结构行106被刻蚀或被掺杂。保护层为整层结构，还覆盖相邻两个初始叠置结构行106之间未被刻蚀的第一导体层101。可选地， 保护层的制备材料包括氧化硅。刻蚀相邻两个叠置结构行106之间的部分衬底100和部分源极行1011，形成部分延伸至两个叠置结构行106下方的第一弧形槽108，如图10所示。
如图9所示，初始叠置结构行106沿第二方向延伸，第二方向平行于衬底100且垂直于第一方向，第一方向为源线203的延伸方向，多个初始叠置结构行106沿第一方向间隔设置。如图9所示，初始叠置结构行106包括叠层设置的源极行1011、初始牺牲半导体行1021和漏极行1031。如图9所示，相邻两个初始叠置结构行106之间存在部分未被刻蚀的第一导体层101，防止后续形成源线203的过程中，出现过度刻蚀的情况。
本申请实施例中，如图10所示，保护层经过刻蚀后，形成保护结构1071。
接着，在第一弧形槽108内形成与第一弧形槽108随形的源线203，包括：在第一弧形槽108以及相邻两个初始叠置结构行106之间填充金属材料，例如钛、钴等金属材料，形成金属层109，如图11所示，金属层109完全填充第一弧形槽108，且金属层109的上表面与初始叠置结构行106的初始牺牲半导体行1021的上表面平齐；采用退火工艺处理金属层109，使得金属层109与部分衬底100和部分源极行1011发生反应，形成包括金属硅化物的源线203，然后去除未反应的金属层109，如图12所示。如图12所示，源线203与第一弧形槽108的表面随形。一条源线203与两个相邻的初始叠置结构行106的源极行1011均连接。
然后，采用沉积工艺沉积介质材料，如氧化硅，并采用CMP(Chemical Mechanical Polishing，化学机械抛光)工艺处理，形成第一平坦层111，如图13所示。可选地，保护结构1071和第一平坦层111的制造材料相同，因此图13中用第一平坦层111来表示两者，图13中没有表示出保护结构1071。
接着，通过刻蚀工艺去除部分第一平坦层111和第一掩膜结构105，形成第一平坦结构1111，第一平坦结构1111的上表面与源极行1021的上表面平齐，使得初始牺牲半导体行1021的两个侧壁暴露，如图14所示。
然后，回刻初始牺牲半导体行1021形成牺牲半导体行1121，得到叠置结构行112，包括：采用选择性刻蚀工艺侧向刻蚀初始牺牲半导体行1021，形成牺牲半导体行1121，使得牺牲半导体行1121的两侧壁均相对于源极行1011和漏极行1031缩进，得到叠置结构行112，如图15所示，叠置结构行112包括叠层设置源极行1011、牺牲半导体行1121和漏极行1031。
在本申请的一个实施例中，上述步骤中采用外延工艺在牺牲半导体行1121的两外侧壁形成半导体行113，具体包括以下步骤：
首先，采用外延工艺在源极行1011、牺牲半导体行1121和漏极行1031的露出面形成半导体层。
由于源极行1011、牺牲半导体行1121和漏极行1031均是基于外延工艺形成，因此可以继续采用外延工艺形成与源极行1011、牺牲半导体行1121和漏极行1031露出的外表面随形的半导体层。
然后，采用刻蚀工艺去除部分半导体层，形成位于牺牲半导体行1121两外侧壁的半导体行113，如图16所示。
在本申请的一个实施例中，上述步骤中图案化叠置结构行112和半导体行113，形成阵列排布的叠置结构116，具体包括以下步骤：在叠置结构行远离衬底的一侧形成掩膜结构；掩膜结构的延伸方向垂直于叠置结构行的延伸方向；基于掩膜结构，采用自对准刻蚀工艺刻蚀叠置结构行和半导体行，形成叠置结构和半导体层。
可选地，首先，采用沉积工艺沉积如氧化硅的介质材料，并采用CMO工艺处理，形成第二平坦层114，如图17所示。接着，在第二平坦层114远离衬底100的一侧形成掩膜结构，掩膜结构包括间隔设置的第一子掩膜结构1151，如图18所示，第一子掩膜结构1151的延伸方向垂直于叠置结构行112的延伸方向。
本申请实施例中，图7-图17为沿第一方向的剖视结构示意图，第二方向垂直于第一方向，图18为在图17所示结构制备得到掩膜结构后的AA向剖面结构示意图，图18中用
Figure PCTCN2022137312-appb-000001
表示第一方向为垂直纸面向内的方向。
然后，基于第一子掩膜结构1151，采用自对准刻蚀工艺刻蚀叠置结构行112和半导体行113，形成叠置结构116和半导体层12，叠置结构116呈阵列排布，并去除未被刻蚀的第二平坦层114，如图19所示。
本申请实施例中，第一子掩膜结构1151为硬掩膜，制作材料包括氧化硅，在刻蚀叠置结构行112和半导体行113的过程中，能够起到自对准刻蚀的作用，从而保障刻蚀的精度。
如图19所示，叠置结构116包括源极11、漏极14，牺牲半导体行1121刻蚀后形成牺牲半导体结构，半导体行113刻蚀后形成半导体层12，牺牲半导体结构由于半导体层12的遮挡而不可见，源极11与位线202连接。图19为沿第二方向的剖视结构示意图，图19中用
Figure PCTCN2022137312-appb-000002
表示第一方向为垂直纸面向内的方向。
在本申请的一个实施例中，上述步骤S702中去除牺牲半导体结构，具体包括：采用选择性刻蚀工艺去除牺牲半导体结构。
在本申请的一个实施例中，上述步骤S703中形成字线和至少部分位于半导体层中第一半导体层和第二半导体层之间的栅极，得到阵列排布的晶体管，具体包括以下步骤：
首先，采用沉积工艺形成与源极11、两个半导体层12的内侧壁以及漏极14围合形成的腔室的周壁随形的第一栅极绝缘层151，以及形成与源极11、两个半导体层12的外侧壁以及漏极14围合形成的凹槽的周壁随形的第二栅极绝缘层152，得到栅极绝缘层15，以使得后续制备栅极13与源极11、漏极14以及半导体层12相绝缘。
然后，采用原子层沉积工艺沉积金属材料，使得金属材料填充第一栅极绝缘层151围合形成的腔室内，填充于第二栅极绝缘层152围合形成的凹槽内，形成初始字线层。
接着，图案化初始字线层，形成字线201、第一栅极131和第二栅极132，如图20所示。图20为沿第一方向的剖视结构示意图，图20中用⊙表示第二方向为垂直纸面向外的方向。
可选地，图案化初始字线层，可以采用SOH(Spin On Hard mask，旋 涂于硬掩膜)工艺，在初始字线层的一侧形成自流平的平坦层，然后在平坦层的一侧之形成光刻胶结构，以光刻胶结构为掩膜刻蚀初始字线层。
本申请实施例中，第一栅极131设置于第一栅极绝缘层151围合形成的腔室内，以使得第一栅极131与半导体层12、源极11和漏极14相绝缘。第二栅极132设置于第二栅极绝缘层152围合形成的凹槽内，以使得第二栅极132与半导体层12、源极11和漏极14相绝缘。
本申请实施例中，两个半导体层12均相对于源极11和漏极14的外轮廓侧向缩进，由于源极11和漏极14是基于外延生长工艺制备得到的，沿垂直于衬底100的方向，源极11和漏极14之间的距离是能够精准控制的，栅极绝缘层15是通过ALD工艺形成的，栅极绝缘层15的厚度也是能够精准控制的，从而使得第一栅极绝缘层151围合形成的腔室的尺寸，以及第二栅极绝缘层152围合形成的凹槽的尺寸能够精准控制，从而能够精准控制形成的第一栅极131和第二栅极132的尺寸，特别是能够精准控制第一栅极131和第二栅极132的长度，从而能够提高栅极13的制备精度，能够保障存储单元的制备精度，进而能够保障存储器中各个存储单元性能的均一性，进而能够保障存储器的性能。
在本申请的一个实施例中，上述步骤S704中在晶体管的源极远离衬底的一侧依次形成连接结构和磁性隧道结，具体包括以下步骤：
首先，采用沉积工艺沉积介质材料，如氧化硅，磨平处理并图案化后形成包括开口的介质结构50，开口使得部分漏极14露出。
然后，在开口内沉积金属材料，例如钛、钴等金属材料，并采用退火工艺处理形成硅化物结构41；硅化物结构41的厚度小于开口的深度。
接着，在硅化物结构41远离衬底100的一侧积金属材料，覆盖硅化物结构41并填充开口，形成与介质结构50上表面齐平的金属结构42，得到连接结构40，如图21所示。
然后，在介质结构50和金属结构42远离衬底100的一侧依次形成初始磁性隧道结层、硬掩膜层和第二光刻胶结构。
接着，以第二光刻胶结构为掩膜图案化硬掩膜层，形成硬掩膜结构 30，继续以硬掩膜结构30为掩膜图案化初始磁性隧道结层，形成磁性隧道结20。在形成磁性隧道结20的过程中，硬掩膜结构30可以起到保护磁性隧道结20的作用。
然后，在硬掩膜结构30远离衬底100的一侧沉积形成封装层60，封装层60覆盖磁性隧道结20的侧壁，如图22所示。
在本申请的一个实施例中，上述步骤S405中在磁性隧道结远离衬底的一侧形成位线，具体包括以下步骤：
首先，在封装层60远离衬底100的一侧形成包括开口的隔离层70，隔离层70的开口使得部分硬掩膜结构30露出。
接着，在隔离层70的开口内沉积金属材料，形成位线202。
应用本申请实施例，至少能够实现如下有益效果：
在本申请实施例所提供的存储器中，通过设置一条源线203的一端与一列存储单元200中各晶体管10的源极11电连接，源线203的另一端与另一列存储单元200中各晶体管10的源极11电连接，从而通过一条源线203能够同时控制两列存储单元200，从而能够减小存储器中源线203的数量，能够降低存储器中走线的排布难度，能够降低存储器的设计成本和制造成本。
本技术领域技术人员可以理解，本申请中已经讨论过的各种操作、方法、流程中的步骤、措施、方案可以被交替、更改、组合或删除。进一步地，具有本申请中已经讨论过的各种操作、方法、流程中的其他步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。进一步地，现有技术中的具有与本申请中公开的各种操作、方法、流程中的步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。
以上所述仅是本申请的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请的方案技术构思的前提下，采用基于本申请技术思想的其他类似实施手段，同样属于本申请实施例的保护范畴。

Claims (17)

  1. 一种存储器，其特征在于，包括：多行多列存储单元、多行字线、多列位线和多列源线；
    所述存储单元包括：晶体管和磁性隧道结；所述晶体管包括第一沟道和第二沟道；
    所述磁性隧道结的一端与所述晶体管的漏极电连接，另一端与所述位线电连接；同一行的各所述存储单元中所述晶体管的栅极与所述字线电连接；一列所述存储单元中各所述晶体管的源极同时与两条所述源线电连接，两条所述源线中，一条所述源线与同一列所述存储单元中各所述晶体管的所述第一沟道电连接，另一所述源线与同一列所述存储单元中各所述晶体管的所述第二沟道电连接；任意两列相邻的所述存储单元中，一条所述源线的一端与一列所述存储单元中各所述晶体管的所述源极电连接，该条所述源线的另一端与另一列所述存储单元中各所述晶体管的所述源极电连接。
  2. 根据权利要求1所述的存储器，其特征在于，所述晶体管为垂直晶体管，所述晶体管和所述磁性隧道结沿垂直衬底的方向叠层设置。
  3. 根据权利要求2所述的存储器，其特征在于，所述晶体管包括在衬底上依次叠层设置的源极、半导体层和漏极；
    所述半导体层包括第一半导体层和第二半导体层，所述第一半导体层和所述第二半导体层间隔设置于所述源极的同一侧分别与所述源极接触；所述第一半导体层包括第一沟道，所述第二半导体层包括第二沟道；
    至少部分所述栅极位于所述第一半导体层和所述第二半导体层之间的间隔区域。
  4. 根据权利要求3所述的存储器，其特征在于，所述第一半导体层 和第二半导体层沿行方向间隔设置；
    所述源线的横截面为顶部具有豁口的弧形状，同一条所述源线中，靠近所述豁口的一端为第一部分，靠近所述豁口的另一端为第二部分；所述第一部分与一列所述存储单元中至少部分所述存储单元中的所述第一半导体层连接，所述第二部分与另一列所述存储单元中至少部分所述存储单元中的所述第二半导体层连接。
  5. 根据权利要求4所述的存储器，其特征在于，所述第一部分在所述衬底的正投影与所述第一半导体层在所述衬底上的投影有交叠，与所述第二半导体层在所述衬底上的投影无交叠；
    所述第二部分在所述衬底的正投影与所述第二半导体层在所述衬底上的投影有交叠，与所述第一半导体层在所述衬底上的投影无交叠。
  6. 根据权利要求5所述的存储器，其特征在于，所述第一部分与所述源极的下表面且靠近所述第一半导体层的区域接触，所述第二部分与所述源极的下表面且靠近所述第二半导体层的区域接触，所述第一部分和所述第二部分在所述源极的投影内的投影无交叠。
  7. 根据权利要求4所述的存储器，其特征在于，所述存储器包括设置于所述源极下方的衬底，任意相邻两列所述存储单元中所述晶体管的所述源极之间的所述衬底处开设有沟槽；所述沟槽的底部和两个侧壁的材料均为金属硅化物；
    所述沟槽的两个侧壁，分别凹于相邻的两列的所述源极下方；位于所述源极下方的、相邻两个所述沟槽的相邻两个所述侧壁，分别属于所述第一部分和第二部分；所述衬底中位于所述相邻两个所述侧壁之间的部分的材料为硅。
  8. 根据权利要求4所述的存储器，其特征在于，所述源极是基于硅 掺杂得到的，且所述源极的导电率小于所述第一部分和所述第二部分的导电率。
  9. 根据权利要求3所述的存储器，其特征在于，所述栅极包括相互连接的第一栅极和第二栅极；
    所述第一栅极为位于所述第一半导体层和所述第二半导体层之间的间隔区域的部分所述栅极；
    所述第二栅极设置于所述第一半导体层和所述第二半导体层的外侧壁，且与所述第一半导体层、所述第二半导体层、所述源极和所述漏极相绝缘。
  10. 根据权利要求9所述的存储器，其特征在于，所述字线包括多个依次交替连接的第一子段和第二子段；
    所述第一子段环绕所述第一栅极和所述第二栅极，与所述第一栅极和所述第二栅极均连接；
    所述第二子段的一端与一个所述第一子段连接，另一端与另一个所述第一子段连接。
  11. 根据权利要求9所述的存储器，其特征在于，还包括：
    所述源极和所述漏极的外轮廓在所述衬底上的投影、围设所述第一半导体层、所述第二半导体层和所述第一栅极的外轮廓在所述衬底上的投影，使得所述源极、所述漏极相对于所述第一半导体层、所述第二半导体层和所述第一栅极向外凸出；
    所述源极和所述漏极的外轮廓在所述衬底上的投影，与所述第二栅极的外轮廓在所述衬底上的投影相重叠。
  12. 根据权利要求3所述的存储器，其特征在于，所述栅极包括相互连接的第一栅极和第二栅极；
    所述栅极整体呈柱状，所述栅极的上表面的不同区域具有分别延伸到下表面的两个相互独立的开口；两个所述开口中分别填充有所述第一半导体层和所述第二半导体层，所述第一半导体层和所述第二半导体层与所在的开口中的所述栅极之间通过栅极绝缘层相绝缘。
  13. 根据权利要求1所述的存储器，其特征在于，所述存储单元还包括：连接结构，设置于所述漏极远离所述源极的一侧；
    所述磁性隧道结设置于所述连接结构远离所述漏极的一侧。
  14. 一种存储器的读写控制方法，其特征在于，包括：
    在读取阶段，通过字线控制待读取存储单元中晶体管处于导通状态，通过位线或一条源线中的一个向所述待读取存储单元的磁性隧道结传输读取信号，以使得位线或一条源线中的另一个感测所述磁性隧道结的存储数据；
    在写入阶段，通过字线控制待写入存储单元中晶体管处于导通状态，通过位线和两条源线控制存储信号流经待写入存储单元中磁性隧道结的方向，以将所述位线或所述源线传输的所述存储信号写入所述磁性隧道结。
  15. 一种存储器的制造方法，其特征在于，包括：
    基于图案化工艺在衬底的一侧形成多条源线和多个阵列排布的叠置结构；所述叠置结构包括叠层设置的源极、牺牲半导体结构和漏极，所述牺牲半导体结构的两外侧壁分别设置有第一半导体层和第二半导体层，沿行方向任意相邻的两个所述叠置结构的源极与同一条所述源线连接；
    去除所述牺牲半导体结构；
    形成字线和至少部分位于所述第一半导体层和所述第二半导体层之间的栅极，得到阵列排布的晶体管；位于同一行的各所述晶体管的所述栅极与同一条所述字线连接；
    在所述晶体管的源极远离所述衬底的一侧依次形成连接结构和磁性 隧道结；
    在所述磁性隧道结远离所述衬底的一侧形成位线。
  16. 根据权利要求15所述的存储器的制造方法，其特征在于，所述基于图案化工艺在衬底的一侧形成多条源线和多个阵列排布的叠置结构，包括：
    在所述衬底形成多条所述源线和多个相互间隔设置的叠置结构行；所述叠置结构行包括叠层设置的源极行、牺牲半导体行和漏极行；
    通过外延工艺在所述牺牲半导体行的两侧壁形成半导体行；
    沿平行于所述衬底且垂直于所述源线的方向，图案化所述叠置结构行和所述半导体行，分别形成多个所述叠置结构以及所述第一半导体层和所述第二半导体层。
  17. 根据权利要求16所述的存储器的制造方法，其特征在于，所述在所述衬底形成多条所述源线和多个相互间隔设置的叠置结构行，包括：
    基于外延工艺在所述衬底一侧依次形成第一导体层、牺牲半导体层和第二导体层；
    图案化所述第一导体层、所述牺牲半导体层、所述第二导体层和部分所述衬底，形成多个第一弧形槽和多个被所述第一弧形槽间隔的初始叠置结构行；所述初始叠置结构行包括叠层设置的源极行、初始牺牲半导体行和漏极行；
    在所述第一弧形槽内形成与所述第一弧形槽随形的所述源线；
    回刻所述初始牺牲半导体行形成所述牺牲半导体行，得到所述叠置结构行。
PCT/CN2022/137312 2022-08-18 2022-12-07 存储器及其制造方法、读写控制方法 WO2024036827A1 (zh)

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