WO2023231306A1 - 场效应管、存储单元及存储单元的制造方法 - Google Patents

场效应管、存储单元及存储单元的制造方法 Download PDF

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WO2023231306A1
WO2023231306A1 PCT/CN2022/131539 CN2022131539W WO2023231306A1 WO 2023231306 A1 WO2023231306 A1 WO 2023231306A1 CN 2022131539 W CN2022131539 W CN 2022131539W WO 2023231306 A1 WO2023231306 A1 WO 2023231306A1
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Prior art keywords
substrate
field effect
effect transistor
source electrode
electrode
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PCT/CN2022/131539
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English (en)
French (fr)
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尹晓明
赵超
韩宝东
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北京超弦存储器研究院
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Publication of WO2023231306A1 publication Critical patent/WO2023231306A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of semiconductor technology. Specifically, the present application relates to a field effect transistor, a memory unit, and a manufacturing method of a memory unit.
  • this application proposes a field effect transistor, a memory unit and a manufacturing method of the memory unit to solve the problem of field effect in the memory during the preparation process of a memory with a vertical structure of field effect transistors in the prior art
  • the technical problem of low preparation accuracy of the channel structure of the tube is a problem of low preparation accuracy of the channel structure of the tube.
  • a field effect transistor including:
  • Source located on the substrate
  • the drain electrode is located above the source electrode and stacked with the source electrode;
  • the gate electrode and the channel structure at least part of the gate electrode is located between the source electrode and the drain electrode, and the gate electrode is located on one side of the first side wall of the channel structure and is insulated from the channel structure; the channel structure extends from the source electrode to The direction of the drain electrode extends and is connected to the source electrode and the drain electrode respectively. Sides of the source electrode and the drain electrode away from the gate electrode protrude relative to the second sidewall of the channel structure away from the gate electrode.
  • embodiments of the present application provide a memory unit, including: a word line, a bit line, and a field effect transistor provided in the first aspect;
  • the bit line is set on the substrate; the field effect transistor is set above the bit line, and the source of the field effect transistor is connected to the bit line, and the orthographic projection of the source and bit line on the substrate has an overlapping area; the word line is located on the field effect One side of the tube is connected to the gate of the field effect tube, and the extension direction of the word line and the bit line has an included angle.
  • embodiments of the present application provide a method of manufacturing a memory unit, including:
  • a plurality of mutually spaced first structural columns are formed on one side of the substrate based on a patterning process.
  • the first structural columns include a plurality of mutually insulated repeating units; the repeating units include a stacked first source, a sacrificial layer and first drain;
  • the semiconductor layer includes a channel structure located between the first source electrode and the first drain electrode;
  • first source electrode Patterning the first source electrode, the first sacrificial structure and the first drain electrode so that one first source electrode forms two spaced apart source electrodes, one first sacrificial structure forms two spaced apart sacrificial structures and one first drain electrode
  • the pole forms two drain electrodes arranged at intervals;
  • the channel structure is located between the source and drain arranged in a stack, and the side of the source and drain away from the gate is opposite to the side of the channel structure away from the gate.
  • the second sidewall protrudes, so that the size of the channel structure manufactured by the epitaxial process matches the distance from the source to the drain, thereby controlling the size of the channel structure and improving the manufacturing accuracy of the channel structure. It can ensure the uniformity of performance of each field effect transistor in the memory, thereby ensuring the performance of the memory.
  • Figure 1 is a schematic structural diagram of a field effect transistor provided by an embodiment of the present application.
  • Figure 2 is a cross-sectional view of a storage unit along the first direction and the third direction according to the embodiment of the present application;
  • Figure 3 is a cross-sectional view of a storage unit along the second direction and the third direction according to the embodiment of the present application;
  • Figure 4 is a schematic flow chart of a method of manufacturing a memory unit provided by an embodiment of the present application.
  • Figure 5 is a schematic flow chart of another memory manufacturing method provided by an embodiment of the present application.
  • Figure 6 is a schematic structural diagram of the first intermediate substrate prepared in the memory preparation method provided by the embodiment of the present application.
  • Figure 7 is a schematic structural diagram after the first mask structure is prepared in the memory preparation method provided by the embodiment of the present application.
  • Figure 8 is a schematic structural diagram after the initial fourth trench and the first structure row are prepared in the memory preparation method provided by the embodiment of the present application;
  • Figure 9 is a schematic structural diagram of the second protective layer prepared in the memory preparation method provided by the embodiment of the present application.
  • Figure 10 is a schematic structural diagram after etching the second protective layer in the memory preparation method provided by the embodiment of the present application.
  • Figure 11 is a schematic structural diagram of the fourth trench after being prepared in the memory manufacturing method provided by the embodiment of the present application.
  • Figure 12 is a schematic structural diagram after the initial metal layer is prepared in the memory preparation method provided by the embodiment of the present application.
  • Figure 13 is a schematic structural diagram of the metal layer prepared in the memory preparation method provided by the embodiment of the present application.
  • Figure 14 is a schematic structural diagram after the bit line structure is prepared in the memory manufacturing method provided by the embodiment of the present application.
  • Figure 15 is a schematic structural diagram after bit lines are prepared in the memory preparation method provided by the embodiment of the present application.
  • Figure 16 is a schematic structural diagram of the second intermediate substrate prepared in the memory preparation method provided by the embodiment of the present application.
  • Figure 17 is a schematic structural diagram after the first sub-mask structure is prepared in the memory preparation method provided by the embodiment of the present application.
  • Figure 18 is a schematic structural diagram after the initial mask layer is prepared in the memory preparation method provided by the embodiment of the present application.
  • Figure 19 is a schematic structural diagram after the mask structure is prepared in the memory preparation method provided by the embodiment of the present application.
  • Figure 20 is a schematic structural diagram after the first trench and the first structure column are prepared in the memory manufacturing method provided by the embodiment of the present application;
  • Figure 21 is a schematic structural diagram after laterally etching the sacrificial layers of all first structural columns in the memory preparation method provided by the embodiment of the present application;
  • Figure 22 is a schematic structural diagram of the semiconductor structure obtained in the memory preparation method provided by the embodiment of the present application.
  • Figure 23 is a schematic structural diagram after preparing a word line metal layer in the memory preparation method provided by the embodiment of the present application.
  • Figure 24 is a schematic structural diagram after the initial word line is prepared in the memory preparation method provided by the embodiment of the present application.
  • Figure 25 is a schematic structural diagram after the third protective layer is prepared in the memory preparation method provided by the embodiment of the present application.
  • Figure 26 is a schematic structural diagram of the word line after the word line is prepared in the memory preparation method provided by the embodiment of the present application;
  • Figure 27 is a schematic structural diagram of the third intermediate substrate prepared in the memory manufacturing method provided by the embodiment of the present application.
  • Figure 28 is a schematic structural diagram after the second trench is prepared in the memory manufacturing method provided by the embodiment of the present application.
  • Figure 29 is a schematic structural diagram after removing the sacrificial structure in the memory preparation method provided by the embodiment of the present application.
  • DRAM Dynamic Random Access Memory
  • the field effect transistor, the memory unit and the manufacturing method of the memory unit provided by this application are intended to solve the above technical problems of the prior art.
  • An embodiment of the present application provides a field effect transistor.
  • the structural diagram of the field effect transistor is shown in Figure 1 , including: a source electrode 1241, a drain electrode 1243, a gate electrode 31 and a channel structure 1151.
  • the source electrode 1241 is located on the substrate 10; the drain electrode 1243 is located above the source electrode 1241 and is stacked with the source electrode 1241; the gate electrode 31 and the channel structure 1151 are at least Part of the gate electrode 31 is located between the source electrode 1241 and the drain electrode 1243, and the gate electrode 31 is located on one side of the first side wall of the channel structure 1151 and is insulated from the channel structure 1151; the channel structure 1151 extends from the source electrode 1241 to The direction of the drain electrode 1243 extends and is connected to the source electrode 1241 and the drain electrode 1243 respectively.
  • the side of the source electrode 1241 and the drain electrode 1243 away from the gate electrode 31 protrudes relative to the second side wall of the channel structure 1151 away from the gate electrode 31 .
  • the channel structure 1151 is located between the source electrode 1241 and the drain electrode 1243 arranged in a stack, and the side of the source electrode 1241 and the drain electrode 1243 away from the gate electrode 31 is opposite to the channel structure 1151 .
  • the channel structure 1151 protrudes away from the second sidewall of the gate 31 , so that the size of the channel structure 1151 manufactured through the epitaxial process matches the distance from the source 1241 to the drain 1243 , so that the channel structure 1151 can be controlled.
  • the size can improve the manufacturing accuracy of the channel structure 1151, thereby ensuring the uniformity of performance of each field effect transistor in the memory, thereby ensuring the performance of the memory.
  • a source electrode 1241 , a drain electrode 1243 , a gate electrode 31 and a channel structure 1151 are provided on one side of the substrate 10 .
  • the gate electrode 31 and the channel structure 1151 are provided in the same layer.
  • the portion of the semiconductor layer 115 between the source electrode 1241 and the drain electrode 1243 is a channel structure 1151 .
  • the channel structure 1151 is represented by a dotted line. There is no dotted line in actual products.
  • the channel structure 1151 includes a first sidewall and a second sidewall that are far apart, wherein the first sidewall is a side of the channel structure 1151 close to the gate 31 , and the second sidewall is a side wall of the channel structure 1151 close to the gate 31 .
  • the sidewall is the side of the channel structure 1151 away from the gate 31 .
  • the gate electrode 31 is located between the source electrode 1241 and the drain electrode 1243, and the gate electrode 31 is located on one side of the first side wall of the channel structure 1151 and is insulated from the channel structure 1151.
  • the structure 1151 extends from the source electrode 1241 to the drain electrode 1243 and is connected to the source electrode 1241 and the drain electrode 1243 respectively. That is, in the direction perpendicular to the substrate 10, the source electrode 1241, the channel structure 1151 and the drain electrode 1243 are stacked in sequence. set up.
  • the source electrode 1241 , the channel structure 1151 and the drain electrode 1243 form a stacked structure 125 .
  • the size of the channel structure 1151 manufactured through the epitaxial process matches the distance from the source 1241 to the drain 1243, thereby controlling the size of the channel structure 1151 and improving the manufacturing accuracy of the channel structure 1151, thereby ensuring The performance of each field effect transistor in the memory is uniform, thereby ensuring the performance of the memory.
  • the orthographic projection of the second sidewall of the channel structure 1151 on the substrate 10 is located at the source electrode 1241 and the drain electrode 1243 on the substrate 10 within the orthographic projection of at least part of the first sidewall of the channel structure 1151 on the substrate 10 , the orthographic projection of the source electrode 1241 and the drain electrode 1243 on the substrate 10 overlaps with the boundary line of the orthographic projection of the source electrode 1241 and the drain electrode 1243 on the substrate 10 .
  • the orthographic projection of the source electrode 1241 on the substrate 10 and the orthographic projection of the drain electrode 1243 on the substrate both cover the orthographic projection of the channel structure 1151 on the substrate 10 .
  • the orthographic projection of the second sidewall of the channel structure 1151 on the substrate 10 is located within the orthographic projection of the source 1241 on the substrate 10 , and the second sidewall of the channel structure 1151 is on the substrate.
  • the orthographic projection of bottom 10 is located within the orthographic projection of drain 1243 on substrate 10 .
  • At least part of the first sidewall of the channel structure 1151 is in the orthographic projection of the substrate 10
  • the source electrode 1241 is in the orthographic projection of the substrate 10
  • the drain electrode 1243 is in the orthographic projection of the substrate 10 .
  • the boundary lines of the orthographic projections overlap.
  • At least one sidewall of the channel structure 1151 is laterally indented relative to the source electrode 1241 and the drain electrode 1243 , so that during the process of manufacturing the channel structure 1151 through an epitaxial process, it is possible to Precisely controlling the size of the channel structure 1151 along the direction from the source 1241 to the drain 1243 can improve the manufacturing accuracy of the channel structure 1151 and ensure the uniformity of performance of each field effect transistor in the memory.
  • a dielectric structure 1244 is also provided between the source electrode 1241 and the drain electrode 1243; the dielectric structure 1244 is located on a side of the second sidewall of the channel structure 1151. On the other side, the dielectric structure 1244 extends in a direction perpendicular to the substrate 10 and is connected to the source electrode 1241 and the drain electrode 1243 respectively.
  • the field effect transistor further includes a dielectric structure 1244, and the dielectric structure 1244, the gate 31 and the channel structure 1511 are arranged in the same layer.
  • the dielectric structure 1244 is located on one side of the second sidewall of the channel structure 1151 , that is, along the second direction, the dielectric structure 1244 is located on a side of the channel structure 1151 away from the gate 31 .
  • the dielectric structure 1244 extends in a direction perpendicular to the substrate 10 and is connected to the source electrode 1241 and the drain electrode 1243 respectively. That is, in the direction perpendicular to the substrate 10, the source electrode 1241, the dielectric structure 1244 and the drain electrode 1243 are connected to the source electrode 1241 and the drain electrode 1243 respectively.
  • the electrodes 1243 are stacked in sequence, so that the dielectric structure 1244 can play a role in supporting the source electrode 1241 and the drain electrode 1243, preventing the parts of the source electrode 1241 and the drain electrode 1243 that are not supported by the channel structure 1151 from floating, and preventing the source electrode 1241 and the drain electrode 1243 from floating.
  • the drain electrode 1243 is broken, thereby ensuring the yield of the field effect transistor.
  • the orthographic projection of the dielectric structure 1244 on the substrate 10 is separated from the orthographic projection of the gate 31 on the substrate 10 .
  • the orthographic projection of the dielectric structure 1244 on the substrate 10 is separated from the orthographic projection of the gate 31 on the substrate 10 , so that the dielectric structure 1244 and the gate 31 are respectively located in the channel structure. 1151 along both sides in the second direction.
  • the location of the dielectric structure 1244 was originally a sacrificial structure used to provide conditions for the epitaxial growth process of the channel structure 1151.
  • the sacrificial structure is located in the channel structure.
  • One side of the second side wall of 1151, therefore, the subsequently formed dielectric structure 1244 will also be located on one side of the second side wall of the channel structure 1151. This will be described in detail later in conjunction with the manufacturing method of the memory unit. No further details will be given here.
  • the orthographic projections of the source electrode 1241 and the drain electrode 1243 on the substrate 10 both cover at least part of the orthographic projection of the gate electrode 31 on the substrate 10 .
  • the orthographic projection of the source electrode 1241 on the substrate 10 covers at least part of the orthographic projection of the gate electrode 31 on the substrate 10
  • the orthographic projection of the drain electrode 1243 on the substrate 10 also covers at least part of it.
  • the gate 31 is an orthographic projection of the substrate 10 . That is, along the direction from the source electrode 1241 to the drain electrode 1243, at least part of the gate electrode 31 is located between the source electrode 1241 and the drain electrode 1243.
  • the gate electrode 31 may all be located between the source electrode 1241 and the drain electrode 1243, that is, in the direction perpendicular to the substrate 10, the source electrode 1241, the gate electrode 31, and the drain electrode 1243 are stacked in sequence.
  • the dielectric structure 1244, the channel structure 1151 and the gate electrode 31 are in the orthographic projection of the substrate 10, and the source electrode 1241 is within the orthographic projection of the substrate 10, and the dielectric structure 1244, the channel structure 1151 and the gate electrode 31 are in The orthographic average drain electrode 1243 of the substrate 10 is within the orthographic projection of the substrate 10, thereby reducing the size and volume of the field effect transistor, which is beneficial to increasing the density of the device field effect transistor. For memory devices, there is It is beneficial to improve the storage density of memory devices.
  • the channel structure 1151 is groove-shaped in a cross-section perpendicular to the substrate 10 , and the gate 31 is located in the groove of the groove-shaped channel structure 1151 .
  • the cross-sectional shape of the channel structure 1151 is a groove shape.
  • the part where the channel structure 1151 connects to the source electrode 1241 and the part where the channel structure 1151 connects to the drain electrode 1243 constitute the groove wall.
  • the remainder of the channel structure 1151 forms the bottom of the trench.
  • the gate 31 is located in the groove of the trench channel structure 1151 .
  • the size of the gate 31 will be consistent with that of the trench channel structure 1151 .
  • the manufacturing accuracy of the gate 31 can be improved, thereby further ensuring the uniformity of performance of each field effect transistor in the memory and further ensuring the performance of the memory.
  • an insulation structure 1161 is provided between the channel structure 1151 and the gate 31 so that the gate 31 is insulated from the channel structure 1151 .
  • an embodiment of the present application provides a memory unit.
  • the structural schematic diagram of the memory unit is shown in Figures 2 and 3.
  • the memory unit includes: a word line 30, a bit line 20 and a memory unit provided by the above embodiments. Any field effect tube.
  • the bit line 20 is disposed on the substrate 10; the field effect transistor is disposed above the bit line 20, and the source electrode 1241 of the field effect transistor is connected to the bit line 20, and the source electrode 1241 and the bit line 20 are on the substrate.
  • the orthographic projection on 10 has an overlapping area; the word line 30 is located on one side of the field effect transistor and is connected to the gate electrode 31 of the field effect transistor.
  • the extension direction of the word line 30 and the bit line 20 has an included angle.
  • the extension direction of the bit line 20 is perpendicular to the extension direction of the word line 30 .
  • the bit line 20 is integrated into the substrate 10 .
  • the bit line 20 and the field effect transistor are The stack is arranged, and the bit line 20 is connected to the source 1241 of the field effect transistor; the word line 30 is located on one side of the field effect transistor and connected to the gate 31 of the field effect transistor.
  • the memory unit includes an array formed by multiple field effect transistors, and the array includes rows of field effect transistors along a direction parallel to the extending direction of the bit line 20 and A column of field effect transistors along a direction parallel to the extension of the word line 30; the sources 1241 of all field effect transistors in the row of field effect transistors are connected to the same bit line 20, and the gates 31 of all field effect transistors in the row of field effect transistors are connected to the same bit line 20.
  • the first direction is defined as the column direction
  • the second direction is defined as the row direction
  • the memory unit includes an array formed by multiple field effect transistors, multiple bit lines 20 and multiple word lines 30.
  • the sources 1241 of all field effect transistors in the field effect transistor row are connected to the same line.
  • the bit lines 20 are connected, and the gates 31 of all the field effect transistors in the field effect transistor row are connected to the same word line 30 .
  • the material of the bit line 20 is metal silicide, and the material of the source electrode 1241 is doped silicon.
  • the material of the bit line 20 is metal silicide
  • the material of the source electrode 1241 is doped with silicon, thereby ensuring the conductivity of the bit line 20 and the source electrode 1241 and facilitating the convenience of the bit line 20 and the source electrode. 1241, thus facilitating the manufacturing of memory cells.
  • an embodiment of the present application provides a method for manufacturing a memory unit.
  • a schematic flow chart of the method is shown in Figure 4. The method includes the following steps S401-S406:
  • the first structural columns include a plurality of mutually insulated repeating units; the repeating units include stacked first sources, sacrificial layer and the first drain.
  • a plurality of mutually spaced first structural columns are formed on one side of the substrate 10 based on a patterning process.
  • the first structural columns include a plurality of mutually insulated repeating units 113 , and the repeating units 113 include The first source electrode 1131, the sacrificial layer 1132 and the first drain electrode 1133 are stacked.
  • S402 Perform an etching back process on the sacrificial layer in the repeating unit to form a first sacrificial structure, so that the first source electrode, the first sacrificial structure and the sidewall of the first drain electrode are combined to form a trench structure.
  • the sacrificial layer 1132 in the repeating unit 113 is etched to form the first sacrificial structure 1141 , so that the first source electrode 1131 , the first sacrificial structure 1141 and the sidewalls of the first drain electrode 1133 are combined to form Trough structure.
  • the semiconductor layer includes a channel structure located between the first source electrode and the first drain electrode.
  • an epitaxial process is used to form a semiconductor layer 115 on the sidewall of the trench structure.
  • the semiconductor layer 115 includes a channel structure 1151 located between the first source electrode 1131 and the first drain electrode 1133.
  • S404 Fill conductive material between two adjacent first structure columns, and pattern the conductive material to form a gate electrode and a word line located on one side of the sidewall of the channel structure.
  • a conductive material is filled between two adjacent first structure columns that have been processed by the etching back process and the epitaxial process, and the conductive material is patterned to form a layer located on the side wall of the channel structure 1151. Gate 31 and word line 30 on both sides.
  • the first source electrode 1131, the first sacrificial structure 1141 and the first drain electrode 1133 are patterned, so that one first source electrode 1131 forms two spaced apart source electrodes 1241, one first The sacrificial structure 1141 forms two spaced apart sacrificial structures 1242 and a first drain electrode 1133 forms two spaced apart drain electrodes 1243 .
  • the sacrificial structure 1242 is removed so that the second sidewall of the channel structure 1151 is exposed.
  • a plurality of mutually spaced first structural columns are formed on one side of the substrate based on a patterning process, and the first structural columns include a plurality of mutually insulated repeating
  • the unit previously also includes: forming a plurality of first structural rows arranged at intervals on one side of the substrate based on a patterning process; the first structural rows include stacked source rows, sacrificial rows and drain rows; in adjacent A metal layer is deposited in the trench between the two first structure rows, at least part of the metal layer is located directly below the source row; the metal layer is processed by an annealing process to form a bit line structure, and the bit line structure is processed by a patterning process to form two Bit lines set at intervals.
  • first structural rows 107 are formed on one side of the substrate 10 based on a patterning process.
  • the first structural rows 107 include stacked source rows 1071 and sacrificial rows. 1072 and drain row 1073.
  • a metal layer 1091 is deposited in the trench between two adjacent first structure rows 107, and at least part of the metal layer 1091 is located directly below the source row.
  • the metal layer 1091 is processed by an annealing process to form a bit line structure 1092
  • the bit line structure 1092 is processed by a patterning process to form two spaced apart bit lines 20 .
  • inventions of the present application provide another method for manufacturing a memory unit.
  • the flow diagram of the method is shown in Figure 5.
  • the method includes the following steps S501-S508:
  • S502 Prepare a second intermediate substrate including bit lines based on the first intermediate substrate.
  • the second intermediate substrate to form at least two first trenches and first structural columns spaced apart and parallel to the first direction.
  • the first structural column includes a plurality of mutually insulated repeating units; the first direction is parallel to the substrate. end.
  • S504 Laterally etch all repeating units of the first structure column to obtain at least two intermediate structure columns; the intermediate structure columns include initial stacked structures arranged at intervals, and the initial stacked structure includes a first source, a first sacrificial structure and The first drain electrode and two side surfaces of the first sacrificial structure are indented relative to the first source electrode and the first drain electrode along a second direction, and the second direction is parallel to the substrate and perpendicular to the first direction.
  • S505 Use an epitaxial process to prepare semiconductor layers on both sides of the initial stacked structure.
  • the semiconductor layer includes channel structures located on both sides of the first sacrificial structure.
  • the structure columns include intermediate stacked structures arranged at intervals, and the intermediate stacked structures include source electrodes, sacrificial structures and drain electrodes.
  • S508 Remove the sacrificial structure to obtain a field effect transistor including a stacked structure.
  • the repeating units of the first structural column are laterally etched so that the two side surfaces of the sacrificial layer of the repeating unit are relative to the first source and the first drain along the second direction.
  • Indent to form the first sacrificial structure prepare semiconductor layers including channel structures on both sides of the initial stacked structure through an epitaxial process, and then remove the sacrificial structure, so that the size of the channel structure in the stacked structure can be accurately controlled, and Improving the preparation accuracy of the channel structure can ensure the uniformity of performance of each field effect transistor in the memory, thereby ensuring the performance of the memory.
  • the first electrode layer 101, the sacrificial semiconductor layer 102 and the second electrode layer 103 are sequentially prepared on one side of the substrate 10 to obtain the first intermediate substrate, which specifically includes: Doped semiconductor layers are sequentially prepared on one side of the substrate 10 to obtain the first electrode layer 101; a sacrificial semiconductor layer 102 is prepared on the side of the first electrode layer 101 away from the substrate 10; and on the side of the sacrificial semiconductor layer 102 away from the substrate 10 Another doped semiconductor layer is prepared on the side to obtain the second electrode layer 103.
  • an epitaxial process may be used to sequentially prepare the first electrode layer 101, the sacrificial semiconductor layer 102, and the second electrode layer 103 on one side of the substrate 10.
  • an epitaxial process is used to prepare a doped semiconductor layer on one side of the substrate 10 so that the semiconductor layer has good conductivity to obtain the first electrode layer 101; then, an epitaxial process is used to form a doped semiconductor layer on one side of the first electrode layer 101.
  • a semiconductor layer is prepared on one side of the sacrificial semiconductor layer 102 to obtain the sacrificial semiconductor layer 102; then, an epitaxial process is used to prepare another doped semiconductor layer on the side of the sacrificial semiconductor layer 102 away from the substrate 10 to obtain the second electrode layer 103.
  • the doped semiconductor layer may be N-type doped or P-type doped, and may be heavily doped.
  • the preparation material of the sacrificial semiconductor layer 102 includes SiGe (silicon germanium), and the first electrode layer 101 and the second electrode layer 103 include doped silicon.
  • the size of the channel structure in the subsequently prepared memory field effect transistor can be controlled along the third direction, that is, by controlling the thickness of the sacrificial semiconductor layer 102 , can control the length of the subsequently prepared channel structure, thereby improving the preparation accuracy of the channel structure length, helping to ensure the uniformity of performance of each field effect transistor in the memory, and helping to ensure the performance of the memory.
  • a first protective layer 104 is prepared on one side to obtain a first intermediate substrate as shown in FIG. 6 .
  • the preparation material of the first protective layer 104 may be silicon oxide, and may adopt CVD (Chemical Vapor Deposition, chemical vapor deposition), PVD (Physical Vapor Deposition, physical vapor deposition) and ALD (Atomic Layer Deposition, atomic layer deposition). ) and other processes to prepare the first protective layer 104.
  • CVD Chemical Vapor Deposition, chemical vapor deposition
  • PVD Physical Vapor Deposition, physical vapor deposition
  • ALD Atomic Layer Deposition, atomic layer deposition
  • a second intermediate substrate including bit lines is prepared based on the first intermediate substrate, including: patterning the first intermediate substrate to form at least two spaced apart and parallel to the second direction.
  • the bit lines 20 and the third dielectric layer 110 form a second intermediate substrate.
  • the bottom of the fourth trench 106 is set to penetrate part of the substrate 10 , and the bottom of the fourth trench 106 extends toward the inside of the substrate 10 along the first direction, so that the subsequently prepared bits are
  • the wire 20 can be electrically connected to the field effect tube prepared subsequently.
  • a plurality of first mask strips 105 are prepared on the side of the first protective layer 104 away from the substrate 10 in the first intermediate substrate.
  • the plurality of first mask strips 105 are arranged at intervals and along the second direction, as shown in Figure 7.
  • the position of the subsequently prepared bit line 20 is defined by setting the first mask strip 105 .
  • patterning the first intermediate substrate to form at least two fourth trenches 106 spaced apart and parallel to the second direction includes: patterning the first intermediate substrate to form at least two spaced apart and parallel fourth trenches 106 .
  • the first structure row 107 includes stacked source rows 1071, sacrificial rows 1072 and drain rows 1073.
  • the bottom of the fourth trench 106 is along the first The direction extends in substrate 10 below at least part of source row 1071 .
  • the first intermediate substrate is patterned using the first mask strip 105 as a mask to form at least two initial fourth trenches 1061 and first structure rows 107 spaced apart and parallel to the second direction.
  • the initial fourth trenches are The bottom of 1061 penetrates part of the substrate 10 to ensure that any two adjacent first structure rows 107 are isolated by the initial fourth trench 1061, and then the first mask strip 105 is removed, as shown in FIG. 8 .
  • a second protective layer 108 conforming to the inner surface of the initial fourth trench 1061 is prepared in the initial fourth trench 1061, as shown in FIG. 9 .
  • the second protective layer 108 conforming to the inner surface of the initial fourth trench 1061 is prepared through an ALD process, so that the second protective layer 108 can protect both sides of the first structure row 107 along the first direction.
  • the preparation material of the second protective layer 108 includes silicon oxide.
  • the bottom wall of the second protective layer 108 is etched, so that part of the substrate 10 covered by the bottom wall is exposed, and second protective structures 1081 located on both sides of the first structure row 107 are obtained, as shown in FIG. 10 .
  • a dry etching process may be used to etch the bottom wall of the second protective layer 108 .
  • the substrate 10 with the bottom of the initial fourth trench 1061 exposed is etched to obtain a fourth trench 106.
  • the bottom of the fourth trench 106 extends along the first direction in the substrate 10 to at least part of the source row 1071.
  • a dry etching process may be used to etch the exposed bottom of the initial fourth trench 1061 of the substrate 10 .
  • two bit lines and a third dielectric layer 110 are prepared in the fourth trench to obtain a second intermediate substrate, including: preparing a metal layer 1091 at the bottom of the fourth trench 106 ; Use an annealing process to process the metal layer 1091 to obtain a bit line structure 1092 conforming to the bottom of the fourth trench 106 ; pattern all the bit line structures 1092 so that each bit line structure 1092 forms two parallel to the second direction bit lines 20, and at least part of each bit line 20 is located below the source row 1071; a third dielectric layer 110 is prepared in the fourth trench 106 to obtain a second intermediate substrate.
  • the initial metal layer 109 is prepared in the structure as shown in FIG. 11 , so that the initial metal layer 109 fills the fourth trench 106 and covers the first structure row 107 , as shown in FIG. 12 .
  • the initial metal layer 109 can be deposited through a CVD process, and the preparation material of the initial metal layer 109 includes Ti (titanium).
  • the metal layer 1091 at the bottom of the fourth trench 106 which specifically includes: etching the initial metal layer 109 to obtain the metal layer 1091 at the bottom of the fourth trench 106, such that the height of the metal layer 1091 along the third direction is higher than The height of the lower surface of the source row 1071 is lower than the height of the upper surface of the source row 1071 , as shown in FIG. 13 .
  • a dry etching process may be used to etch the initial metal layer 109 .
  • an annealing process is used to process the metal layer 1091, so that the metal material of the metal layer 1091 can react with the silicon material of the substrate 10, and the remaining unreacted portion of the metal layer 1091 is removed, thereby obtaining a bottom portion corresponding to the fourth trench 106.
  • shaped bit line structure 1092 as shown in Figure 14.
  • bit line structures 1092 are patterned, so that each bit line structure 1092 forms two bit lines 20 parallel to the second direction, and at least part of each bit line 20 is located below the source row 1071, as shown in FIG. 15 shown.
  • a dry etching process is used to etch the bit line structure 1092, so that each bit line structure 1092 forms two independent bit lines 20, so that each bit line 20 can be connected to the field effect tube circuit of the same row prepared subsequently. connect.
  • a third dielectric layer 110 is prepared in the fourth trench 106 to obtain a second intermediate substrate.
  • a CVD or ALD process is used to deposit and prepare the third dielectric layer 110 in the fourth trench 106 to obtain a second intermediate substrate, as shown in FIG. 16 .
  • a CMP (Chemical Mechanical Polishing) process can be used to expose the first structure rows 107 .
  • the second intermediate substrate is patterned to form at least two first trenches 112 spaced apart and parallel to the first direction and a first groove 112 including a plurality of mutually insulated repeating units 113.
  • the structure row includes: preparing a mask structure 111 on one side of the second intermediate substrate, patterning the second intermediate substrate using the mask structure 111 as a mask, and forming the first trench 112 and the first structure row, the first trench The bottom of 112 penetrates part of the substrate 10 .
  • preparing the mask structure 111 on one side of the second intermediate substrate in the above steps includes: preparing at least two first spaced apart and parallel to the first direction on one side of the second intermediate substrate. sub-mask structures 1111; prepare second sub-mask structures 1113 on both end surfaces of each first sub-mask structure 1111 along the second direction; and pattern all intermediate structure columns to obtain at least two structure columns 123, including : Etch the first sub-mask structure 1111 and the portion of the middle structure column covered by it, so that each middle structure column forms a second trench 122 parallel to the first direction and two second trenches 122 separated by the second trench 122 . Structure column 123.
  • At least two first sub-mask structures 1111 spaced apart and parallel to the first direction are prepared on one side of the second intermediate substrate, as shown in Figure 17 Show.
  • an ALD process is used to deposit SiN (silicon nitride) material to prepare a plurality of first sub-mask structures 1111 arranged at intervals and extending along the first direction.
  • the orthographic projection of the first sub-mask structure 1111 on the substrate 10 is located between two adjacent structure columns 123 prepared subsequently.
  • second sub-mask structures 1113 are prepared on both end surfaces of each first sub-mask structure 1111 along the second direction, specifically including:
  • an ALD process is used to deposit and prepare an initial mask layer 1112 on one side of the first sub-mask structure 1111 and the area on the side of the second intermediate substrate that is not covered by the first sub-mask structure 1111, so that the initial mask layer 1112 Cover the first sub-mask structure 1111 and one side of the second intermediate substrate, as shown in FIG. 18 .
  • the preparation material of the initial mask layer 1112 includes silicon oxide.
  • a dry etching process is used to etch the initial mask layer 1112, so that second sub-mask structures 1113 are formed on both end surfaces of each first sub-mask structure 1111 along the second direction, thereby preparing a first sub-mask structure 1113 including the first sub-mask structure 1111.
  • the mask structure 111 of the second sub-mask structure 1113 of the mask structure 1111 is as shown in FIG. 19 .
  • the mask structure 111 includes two second sub-mask structures 1113 and one first sub-mask structure 1111 , and the cross-sectional shape of the mask structure 111 is similar to a semicircle.
  • a first sub-mask structure 1111 is provided between any two adjacent second sub-mask structures 1113 or is separated from each other.
  • the first sub-mask structure 1111 in the mask structure 111 plays the role of alignment definition; at the same time, in the subsequent process of preparing the field effect transistor, the mask structure 1111 plays the role of alignment definition.
  • the membrane structure 111 plays a role in protecting the subsequently prepared structural array 123.
  • patterning the second intermediate substrate to form at least two first trenches 112 and first structure rows spaced apart and parallel to the first direction specifically includes: etching the first trench 112 using the mask structure 111 as a mask.
  • the two intermediate substrates form at least two first trenches 112 and first structural rows spaced apart and parallel to the first direction.
  • the first structure column includes repeating units 113 spaced apart along the first direction, and a third dielectric structure 1101 is disposed between two adjacent repeating units 113 (not shown in Figure 20 due to the obstruction of the repeating units 113 out), as shown in Figure 20.
  • the third dielectric structure 1101 is obtained by patterning the third dielectric layer 110 .
  • the repeating unit 113 includes a first source electrode 1131, a sacrificial layer 1132, a first drain electrode 1133 and an initial protection structure 1134 stacked in sequence.
  • the above-mentioned step S504 specifically includes: laterally etching the repeating units 113 of all the first structural columns to obtain at least two intermediate structural columns; the intermediate structural columns include initial stacked structures 114 arranged at intervals, and the initial stacked structures 114 are arranged at intervals.
  • the structure 114 includes a first source electrode 1131, a first sacrificial structure 1141 and a first drain electrode 1133. Both side surfaces of the first sacrificial structure 1141 are indented relative to the first source electrode 1131 and the first drain electrode 1133 along the second direction, such as As shown in Figure 21.
  • the initial stacked structure 114 is obtained by lateral etching of the repeating unit 113 .
  • the above-mentioned step S505 specifically includes: using an epitaxial process to prepare semiconductor layers 115 on both sides of the initial stacked structure 114, as shown in FIG. 22.
  • the first source electrode 1131, the first sacrificial structure 1141 and the first drain electrode 1133 all include semiconductor materials, the material used to form the semiconductor layer 115 will only be used in the first source electrode 1131, The first sacrificial structure 1141 and the first drain electrode 1133 are grown on both sides and do not grow to the third dielectric structure 1101, so that the width of the prepared semiconductor layer 115 can be accurately controlled; the first sacrificial structure 1141 is located in the semiconductor layer 115 The two side parts serve as the channel structure 1151 of the subsequently prepared field effect transistor.
  • the length of the prepared channel structure 1151 can be accurately controlled, so that It can accurately control the size of the channel structure in the stacked structure that is subsequently prepared, and can improve the preparation accuracy of the channel structure, thereby ensuring the uniformity of performance of each field effect transistor in the memory that is subsequently prepared, thereby ensuring the performance of the memory that is subsequently prepared. .
  • preparing an insulating structure and two word lines in the first trench 112 in step S506 includes: preparing an insulating structure conforming to the inner surface of the first trench 112 in the first trench 112.
  • Initial insulating layer, the initial insulating layer includes an insulating structure 1161; prepare initial word lines 118 on the inner surface side of the initial insulating layer; pattern all initial word lines 118 so that each initial word line 118 forms a line parallel to the first direction
  • the third trench 120 and two word lines 30 are inserted into part of the substrate 10 .
  • a high-k dielectric material with a relatively high dielectric constant is deposited in the first trench 112 to form an initial insulating layer conforming to the inner surface of the first trench 112.
  • the initial insulating layer includes components located in the initial stacked structure. Initial insulation structures 116 on both sides of 114 .
  • a high-k word line metal material with a higher dielectric constant such as TiN (titanium nitride) is deposited on the inner surface side of the initial insulating layer.
  • a CMP process is used to obtain the word line metal layer 117, as shown in Figure 23 Show.
  • the word line metal layer 117 is etched and stopped at a set position to obtain the initial word line 118, as shown in FIG. 24 .
  • the word line metal layer 117 is etched through a dry etching process, so that the height of the prepared initial word line 118 along the third direction is higher than the height of the lower surface of the first drain electrode 1133 and lower than the first drain electrode 1133 The height of the upper surface.
  • part of the initial insulating structure 116 will be etched to obtain the insulating structure 1161.
  • the insulating structure 1161 conforms to the surface of the semiconductor layer 115 so that the insulating structure 1161 conforms to the surface of the semiconductor layer 115. 1161 can isolate the initial word line 118 and the initial stack structure 114.
  • a third protective layer 119 is formed on the surface of the mask structure 111 through deposition and etching processes, as shown in FIG. 25 .
  • the deposition process may specifically adopt an ALD process.
  • each initial word line 118 is etched through a dry etching process, so that each initial word line 118 forms a third trench 120 parallel to the first direction and two word lines 30, as shown in FIG. 26 .
  • the third trench 120 penetrates part of the substrate 10 to isolate two adjacent word lines 30 and prevent the two adjacent word lines 30 from being electrically connected.
  • the third trench 120 will display part of the word line 20 and part of the third dielectric structure 1101 .
  • the portion of each word line 30 located in the recess of the insulation structure 1161 forms the gate electrode 31 of the field effect transistor prepared subsequently.
  • the above step S507 also includes: filling the second dielectric layer 121 between the two adjacent word lines 30 in the first trench 112 to obtain a third intermediate substrate.
  • the first trench 112 includes a third trench 120 between two adjacent word lines 30 .
  • a deposition process is used to deposit and prepare the second dielectric layer 121 in the first trench 112, so that part of the second dielectric layer 121 is filled between two adjacent word lines 30, and then the CMP process is used to smooth it, so that The third intermediate substrate is shown in Figure 27.
  • the second dielectric layer 121, the second sub-mask structure 1113, the third protection structure 1191 and the initial protection structure 1134 are all made of the same materials, the second sub-mask is not marked in Figure 27 structure 1113, the third protection structure 1191 and the initial protection structure 1134, but as a part of the second dielectric layer 121.
  • patterning all the intermediate structure columns in the above step S507 to obtain at least two structure columns includes: patterning the third intermediate substrate so that each intermediate structure column forms an intermediate structure column parallel to the first direction.
  • patterning all the intermediate structure columns to obtain at least two structure columns 123 includes: etching the first sub-mask structure 1111 and the portion of the intermediate structure columns covered by it, so that each intermediate structure column forms an A second groove 122 parallel to the first direction and two structural columns 123 separated by the second groove 122 .
  • the first sub-mask structure 111 and the portion of the intermediate structure column covered by the first sub-mask structure 1111 are etched, so that each intermediate structure column forms a structure parallel to the first sub-mask structure 1111.
  • the second trench 122 in one direction and the two structural rows 123 separated by the second trench 122 are as shown in FIG. 28 .
  • the structure column 123 includes spaced-apart middle stacked structures 124 , and the middle stacked structures 124 include a source electrode 1241 , a sacrificial structure 1242 , a drain electrode 1243 and a channel structure 1151 .
  • the sacrificial structure 1242 of the intermediate stack structure 124 is exposed.
  • the bottom of the second trench 122 penetrates part of the substrate 10 , thereby ensuring that the two structure columns 123 are effectively separated.
  • the second dielectric layer 121 is etched to form a second dielectric structure 1211 located above the structure row 123 .
  • the sacrificial structure 1242 is removed in the above step S508 to obtain a field effect transistor including the stacked structure 125, which specifically includes: removing the sacrificial structure 1242 exposed in the second trench 122 by etching, so that the intermediate stacked structure 124 forms a stacked structure 125 as shown in FIG. 29 .
  • the stacked structure 125 includes a source electrode 1241, a channel structure 1151 and a drain electrode 1243.
  • Each word line 30 includes a gate 31 corresponding to the channel structure 1151 of the stacked structure 125, thereby obtaining field effect transistors arranged in an array.
  • the above step S508 also includes: depositing dielectric material so that the dielectric material fills the second trench 122, and then smoothing it through a CMP process to make the dielectric material layer flush with the upper surface of the second dielectric structure 1211. , obtaining the fourth dielectric layer 126, as shown in FIG. 3 .
  • the fourth dielectric layer 126 and the second dielectric structure 1211 are made of the same material, the second dielectric structure 1211 is not marked in FIG. 3 , but is used as a part of the fourth dielectric layer 126 .
  • part of the dielectric material will be filled into another groove formed by the second sidewall of the channel structure 1151, the source electrode 1241 and the drain electrode 1243 to form a dielectric layer. Structure1261.
  • the source electrode 1241 and the drain electrode 1243 can be converted into each other, that is, the source electrode 1241 can serve as one of the source electrode and the drain electrode, and the drain electrode 1243 can serve as one of the source electrode and the drain electrode. another.
  • the field effect transistor includes: a stacked structure 125, which is disposed on the substrate.
  • the stacked structure 125 includes a source electrode 1241, a channel structure 1151 and a drain electrode 1243 stacked along a third direction, and the channel structure 1151 is indented relative to the source electrode 1241 and the drain electrode 1243 along the second direction;
  • the third direction is perpendicular to the substrate 10;
  • the gate 31 is at least partially disposed in the lateral groove formed by the source 1241, the channel structure 1151 and the drain 1243; the insulation structure 1161 is disposed between the gate 31 and the stack placed between structure 125
  • the gate electrode 31 is disposed on one side of the stacked structure 125 along the second direction, and the orthographic projections of the source electrode 1241, the drain electrode 1243 and the gate electrode 31 on the substrate 10 all at least partially overlap, that is, along the second direction. In three directions, part of the gate electrode 31 is sandwiched between the source electrode 1241 and the drain electrode 1243.
  • inventions of the present application provide another memory, which is prepared based on any of the memory preparation methods provided in the above embodiments.
  • the memory includes: a substrate 10, at least two word lines 30, at least two bit lines 20 and at least two field effect transistors; the bit lines 20 are arranged in the substrate 10, the bit lines 20 are parallel to the second direction, and the field effect transistors located in the same row along the second direction are connected to the same bit line 20;
  • the word line 30 is arranged on one side of the field effect transistor along the second direction.
  • the word line 30 is parallel to the first direction.
  • the field effect transistors located in the same column along the first direction are connected to the same word line 30; the first direction is parallel to the substrate. Bottom 10, and perpendicular to the second direction.
  • each word line 30 includes a gate 31 of each field effect transistor located in the same column.
  • embodiments of the present application provide an electronic device, which at least partially includes any memory as provided in the above embodiments.
  • the electronic device includes a smartphone, computer, tablet, artificial intelligence device, wearable device or power bank.
  • the electronic equipment is not limited to the above-mentioned types. Persons skilled in the art can install any of the memories provided by the above embodiments of the present application in different devices according to actual application requirements, thereby obtaining the results of the present application.
  • the electronic device provided by the embodiment provided by the embodiment.
  • the channel structure 1151 is located between the stacked source electrode 1241 and the drain electrode 1243, and the sides of the source electrode 1241 and the drain electrode 1243 away from the gate electrode 31 are opposite to each other.
  • the second sidewall of the channel structure 1151 is protruded away from the gate electrode 31, so that the size of the channel structure 1151 manufactured by the epitaxial process matches the distance from the source electrode 1241 to the drain electrode 1243, so that the channel structure can be controlled.
  • the size of 1151 can improve the manufacturing accuracy of the channel structure 1151, thereby ensuring the uniformity of performance of each field effect transistor in the memory, thereby ensuring the performance of the memory.
  • the gate 31 is located in the groove of the trench structure 1151.
  • the size of the gate 31 It will match the size of the trench channel structure 1151, so that the size of the gate 31 can be controlled, and the manufacturing accuracy of the gate 31 can be improved, thereby further ensuring the uniformity of performance of each field effect transistor in the memory, and further ensuring the quality of the memory. performance.
  • steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can be alternated, changed, combined, or deleted.
  • steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can also be alternated, changed, rearranged, decomposed, combined, or deleted.
  • steps, measures, and solutions in the prior art with various operations, methods, and processes disclosed in this application can also be replaced, changed, rearranged, decomposed, combined, or deleted.
  • first and second are used for descriptive purposes only and shall not be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of this application, unless otherwise stated, “plurality” means two or more.
  • connection should be understood in a broad sense.
  • connection or integral connection; it can be directly connected, or indirectly connected through an intermediary, or it can be internal connection between two components.
  • connection or integral connection; it can be directly connected, or indirectly connected through an intermediary, or it can be internal connection between two components.

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Abstract

本申请实施例提供了一种场效应管、存储单元及存储单元的制造方法。在本申请实施例所提供的场效应管中，沟道结构位于叠层设置的源极和漏极之间，且源极和漏极远离栅极的一侧相对于沟道结构远离栅极的第二侧壁凸出，从而使得通过外延工艺制造得到的沟道结构的尺寸与源极至漏极的距离相匹配，从而能够控制沟道结构的尺寸，能够提高沟道结构的制造精度，从而能够保障存储器中各个场效应管性能的均一性，进而保障存储器的性能。

Description

场效应管、存储单元及存储单元的制造方法 技术领域
本申请涉及半导体技术领域，具体而言，本申请涉及一种场效应管、存储单元及存储单元的制造方法。
背景技术
随着半导体技术的发展，特别是半导体器件集成化技术的发展，目前垂直结构的场效应晶体管是研究的重点方向。
目前在具有垂直结构的场效应管的存储器制备过程中，存储器中场效应管的沟道结构的制备精度较低，导致制备的沟道结构的性能波动较大，进而导致场效应管的性能波动较大。
发明内容
本申请针对现有方式的缺点，提出一种场效应管、存储单元及存储单元的制造方法，用以解决现有技术存在具有垂直结构的场效应管的存储器的制备过程中，存储器中场效应管的沟道结构的制备精度较低的技术问题。
第一个方面，本申请实施例提供了一种场效应管，包括：
源极，位于衬底上；
漏极，位于源极上方且与源极叠层设置；
栅极和沟道结构，至少部分栅极位于源极和漏极之间，且栅极位于沟道结构的第一侧壁的一侧并与沟道结构相绝缘；沟道结构从源极至漏极的方向延伸并分别与源极和漏极连接，源极和漏极远离栅极的一侧相对于沟道结构远离栅极的第二侧壁凸出。
第二个方面，本申请实施例提供了一种存储单元，包括：字线、位线和第一个方面所提供的场效应管；
位线设置于衬底上；场效应管设置于位线上方，且场效应管的源极与位线连接，源极和位线在衬底上的正投影具有重叠区域；字线位于场效应管的一侧，并与场效应管的栅极连接，字线与位线的延伸方向具有夹角。
第三个方面，本申请实施例提供了一种存储单元的制造方法，包括：
基于图案化工艺在衬底的一侧形成多个相互间隔设置的第一结构列，第一结构列包括多个相互绝缘的重复单元；重复单元包括叠层设置的第一源极、牺牲层和第一漏极；
对重复单元中的牺牲层进行回刻处理，形成第一牺牲结构，使得第一源极、第一牺牲结构和第一漏极的侧壁组合形成槽形结构；
采用外延工艺在槽形结构的侧壁形成半导体层，半导体层包括位于第一源极和第一漏极之间的沟道结构；
在相邻两个第一结构列之间填充导电材料，对导电材料进行图案化形成位于沟道结构侧壁一侧的栅极和字线；
图案化第一源极、第一牺牲结构和第一漏极，使得一个第一源极形成两个间隔设置的源极、一个第一牺牲结构形成两个间隔设置的牺牲结构以及一个第一漏极形成两个间隔设置的漏极；
去除牺牲结构。
本申请实施例提供的技术方案带来的有益技术效果包括：
在本申请实施例所提供的场效应管中，沟道结构位于叠层设置的源极和漏极之间，且源极和漏极远离栅极的一侧相对于沟道结构远离栅极的第二侧壁凸出，从而使得通过外延工艺制造得到的沟道结构的尺寸与源极至漏极的距离相匹配，从而能够控制沟道结构的尺寸，能够提高沟道结构的制造精度，从而能够保障存储器中各个场效应管性能的均一性，进而保障存储器的性能。
本申请附加的方面和优点将在下面的描述中部分给出，这些将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为本申请实施例提供的一种场效应管的结构示意图；
图2为本申请实施例提供的一种存储单元沿第一方向和第三方向所在平面的剖视图；
图3为本申请实施例提供的一种存储单元沿第二方向和第三方向所在平面的剖视图；
图4为本申请实施例提供的一种存储单元的制造方法的流程示意图；
图5为本申请实施例提供的另一种存储器的制造方法的流程示意图；
图6为本申请实施例提供的存储器的制备方法中制备得到的第一中间基板的结构示意图；
图7为本申请实施例提供的存储器的制备方法中制备得到第一掩膜结构后的结构示意图；
图8为本申请实施例提供的存储器的制备方法中制备得到初始第四沟槽和第一结构行后的结构示意图；
图9为本申请实施例提供的存储器的制备方法中制备得到第二保护层后的结构示意图；
图10为本申请实施例提供的存储器的制备方法中刻蚀第二保护层后的结构示意图；
图11为本申请实施例提供的存储器的制备方法中制备得到第四沟槽后的结构示意图；
图12为本申请实施例提供的存储器的制备方法中制备得到初始金属层后的结构示意图；
图13为本申请实施例提供的存储器的制备方法中制备得到金属层后的结构示意图；
图14为本申请实施例提供的存储器的制备方法中制备得到位线结构后的结构示意图；
图15为本申请实施例提供的存储器的制备方法中制备得到位线后的 结构示意图；
图16为本申请实施例提供的存储器的制备方法中制备得到的第二中间基板的结构示意图；
图17为本申请实施例提供的存储器的制备方法中制备得到第一子掩膜结构后的结构示意图；
图18为本申请实施例提供的存储器的制备方法中制备得到初始掩膜层后的结构示意图；
图19为本申请实施例提供的存储器的制备方法中制备得到掩膜结构后的结构示意图；
图20为本申请实施例提供的存储器的制备方法中制备得到第一沟槽和第一结构列后的结构示意图；
图21为本申请实施例提供的存储器的制备方法中侧向刻蚀所有第一结构列的牺牲层后的结构示意图；
图22为本申请实施例提供的存储器的制备方法中得到半导体结构后的结构示意图；
图23为本申请实施例提供的存储器的制备方法中制备得到字线金属层后的结构示意图；
图24为本申请实施例提供的存储器的制备方法中制备得到初始字线后的结构示意图；
图25为本申请实施例提供的存储器的制备方法中制备得到第三保护层后的结构示意图；
图26为本申请实施例提供的存储器的制备方法中制备得到字线后的结构示意图；
图27为本申请实施例提供的存储器的制备方法中制备得到的第三中间基板的结构示意图；
图28为本申请实施例提供的存储器的制备方法中制备得到第二沟槽后的结构示意图；
图29为本申请实施例提供的存储器的制备方法中去除牺牲结构后的 结构示意图。
附图标记说明：
10-衬底；20-位线；30-字线；31-栅极；
101-第一电极层；102-牺牲半导体层；103-第二电极层；104-第一保护层；105-第一掩膜条；106-第四沟槽；1061-初始第四沟槽；
107-第一结构行；1071-源极行；1072-牺牲行；1073-漏极行；
108-第二保护层；1081-第二保护结构；109-初始金属层；1091-金属层；1092-位线结构；
110-第三介质层；1101-第三介质结构；
111-掩膜结构；1111-第一子掩膜结构；1112-初始掩膜层；1113-第二子掩膜结构；
112-第一沟槽；113-重复单元；1131-第一源极；1132-牺牲层；1133-第一漏极；1134-初始保护结构；
114-初始叠置结构；1141-第一牺牲结构；115-半导体层；1151-沟道结构；
116-初始绝缘结构；1161-绝缘结构；117-字线金属层；118-初始字线；
119-第三保护层；1191-第三保护结构；
120-第三沟槽；121-第二介质层；1211-第二介质结构；122-第二沟槽；123-结构列；
124-中间叠置结构；1241-源极；1242-牺牲结构；1243-漏极；
125-叠置结构；126-第四介质层。
具体实施方式
下面结合本申请中的附图描述本申请的实施例。应理解，下面结合附图所阐述的实施方式，是用于解释本申请实施例的技术方案的示例性描述，对本申请实施例的技术方案不构成限制。
本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。应该进一步理 解的是，本申请的说明书中使用的措辞“包括”是指存在所述特征、整数、步骤、和/或操作，但不排除实现为本技术领域所支持其他特征、信息、数据、步骤、操作和/或它们的组合等。这里使用的术语“和/或”指该术语所限定的项目中的至少一个，例如“A和/或B”可以实现为“A”，或者实现为“B”，或者实现为“A和B”。
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
首先对本申请涉及的几个名词进行介绍和解释：
目前，随着半导体器件集成化技术的发展，特别是在以DRAM(Dynamic Random Access Memory，动态随机存取存储器)为代表的存储器的集成化过程中，多采用具有垂直结构的场效应管代替平面型晶体管，从而能够将源漏端布线面积节约下来，从而在不缩减存储器特征尺寸的情况下增加存储密度。
但是，目前在具有垂直结构的场效应管的存储器制备过程中，由于掺杂深度难以精准控制，导致存储器中场效应管的沟道结构的尺寸，特别是沟道结构的宽度波动较大，从而导致沟道结构的制备精度较低，导致制备的沟道结构的性能波动较大，进而导致场效应管的性能波动较大。
本申请提供的场效应管、存储单元及存储单元的制造方法，旨在解决现有技术的如上技术问题。
下面以具体地实施例对本申请的技术方案以及本申请的技术方案如何解决上述技术问题进行详细说明。需要指出的是，下述实施方式之间可以相互参考、借鉴或结合，对于不同实施方式中相同的术语、相似的特征以及相似的实施步骤等，不再重复描述。
本申请实施例提供了一种场效应管，该场效应管的结构示意图如图1所示，包括：源极1241、漏极1243、栅极31和沟道结构1151。
本申请实施例中，如图1所示，源极1241，位于衬底10上；漏极1243，位于源极1241上方且与源极1241叠层设置；栅极31和沟道结构1151，至少部分栅极31位于源极1241和漏极1243之间，且栅极31位于沟道结构1151的第一侧壁的一侧并与沟道结构1151相绝缘；沟道结构1151从 源极1241至漏极1243的方向延伸并分别与源极1241和漏极1243连接，源极1241和漏极1243远离栅极31的一侧相对于沟道结构1151远离栅极31的第二侧壁凸出。
在本申请实施例所提供的场效应管中，沟道结构1151位于叠层设置的源极1241和漏极1243之间，且源极1241和漏极1243远离栅极31的一侧相对于沟道结构1151远离栅极31的第二侧壁凸出，从而使得通过外延工艺制造得到的沟道结构1151的尺寸与源极1241至漏极1243的距离相匹配，从而能够控制沟道结构1151的尺寸，能够提高沟道结构1151的制造精度，从而能够保障存储器中各个场效应管性能的均一性，进而保障存储器的性能。
本申请实施例中，如图1所示，衬底10的一侧设置有源极1241、漏极1243、栅极31和沟道结构1151，栅极31和沟道结构1151同层设置。如图1所示，半导体层115位于源极1241和漏极1243之间的部分为沟道结构1151，图1中用虚线表示沟道结构1151，实际产品中并不存在虚线。
如图1所示，沿第二方向，沟道结构1151包括相远离的第一侧壁和第二侧壁，其中，第一侧壁为沟道结构1151靠近栅极31的一侧，第二侧壁为沟道结构1151远离栅极31的一侧。
本申请实施例中，至少部分栅极31位于源极1241和漏极1243之间，且栅极31位于沟道结构1151的第一侧壁的一侧并与沟道结构1151相绝缘，沟道结构1151从源极1241至漏极1243的方向延伸并分别与源极1241和漏极1243连接，即沿垂直于衬底10的方向上，源极1241、沟道结构1151和漏极1243依次层叠设置。可选地，如图1所示，源极1241、沟道结构1151和漏极1243形成叠置结构125。
如图1所示，沿平行于第二方向上，源极1241和漏极1243远离栅极31的一侧相对于沟道结构1151远离栅极31的第二侧壁凸出。从而使得通过外延工艺制造得到的沟道结构1151的尺寸与源极1241至漏极1243的距离相匹配，从而能够控制沟道结构1151的尺寸，能够提高沟道结构1151的制造精度，从而能够保障存储器中各个场效应管性能的均一性， 进而保障存储器的性能。
可选地，如图1所示，在本申请的一个实施例中，沟道结构1151的第二侧壁在衬底10上的正投影，位于源极1241和漏极1243在衬底10上的正投影内；至少部分沟道结构1151的第一侧壁在衬底10上的正投影，与源极1241和漏极1243在衬底10上的正投影的边界线相重叠。
本申请实施例中，如图1所示，源极1241在衬底10的正投影和漏极1243在衬底的正投影，均覆盖沟道结构1151在衬底10的正投影。
可选地，如图1所示，沟道结构1151的第二侧壁在衬底10的正投影位于源极1241在衬底10的正投影内，沟道结构1151的第二侧壁在衬底10的正投影位于漏极1243在衬底10的正投影内。
可选地，如图1所示，至少部分沟道结构1151的第一侧壁在衬底10的正投影、源极1241在衬底10的正投影的边界线以及漏极1243在衬底10的正投影的边界线相重叠。
本申请实施例中，如图1所示，沟道结构1151中至少一个侧壁相对于源极1241和漏极1243侧向缩进，从而在通过外延工艺制造沟道结构1151的过程中，能够精准控制沟道结构1151沿源极1241至漏极1243方向上的尺寸，从而能够提高沟道结构1151的制造精度，能够保障存储器中各个场效应管性能的均一性。
可选地，如图1所示，在本申请的一个实施例中，源极1241和漏极1243之间还设置有介质结构1244；介质结构1244位于沟道结构1151的第二侧壁的一侧，介质结构1244沿垂直于衬底10的方向延伸并分别与源极1241和漏极1243连接。
本申请实施例中，场效应管还包括介质结构1244，介质结构1244、栅极31和沟道结构1511同层设置。可选地，如图1所示，介质结构1244位于沟道结构1151的第二侧壁的一侧，即沿第二方向，介质结构1244位于沟道结构1151远离栅极31的一侧。
本申请实施例中，介质结构1244沿垂直于衬底10的方向延伸并分别与源极1241和漏极1243连接，即沿垂直于衬底10的方向上，源极1241、 介质结构1244和漏极1243依次层叠设置，从而使得介质结构1244能够起到支撑源极1241和漏极1243的作用，防止源极1241和漏极1243未被沟道结构1151支撑的部分悬空，能够防止源极1241和漏极1243出现断裂的现象，从而能够保障场效应管的成品率。
可选地，如图1所示，在本申请的一个实施例中，介质结构1244在衬底10的正投影与栅极31在衬底10的正投影相分离。
本申请实施例中，如图1所示，介质结构1244在衬底10的正投影与栅极31在衬底10的正投影相分离，以使得介质结构1244和栅极31分别位于沟道结构1151沿第二方向上的两侧。
在场效应管的制造过程中，介质结构1244所在位置处原为用于为沟道结构1151的外延生长工艺提供条件的牺牲结构，为了避免牺牲结构影响栅极31的生长，牺牲结构位于沟道结构1151的第二侧壁的一侧，因此，使得后续形成的介质结构1244也会位于沟道结构1151的第二侧壁的一侧，这会在后文中结合存储单元的制造方法进行详细说明，此处不再赘述。
可选地，如图1所示，在本申请的一个实施例中，源极1241和漏极1243在衬底10上的正投影均覆盖至少部分栅极31在衬底10上的正投影。
本申请实施例中，如图1所示，源极1241在衬底10的正投影覆盖至少部分栅极31在衬底10的正投影，漏极1243在衬底10的正投影也覆盖至少部分栅极31在衬底10的正投影。即沿源极1241指向漏极1243的方向上，至少部分栅极31位于源极1241和漏极1243之间。
可选地，栅极31可全部位于源极1241和漏极1243之间，即沿垂直于衬底10的方向上，源极1241、栅极31和漏极1243依次层叠设置。可选地，介质结构1244、沟道结构1151和栅极31在衬底10的正投影均位源极1241在衬底10的正投影内，介质结构1244、沟道结构1151和栅极31在衬底10的正投影均位漏极1243在衬底10的正投影内，从而能够减小场效管的尺寸的体积，有利于提高器件中场效应管的密度，对于存储器件而言，有利于提高存储器件的存储密度。
可选地，如图1所示，在本申请的一个实施例中，沟道结构1151在 垂直于衬底10的截面内呈槽形，栅极31位于槽形沟道结构1151的凹槽内。
本申请实施例中，如图1所示，沟道结构1151的截面形状呈槽形，沟道结构1151与源极1241连接的部分和沟道结构1151与漏极1243连接的部分构成槽壁，沟道结构1151剩余的部分构成槽底。
如图1所示，栅极31位于槽形沟道结构1151的凹槽内，在沟道结构1151的尺寸能够得到精准控制的情况下，栅极31的尺寸会与槽形沟道结构1151的尺寸相匹配，从而能够控制栅极31的尺寸，能够提高栅极31的制造精度，从而能够进一步保障存储器中各个场效应管性能的均一性，进一步保障存储器的性能。
可选地，如图1所示，沟道结构1151和栅极31之间设置有绝缘结构1161，以使得栅极31与沟道结构1151相绝缘。
基于同一发明构思，本申请实施例提供了一种存储单元，该存储单元的结构示意图如图2和图3所示，存储单元包括：字线30、位线20和上述各实施例所提供的任一场效应管。
本申请实施例中，位线20设置于衬底10上；场效应管设置于位线20上方，且场效应管的源极1241与位线20连接，源极1241和位线20在衬底10上的正投影具有重叠区域；字线30位于场效应管的一侧，并与场效应管的栅极31连接，字线30与位线20的延伸方向具有夹角。
可选地，如图2和图3所示，位线20的延伸方向垂直于字线30的延伸方向，位线20集成于衬底10内，沿第三方向上，位线20和场效应管叠层设置，且位线20与场效应管的源极1241连接；字线30位于场效应管的一侧，并与场效应管的栅极31连接。
可选地，如图2和图3所示，在本申请的一个实施例中，存储单元包括多个场效应管形成的阵列，阵列包括沿平行于位线20延伸方向的场效应管行和沿平行于字线30延伸方向的场效应管列；场效应管行的所有场效应管的源极1241与同一条位线20连接，场效管列的所有场效应管的栅极31与同一条字线30连接。
本申请实施例中，如图2和图3所示，定义沿第一方向为列方向，沿第二方向为行方向。
可选地，本申请实施例中，存储单元包括多个场效应管形成的阵列、多条位线20和多条字线30，场效应管行的所有场效应管的源极1241与同一条位线20连接，场效管列的所有场效应管的栅极31与同一条字线30连接。
可选地，在本申请的一个实施例中，位线20的材料为金属硅化物，源极1241的材料为掺杂的硅。
在本申请的一个实施中，位线20的材料为金属硅化物，源极1241的材料为硅掺杂，从而能够保障位线20和源极1241的导电率，且便于位线20和源极1241的制造，从而能够便于存储单元的制造。
基于同一发明构思，本申请实施例提供了一种存储单元的制造方法，该方法的流程示意图如图4所示，该方法包括如下步骤S401-S406：
S401，基于图案化工艺在衬底的一侧形成多个相互间隔设置的第一结构列，第一结构列包括多个相互绝缘的重复单元；重复单元包括叠层设置的第一源极、牺牲层和第一漏极。
可选地，如图20所示，基于图案化工艺在衬底10的一侧形成多个相互间隔设置第一结构列，第一结构列包括多个相互绝缘的重复单元113，重复单元113包括叠层设置的第一源极1131、牺牲层1132和第一漏极1133。
S402，对重复单元中的牺牲层进行回刻处理，形成第一牺牲结构，使得第一源极、第一牺牲结构和第一漏极的侧壁组合形成槽形结构。
可选地，如图21所示，刻蚀重复单元113中的牺牲层1132形成第一牺牲结构1141，使得第一源极1131、第一牺牲结构1141和第一漏极1133的侧壁组合形成槽形结构。
S403，采用外延工艺在槽形结构的侧壁形成半导体层，半导体层包括位于第一源极和第一漏极之间的沟道结构。
可选地，如图22所示，采用外延工艺在槽形结构的侧壁形成半导体 层115，半导体层115包括位于第一源极1131和第一漏极1133之间的沟道结构1151。
S404，在相邻两个第一结构列之间填充导电材料，对导电材料进行图案化形成位于沟道结构侧壁一侧的栅极和字线。
可选地，如图26所示，在经过回刻处理和外延工艺处理后的相邻两个第一结构列之间填充导电材料，对导电材料进行图案化形成位于沟道结构1151侧壁一侧的栅极31和字线30。
S405，图案化第一源极、第一牺牲结构和第一漏极，使得一个第一源极形成两个间隔设置的源极、一个第一牺牲结构形成两个间隔设置的牺牲结构以及一个第一漏极形成两个间隔设置的漏极。
可选地，如图28所示，图案化第一源极1131、第一牺牲结构1141和第一漏极1133，使得一个第一源极1131形成两个间隔设置的源极1241、一个第一牺牲结构1141形成两个间隔设置的牺牲结构1242以及一个第一漏极1133形成两个间隔设置的漏极1243。
S406，去除牺牲结构1242。
可选地，如图29所示，去除牺牲结构1242，使得沟道结构1151的第二侧壁暴露。
可选地，在本申请的一个实施例中，在上述步骤S401基于图案化工艺在衬底的一侧形成多个相互间隔设置的第一结构列，第一结构列包括多个相互绝缘的重复单元，之前还包括：基于图案化工艺在衬底的一侧形成多个间隔设置的第一结构行；第一结构行包括叠层设置的源极行、牺牲行和漏极行；在相邻两个第一结构行之间的沟槽内沉积金属层，至少部分金属层位于源极行的正下方；采用退火工艺处理金属层以形成位线结构，通过图案化工艺处理位线结构形成两条间隔设置的位线。
可选地，如图8所示，基于图案化工艺在衬底10的一侧形成多个间隔设置的第一结构行107，第一结构行107包括叠层设置的源极行1071、牺牲行1072和漏极行1073。
可选地，如图13所示，在相邻两个第一结构行107之间的沟槽内沉 积金属层1091，至少部分金属层1091位于源极行的正下方。
可选地，如图14所示，采用退火工艺处理金属层1091以形成位线结构1092，通过图案化工艺处理位线结构1092形成两条间隔设置的位线20。
基于同一发明构思，本申请实施例提供了另一种存储单元的制造方法，该方法的流程示意图如图5所示，该方法包括如下步骤S501-S508：
S501，在衬底的一侧依次制备第一电极层、牺牲半导体层和第二电极层，得到第一中间基板。
S502，基于第一中间基板制备得到包括位线的第二中间基板。
S503，图案化第二中间基板，形成至少两个间隔且平行于第一方向的第一沟槽和第一结构列，第一结构列包括多个相互绝缘的重复单元；第一方向平行于衬底。
S504，侧向刻蚀所有第一结构列的重复单元，得到至少两个中间结构列；中间结构列包括间隔排列的初始叠置结构，初始叠置结构包括第一源极、第一牺牲结构和第一漏极，第一牺牲结构的两侧面沿第二方向相对于第一源极和第一漏极缩进，第二方向平行于衬底且垂直于第一方向。
S505，采用外延工艺在初始叠置结构的两侧面制备半导体层，半导体层包括位于第一牺牲结构的两侧面的沟道结构。
S506，在第一沟槽内制备绝缘结构和两条字线；绝缘结构与半导体层的表面随形，字线包括位于绝缘结构中凹部内的栅极。
S507，图案化所有中间结构列，得到至少两个结构列；结构列包括间隔排列的中间叠置结构，中间叠置结构包括源极、牺牲结构和漏极。
S508，去除牺牲结构，得到包括叠置结构的场效应管。
在本申请实施例提供的存储器的制备方法中，通过侧向刻蚀第一结构列的重复单元，使得重复单元的牺牲层的两侧面沿第二方向相对于第一源极和第一漏极缩进形成第一牺牲结构，通过外延工艺在初始叠置结构的两侧面制备包括沟道结构的半导体层，然后去除牺牲结构，从而能够精准控制制备得到叠置结构中沟道结构的尺寸，能够提高沟道结构的制备精度，从而能够保障存储器中各个场效应管性能的均一性，进而保障存储器的性 能。
为了便于读者直观了解本申请实施例所提供的存储器的制备方法以及采用该方法制备得到的存储器的优点，下面将结合图6-图29进行具体说明。
在本申请的一个实施例中，上述步骤S501中在衬底10的一侧依次制备第一电极层101、牺牲半导体层102和第二电极层103，得到第一中间基板，具体包括：在衬底10的一侧依次制备掺杂的半导体层，得到第一电极层101；在第一电极层101远离衬底10的一侧制备牺牲半导体层102；在牺牲半导体层102远离衬底10的一侧制备另一掺杂的半导体层，得到第二电极层103。
本申请实施例中，可以采用外延工艺在衬底10的一侧依次制备第一电极层101、牺牲半导体层102和第二电极层103。
具体的，采用外延工艺在衬底10的一侧制备掺杂的半导体层，使得该半导体层具有良好的导电性，得到第一电极层101；然后，采用外延工艺在第一电极层101的一侧制备半导体层，得到牺牲半导体层102；接着，采用外延工艺在牺牲半导体层102远离衬底10的一侧制备另一掺杂的半导体层，得到第二电极层103。
可选地，掺杂的半导体层既可以是N型掺杂，也可是P型掺杂，且为重度掺杂。
本申请实施例中，牺牲半导体层102的制备材料包括SiGe(硅锗)，第一电极层101和第二电极层103包括掺杂的硅。
本申请实施例中，通过控制牺牲半导体层102沿第三方向的尺寸，可以控制后续制备得到的存储器中场效应管中沟道结构沿第三方向的尺寸，即通过控制牺牲半导体层102的厚度，可以控制后续制备得到的沟道结构的长度，从而能够提高沟道结构长度的制备精度，有助于保障存储器中各个场效应管性能的均一性，有助于保障存储器的性能。
可选地，为了保护避免后续制备工序影响第一电极层101、牺牲半导体层102和第二电极层103，特别是避免影响第二电极层103，需要在第 二电极层103远离衬底10的一侧制备得到第一保护层104，得到如图6所示的第一中间基板。
可选地，第一保护层104的制备材料可以是氧化硅，可以采用CVD(Chemical Vapor Deposition，化学气相沉积)、PVD(Physical Vapor Deposition，物理气相沉积)以及ALD(Atomic Layer Deposition，原子层沉积)等工艺制备得到第一保护层104。
在本申请的一个实施例中，上述步骤S502中基于第一中间基板制备得到包括位线的第二中间基板，包括：图案化第一中间基板，形成至少两个间隔且平行于第二方向的第四沟槽106；第四沟槽106的底部探入于部分衬底10，第四沟槽106的底部沿第一方向向衬底10的内部延伸；在第四沟槽106内制备两条位线20和第三介质层110，得到第二中间基板。
本申请实施例中，通过设置第四沟槽106的底部探入于部分衬底10，且第四沟槽106的底部沿第一方向向衬底10的内部延伸，从而使得后续制备得到的位线20能够与后续制备得到的场效应管电连接。
本申请实施例中，在第一中间基板中第一保护层104远离衬底10的一侧制备得到多个第一掩膜条105，多个第一掩膜条105间隔排列，且沿第二方向延伸，如图7所示。本申请实施例中，通过设置第一掩膜条105来定义后续制备得到的位线20的位置。
在本申请的一个实施例中，图案化第一中间基板，形成至少两个间隔且平行于第二方向的第四沟槽106，包括：图案化第一中间基板，形成至少两个间隔且平行于第二方向的第四沟槽106和第一结构行107，第一结构行107包括叠置的源极行1071、牺牲行1072和漏极行1073，第四沟槽106的底部沿第一方向在衬底10中延伸至至少部分源极行1071的下方。
具体的，以第一掩膜条105为掩膜图案化第一中间基板，形成至少两个间隔且平行于第二方向的初始第四沟槽1061和第一结构行107，初始第四沟槽1061的底部探入部分衬底10，从而能够保障任意相邻两个第一结构行107被初始第四沟槽1061所隔离开，然后去除第一掩膜条105，如图8所示。
接着，在初始第四沟槽1061内制备与初始第四沟槽1061内表面随形的第二保护层108，如图9所示。可选地，通过ALD的工艺制备得到与初始第四沟槽1061内表面随形的第二保护层108，使得第二保护层108能够保护第一结构行107沿第一方向的两个侧面。可选地，第二保护层108的制备材料包括氧化硅。
然后，刻蚀第二保护层108的底壁，使得被底壁所覆盖的部分衬底10暴露，得到位于护第一结构行107两侧面的第二保护结构1081，如图10所示。可选地，可以采用干刻工艺刻蚀第二保护层108的底壁。
接着，刻蚀初始第四沟槽1061的底部暴露的衬底10，得到第四沟槽106，第四沟槽106的底部沿第一方向在衬底10中延伸至至少部分源极行1071的下方，如图11所示。可选地，可以采用干刻工艺刻蚀初始第四沟槽1061的底部暴露的衬底10。
在本申请的一个实施例中，上述步骤中在第四沟槽内制备两条位线和第三介质层110，得到第二中间基板，包括：在第四沟槽106的底部制备金属层1091；采用退火工艺处理金属层1091，得到与第四沟槽106的底部随形的位线结构1092；图案化所有位线结构1092，使得每条位线结构1092形成两条平行于第二方向的位线20，且每条位线20的至少部分位于源极行1071的下方；在第四沟槽106内制备第三介质层110，得到第二中间基板。
本申请实施例中，在如图11所示的结构中制备初始金属层109，使得初始金属层109填充第四沟槽106并覆盖第一结构行107，如图12所示。可选地，可以通过CVD工艺沉积得到初始金属层109，初始金属层109的制备材料包括Ti(钛)。
然后，在第四沟槽106的底部制备金属层1091，具体包括：刻蚀初始金属层109，得到位于第四沟槽106底部的金属层1091，使得金属层1091沿第三方向的高度高于源极行1071下表面的高度，且低于源极行1071上表面的高度，如图13所示。可选地，可以采用干刻工艺刻蚀初始金属层109。
接着，采用退火工艺处理金属层1091，使得金属层1091的金属材料能够与衬底10的硅材料发生反应，并去除金属层1091剩余未反应的部分，从而得到与第四沟槽106的底部随形的位线结构1092，如图14所示。
应该说明的是，如图6-图29所示，只是展示了制备过程中各个中间结构的局部。
然后，图案化所有位线结构1092，使得每条位线结构1092形成两条平行于第二方向的位线20，且每条位线20的至少部分位于源极行1071的下方，如图15所示。具体的，采用干刻工艺刻蚀位线结构1092，使得每条位线结构1092形成两条独立的位线20，从使得每条位线20能够与后续制备得到的同一行的场效应管电连接。
接着，在第四沟槽106内制备第三介质层110，得到第二中间基板。具体的，采用CVD或ALD工艺在第四沟槽106内沉积制备得到第三介质层110，从而得到第二中间基板，如图16所示。可选地，在沉积制备得到第三介质层110后，可以采用CMP(Chemical Mechanical Polishing，化学机械抛光)工艺处理，使得第一结构行107出露。
在本申请的一个实施例中，上述步骤S503中图案化第二中间基板，形成至少两个间隔且平行于第一方向的第一沟槽112和包括多个相互绝缘的重复单元113的第一结构列，包括：在第二中间基板的一侧制备掩膜结构111，以掩膜结构111为掩膜图案化第二中间基板，形成第一沟槽112和第一结构列，第一沟槽112底部探入于部分衬底10。
在本申请的一个实施例中，上述步骤中在第二中间基板的一侧制备掩膜结构111，包括：在第二中间基板的一侧制备至少两个间隔且平行于第一方向的第一子掩膜结构1111；在每个第一子掩膜结构1111沿第二方向的两端面制备第二子掩膜结构1113；以及，图案化所有中间结构列，得到至少两个结构列123，包括：刻蚀第一子掩膜结构1111和被其覆盖中间结构列的部分，使得每个中间结构列形成一个平行于第一方向的第二沟槽122和被第二沟槽122分隔的两个结构列123。
本申请实施例中，基于如图16所示的第二中间基板，在第二中间基 板的一侧制备至少两个间隔且平行于第一方向的第一子掩膜结构1111，如图17所示。可选地，采用ALD工艺沉积SiN(氮化硅)材料制备得到多个间隔设置且沿第一方向延伸的第一子掩膜结构1111。
可选地，第一子掩膜结构1111在衬底10的正投影位于后续制备得到的两个相邻的结构列123之间。
本申请实施中，在每个第一子掩膜结构1111沿第二方向的两端面制备第二子掩膜结构1113，具体包括：
然后，采用ALD工艺在第一子掩膜结构1111的一侧和第二中间基板一侧未被第一子掩膜结构1111遮盖的区域沉积制备一初始掩膜层1112，使得初始掩膜层1112覆盖第一子掩膜结构1111和第二中间基板一侧，如图18所示。可选地，初始掩膜层1112的制备材料包括氧化硅。
接着，采用干法刻蚀工艺刻蚀初始掩膜层1112，使得每个第一子掩膜结构1111沿第二方向的两端面形成有第二子掩膜结构1113，从而制备得到包括第一子掩膜结构1111的第二子掩膜结构1113的掩膜结构111，如图19所示。
本申请实施例中，如图19所示，掩膜结构111包括两个第二子掩膜结构1113和一个第一子掩膜结构1111，掩膜结构111的截面形状类似半圆形。任意相邻两个第二子掩膜结构1113之间设置有第一子掩膜结构1111或相互分隔开。
本申请实施例中，在后续制备字线30的过程中，掩膜结构111中的第一子掩膜结构1111起到对准定义的作用；同时，在后续制备场效应管的过程中，掩膜结构111起到保护后续制备得到的结构列123的作用。
本申请实施例中，图案化第二中间基板，形成至少两个间隔且平行于第一方向的第一沟槽112和第一结构列，具体包括：以掩膜结构111为掩膜刻蚀第二中间基板，形成至少两个间隔且平行于第一方向的第一沟槽112和第一结构列。
本申请实施例中，第一结构列包括沿第一方向间隔设置的重复单元113，相邻两个重复单元113之间设置有第三介质结构1101(图20中由 于重复单元113的遮挡未示出)，如图20所示。第三介质结构1101是通过图案化第三介质层110得到的。
如图20所示，第一沟槽112的底部探入于部分衬底10，从而使得相邻的两个第一结构列相互隔离开。重复单元113包括依次叠置的第一源极1131、牺牲层1132、第一漏极1133和初始保护结构1134。
本申请实施例中，上述步骤S504具体包括：侧向刻蚀所有第一结构列的重复单元113，得到至少两个中间结构列；中间结构列包括间隔排列的初始叠置结构114，初始叠置结构114包括第一源极1131、第一牺牲结构1141和第一漏极1133，第一牺牲结构1141的两侧面沿第二方向相对于第一源极1131和第一漏极1133缩进，如图21所示。
可选地，结合图20和图21可知，初始叠置结构114由重复单元113侧向刻蚀后得到。
本申请实施例中，如图21所示，由于第一牺牲结构1141的侧向缩进，使得被重复单元113遮挡的第三介质结构1101部分出露。
本申请实施例中，上述步骤S505具体包括：采用外延工艺在初始叠置结构114的两侧面制备半导体层115，如图22所示。
本申请实施例中，由于第一源极1131、第一牺牲结构1141和第一漏极1133均包括半导电体材料，因此，用于形成半导体层115的材料只会在第一源极1131、第一牺牲结构1141和第一漏极1133的两侧面生长形成，并不会生长到第三介质结构1101，从而能够精准控制制备得到的半导体层115宽度；半导体层115中位于第一牺牲结构1141的两侧面的部分作为后续制备得到的场效应管的沟道结构1151，由于第一牺牲结构1141沿第三方向的尺寸能够精准控制，从而能够精准控制制备得到的沟道结构1151的长度，从而能够精准控制后续制备得到叠置结构中沟道结构的尺寸，能够提高沟道结构的制备精度，从而能够保障后续制备得到存储器中各个场效应管性能的均一性，进而保障后续制备得到存储器的性能。
在本申请的一个实施例中，上述步骤S506中在第一沟槽内制备绝缘结构和两条字线，包括：在第一沟槽112内制备与第一沟槽112的内表面 随形的初始绝缘层，初始绝缘层包括绝缘结构1161；在初始绝缘层的内表面一侧制备初始字线118；图案化所有初始字线118，使得每个条初始字线118形成一个平行于第一方向的第三沟槽120和两条字线30，第三沟槽120探入于部分衬底10。
本申请实施例中，在第一沟槽112内沉积介电常数较高的高k介质材料形成与第一沟槽112的内表面随形的初始绝缘层，初始绝缘层包括位于初始叠置结构114的两侧面的初始绝缘结构116。然后，在初始绝缘层的内表面一侧沉积介电常数较高的高k字线金属材料，如TiN(氮化钛)，接着，采用CMP工艺处理得到字线金属层117，如图23所示。
然后，刻蚀字线金属层117并停止在设定位置处，得到初始字线118，如图24所示。可选地，通过干刻工艺刻蚀字线金属层117，使得制备得到的初始字线118沿第三方向的高度高于第一漏极1133下表面的高度，且低于第一漏极1133上表面的高度。可选地，通过干刻工艺刻蚀字线金属层117的过程中，会刻蚀初始绝缘结构116的部分，从而得到绝缘结构1161，绝缘结构1161与半导体层115的表面随形从而使得绝缘结构1161能够隔离开初始字线118和初始叠置结构114。
接着，通过沉积和刻蚀工艺在掩膜结构111的表面形成第三保护层119，如图25所示。可选地，沉积工艺具体可以采用ALD工艺。
然后，通过干刻工艺刻蚀处理所有初始字线118，使得每个条初始字线118形成一个平行于第一方向的第三沟槽120和两条字线30，如图26所示。本申请实施例中，第三沟槽120探入于部分衬底10，从而使得相邻两条字线30隔离开来，避免相邻两条字线30电连接。
如图26所示，沿第一方向，第三沟槽120会显示部分字线20和部分第三介质结构1101。本申请实施例中，每条字线30位于绝缘结构1161凹部内的部分形成后续制备得到的场效应管的栅极31。
在通过干刻工艺刻蚀处理所有初始字线118的过程中，第三保护层119位于掩膜结构111的表面的部分会被刻蚀掉，从而形成位于初始叠置结构114两侧面的第三保护结构1191。
在本申请的一个实施例中，上述步骤S507之前还包括：在第一沟槽112内相邻的两条字线30之间填充第二介质层121，得到第三中间基板。
本申请实施例中，第一沟槽112包括相邻两条字线30之间的第三沟槽120。具体的，采用沉积工艺在第一沟槽112内沉积制备第二介质层121，使得部分第二介质层121填充于相邻的两条字线30之间，然后采用CMP工艺磨平处理，得到第三中间基板，如图27所示。本申请实施例中，由于第二介质层121、第二子掩膜结构1113、第三保护结构1191和初始保护结构1134的制备材料均相同，因此，图27中未标出第二子掩膜结构1113、第三保护结构1191和初始保护结构1134，而是将其作为第二介质层121的一部分。
在本申请的一个实施例中，上述步骤S507中图案化所有中间结构列，得到至少两个结构列，包括：图案化第三中间基板，使得每个中间结构列形成一个平行于第一方向的第二沟槽122和至少一个结构列123；第二沟槽122探入于部分衬底10。
本申请实施例中，图案化所有中间结构列，得到至少两个结构列123，包括：刻蚀第一子掩膜结构1111和被其覆盖中间结构列的部分，使得每个中间结构列形成一个平行于第一方向的第二沟槽122和被第二沟槽122分隔的两个结构列123。
具体的，以第一子掩膜结构1111为基准，刻蚀第一子掩膜结构111和中间结构列被第一子掩膜结构1111覆盖的部分，使得每个中间结构列形成一个平行于第一方向的第二沟槽122和被第二沟槽122分隔的两个结构列123，如图28所示。
本申请实施例中，结构列123包括间隔排列的中间叠置结构124，中间叠置结构124包括源极1241、牺牲结构1242、漏极1243和沟道结构1151。从而使得中间叠置结构124的牺牲结构1242暴露出来。如图28所示，第二沟槽122的底部探入部分衬底10，从而确保有效分隔开两个结构列123。如图28所示，第二介质层121被刻蚀后形成位于结构列123上方的第二介质结构1211。
本申请实施例中，上述步骤S508中去除牺牲结构1242，得到包括叠置结构125的场效应管，具体包括：通过刻蚀去除暴露在第二沟槽122的牺牲结构1242，使得中间叠置结构124形成叠置结构125，如图29所示。叠置结构125包括源极1241、沟道结构1151和漏极1243。每条字线30包括与叠置结构125的沟道结构1151对应的栅极31，从而得到阵列排布的场效应管。
本申请实施例中，上述步骤S508之后还包括：沉积介质材料，使得介质材料填充第二沟槽122，然后通过CMP工艺磨平处理，使得介质材料层与第二介质结构1211的上表面平齐，得到第四介质层126，如图3所示。本申请实施例中，由于第四介质层126和第二介质结构1211的制备材料均相同，因此，图3中未标出第二介质结构1211，而是将其作为第四介质层126的一部分。
可选地，在制备第四介质层126的过程中，会有部分介质材料填充到沟道结构1151第二侧壁、源极1241和漏极1243围合形成的另一凹槽中，形成介质结构1261。
应该说明的是，本申请实施例中，源极1241和漏极1243可以相互转换，即源极1241可以充当源极、漏极中的一种，漏极1243可以充当源极、漏极中的另一种。
基于同一发明构思，本申请实施例提供了另一种场效应管，基于上述各个实施例所提供的任一种存储器的制备方法制备得到，场效应管包括：叠置结构125，设置于衬底10的一侧，叠置结构125包括沿第三方向叠置的源极1241、沟道结构1151和漏极1243，沟道结构1151沿第二方向相对于源极1241和漏极1243缩进；第三方向垂直于衬底10；栅极31，至少部分设置于源极1241、沟道结构1151和漏极1243围合形成的侧向凹槽中；绝缘结构1161，设置于栅极31和叠置结构125之间
本申请实施例中，栅极31设置于叠置结构125沿第二方向的一侧面，且源极1241、漏极1243和栅极31在衬底10的正投影均至少部分重叠，即沿第三方向，部分栅极31夹设于源极1241和漏极1243之间。
基于同一发明构思，本申请实施例提供了另一种存储器，基于上述各个实施例所提供的任一种存储器的制备方法制备得到，存储器包括：衬底10、至少两条字线30、至少两条位线20和至少两个场效应管；位线20设置于衬底10内，位线20平行于第二方向，沿第二方向位于同一行的场效应管与同一条位线20连接；字线30设置于场效应管沿第二方向的一侧，字线30平行于第一方向，沿第一方向位于同一列的场效应管与同一条字线30连接；第一方向平行于衬底10，且垂直于第二方向。
在本申请的一个实施例中，每条字线30包括位于同一列的各场效应管的栅极31。
基于同一发明构思，本申请实施例提供了一种电子设备，至少部分包括如上述各个实施例所提供的任一种存储器。
本申请实施例中，由于电子设备采用了前述各实施例提供的任一种存储器，其原理和技术效果请参阅前述各实施例，在此不再赘述。
可选地，电子设备包括智能电话、计算机、平板电脑、人工智能设备、可穿戴设备或移动电源。
应该说明的是，电子设备并不局限于上述几种，本领域技术人员可以根据实际的应用需求，在不同的设备中设置本申请上述各个实施例所提供的任一种存储器，从而得到本申请实施例所提供的电子设备。
应用本申请实施例，至少能够实现如下有益效果：
1、在本申请实施例所提供的场效应管中，沟道结构1151位于叠层设置的源极1241和漏极1243之间，且源极1241和漏极1243远离栅极31的一侧相对于沟道结构1151远离栅极31的第二侧壁凸出，从而使得通过外延工艺制造得到的沟道结构1151的尺寸与源极1241至漏极1243的距离相匹配，从而能够控制沟道结构1151的尺寸，能够提高沟道结构1151的制造精度，从而能够保障存储器中各个场效应管性能的均一性，进而保障存储器的性能。
2、在本申请实施例所提供的场效应管中，栅极31位于槽形沟道结构1151的凹槽内，在沟道结构1151的尺寸能够得到精准控制的情况下，栅 极31的尺寸会与槽形沟道结构1151的尺寸相匹配，从而能够控制栅极31的尺寸，能够提高栅极31的制造精度，从而能够进一步保障存储器中各个场效应管性能的均一性，进一步保障存储器的性能。
本技术领域技术人员可以理解，本申请中已经讨论过的各种操作、方法、流程中的步骤、措施、方案可以被交替、更改、组合或删除。进一步地，具有本申请中已经讨论过的各种操作、方法、流程中的其他步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。进一步地，现有技术中的具有与本申请中公开的各种操作、方法、流程中的步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。
在本申请的描述中，词语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方向或位置关系，为基于附图所示的示例性的方向或位置关系，是为了便于描述或简化描述本申请的实施例，而不是指示或暗示所指的装置或部件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
应该理解的是，虽然附图的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤的实施顺序并不受限于箭头所指示的顺序。除非本文 中有明确的说明，否则在本申请实施例的一些实施场景中，各流程中的步骤可以按照需求以其他的顺序执行。而且，各流程图中的部分或全部步骤基于实际的实施场景，可以包括多个子步骤或者多个阶段。这些子步骤或者阶段中的部分或全部可以在同一时刻被执行，也可以在不同的时刻被执行在执行时刻不同的场景下，这些子步骤或者阶段的执行顺序可以根据需求灵活配置，本申请实施例对此不限制。
以上所述仅是本申请的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请的方案技术构思的前提下，采用基于本申请技术思想的其他类似实施手段，同样属于本申请实施例的保护范畴。

Claims (11)

  1. 一种场效应管，其特征在于，包括：
    源极，位于衬底上；
    漏极，位于所述源极上方且与所述源极叠层设置；
    栅极和沟道结构，至少部分所述栅极位于所述源极和所述漏极之间，且所述栅极位于所述沟道结构的第一侧壁的一侧并与所述沟道结构相绝缘；所述沟道结构从所述源极至所述漏极的方向延伸并分别与所述源极和所述漏极连接，所述源极和所述漏极远离所述栅极的一侧相对于所述沟道结构远离所述栅极的第二侧壁凸出。
  2. 根据权利要求1所述的场效应管，其特征在于，所述沟道结构的第二侧壁在所述衬底上的正投影，位于所述源极和所述漏极在所述衬底上的正投影内；
    至少部分所述沟道结构的第一侧壁在所述衬底上的正投影，与所述源极和所述漏极在所述衬底上的正投影的边界线相重叠。
  3. 根据权利要求1所述的场效应管，其特征在于，所述源极和所述漏极之间还设置有介质结构；所述介质结构位于所述沟道结构的第二侧壁的一侧，所述介质结构沿垂直于所述衬底的方向延伸并分别与所述源极和所述漏极连接。
  4. 根据权利要求3所述的场效应管，其特征在于，所述介质结构在所述衬底的正投影与所述栅极在所述衬底的正投影相分离。
  5. 根据权利要求1所述的场效应管，其特征在于，所述源极和所述漏极在所述衬底上的正投影均覆盖至少部分所述栅极在所述衬底上的正投影。
  6. 根据权利要求1所述的场效应管，其特征在于，所述沟道结构在垂直于所述衬底的截面内呈槽形，所述栅极位于所述槽形沟道结构的凹槽内。
  7. 一种存储单元，其特征在于，包括：字线、位线和上述权利要求1-6任一所述的场效应管；
    所述位线设置于衬底上；所述场效应管设置于所述位线上方，且所述场效应管的源极与所述位线连接，所述源极和所述位线在所述衬底上的正投影具有重叠区域；所述字线位于所述场效应管的一侧，并与所述场效应管的栅极连接，所述字线与所述位线的延伸方向具有夹角。
  8. 根据权利要求7所述的存储单元，其特征在于，包括多个所述场效应管形成的阵列，所述阵列包括沿平行于所述位线延伸方向的场效应管行和沿平行于所述字线延伸方向的场效应管列；
    所述场效应管行的所有所述场效应管的所述源极与同一条所述位线连接，所述场效管列的所有所述场效应管的栅极与同一条所述字线连接。
  9. 根据权利要求7所述的存储单元，其特征在于，所述位线的材料为金属硅化物，所述源极的材料为掺杂的硅。
  10. 一种存储单元的制造方法，其特征在于，包括：
    基于图案化工艺在衬底的一侧形成多个相互间隔设置的第一结构列，所述第一结构列包括多个相互绝缘的重复单元；所述重复单元包括叠层设置的第一源极、牺牲层和第一漏极；
    对所述重复单元中的所述牺牲层进行回刻处理，形成第一牺牲结构，使得所述第一源极、所述第一牺牲结构和所述第一漏极的侧壁组合形成槽形结构；
    采用外延工艺在所述槽形结构的侧壁形成半导体层，半导体层包括位于所述第一源极和所述第一漏极之间的沟道结构；
    在相邻两个所述第一结构列之间填充导电材料，对所述导电材料进行图案化形成位于沟道结构侧壁一侧的栅极和字线；
    图案化所述第一源极、所述第一牺牲结构和所述第一漏极，使得一个所述第一源极形成两个间隔设置的源极、一个所述第一牺牲结构形成两个间隔设置的牺牲结构以及一个所述第一漏极形成两个间隔设置的漏极；
    去除所述牺牲结构。
  11. 根据权利要求10所述的存储单元的制造方法，其特征在于，所述基于图案化工艺在衬底的一侧形成多个相互间隔设置的第一结构列，所述第一结构列包括多个相互绝缘的重复单元，之前还包括：
    基于图案化工艺在所述衬底的一侧形成多个间隔设置的第一结构行；所述第一结构行包括叠层设置的源极行、牺牲行和漏极行；
    在相邻两个第一结构行之间的沟槽内沉积金属层，至少部分所述金属层位于所述源极行的正下方；
    采用退火工艺处理所述金属层以形成位线结构，通过图案化工艺处理位线结构形成两条间隔设置的位线。
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