WO2024036725A1 - 监测电路以及存储系统 - Google Patents

监测电路以及存储系统 Download PDF

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Publication number
WO2024036725A1
WO2024036725A1 PCT/CN2022/124145 CN2022124145W WO2024036725A1 WO 2024036725 A1 WO2024036725 A1 WO 2024036725A1 CN 2022124145 W CN2022124145 W CN 2022124145W WO 2024036725 A1 WO2024036725 A1 WO 2024036725A1
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Prior art keywords
node
voltage
inverter
signal
circuit
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PCT/CN2022/124145
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English (en)
French (fr)
Inventor
秦建勇
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长鑫存储技术有限公司
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Priority to US18/449,044 priority Critical patent/US20240061026A1/en
Publication of WO2024036725A1 publication Critical patent/WO2024036725A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing

Definitions

  • the embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a monitoring circuit and a storage system.
  • Volatile memory devices such as dynamic random access memory (DRAM) devices, store data by charging or discharging capacitors in the memory cells, and lose the stored data when power is removed.
  • Non-volatile memory devices such as flash memory devices, retain stored data even when power is removed.
  • Volatile memory devices are widely used as main memory for various devices, while non-volatile memory devices are widely used for storing program codes and/or data in various electronic devices such as computers, mobile devices, and the like.
  • Storage systems usually operate in multiple voltage domains, and different voltage domains provide different voltages.
  • the storage system When the voltages provided by different voltage domains meet the requirements, the storage system is in a normal power-on state, and the read and write operations performed during this period are highly accurate; when the voltages provided by different voltage domains do not meet the requirements, the storage system is in an abnormal power-on state.
  • the power status will affect the normal reading and writing of the storage system. Therefore, monitoring whether the voltage provided by each voltage domain meets the requirements is very important for improving the read and write performance of the storage system.
  • Embodiments of the present disclosure provide a monitoring circuit and a storage system, which are at least conducive to monitoring whether the first voltage domain, the second voltage domain, and the third voltage domain are powered on normally.
  • embodiments of the present disclosure provide a monitoring circuit, including: a voltage detection module that outputs a first detection signal, a second detection signal and a third detection signal through a first node, a second node and a third node respectively.
  • Three detection signals configured to detect whether the first voltage provided by the first voltage domain is greater than or equal to the first preset value, and if so, the first detection signal has a first preset level; detecting the second voltage domain Whether the second voltage provided is greater than or equal to the second preset value, if so, the second detection signal has a second preset level; detecting whether the third voltage provided by the third voltage domain is greater than or equal to the third preset value value, if yes, then the third detection signal has a third preset level; the logic circuit module is connected to the first node, the second node and the third node, and outputs a monitoring signal through the fourth node, is configured to determine whether the first detection signal has the first preset level, whether the second detection signal has the second preset level, and whether the third detection signal has the third Three preset levels, if yes, then the monitoring signal is in a valid state, if not, then the monitoring signal is in an invalid state.
  • the voltage detection module has a first output element that directly outputs the first detection signal to the logic circuit module, and a second output element that directly outputs the second detection signal to the logic circuit module.
  • An output element has a third output element that directly outputs the third detection signal to the logic circuit module; the first output element, the second output element and the third output element all work on the third Two voltage domains; the logic circuit module includes a logic operation element directly connected to the first node, the second node and the third node, and the logic operation element operates in the second voltage domain;
  • the first preset value is greater than the second preset value; the second preset value is greater than the third preset value.
  • the voltage detection module includes: a first detection unit, the output terminal being the first node, configured to detect whether the first voltage is greater than or equal to the first preset value;
  • the second detection unit whose output terminal is the second node, is configured to detect whether the second voltage is greater than or equal to the second preset value;
  • the third detection unit whose output terminal is the third node, is configured to detect whether the second voltage is greater than or equal to the second preset value; It is configured to detect whether the third voltage is greater than or equal to the third preset value.
  • the first detection unit includes: a first detection circuit, used to detect whether the first voltage is greater than or equal to the first preset value, and if so, output the voltage with the first voltage through the output terminal.
  • the first detection signal of a preset level a first inverter, working in the first voltage domain, the input end of the first inverter is connected to the output end of the first detection circuit;
  • Two inverters, working in the second voltage domain, the input terminal of the second inverter is connected to the output terminal of the first inverter, and the output terminal of the second inverter serves as the third One node.
  • the first detection circuit includes: a first resistor and a second resistor connected in series, one end of the first resistor receives the first voltage, the other end of the first resistor and the second resistor One end of the two resistors is connected to the first voltage dividing node, and the other end of the second resistor is connected to ground; a third resistor, one end of the third resistor receives the first voltage; a first NMOS tube, the first NMOS tube The gate is connected to the first voltage dividing node, the drain is connected to the other end of the third resistor and serves as the output end of the first detection circuit, and the source is connected to ground.
  • the first detection circuit further includes: a first capacitor, one end of the first capacitor is connected to the first voltage dividing node, and the other end is connected to ground.
  • the second detection unit includes: a second detection circuit for detecting whether the second voltage is greater than or equal to the second preset value, and if so, outputting the voltage with the first voltage through the output terminal.
  • the second detection signal of two preset levels; a third inverter, working in the second voltage domain, the input end of the third inverter is connected to the output end of the second detection circuit;
  • Four inverters, working in the second voltage domain, the input terminal of the fourth inverter is connected to the output terminal of the third inverter, and the output terminal of the fourth inverter serves as the third Two nodes.
  • the third detection unit includes: a third detection circuit for detecting whether the third voltage is greater than or equal to the third preset value, and if so, outputting the voltage with the third voltage through the output terminal.
  • the third detection signal of three preset levels a fifth inverter, working in the third voltage domain, the input end of the fifth inverter is connected to the output end of the third detection circuit;
  • the third output element includes: a first level conversion unit, working in the second voltage domain, connected to the output end of the fifth inverter, and outputting the third detection signal; an even number A cascaded sixth inverter, the sixth inverter operates in the second voltage domain, the input terminal of the sixth inverter at the first stage receives the third detection signal, and the input terminal of the sixth inverter at the last stage receives the third detection signal.
  • the output terminal of the sixth inverter of the stage serves as the third node.
  • the first level conversion unit includes: a fourth resistor and a second NMOS transistor.
  • One end of the fourth resistor receives the second voltage, and the other end is connected to the drain of the second NMOS transistor.
  • the source electrode of the second NMOS transistor is connected to the ground and serves as the output node for outputting the third detection signal.
  • the gate electrode of the second NMOS transistor is connected to the output terminal of the fifth inverter.
  • the logic circuit module includes: a NOR circuit, connected to the first node, the second node and the third node, operating in the second voltage domain, and passing through a fifth The node outputs the monitoring signal; wherein the first preset level, the second preset level and the third preset level are the same level; a driving circuit, the driving circuit is provided by The fifth node transmits the transmission path of the monitoring signal to the fourth node.
  • the driving circuit includes: a first driving circuit, working in the first voltage domain, providing a first transmission path for transmitting the monitoring signal from the fifth node to the sixth node, the The sixth node is located between the fourth node and the fifth node; a second drive circuit works in the second voltage domain and provides the monitoring signal to be transmitted from the sixth node to the fourth node. the second transmission path.
  • the first driving circuit includes: a second level conversion unit connected to the fifth node and working in the first voltage domain, receiving the monitoring signal and outputting a monitoring inverted signal,
  • the monitoring inverted signal and the monitoring signal are mutually inverted signals;
  • the eighth inverter works in the first voltage domain, and the input end of the eighth inverter receives the monitoring inverted signal,
  • the output terminal of the eighth inverter serves as the sixth node.
  • the second driving circuit includes: an even number of ninth inverters in cascade, the ninth inverters all operate in the second voltage domain, and the ninth inverters in the first stage The input end of the inverter is connected to the sixth node, and the output end of the ninth inverter in the last stage serves as the fourth node.
  • another aspect of the present disclosure provides a storage system, including: a power supply network, the power supply network having the first voltage domain, the second voltage domain and the third voltage domain; the monitoring circuit provided by any of the above embodiments.
  • the first detection signal is used to indicate whether the first voltage provided by the first voltage domain meets the requirements. If the first voltage is greater than or equal to the first preset value, the first detection signal The signal meets the requirements.
  • the second detection signal is used to indicate whether the second voltage provided by the second voltage domain meets the requirements. If the second voltage is greater than or equal to the second preset value, the second detection signal meets the requirements.
  • the third detection signal is used to indicate whether the third voltage provided by the third voltage domain meets the requirements. If the third voltage is greater than or equal to the third preset value, the third detection signal meets the requirements. Under the condition that the first detection signal, the second detection signal and the third detection signal all meet the requirements, a monitoring signal of a valid state is generated. By monitoring whether the signal is in a valid state, it can be known whether the first voltage, the second voltage and the third voltage respectively provided by the first voltage domain, the second voltage domain and the third voltage domain meet the requirements.
  • Figure 1 is a functional block diagram of a monitoring circuit provided by an embodiment of the present disclosure
  • FIG. 2 is another functional block diagram of a monitoring circuit provided by an embodiment of the present disclosure
  • FIG. 3 is another functional block diagram of a monitoring circuit provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic circuit structure diagram of a monitoring circuit provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic circuit structure diagram of the first detection circuit in the monitoring circuit provided by an embodiment of the present disclosure
  • Figure 6 is a signal waveform diagram of the first voltage, the first voltage dividing node and the output end of the first detection circuit in Figure 5;
  • FIG. 7 to 9 are three different schematic diagrams of voltage waveforms and monitoring signals in the first voltage domain, the second voltage domain, and the third voltage domain in embodiments of the present disclosure.
  • Figure 10 is a functional block diagram of the storage system provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic circuit structure diagram of a trigger circuit in a storage system provided by an embodiment of the present disclosure
  • Figure 12 is a timing diagram of oscillation signals, monitoring signals and trigger signals in the storage system provided by an embodiment of the present disclosure.
  • Figure 1 is a functional block diagram of a monitoring circuit provided by an embodiment of the present disclosure.
  • the monitoring circuit includes: a voltage detection module 101, which outputs a first detection signal, a second detection signal, and a third detection signal through a first node na, a second node nb, and a third node nc respectively.
  • the logic circuit module 102 is connected to the first node na, the second node nb and the third node nc, and outputs the monitoring signal PorN_D through the fourth node no, and is configured to determine the Whether a detection signal has a first preset level, whether a second detection signal has a second preset level and whether a third detection signal has a third preset level, if so, then the monitoring signal PorN_D is in a valid
  • the monitoring circuit can be used in a storage system to monitor whether the first voltage domain Vdd1, the second voltage domain Vdd2H and the third voltage domain Vdd2L that supply power to the storage array of the storage system meet the power supply requirements of the storage array.
  • the first detection signal is used to indicate whether the first voltage provided by the first voltage domain Vdd1 meets the requirements. If the first voltage is greater than or equal to the first preset value, the first detection signal meets the requirements.
  • the second detection signal is used to indicate whether the second voltage provided by the second voltage domain Vdd2H meets the requirements. If the second voltage is greater than or equal to the second preset value, the second detection signal meets the requirements.
  • the third detection signal is used to indicate whether the third voltage provided by the third voltage domain Vdd2L meets the requirements. If the third voltage is greater than or equal to the third preset value, the third detection signal meets the requirements. Under the condition that the first detection signal, the second detection signal and the third detection signal all meet the requirements, the monitoring signal PorN_D of the valid state is generated.
  • the monitoring signal PorN_D by obtaining whether the monitoring signal PorN_D is in a valid state or an invalid state, it can be known whether the voltages provided by each of the first voltage domain Vdd1, the second voltage domain Vdd2H and the third voltage domain Vdd2L meet the requirements, so as to facilitate the adoption
  • the first voltage domain Vdd1, the second voltage domain Vdd2H and the third voltage domain Vdd2L that meet the requirements supply power to the storage array in the storage system, thereby ensuring that the storage array performs correct read and write operations.
  • first preset value the relationship between the first preset value, the second preset value and the third preset value can be determined according to the actual values of the first voltage domain Vdd1, the second voltage domain Vdd2H and the third voltage domain Vdd2L.
  • Reasonable settings are required. details as follows:
  • Vdd1>Vdd2H>Vdd2L this is a normal power-on state (that is, the first voltage domain, the second voltage domain, and the third voltage domain all meet the requirements);
  • Vdd2H>Vdd1 this is an abnormal power-on state ( That is, the first voltage domain and the second voltage domain do not meet the requirements);
  • Vdd2L>Vdd2H this is an abnormal power-on state (that is, the second voltage domain and the third voltage domain do not meet the requirements).
  • the first preset value is greater than the second preset value
  • the second preset value is greater than the third preset value.
  • Vdd2H>Vdd2L>Vdd1 this is the normal power-on state
  • Vdd2L>Vdd2H this is the abnormal power-on state
  • Vdd1>Vdd2H this is the abnormal power-on state
  • the second preset value is greater than the third preset value
  • the third preset value is greater than the first preset value
  • Vdd2H>Vdd1>Vdd2L this is a normal power-on state (that is, the first voltage domain, the second voltage domain, and the third voltage domain all meet the requirements);
  • Vdd2L>Vdd2H this is an abnormal power-on state.
  • Vdd1>Vdd2H this is an abnormal power-on state.
  • the second preset value is greater than the first preset value, and the first preset value is greater than the third preset value.
  • Vdd1 actually refers to the voltage value of the first voltage
  • Vdd2H actually refers to the voltage value of the second voltage
  • Vdd2L actually refers to the voltage value of the third voltage.
  • Vdd1>Vdd2H>Vdd2L is a common power requirement for LPDDR5 DRAM storage systems.
  • Figure 2 is another functional block diagram of a monitoring circuit provided by an embodiment of the present disclosure.
  • the voltage detection module 101 may have a first output element 11 that directly outputs a first detection signal to the logic circuit module 102 and a second output that directly outputs a second detection signal to the logic circuit module 102 .
  • the element 12 has a third output element 13 that directly outputs a third detection signal to the logic circuit module 102; the first output element 11, the second output element 12 and the third output element 13 all work in the second voltage domain Vdd2H; the logic circuit
  • the module 102 includes a logic operation element 14 directly connected to the first node na, the second node nb and the third node nc, and the logic operation element 14 works in the second voltage domain Vdd2H; the first preset value is greater than the second preset value ; The second preset value is greater than the third preset value.
  • the output terminal of the first output element 11 is the first node na
  • the output terminal of the second output element 12 is the second node nb
  • the output terminal of the third output element 13 is the third node nc
  • the logic operation element 14 and The first output element 11 , the second output element 12 and the third output element 13 are directly connected, and all four of them operate in the second voltage domain Vdd2H.
  • the first output element 11 , the second output element 12 and the third output element 13 are all directly connected to the voltage domain in the illustration, it does not mean that the output elements directly output the input voltage of the voltage domain directly.
  • Figure 3 is another functional block diagram of a monitoring circuit provided by an embodiment of the present disclosure.
  • the voltage detection module 101 may include: a first detection unit 111, the output end is the first node na, and is The second detection unit 121 is configured to detect whether the first voltage is greater than or equal to the first preset value; the second detection unit 121, whose output terminal is the second node nb, is configured to detect whether the second voltage is greater than or equal to the second preset value; The third detection unit 131, whose output terminal is the third node nc, is configured to detect whether the third voltage is greater than or equal to the third preset value.
  • the first detection unit 111 If the first voltage is greater than or equal to the first preset value, the first detection unit 111 outputs a first detection signal with the first preset level, defining that the first detection signal with the first preset level is valid; if If a voltage is less than the first preset value, the first detection unit 111 outputs an invalid first detection signal, that is, the level of the first detection signal is not the first preset level at this time.
  • the first detection unit 111 may have a first output element whose output terminal is the first node. That is to say, the first detection unit 111 includes a first output element directly connected to the logic circuit module 102, and the first output element Work in the second voltage domain Vdd2H.
  • the second detection unit 121 If the second voltage is greater than or equal to the second preset value, the second detection unit 121 outputs a second detection signal with the second preset level, defining that the second detection signal with the second preset level is valid; if If the second voltage is less than the second preset value, the second detection unit 121 outputs an invalid second detection signal, that is, the level of the second detection signal is not the second preset level at this time.
  • the second detection unit 121 may have a second output element whose output terminal is the second node. That is to say, the second detection unit 121 includes a second output element directly connected to the logic circuit module 102, and the second output element Work in the second voltage domain Vdd2H.
  • the third detection unit 131 If the third voltage is greater than or equal to the third preset value, the third detection unit 131 outputs a third detection signal with the third preset level, defining that the third detection signal with the third preset level is valid; if If the third voltage is less than the third preset value, the third detection unit 131 outputs an invalid third detection signal, that is, the level of the third detection signal is not the third preset level at this time.
  • the third detection unit 131 may have a third output element whose output terminal is the third node. That is to say, the third detection unit 131 includes a third output element directly connected to the logic circuit module 102, and the third output element Work in the second voltage domain Vdd2H.
  • the first preset level, the second preset level and the third preset level may all be low levels, that is, a valid first detection signal, a valid second detection signal And the valid third detection signal is a low-level signal, which is a logic "0".
  • the first preset level, the second preset level and the third preset level may all be high levels, that is to say, the effective first detection signal, the effective second detection signal
  • the detection signal and the effective third detection signal are both high-level signals, which is logic "1". It can be understood that, according to the actual circuit design of the first detection unit, the second detection unit and the third detection unit, the first preset level, the second preset level and the third preset level may all be low voltage. One of flat or high level.
  • Figure 4 is a schematic circuit structure diagram of a monitoring circuit provided by an embodiment of the present disclosure.
  • the first detection unit 111 may include: a first detection circuit 21 for detecting whether the first voltage is greater than Or equal to the first preset value, if so, the first detection signal with the first preset level is output through the output terminal; the first inverter inv1 works in the first voltage domain Vdd1, and the first inverter inv1 The input terminal is connected to the output terminal of the first detection circuit 21; the second inverter inv2 works in the second voltage domain Vdd2H, the input terminal of the second inverter inv2 is connected to the output terminal of the first inverter inv1, and the second inverter inv2 operates in the second voltage domain Vdd2H.
  • the output end of phase device inv2 serves as the first node na.
  • the second inverter inv2 is the first output element.
  • FIG. 5 is a schematic circuit structure diagram of the first detection circuit in the monitoring circuit provided by the embodiment of the present disclosure.
  • the first detection circuit 21 includes: a first resistor R1 and a second resistor R2 connected in series.
  • the first resistor One end of R1 receives the first voltage, the other end of the first resistor R1 and one end of the second resistor R2 are connected to the first voltage dividing node Vdiv, the other end of the second resistor R2 is connected to ground;
  • the third resistor R3, one end of the third resistor R3 receives The first voltage, that is, one end of the third resistor R3 works in the first voltage domain Vdd1;
  • the gate of the first NMOS transistor MN1 is connected to the first voltage dividing node Vdiv, and the drain is connected to the other end of the third resistor R3.
  • the source is grounded.
  • FIG. 6 is a signal waveform diagram of the first voltage (Vin), the first voltage dividing node (Vdiv) and the output terminal (OUT) of the first detection circuit in FIG. 5 .
  • the first preset level is low level
  • the working principle of the first detection circuit 21 is as follows:
  • the first NMOS transistor MN1 is turned on.
  • the voltage of the output terminal of the first detection circuit 21 ie, the source of the first NMOS transistor MN1 will be quickly pulled down, causing the output terminal of the first detection circuit 21 to output low.
  • the level signal that is, the output terminal of the first detection circuit 21 outputs a first detection signal with a first preset level.
  • the first detection circuit 21 may further include: a first capacitor C, one end of the first capacitor C is connected to the first voltage dividing node Vdiv, and the other end is connected to ground.
  • the first capacitor C can denoise the first voltage dividing node Vdiv.
  • any one of the first resistor R1, the second resistor R2, and the third resistor R3 may be a single resistor, a plurality of resistors connected in series, or a plurality of resistors connected in parallel.
  • the resistance values of the first resistor R1 and the second resistor R2 can be reasonably selected according to the actual circuit requirements, that is, according to the first preset value, that is, the value of R2/(R1+R2) can be reasonably selected, so that It is ensured that the first NMOS transistor MN1 is turned on when the first voltage is greater than or equal to the first preset value.
  • the second detection unit 121 may include: a second detection circuit 22 for detecting whether the second voltage is greater than or equal to the second preset value, and if so, outputting the first voltage through the output terminal.
  • Two second detection signals of preset levels a third inverter inv3, working in the second voltage domain Vdd2H, the input terminal of the third inverter inv3 is connected to the output terminal of the second detection circuit 22;
  • a fourth inverter inv4 works in the second voltage domain Vdd2H, the input terminal of the fourth inverter inv4 is connected to the output terminal of the third inverter inv3, and the output terminal of the fourth inverter inv4 serves as the second node nb.
  • the fourth inverter inv4 is the second output element.
  • the second detection circuit 22 may include: a fifth resistor and a sixth resistor connected in series, one end of the fifth resistor receives the second voltage, the other end of the fifth resistor and one end of the sixth resistor are both connected to the second voltage dividing node, and the sixth resistor receives the second voltage.
  • the other end of the resistor is grounded; a seventh resistor, one end of the seventh resistor receives the first voltage; a third NMOS transistor, the gate of the third NMOS transistor is connected to the second voltage dividing node, and the drain is connected to the other end of the seventh resistor and serves as the third NMOS transistor.
  • the output terminal of the second detection circuit has its source connected to ground.
  • the second detection circuit 22 may also include: a second capacitor, one end of the second capacitor is connected to the second voltage dividing node, and the other end is connected to ground.
  • the second preset level is low level.
  • the second detection circuit 22 reference may be made to the foregoing detailed description of the first detection circuit 21, which will not be described again here.
  • the gate of the third NMOS transistor receives the second target voltage and is turned on.
  • the resistance values of the fifth resistor and the sixth resistor can be reasonably selected according to the second preset value to ensure that the third NMOS transistor is turned on when the second voltage is greater than or equal to the second preset value.
  • the first preset value is greater than the second preset value. If the channel width to length ratios of the first NMOS transistor and the third NMOS transistor are the same and the first target voltage is equal to the second target voltage, then R2/( The value of R1+R2) should be smaller than the value of R6/(R5+R6).
  • R5 is the resistance value of the fifth resistor
  • R6 is the resistance value of the sixth resistor.
  • the third detection unit 131 may include: a third detection circuit 23 for detecting whether the third voltage is greater than or equal to the third preset value, and if so, outputting the third voltage with the third preset value through the output terminal.
  • the third detection circuit 23 may include: a seventh resistor and an eighth resistor connected in series, one end of the seventh resistor receives the third voltage, the other end of the seventh resistor and one end of the eighth resistor are both connected to the third voltage dividing node, and the eighth resistor receives the third voltage.
  • the other end of the resistor is connected to the ground; the ninth resistor, one end of the ninth resistor receives the third voltage; the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the third voltage dividing node, the drain is connected to the other end of the ninth resistor and serves as the third voltage dividing node.
  • the source of the output terminal of the third detection circuit 23 is grounded.
  • the third detection circuit also includes: a third capacitor, one end of the third capacitor is connected to the third voltage dividing node, and the other end is connected to ground.
  • the third preset level is low level.
  • the third detection circuit 23 reference may be made to the foregoing detailed description of the first detection circuit 21, which will not be described again here.
  • the gate of the fourth NMOS transistor receives the third target voltage and is turned on.
  • the resistance values of the seventh resistor and the eighth resistor can be reasonably selected according to the third preset value to ensure that the fourth NMOS transistor is turned on when the third voltage is greater than or equal to the third preset value.
  • the second preset value is greater than the third preset value. If the channel width to length ratios of the third NMOS transistor and the fourth NMOS transistor are the same and the first target voltage is equal to the third target voltage, then R2/( The value of R1+R2) should be less than the value of R8/(R7+R8).
  • R7 is the resistance value of the seventh resistor
  • R8 is the resistance value of the eighth resistor.
  • the third output element 24 may include: a first level conversion unit 214, working in the second voltage domain Vdd2H, connected to the output end of the fifth inverter inv5, and outputting the third Detection signal; an even number of cascaded sixth inverters inv6, the sixth inverter inv6 works in the second voltage domain Vdd2H, the input end of the sixth inverter inv6 at the first stage receives the third detection signal, and at the end The output terminal of the sixth inverter inv6 of the stage serves as the third node nc.
  • the output terminal of the third detection circuit 23 outputs a third detection signal with a third preset level, and the third preset level is Low level; correspondingly, the output terminal of the fifth inverter inv5 outputs a high level; the first level conversion unit 214 is connected to the output terminal of the fifth inverter inv5, and performs level flipping on the high level, to re-output the third detection signal with the third preset level.
  • An even number of cascaded sixth inverters inv6 is beneficial to improving the transmission capability of the third detection signal for continued transmission.
  • the third detection signal output by the third detection circuit 23 is invalid, that is, the third detection signal is a high level signal; correspondingly, the output terminal of the fifth inverter inv5 outputs low level; the first level conversion unit 214 performs level flipping on the low level to output a high level signal, that is, the first level conversion unit 214 outputs an invalid third detection signal.
  • the third preset level may be a high level, and the working principles of the first level conversion unit 214, the fifth inverter inv5, and the sixth inverter inv6 will not be described again here.
  • the first level conversion unit 214 may include: a fourth resistor R4 and a second NMOS transistor MN2. One end of the fourth resistor R4 receives the second voltage, and the other end is connected to the drain of the second NMOS transistor MN2. As an output node that outputs the third detection signal, the source of the second NMOS transistor MN2 is connected to the ground, and the gate of the second NMOS transistor MN2 is connected to the output terminal of the fifth inverter inv5.
  • One end of the fourth resistor R4 works in the second voltage domain Vdd2H.
  • the logic circuit module 102 includes: a NOR circuit 112 connected to the first node na, the second node nb and the third node nc, and operates in the second voltage domain Vdd2H, and outputs a monitoring signal through the fifth node nd. PorN_D; wherein the first preset level, the second preset level and the third preset level are the same level; the driving circuit 122 provides monitoring of transmission from the fifth node nd to the fourth node no. Transmission path of signal PorN_D.
  • the fifth node nd is the output terminal of the NOR circuit 112 .
  • the first preset level, the second preset level and the third preset level are the same level, that is, the first detection signal with the first preset level and the second detection signal with the second preset level.
  • the signal and the third detection signal having the third preset level are both logic "1" or both are logic "0".
  • the first preset level, the second preset level and the third preset level are all low levels, that is to say, the first detection signal with the first preset level, the second preset level with the first detection signal with the second preset level
  • the second detection signal with the preset level and the third detection signal with the third preset level are both logic "0”.
  • the active state monitoring signal PorN_D is a high level signal, which is a logic "1”. When the monitoring signal PorN_D of the invalid state is a low level signal, it is a logic "0".
  • the first preset level, the second preset level and the third preset level may all be high levels, that is to say, the first detection signal having the first preset level , the second detection signal with the second preset level and the third detection signal with the third preset level are both logic "1".
  • the active state monitoring signal PorN_D is a low level signal, which is logic. "0”
  • the invalid status monitoring signal PorN_D is a high level signal, which is a logic "1".
  • the NOR circuit 112 may include: a NOR gate Nor, operating in the second voltage domain Vdd2H, and the three input terminals of the NOR gate Nor are connected to the first node na and the second node respectively. nb and the third node nc; an even number of cascaded seventh inverters inv7, the seventh inverter inv7 all work in the second voltage domain Vdd2H, and the input end of the seventh inverter inv7 in the first stage is connected or not
  • the output terminal of the gate Nor and the output terminal of the seventh inverter inv7 in the last stage serve as the fifth node nd.
  • the NOR gate Nor is a logic operation element directly connected to the first node na, the second node nb and the third node nc.
  • An even number of cascaded seventh inverters inv7 can improve the transmission capability of the monitoring signal PorN_D.
  • the specific circuit position where the monitoring signal PorN_D is actually used is usually relatively far from the fifth node nd of the NOR circuit 112.
  • the fourth node no can be directly connected to the output end of the specific circuit where the monitoring signal PorN_D is actually used. Connection, the driving circuit 122 can improve the transmission capability of the monitoring signal PorN_D from the fifth node nd to the fourth node no, which is beneficial to improving the transmission speed and transmission accuracy of the monitoring signal PorN_D.
  • the driving circuit 122 may include: a first driving circuit 120, operating in the first voltage domain Vdd1, providing a first transmission path for transmitting the monitoring signal PorN_D from the fifth node nd to the sixth node ne, which is located at the fourth node no. and the fifth node nd; the second driving circuit 220 operates in the second voltage domain Vdd2H and provides a second transmission path for transmitting the monitoring signal PorN_D from the sixth node ne to the fourth node.
  • the first driving circuit 120 is further away from the fourth node no than the second driving circuit 220. Therefore, the first driving circuit 120 adopts the first voltage domain Vdd1 with a relatively large voltage, and the second driving circuit 220 works in a relatively large voltage domain. Small second voltage domain Vdd2H. It can be understood that in other embodiments, the first driving circuit 120 and the second driving circuit 220 may both operate in the first voltage domain Vdd1 or both operate in the second voltage domain Vdd2H.
  • the first driving circuit 120 includes: a second level conversion unit 41, connected to the fifth node nd, and working in the first voltage domain Vdd1, receiving the monitoring signal PorN_D and outputting the monitoring inversion signal, and the monitoring inversion signal interacts with the monitoring signal PorN_D.
  • the eighth inverter inv8 works in the first voltage domain Vdd1
  • the input terminal of the eighth inverter inv8 receives and monitors the inverted signal
  • the output terminal of the eighth inverter inv8 serves as the sixth node ne.
  • the monitoring signal PorN_D is in a valid state, and the monitoring signal PorN_D in the valid state is a high-level signal; correspondingly, the output end of the seventh inverter inv7 (i.e., the last stage) in the last stage (i.e., the last stage) The fifth node nd) outputs a high level; the second level conversion unit 41 is connected to the output end of the seventh inverter inv7 in the last stage, and performs level flipping on the high level to output a low level signal; The low-level signal is transmitted to the eighth inverter inv8, and the output terminal of the eighth inverter inv8 (i.e., the sixth node ne) outputs a high-level signal.
  • the high-level signal is the high-level monitoring signal PorN_D. That is, the monitoring signal PorN_D of the effective state. If the monitoring signal PorN_D is in an invalid state, and the monitoring signal PorN_D in the invalid state is a low level signal; correspondingly, the output end of the seventh inverter inv7 in the last stage outputs a low level; the second level conversion unit 41 pairs The low level is level flipped to output a high level signal; the high level signal is transmitted to the eighth inverter inv8, and the output end of the eighth inverter inv8 outputs a low level signal. The low level signal That is, the monitoring signal PorN_D is invalid.
  • the monitoring signal PorN_D is in a valid state, and the monitoring signal PorN_D in the valid state can also be a low-level signal.
  • the monitoring signal PorN_D in the invalid state can also be a high-level signal.
  • the second level conversion unit 41 may include: a tenth resistor R10 and a fifth NMOS transistor MN5. One end of the tenth resistor R10 receives the first voltage, and the other end is connected to the drain of the fifth NMOS transistor MN5 and serves as the second level. At the output end of the conversion unit 41, the source of the fifth NMOS transistor MN5 is connected to the ground, and the gate of the fifth NMOS transistor MN5 is connected to the fifth node nd.
  • one end of the tenth resistor R10 works in the first voltage domain Vdd1.
  • the second driving circuit 220 may include: an even number of cascaded ninth inverters inv9 , the ninth inverters inv9 all work in the second voltage domain Vdd2H, and are in the first stage.
  • the input terminal of the ninth inverter inv9 is connected to the sixth node ne, and the output terminal of the ninth inverter in the last stage serves as the fourth node no.
  • even number mentioned in the embodiment of the present disclosure can be any even number such as 2, 4, 6, 8, 10, 14, etc.
  • odd number can be any odd number such as 1, 3, 5, 7, 9, etc. .
  • FIGS 7 to 9 are three different schematic diagrams of voltage waveforms and monitoring signals in the first voltage domain, the second voltage domain, and the third voltage domain. Take Vdd1>Vdd2H>Vdd2L as normal power-on, and the monitoring signal PorN_D of the effective state is a high-level signal as an example:
  • the monitoring signal PorN_D is a high-level signal; during the abnormal power-on period, the monitoring signal PorN_D is a low-level signal. No matter how the voltages provided by the first voltage domain Vdd1, the second voltage domain Vdd2H and the third voltage domain Vdd2L change, the monitoring signal PorN_D outputted during the period satisfying Vdd1>Vdd2H>Vdd2L is valid.
  • the monitoring circuit provided by the embodiment of the present disclosure can learn whether the voltages provided by the first voltage domain Vdd1, the second voltage domain Vdd2H and the third voltage domain Vdd2L respectively meet the requirements by obtaining whether the monitoring signal PorN_D is in a valid state.
  • FIG. 10 is a functional block diagram of a storage system provided by an embodiment of the disclosure
  • FIG. 11 is a schematic circuit structure diagram of a trigger circuit in the storage system provided by an embodiment of the disclosure.
  • the storage system provided by the embodiment of the present disclosure includes: a power supply network 300 having a first voltage domain Vdd1, a second voltage domain Vdd2H and a third voltage domain Vdd2L; and the monitoring circuit 301 provided by the above embodiment.
  • the storage system may be a DRAM storage system, such as a DDR5 DRAM storage system or a DDR4 DRAM storage system. In other embodiments, the storage system may also be an SRAM storage system, an SDRAM storage system, a ROM storage system or a flash memory storage system.
  • the storage system may further include: a trigger circuit 302 configured to generate at least one trigger signal in response to the monitoring signal PorN_D having a valid state.
  • the trigger circuit 302 and the monitoring circuit 300 can be integrated in a POR (Power on Reset) module, and the POR module outputs the monitoring signal PorN_D and the trigger signal.
  • POR Power on Reset
  • the trigger circuit 302 may generate multiple trigger signals with different time intervals between the level changing edges of the monitoring signal PorN_D. Among them, if the effective state of the monitoring signal PorN_D is high level, the level changing edge is the rising edge of the level; if the effective state of the monitoring signal PorN_D is low level, the level changing edge is the falling edge.
  • the trigger circuit 302 may include: an oscillator 312 that oscillates in response to the monitoring signal PorN_D with a valid state and outputs the oscillation signal OSC; a counter 322 configured to count the number of times of the oscillation signal OSC to obtain a count value , and outputs the count value B ⁇ n:0>; the logic decoding circuit 332 is configured to generate a trigger signal according to the count value B ⁇ n:0>.
  • the oscillator 312 may be an RC delay based Ring oscillator, including: a NAND gate AN, one input end of the NAND gate AN receives a power-on signal; at least two cascaded resistors R and at least two Inverter inv, the resistor R in the first stage is connected to the output end of NAND gate AN, the resistor in the last stage is connected to the other end of NAND gate AN through an inverter inv, and the two resistors R in adjacent stages Connected via an inverter inv; at least two capacitors C1, one end of the capacitor C1 is connected to the connection node between the resistor R and the input end of the inverter inv, and the other end is connected to ground. It should be noted that FIG.
  • the oscillator 312 may include N resistors R, N inverters inv and N A capacitor C1, N can be any even number greater than or equal to 2, such as 4, 6, 8, etc.
  • the oscillator 312 may also be an LC oscillator or a quartz crystal oscillator.
  • the counter 322 obtains the number of oscillation cycles of the oscillator 312 by counting the number of oscillations. It can be understood that the count value B ⁇ n:0> represents the number of cycles of the oscillation cycle.
  • the count value B ⁇ n:0> serves as an enable signal that enables the logic decoding circuit 332 to generate a trigger signal.
  • the logic decoding circuit 332 When the count value B ⁇ n:0> reaches a preset value, the logic decoding circuit 332 generates a trigger signal.
  • the trigger signal can be high. level signal.
  • the count value B ⁇ n:0> represents the number of oscillation cycles, and the duration of a single oscillation cycle of the oscillator 312 can be known, and the corresponding count value B ⁇ n:0> can also represent the oscillation duration,
  • the preset value also represents the preset duration. When the count value B ⁇ n:0> reaches the preset value, it indicates that the oscillation duration meets the preset duration, and the logic decoding circuit 332 generates a trigger signal.
  • Counter 322 may be a flip-flop based counting circuit.
  • the counter 322 may be an 8-bit counter, and n in the corresponding count value B ⁇ n:0> is 7. It can be understood that the number of bits of the counter 322 can be determined according to actual needs.
  • the counter 322 has a maximum count value, and the maximum count value represents the maximum oscillation duration, as long as the maximum oscillation duration represented by the maximum count value of the counter 322 is less than or equal to the predetermined value. Just set the default duration of the representation.
  • the counter 322 may be a 4-bit counter, a 16-bit counter, a 32-bit counter, etc.
  • the logic decoding circuit 332 may also be configured to generate a plurality of trigger signals with different delays compared to the level change edges of the monitoring signal PorN_D, wherein the logic decoding circuit 332 generates the first reset signal CntRst after generating a trigger signal. , and the counter 322 resets the count value B ⁇ n:0> to zero in response to the first reset signal CntRst, and after the count value B ⁇ n:0> returns to zero, the counter 322 restarts counting, and when the count value B ⁇ n: :0>The next trigger signal is generated when the preset value is reached, and the first reset signal CntRst is generated accordingly. This cycle continues until a preset number of trigger signals are generated. In addition, after all trigger signals are generated, the logic decoding circuit 332 may also generate a second reset signal, and the oscillator 312 stops oscillating in response to the second reset signal.
  • the delays between trigger signals generated sequentially in time may be the same or different, that is, the preset values corresponding to different trigger signals may be the same or different.
  • Figure 12 is a timing diagram of oscillation signals, monitoring signals and trigger signals in a storage system provided by an embodiment of the present disclosure.
  • the logic decoding circuit 332 generates four trigger signals as an example, respectively. a trigger signal PorN_A1, a second trigger signal PorN_A2, a third trigger signal PorN_A3 and a fourth trigger signal PorN_A4, and monitoring signal PorN_D, the first trigger signal PorN_A1, the second trigger signal PorN_A2, the third trigger signal PorN_A3 and the fourth trigger signal There is a time delay between PorN_A4 respectively.
  • the logic decoding circuit 332 may also be configured to generate a second reset signal after all trigger signals are generated, and the oscillator 312 stops oscillating in response to the second reset signal. In conjunction with Figures 11 and 12, After the fourth trigger signal PorN_A4 is generated, the oscillator 312 stops oscillating. Logic decoding circuit 332 may also be configured to latch all trigger signals after all trigger signals are generated.
  • the trigger circuit 302 may also be configured to reset the trigger signal to a low level if the monitoring signal PorN_D changes from a valid state to an invalid state.
  • Figures 7 to 9 also illustrate the timing diagrams of each trigger signal.
  • an effective monitoring signal PorN_D is generated, and multiple trigger signals with different delays are also generated, that is, the first trigger signal PorN_A1, the second trigger signal PorN_A2, and the third trigger signal PorN_A2 are generated.
  • the storage system may also include: an analog circuit module 303; a digital circuit module 304; and a storage array 305.
  • Storage array 305 is used for read and write operations.
  • the analog circuit module 303 responds to the trigger signal and generates a first control signal
  • the digital circuit module 304 responds to the monitoring signal PorN_D and generates a second control signal
  • both the first control signal and the second control signal are transmitted to the storage array 305 .
  • the monitoring signal PorN_D can also be transmitted to the storage array 305 .
  • the analog circuit module 303 may receive the first trigger signal PorN_A1, the second trigger signal PorN_A2, the third trigger signal PorN_A3 and the fourth trigger signal PorN_A4, and use them as enable signals to enable different circuit modules in the analog circuit module 303 respectively.
  • the analog circuit module 303 can work in the first voltage domain Vdd1 and the second voltage domain Vdd2H
  • the digital circuit module 304 can work in the second voltage domain Vdd2H and the third voltage domain Vdd2L.
  • the storage system provided by the embodiment of the present disclosure can monitor whether the voltages provided by the first voltage domain Vdd1, the second voltage domain Vdd2H and the third voltage domain Vdd2L respectively meet the requirements, and perform read and write operations under normal power-on conditions.

Abstract

本公开实施例提供一种监测电路以及存储系统，监测电路包括：电压检测模块，被配置为，检测第一电压域提供的第一电压是否大于或等于第一预设值，若是，则第一检测信号具有第一预设电平；检测第二电压域提供的第二电压是否大于或等于第二预设值，若是，则第二检测信号具有第二预设电平；检测第三电压域提供的第三电压是否大于或等于第三预设值，若是，则第三检测信号具有第三预设电平；逻辑电路模块，通过第四节点输出监测信号，被配置为，判断第一检测信号是否具有第一预设电平、第二检测信号是否具有第二预设电平且第三检测信号是否具有第三预设电平，若是，则监测信号为有效状态。本公开实施例至少有利于监测是否正常上电。

Description

监测电路以及存储系统
交叉引用
本公开要求于2022年08月19日递交的名称为“监测电路以及存储系统”、申请号为202211000055.3的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开实施例涉及半导体技术领域，特别涉及一种监测电路以及存储系统。
背景技术
用于存储数据的存储系统可被分为易失性存储器装置和非易失性存储器装置。诸如动态随机存取存储器(DRAM)装置的易失性存储器装置通过为存储器单元中的电容器充电或放电来存储数据，并且当断电时丢失存储的数据。诸如闪速存储器装置的非易失性存储器装置即使当断电时也保持存储的数据。易失性存储器装置广泛用作各种设备的主存储器，而非易失性存储器装置广泛用于在例如计算机、移动装置等的各种电子装置中存储程序代码和/或数据。
存储系统通常工作在多个电压域(domain)，不同电压域提供的电压各不相同。当不同电压域提供的电压均符合需求时，存储系统处于正常上电状态，在此期间进行的读写操作准确性高；当不同电压域提供的电压不符合需求时，存储系统处于非正常上电状态，会影响存储系统进行正常的读写。因此，监测各电压域提供的电压是否符合需求，对于改善存储系统的读写性能非常重要。
发明内容
本公开实施例提供一种监测电路以及存储系统，至少有利于监测第一电压域、第二电压域以及第三电压域是否为正常上电。
根据本公开一些实施例，本公开实施例一方面提供一种监测电路，包括：电压检测模块，通过第一节点、第二节点和第三节点分别输出第一检测信号、第二检测信号和第三检测信号，被配置为，检测第一电压域提供的第一电压是否大于或等于第一预设值，若是，则所述第一检测信号具有第一预设电平；检测第二电压域提供的第二电压是否大于或等于第二预 设值，若是，则所述第二检测信号具有第二预设电平；检测第三电压域提供的第三电压是否大于或等于第三预设值，若是，则所述第三检测信号具有第三预设电平；逻辑电路模块，连接所述第一节点、所述第二节点以及所述第三节点，通过第四节点输出监测信号，被配置为，判断所述第一检测信号是否具有所述第一预设电平、所述第二检测信号是否具有所述第二预设电平且所述第三检测信号是否具有所述第三预设电平，若是，则所述监测信号为有效状态，若否，则所述监测信号为无效状态。
在一些实施例中，所述电压检测模块具有直接向所述逻辑电路模块输出所述第一检测信号的第一输出元件，具有直接向所述逻辑电路模块输出所述第二检测信号的第二输出元件，具有直接向所述逻辑电路模块输出所述第三检测信号的第三输出元件；所述第一输出元件、所述第二输出元件以及所述第三输出元件均工作在所述第二电压域；所述逻辑电路模块包括直接与所述第一节点、所述第二节点以及所述第三节点连接的逻辑运算元件，且所述逻辑运算元件工作在所述第二电压域；所述第一预设值大于所述第二预设值；所述第二预设值大于所述第三预设值。
在一些实施例中，所述电压检测模块包括：第一检测单元，输出端为所述第一节点，被配置为，检测所述第一电压是否大于或等于所述第一预设值；第二检测单元，输出端为所述第二节点，被配置为，检测所述第二电压是否大于或等于所述第二预设值；第三检测单元，输出端为所述第三节点，被配置为，检测所述第三电压是否大于或等于所述第三预设值。
在一些实施例中，所述第一检测单元包括：第一检测电路，用于检测所述第一电压是否大于或等于所述第一预设值，若是，则通过输出端输出具有所述第一预设电平的所述第一检测信号；第一反相器，工作在所述第一电压域，所述第一反相器的输入端连接所述第一检测电路的输出端；第二反相器，工作在所述第二电压域，所述第二反相器的输入端连接所述第一反相器的输出端，所述第二反相器的输出端作为所述第一节点。
在一些实施例中，所述第一检测电路包括：相串联的第一电阻和第二电阻，所述第一电阻一端接收所述第一电压，所述第一电阻的另一端以及所述第二电阻的一端均连接第一分压节点，所述第二电阻的另一端接地；第三电阻，所述第三电阻一端接收所述第一电压；第一NMOS管，所述第一NMOS管的栅极连接所述第一分压节点，漏极连接所述第三电阻的另一端并作为所述第一检测电路的输出端，源极接地。
在一些实施例中，所述第一检测电路还包括：第一电容，所述第一电容一端连接所述第一分压节点，另一端接地。
在一些实施例中，所述第二检测单元包括：第二检测电路，用于检测所述第二电压是否大于或等于所述第二预设值，若是，则通过输出端输出具有所述第二预设电平的所述第二检测信号；第三反相器，工作在所述第二电压域，所述第三反相器的输入端连接所述第二检 测电路的输出端；第四反相器，工作在所述第二电压域，所述第四反相器的输入端连接所述第三反相器的输出端，所述第四反相器的输出端作为所述第二节点。
在一些实施例中，所述第三检测单元包括：第三检测电路，用于检测所述第三电压是否大于或等于所述第三预设值，若是，则通过输出端输出具有所述第三预设电平的所述第三检测信号；第五反相器，工作在所述第三电压域，所述第五反相器的输入端连接所述第三检测电路的输出端；第三输出元件，工作在所述第二电压域，所述第三输出元件的输入端与所述第五反相器的输出端连接，所述第三输出元件的输出端作为所述第三节点。
在一些实施例中，所述第三输出元件包括：第一电平转换单元，工作在第二电压域，连接所述第五反相器的输出端，并输出所述第三检测信号；偶数个级联的第六反相器，所述第六反相器工作在所述第二电压域，处于首级的所述第六反相器的输入端接收所述第三检测信号，处于尾级的所述第六反相器的输出端作为所述第三节点。
在一些实施例中，所述第一电平转换单元包括：第四电阻以及第二NMOS管，所述第四电阻的一端接收所述第二电压，另一端与所述第二NMOS管的漏极连接且作为输出所述第三检测信号的输出节点，所述第二NMOS管的源极接地，所述第二NMOS管的栅极连接所述第五反相器的输出端。
在一些实施例中，所述逻辑电路模块包括：或非电路，连接所述第一节点、所述第二节点以及所述第三节点，且工作在所述第二电压域，并通过第五节点输出所述监测信号；其中，所述第一预设电平、所述第二预设电平以及所述第三预设电平为同一电平；驱动电路，所述驱动电路提供在由所述第五节点向所述第四节点传输所述监测信号的传输路径。
在一些实施例中，所述驱动电路包括：第一驱动电路，工作在所述第一电压域，提供由所述第五节点向第六节点传输所述监测信号的第一传输路径，所述第六节点位于所述第四节点与所述第五节点之间；第二驱动电路，工作在所述第二电压域，提供由所述第六节点向所述第四节点传输所述监测信号的第二传输路径。
在一些实施例中，所述第一驱动电路包括：第二电平转换单元，连接所述第五节点，且工作在所述第一电压域，接收所述监测信号并输出监测反相信号，所述监测反相信号与所述监测信号互为反相信号；第八反相器，工作在所述第一电压域，所述第八反相器的输入端接收所述监测反相信号，所述第八反相器的输出端作为所述第六节点。
在一些实施例中，所述第二驱动电路包括：偶数个级联的第九反相器，所述第九反相器均工作在所述第二电压域，处于首级的所述第九反相器的输入端连接所述第六节点，处于尾级的所述第九反相器的输出端作为所述第四节点。
根据本公开另一些实施例，本公开实施例另一方面提供一种存储系统，包括：电源网 络，所述电源网络具有所述第一电压域、所述第二电压域以及所述第三电压域；上述任意实施例提供的监测电路。
本公开实施例提供的技术方案至少具有以下优点：
本公开实施例提供的监测电路的技术方案中，第一检测信号用于表示第一电压域提供的第一电压是否符合需求，若第一电压大于或等于第一预设值，则第一检测信号符合需求。第二检测信号用于表示第二电压域提供的第二电压是否符合需求，若第二电压大于或等于第二预设值，则第二检测信号符合需求。第三检测信号用于表示第三电压域提供的第三电压是否符合需求，若第三电压大于或等于第三预设值，则第三检测信号符合需求。在第一检测信号、第二检测信号以及第三检测信号均符合需求的条件下，生成有效状态的监测信号。通过监测信号是否为有效状态，可以获知第一电压域、第二电压域以及第三电压域分别提供的第一电压、第二电压和第三电压是否符合需求。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的监测电路的一种功能框图；
图2为本公开实施例提供的监测电路的另一种功能框图；
图3为本公开实施例提供的监测电路的又一种功能框图；
图4为本公开实施例提供的监测电路的一种电路结构示意图；
图5为本公开实施例提供的监测电路中第一检测电路的一种电路结构示意图；
图6为图5中第一电压、第一分压节点以及第一检测电路的输出端的信号波形图；
图7至图9为本公开实施例中第一电压域、第二电压域、第三电压域的电压波形图与监测信号的三种不同示意图；
图10为本公开实施例提供的存储系统的一种功能框图；
图11为本公开实施例提供的存储系统中触发电路的一种电路结构示意图；
图12为本公开实施例提供的存储系统中振荡信号、监测信号以及触发信号的时序图。
具体实施方式
图1为本公开实施例提供的监测电路的一种功能框图。
参考图1，本公开实施例提供的监测电路包括：电压检测模块101，通过第一节点na、第二节点nb和第三节点nc分别输出第一检测信号、第二检测信号和第三检测信号，被配置为，检测第一电压域Vdd1提供的第一电压是否大于或等于第一预设值，若是，则第一检测信号具有第一预设电平；检测第二电压域Vdd2H提供的第二电压是否大于或等于第二预设值，若是，则第二检测信号具有第二预设电平；检测第三电压域Vdd2L提供的第三电压是否大于或等于第三预设值，若是，则第三检测信号具有第三预设电平；逻辑电路模块102，连接第一节点na、第二节点nb以及第三节点nc，通过第四节点no输出监测信号PorN_D，被配置为，判断第一检测信号是否具有第一预设电平、第二检测信号是否具有第二预设电平且第三检测信号是否具有第三预设电平，若是，则监测信号PorN_D为有效状态，若否，则监测信号PorN_D为无效状态。
监测电路可应用于存储系统中，用于监测向存储系统的存储阵列供电的第一电压域Vdd1、第二电压域Vdd2H和第三电压域Vdd2L是否满足存储阵列的供电需求。本公开实施例中，通过监测信号PorN_D是否为有效状态，可以获知第一电压域Vdd1、第二电压域Vdd2H以及第三电压域Vdd2L分别提供的第一电压、第二电压和第三电压是否符合需求。第一检测信号用于表示第一电压域Vdd1提供的第一电压是否符合需求，若第一电压大于或等于第一预设值，则第一检测信号符合需求。第二检测信号用于表示第二电压域Vdd2H提供的第二电压是否符合需求，若第二电压大于或等于第二预设值，则第二检测信号符合需求。第三检测信号用于表示第三电压域Vdd2L提供的第三电压是否符合需求，若第三电压大于或等于第三预设值，则第三检测信号符合需求。在第一检测信号、第二检测信号以及第三检测信号均符合需求的条件下，生成有效状态的监测信号PorN_D。因此，本公开实施例中通过获取监测信号PorN_D是有效状态还是无效状态，便可获知第一电压域Vdd1、第二电压域Vdd2H以及第三电压域Vdd2L各自提供的电压是否符合需求，以便于采用符合需求的第一电压域Vdd1、第二电压域Vdd2H以及第三电压域Vdd2L向存储系统中的存储阵列供电，进而保证存储阵列进行正确的读写操作。
可以理解的是，第一预设值、第二预设值以及第三预设值之间的大小关系，可以根据实际对第一电压域Vdd1、第二电压域Vdd2H以及第三电压域Vdd2L的需求进行合理设置。具体如下：
在一个例子中，Vdd1＞Vdd2H＞Vdd2L，此为正常上电状态(即第一电压域、第二电 压域以及第三电压域均符合需求)；Vdd2H＞Vdd1，此为非正常上电状态(即第一电压域和第二电压域不符合需求)；Vdd2L＞Vdd2H，此为非正常上电状态(即第二电压域和第三电压域不符合要求)。相应的，第一预设值大于第二预设值，第二预设值大于第三预设值。
在另一个例子中，Vdd2H＞Vdd2L＞Vdd1，此为正常上电状态；Vdd2L＞Vdd2H，此为非正常上电状态；Vdd1＞Vdd2H，此为非正常上电状态。相应的，第二预设值大于第三预设值，第三预设值大于第一预设值。
在又一个例子中，Vdd2H＞Vdd1＞Vdd2L，此为正常上电状态(即第一电压域、第二电压域以及第三电压域均符合需求)；Vdd2L＞Vdd2H，此为非正常上电状态；Vdd1＞Vdd2H，此为非正常上电状态。相应的，第二预设值大于第一预设值，第一预设值大于第三预设值。
可以理解的是，上述关系式中，Vdd1实际指第一电压的电压值，Vdd2H实际指第二电压的电压值，Vdd2L实际指第三电压的电压值。在一些实施例中，Vdd1＞Vdd2H＞Vdd2L，为LPDDR5 DRAM存储系统常用的一种电源需求。
图2为本公开实施例提供的监测电路的另一种功能框图。参考图2，在一些实施例中，电压检测模块101可以具有直接向逻辑电路模块102输出第一检测信号的第一输出元件11，具有直接向逻辑电路模块102输出第二检测信号的第二输出元件12，具有直接向逻辑电路模块102输出第三检测信号的第三输出元件13；第一输出元件11、第二输出元件12以及第三输出元件13均工作在第二电压域Vdd2H；逻辑电路模块102包括直接与第一节点na、第二节点nb以及第三节点nc连接的逻辑运算元件14，且逻辑运算元件14工作在第二电压域Vdd2H；第一预设值大于第二预设值；第二预设值大于第三预设值。
第一输出元件11的输出端即为第一节点na，第二输出元件12的输出端即为第二节点nb，第三输出元件13的输出端即为第三节点nc；逻辑运算元件14与第一输出元件11、第二输出元件12以及第三输出元件13直接连接，且四者均工作在第二电压域Vdd2H。需要说明的是，虽然第一输出元件11、第二输出元件12以及第三输出元件13在图示中均与电压域直接连接，但并不表示输出元件直接将电压域的输入电压直接输出，输出元件与相应待检测的电压域(或者说输入电压)之间还有其他检测单元，或者说输出元件属于对应的检测单元的一部分，只不过在此进行了省略。
图3为本公开实施例提供的监测电路的又一种功能框图，参考图3，在一些实施例中，电压检测模块101可以包括：第一检测单元111，输出端为第一节点na，被配置为，检测第一电压是否大于或等于第一预设值；第二检测单元121，输出端为第二节点nb，被配置为，检测第二电压是否大于或等于第二预设值；第三检测单元131，输出端为第三节点nc，被配置为，检测第三电压是否大于或等于第三预设值。
若第一电压大于或等于第一预设值，则第一检测单元111输出具有第一预设电平的第 一检测信号，定义具有第一预设电平的第一检测信号有效；若第一电压小于第一预设值，则第一检测单元111输出无效的第一检测信号，即此时第一检测信号的电平并非为第一预设电平。其中，第一检测单元111可以具有输出端为第一节点的第一输出元件，也就是说，第一检测单元111中包括与逻辑电路模块102直接连接的第一输出元件，且第一输出元件工作在第二电压域Vdd2H。
若第二电压大于或等于第二预设值，则第二检测单元121输出具有第二预设电平的第二检测信号，定义具有第二预设电平的第二检测信号有效；若第二电压小于第二预设值，则第二检测单元121输出无效的第二检测信号，即此时第二检测信号的电平并非为第二预设电平。其中，第二检测单元121可以具有输出端为第二节点的第二输出元件，也就是说，第二检测单元121中包括与逻辑电路模块102直接连接的第二输出元件，且第二输出元件工作在第二电压域Vdd2H。
若第三电压大于或等于第三预设值，则第三检测单元131输出具有第三预设电平的第三检测信号，定义具有第三预设电平的第三检测信号有效；若第三电压小于第三预设值，则第三检测单元131输出无效的第三检测信号，即此时第三检测信号的电平并非为第三预设电平。其中，第三检测单元131可以具有输出端为第三节点的第三输出元件，也就是说，第三检测单元131中包括与逻辑电路模块102直接连接的第三输出元件，且第三输出元件工作在第二电压域Vdd2H。
在一些实施例中，第一预设电平、第二预设电平以及第三预设电平可以均为低电平，也就说，有效的第一检测信号、有效的第二检测信号以及有效的第三检测信号均为低电平信号即为逻辑“0”。在另一些实施例中，第一预设电平、第二预设电平以及第三预设电平也可以均为高电平，也就是说，有效的第一检测信号、有效的第二检测信号以及有效的第三检测信号均为高电平信号即为逻辑“1”。可以理解的是，根据第一检测单元、第二检测单元以及第三检测单元的实际电路设计，第一预设电平、第二预设电平以及第三预设电平可以均为低电平或者高电平中的一者。
图4为本公开实施例提供的监测电路的一种电路结构示意图，参考图4，在一些实施例中，第一检测单元111可以包括：第一检测电路21，用于检测第一电压是否大于或等于第一预设值，若是，则通过输出端输出具有第一预设电平的第一检测信号；第一反相器inv1，工作在第一电压域Vdd1，第一反相器inv1的输入端连接第一检测电路21的输出端；第二反相器inv2，工作在第二电压域Vdd2H，第二反相器inv2的输入端连接第一反相器inv1的输出端，第二反相器inv2的输出端作为第一节点na。
可以理解的是，第二反相器inv2即为第一输出元件。
图5为本公开实施例提供的监测电路中第一检测电路的一种电路结构示意图，参考图 5，第一检测电路21包括：相串联的第一电阻R1和第二电阻R2，第一电阻R1一端接收第一电压，第一电阻R1的另一端以及第二电阻R2的一端均连接第一分压节点Vdiv，第二电阻R2的另一端接地；第三电阻R3，第三电阻R3一端接收第一电压，即第三电阻R3一端工作在第一电压域Vdd1；第一NMOS管MN1，第一NMOS管MN1的栅极连接第一分压节点Vdiv，漏极连接第三电阻R3的另一端并作为第一检测电路21的输出端，源极接地。
图6为图5中第一电压(Vin)、第一分压节点(Vdiv)以及第一检测电路的输出端(OUT)的信号波形图。结合参考图5及图6，第一预设电平为低电平，第一检测电路21的工作原理如下：
第一电阻R1和第二电阻R2起到分压的作用，调节第一分压节点Vdiv的电压。具体地，第一电压为Vin，则在第一NMOS管MN1导通之前，第一分压节点Vdiv＝R2×Vin/(R1+R2)，第一检测电路21的输出端的电压由第三电阻R3上拉至与第一电压Vin相当。第一电压Vin逐渐增加，第一分压节点Vdiv的电压随之增加，在第一分压节点Vdiv增加至第一目标电压后，第一NMOS管MN1的栅极基于该第一目标电压的控制使得第一NMOS管MN1导通，相应的，第一检测电路21的输出端(即第一NMOS管MN1的源极)的电压将被迅速拉低，使得第一检测电路21的输出端输出低电平信号，即第一检测电路21的输出端输出具有第一预设电平的第一检测信号。
继续参考图5，第一检测电路21还可以包括：第一电容C，第一电容C一端连接第一分压节点Vdiv，另一端接地。第一电容C可以对第一分压节点Vdiv进行去噪。
可以理解的是，第一电阻R1、第二电阻R2以及第三电阻R3中的任一者均可以为单个电阻、多个电阻串联或者多个电阻并联构成。
根据前述的分析可以发现，可以根据实际的电路需求，即根据第一预设值合理选择第一电阻R1和第二电阻R2的电阻值，即合理选择R2/(R1+R2)的值，以保证第一NMOS管MN1在第一电压大于或等于第一预设值时导通。
继续参考图4，在一些实施例中，第二检测单元121可以包括：第二检测电路22，用于检测第二电压是否大于或等于第二预设值，若是，则通过输出端输出具有第二预设电平的第二检测信号；第三反相器inv3，工作在第二电压域Vdd2H，第三反相器inv3的输入端连接第二检测电路22的输出端；第四反相器inv4，工作在第二电压域Vdd2H，第四反相器inv4的输入端连接第三反相器inv3的输出端，第四反相器inv4的输出端作为第二节点nb。
可以理解的是，第四反相器inv4即为第二输出元件。
第二检测电路22可以包括：相串联的第五电阻和第六电阻，第五电阻一端接收第二电压，第五电阻的另一端以及第六电阻的一端均连接第二分压节点，第六电阻的另一端接地； 第七电阻，第七电阻一端接收第一电压；第三NMOS管，第三NMOS管的栅极连接第二分压节点，漏极连接第七电阻的另一端且作为第二检测电路的输出端，源极接地。
第二检测电路22还可以包括：第二电容，第二电容一端连接第二分压节点，另一端接地。
其中，第二预设电平为低电平。有关第二检测电路22的一种具体实现方式，可以参考前述对第一检测电路21的详细说明，在此不再赘述。
第三NMOS管的栅极接收第二目标电压导通。可以根据第二预设值，合理选择第五电阻与第六电阻的电阻值，以保证第三NMOS管在第二电压大于或等于第二预设值时导通。在一些实施例中，第一预设值大于第二预设值，若第一NMOS管与第三NMOS管的沟道宽长比相同，第一目标电压等于第二目标电压，则R2/(R1+R2)的值应小于R6/(R5+R6)的值，R5为第五电阻的电阻值，R6为第六电阻的电阻值。
继续参考图4，在一些实施例中，第三检测单元131可以包括：第三检测电路23，用于检测第三电压是否大于或等于第三预设值，若是，则通过输出端输出具有第三预设电平的第三检测信号；第五反相器inv5，工作在第三电压域Vdd2L，第五反相器inv5的输入端连接第三检测电路23的输出端；第三输出元件24，工作在第二电压域Vdd2H，第三输出元件24的输入端与第五反相器inv5的输出端连接，第三输出元件24的输出端作为第三节点nc。
第三检测电路23可以包括：相串联的第七电阻和第八电阻，第七电阻一端接收第三电压，第七电阻的另一端以及第八电阻的一端均连接第三分压节点，第八电阻的另一端接地；第九电阻，第九电阻一端接收第三电压；第四NMOS管，第四NMOS管的栅极连接第三分压节点，漏极连接第九电阻的另一端且作为第三检测电路23的输出端，源极接地。
第三检测电路还包括：第三电容，所述第三电容一端连接第三分压节点，另一端接地。
其中，第三预设电平为低电平。有关第三检测电路23的一种具体实现方式，可以参考前述对第一检测电路21的详细说明，在此不再赘述。
第四NMOS管的栅极接收第三目标电压导通。可以根据第三预设值，合理选择第七电阻与第八电阻的电阻值，以保证第四NMOS管在第三电压大于或等于第三预设值时导通。在一些实施例中，第二预设值大于第三预设值，若第三NMOS管与第四NMOS管的沟道宽长比相同，第一目标电压等于第三目标电压，则R2/(R1+R2)的值应小于R8/(R7+R8)的值，R7为第七电阻的电阻值，R8为第八电阻的电阻值。
继续参考图4，在一些实施例中，第三输出元件24可以包括：第一电平转换单元214，工作在第二电压域Vdd2H，连接第五反相器inv5的输出端，并输出第三检测信号；偶数个级联的第六反相器inv6，第六反相器inv6工作在第二电压域Vdd2H，处于首级的第六反相器inv6 的输入端接收第三检测信号，处于尾级的第六反相器inv6的输出端作为第三节点nc。
在一些例子中，在检测到第三电压大于或等于第三预设值期间，第三检测电路23的输出端输出具有第三预设电平的第三检测信号，第三预设电平为低电平；相应的，第五反相器inv5的输出端输出高电平；第一电平转换单元214连接第五反相器inv5的输出端，并对该高电平进行电平翻转，以重新输出具有第三预设电平的第三检测信号。偶数个级联的第六反相器inv6有利于提高第三检测信号继续传输的传输能力。若第三电压小于第三预设值，则第三检测电路23输出的第三检测信号无效，即第三检测信号为高电平信号；相应的，第五反相器inv5的输出端输出低电平；第一电平转换单元214对该低电平进行电平翻转，以输出高电平信号，即第一电平转换单元214输出无效的第三检测信号。
在另一些实施例中，第三预设电平可以为高电平，有关第一电平转换单元214、第五反相器inv5以及第六反相器inv6的工作原理在此不再赘述。
继续参考图4，第一电平转换单元214可以包括：第四电阻R4以及第二NMOS管MN2，第四电阻R4的一端接收第二电压，另一端与第二NMOS管MN2的漏极连接且作为输出第三检测信号的输出节点，第二NMOS管MN2的源极接地，第二NMOS管MN2的栅极连接第五反相器inv5的输出端。
第四电阻R4的一端工作在第二电压域Vdd2H。
继续参考图4，逻辑电路模块102包括：或非电路112，连接第一节点na、第二节点nb以及第三节点nc，且工作在第二电压域Vdd2H，并通过第五节点nd输出监测信号PorN_D；其中，第一预设电平、第二预设电平以及第三预设电平为同一电平；驱动电路122，驱动电路122提供在由第五节点nd向第四节点no传输监测信号PorN_D的传输路径。
第五节点nd为或非电路112的输出端。第一预设电平、第二预设电平以及第三预设电平为同一电平，即具有第一预设电平的第一检测信号、具有第二预设电平的第二检测信号以及具有第三预设电平的第三检测信号均为逻辑“1”或者均为逻辑“0”。
在一些例子中，第一预设电平、第二预设电平以及第三预设电平均为低电平，也就是说，具有第一预设电平的第一检测信号、具有第二预设电平的第二检测信号以及具有第三预设电平的第三检测信号均为逻辑“0”，相应的，有效状态的监测信号PorN_D为高电平信号即为逻辑“1”，无效状态的监测信号PorN_D为低电平信号即为逻辑“0”。
在另一些例子中，第一预设电平、第二预设电平以及第三预设电平也可以均为高电平，也就是说，具有第一预设电平的第一检测信号、具有第二预设电平的第二检测信号以及具有第三预设电平的第三检测信号均为逻辑“1”，相应的，有效状态的监测信号PorN_D为低电平信号即为逻辑“0”，无效状态的监测信号PorN_D为高电平信号即为逻辑“1”。
继续参考图4，在一些实施例中，或非电路112可以包括：或非门Nor，工作在第二电压域Vdd2H，或非门Nor的三个输入端分别连接第一节点na、第二节点nb以及第三节点nc；偶数个级联的第七反相器inv7，第七反相器inv7均工作在第二电压域Vdd2H，处于首级的第七反相器inv7的输入端连接或非门Nor的输出端，处于尾级的第七反相器inv7的输出端作为第五节点nd。其中，或非门Nor即为与第一节点na、第二节点nb以及第三节点nc直接连接的逻辑运算元件。
偶数个级联的第七反相器inv7可以提高监测信号PorN_D的传输能力。
一般情况下，实际要用到监测信号PorN_D的具体电路位置通常离或非电路112的第五节点nd相对较远，第四节点no可以与实际要用到监测信号PorN_D的具体电路的输出端直接连接，驱动电路122可以提高监测信号PorN_D由第五节点nd向第四节点no传输的传输能力，有利于提高监测信号PorN_D的传输速度以及传输准确性。
驱动电路122可以包括：第一驱动电路120，工作在第一电压域Vdd1，提供由第五节点nd向第六节点ne传输监测信号PorN_D的第一传输路径，第六节点ne位于第四节点no与第五节点nd之间；第二驱动电路220，工作在第二电压域Vdd2H，提供由第六节点ne向第四节点传输监测信号PorN_D的第二传输路径。
第一驱动电路120较第二驱动电路220而言距离第四节点no更远，因此，第一驱动电路120采用电压相对较大的第一电压域Vdd1，第二驱动电路220工作在电压相对较小的第二电压域Vdd2H。可以理解的是，在其他实施例中，第一驱动电路120和第二驱动电路220可以均工作在第一电压域Vdd1或者均工作在第二电压域Vdd2H。
第一驱动电路120包括：第二电平转换单元41，连接第五节点nd，且工作在第一电压域Vdd1，接收监测信号PorN_D并输出监测反相信号，监测反相信号与监测信号PorN_D互为反相信号；第八反相器inv8，工作在第一电压域Vdd1，第八反相器inv8的输入端接收监测反相信号，第八反相器inv8的输出端作为第六节点ne。
在一些例子中，监测信号PorN_D为有效状态，且有效状态的监测信号PorN_D为高电平信号；相应的，处于尾级(即最后一级)的第七反相器inv7的输出端(即第五节点nd)输出高电平；第二电平转换单元41连接处于尾级的第七反相器inv7的输出端，并对该高电平进行电平翻转，以输出低电平信号；该低电平信号传输至第八反相器inv8，第八反相器inv8的输出端(即第六节点ne)输出高电平信号，该高电平信号即为具有高电平的监测信号PorN_D即有效状态的监测信号PorN_D。若监测信号PorN_D为无效状态，且无效状态的监测信号PorN_D为低电平信号；相应的，处于尾级的第七反相器inv7的输出端输出低电平；第二电平转换单元41对该低电平进行电平翻转，以输出高电平信号；该高电平信号传输至第八反相器inv8，第八反相器inv8的输出端输出低电平信号，该低电平信号即为无效的监测信号 PorN_D。
在另一些例子中，监测信号PorN_D为有效状态，且有效状态的监测信号PorN_D也可以为低电平信号，相应的，无效状态的监测信号PorN_D也可以为高电平信号，关于第七反相器inv7、第二电平转换单元41和第八反相器inv8的工作原理不再赘述。
第二电平转换单元41可以包括：第十电阻R10以及第五NMOS管MN5，第十电阻R10的一端接收第一电压，另一端与第五NMOS管MN5的漏极连接且作为第二电平转换单元41的输出端，第五NMOS管MN5的源极接地，第五NMOS管MN5的栅极连接第五节点nd。
即第十电阻R10的一端工作在第一电压域Vdd1。
继续参考图4，在一些实施例中，第二驱动电路220可以包括：偶数个级联的第九反相器inv9，第九反相器inv9均工作在第二电压域Vdd2H，处于首级的第九反相器inv9的输入端连接第六节点ne，处于尾级的第九反相器的输出端作为第四节点no。
可以理解的是，本公开实施例中提及的“偶数”可以为2、4、6、8、10、14等任意偶数，“奇数”可以为1、3、5、7、9等任意奇数。
图7至图9为第一电压域、第二电压域、第三电压域的电压波形图与监测信号的三种不同示意图。以Vdd1＞Vdd2H＞Vdd2L为正常上电，且有效状态的监测信号PorN_D为高电平信号为例：
结合参考图7至图9，在Vdd1＞Vdd2H＞Vdd2L期间即正常上电期间，监测信号PorN_D为高电平信号；在非正常上电期间，监测信号PorN_D为低电平信号。无论第一电压域Vdd1、第二电压域Vdd2H以及第三电压域Vdd2L各自提供的电压如何变化，只有在满足Vdd1＞Vdd2H＞Vdd2L期间输出的监测信号PorN_D才为有效状态。
可见，本公开实施例提供的监测电路，通过获取监测信号PorN_D是否为有效状态，可以获知第一电压域Vdd1、第二电压域Vdd2H以及第三电压域Vdd2L分别提供的电压是否符合需求。
本公开另一实施例还提供一种存储系统，包括上述实施例提供的监测电路。图10为本公开实施例提供的存储系统的一种功能框图，图11为本公开实施例提供的存储系统中触发电路的一种电路结构示意图。以下将结合附图对本公开实施例提供的存储系统进行详细说明，需要说明的是，与前述实施例相同或相应的部分，可参考前述实施例的详细描述，以下将不做赘述。
参考图10，本公开实施例提供的存储系统包括：电源网络300，电源网络300具有第一电压域Vdd1、第二电压域Vdd2H以及第三电压域Vdd2L；上述实施例提供的监测电路301。
存储系统可以为DRAM存储系统，例如为DDR5 DRAM存储系统或者DDR4 DRAM存储系统。在其他实施例中，存储系统还可以为SRAM存储系统、SDRAM存储系统、ROM存储系统或者闪存存储系统。
存储系统还可以包括：触发电路302，响应于具有有效状态的监测信号PorN_D以生成至少一个触发信号。其中，触发电路302与监测电路300可以集成于POR(Power on Reset)模块内，POR模块输出监测信号PorN_D以及触发信号。
触发电路302可以生成与监测信号PorN_D的电平变化沿之间具有不同时间间隔的多个触发信号。其中，监测信号PorN_D的有效状态为高电平，则电平变化沿为电平上升沿；监测信号PorN_D的有效状态为低电平，则电平变化沿为电平下降沿。
参考图11，触发电路302可以包括：振荡器312，响应于具有有效状态的监测信号PorN_D进行振荡，并输出振荡信号OSC；计数器322，被配置为，对振荡信号OSC的次数进行计数获取计数值，并输出计数值B<n:0>；逻辑解码电路332，被配置为，根据计数值B<n:0>生成触发信号。
振荡器312可以为RC延迟环振荡器(RC delay based Ring oscillator)，包括：与非门AN，与非门AN的一输入端接收上电信号；级联的至少两个电阻R以及至少两个反相器inv，处于首位的电阻R与与非门AN的输出端连接，处于尾级的电阻经由一反相器inv与与非门AN的另一端连接，且相邻级的两个电阻R经由一反相器inv连接；至少两个电容C1，电容C1的一端与电阻R和反相器inv输入端的连接节点连接，另一端接地。需要说明的是，图3中仅示意出了2个电阻R、2个反相器inv以及2个电容C1，实际上，振荡器312可以包括N个电阻R、N个反相器inv以及N个电容C1，N可以为大于或等于2的任意偶数，如4、6、8等。
在另一些例子中，振荡器312也可以为LC振荡器或者石英晶体振荡器等。
计数器322通过对振荡次数进行计数的方式，获取振荡器312的振荡周期的周期数量，可以理解为，计数值B<n:0>即表征振荡周期的周期数量。计数值B<n:0>作为使能逻辑解码电路332生成触发信号的使能信号，在计数值B<n:0>到达预设值时逻辑解码电路332生成触发信号，触发信号可以为高电平信号。
可以理解的是，计数值B<n:0>表征振荡周期的周期数量，且振荡器312的单个振荡周期的时长可以被获知，相应的计数值B<n:0>也可以表征振荡时长，预设值也相应表征预设时长，计数值B<n:0>达到预设值即表明振荡时长满足预设时长，逻辑解码电路332生成触发信号。
计数器322可以为基于触发器的计数电路。在一个具体例子中，计数器322可以为8 位(bit)计数器，相应计数值B<n:0>中n为7。可以理解的是，计数器322的比特位数可以根据实际需要确定，计数器322具有最大计数值，且最大计数值表征最大振荡时长，只要满足计数器322的最大计数值表征的最大振荡时长小于或等于预设值表征的预设时长即可。例如，计数器322可以为4位计数器、16位计数器或者32位计数器等。
逻辑解码电路332还可以被配置为，生成多个相较于监测信号PorN_D的电平变化沿具有不同延迟的触发信号，其中，逻辑解码电路332在生成一触发信号后，生成第一复位信号CntRst，且计数器322响应于第一复位信号CntRst对计数值B<n:0>归零，且在计数值B<n:0>归零后，计数器322重新开始计数，并在计数值B<n:0>到达预设值时产生下一个触发信号，并相应生成第一复位信号CntRst。如此循环，直至生成预设数量的触发信号。此外，在所有触发信号均生成之后，逻辑解码电路332还可以生成第二复位信号，振荡器312响应于第二复位信号停止振荡。
可以理解的是，在时间上依次产生的触发信号之间的延迟可以相同，也可以不同，即与不同触发信号相对应的预设值可以相同，也可以不同。
参考图12，图12为本公开实施例提供的存储系统中振荡信号、监测信号以及触发信号的时序图，在一些实施例中，以逻辑解码电路332生成4个触发信号作为示例，分别为第一触发信号PorN_A1、第二触发信号PorN_A2、第三触发信号PorN_A3以及第四触发信号PorN_A4，且监测信号PorN_D、第一触发信号PorN_A1、第二触发信号PorN_A2、第三触发信号PorN_A3以及第四触发信号PorN_A4之间分别具有时间延迟。
在一些实施例中，逻辑解码电路332还可以被配置为，在所有触发信号均生成之后，生成第二复位信号，且振荡器312响应于第二复位信号停止振荡，结合图11及图12，在第四触发信号PorN_A4生成之后，振荡器312停止振荡。逻辑解码电路332还可以被配置为，在所有触发信号均生成之后，锁存所有的触发信号。
触发电路302还可以被配置为，若监测信号PorN_D由有效状态变为无效状态，则将触发信号复位为低电平。
图7至图9还示意出了各触发信号的时序图。结合参考图7至图9，在正常上电状态下，生成有效的监测信号PorN_D，且还生成具有不同延迟的多个触发信号，即生成第一触发信号PorN_A1、第二触发信号PorN_A2、第三触发信号PorN_A3和第四触发信号PorN_A4。
存储系统还可以包括：模拟电路模块303；数字电路模块304；存储阵列305。存储阵列305用于进行读写操作。其中，模拟电路模块303响应于触发信号，并生成第一控制信号；数字电路模块304响应于监测信号PorN_D，并生成第二控制信号；第一控制信号以及第二控制信号均传输至存储阵列305。此外，监测信号PorN_D也可以传输至存储阵列305。
模拟电路模块303可以接收第一触发信号PorN_A1、第二触发信号PorN_A2、第三触发信号PorN_A3以及第四触发信号PorN_A4，并分别作为使能模拟电路模块303中不同电路模块的使能信号。其中的，模拟电路模块303可以工作在第一电压域Vdd1和第二电压域Vdd2H，数字电路模块304可以工作在第二电压域Vdd2H和第三电压域Vdd2L。
本公开实施例提供的存储系统，可以监测到第一电压域Vdd1、第二电压域Vdd2H以及第三电压域Vdd2L分别提供的电压是否符合需求，且在正常上电情况下进行读写操作。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作各自更动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。

Claims (15)

  1. 一种监测电路，包括：
    电压检测模块，通过第一节点、第二节点和第三节点分别输出第一检测信号、第二检测信号和第三检测信号，被配置为，检测第一电压域提供的第一电压是否大于或等于第一预设值，若是，则所述第一检测信号具有第一预设电平；检测第二电压域提供的第二电压是否大于或等于第二预设值，若是，则所述第二检测信号具有第二预设电平；检测第三电压域提供的第三电压是否大于或等于第三预设值，若是，则所述第三检测信号具有第三预设电平；
    逻辑电路模块，连接所述第一节点、所述第二节点以及所述第三节点，通过第四节点输出监测信号，被配置为，判断所述第一检测信号是否具有所述第一预设电平、所述第二检测信号是否具有所述第二预设电平且所述第三检测信号是否具有所述第三预设电平，若是，则所述监测信号为有效状态，若否，则所述监测信号为无效状态。
  2. 如权利要求1所述的监测电路，其中，所述电压检测模块具有直接向所述逻辑电路模块输出所述第一检测信号的第一输出元件，具有直接向所述逻辑电路模块输出所述第二检测信号的第二输出元件，具有直接向所述逻辑电路模块输出所述第三检测信号的第三输出元件；所述第一输出元件、所述第二输出元件以及所述第三输出元件均工作在所述第二电压域；
    所述逻辑电路模块包括直接与所述第一节点、所述第二节点以及所述第三节点连接的逻辑运算元件，且所述逻辑运算元件工作在所述第二电压域；
    所述第一预设值大于所述第二预设值；所述第二预设值大于所述第三预设值。
  3. 如权利要求1所述的监测电路，其中，所述电压检测模块包括：
    第一检测单元，输出端为所述第一节点，被配置为，检测所述第一电压是否大于或等于所述第一预设值；
    第二检测单元，输出端为所述第二节点，被配置为，检测所述第二电压是否大于或等于所述第二预设值；
    第三检测单元，输出端为所述第三节点，被配置为，检测所述第三电压是否大于或等于所述第三预设值。
  4. 如权利要求3所述的监测电路，其中，所述第一检测单元包括：
    第一检测电路，用于检测所述第一电压是否大于或等于所述第一预设值，若是，则通过输 出端输出具有所述第一预设电平的所述第一检测信号；
    第一反相器，工作在所述第一电压域，所述第一反相器的输入端连接所述第一检测电路的输出端；
    第二反相器，工作在所述第二电压域，所述第二反相器的输入端连接所述第一反相器的输出端，所述第二反相器的输出端作为所述第一节点。
  5. 如权利要求4所述的监测电路，其中，所述第一检测电路包括：
    相串联的第一电阻和第二电阻，所述第一电阻一端接收所述第一电压，所述第一电阻的另一端以及所述第二电阻的一端均连接第一分压节点，所述第二电阻的另一端接地；
    第三电阻，所述第三电阻一端接收所述第一电压；
    第一NMOS管，所述第一NMOS管的栅极连接所述第一分压节点，漏极连接所述第三电阻的另一端并作为所述第一检测电路的输出端，源极接地。
  6. 如权利要求5所述的监测电路，其中，所述第一检测电路还包括：第一电容，所述第一电容一端连接所述第一分压节点，另一端接地。
  7. 如权利要求3所述的监测电路，其中，所述第二检测单元包括：
    第二检测电路，用于检测所述第二电压是否大于或等于所述第二预设值，若是，则通过输出端输出具有所述第二预设电平的所述第二检测信号；
    第三反相器，工作在所述第二电压域，所述第三反相器的输入端连接所述第二检测电路的输出端；
    第四反相器，工作在所述第二电压域，所述第四反相器的输入端连接所述第三反相器的输出端，所述第四反相器的输出端作为所述第二节点。
  8. 如权利要求3所述的监测电路，其中，所述第三检测单元包括：
    第三检测电路，用于检测所述第三电压是否大于或等于所述第三预设值，若是，则通过输出端输出具有所述第三预设电平的所述第三检测信号；
    第五反相器，工作在所述第三电压域，所述第五反相器的输入端连接所述第三检测电路的输出端；
    第三输出元件，工作在所述第二电压域，所述第三输出元件的输入端与所述第五反相器的输出端连接，所述第三输出元件的输出端作为所述第三节点。
  9. 如权利要求8所述的监测电路，其中，所述第三输出元件包括：
    第一电平转换单元，工作在第二电压域，连接所述第五反相器的输出端，并输出所述第三 检测信号；
    偶数个级联的第六反相器，所述第六反相器工作在所述第二电压域，处于首级的所述第六反相器的输入端接收所述第三检测信号，处于尾级的所述第六反相器的输出端作为所述第三节点。
  10. 如权利要求9所述的监测电路，其中，所述第一电平转换单元包括：
    第四电阻以及第二NMOS管，所述第四电阻的一端接收所述第二电压，另一端与所述第二NMOS管的漏极连接且作为输出所述第三检测信号的输出节点，所述第二NMOS管的源极接地，所述第二NMOS管的栅极连接所述第五反相器的输出端。
  11. 如权利要求1所述的监测电路，其中，所述逻辑电路模块包括：
    或非电路，连接所述第一节点、所述第二节点以及所述第三节点，且工作在所述第二电压域，并通过第五节点输出所述监测信号；其中，所述第一预设电平、所述第二预设电平以及所述第三预设电平为同一电平；
    驱动电路，所述驱动电路提供在由所述第五节点向所述第四节点传输所述监测信号的传输路径。
  12. 如权利要求11所述的监测电路，其中，所述驱动电路包括：
    第一驱动电路，工作在所述第一电压域，提供由所述第五节点向第六节点传输所述监测信号的第一传输路径，所述第六节点位于所述第四节点与所述第五节点之间；
    第二驱动电路，工作在所述第二电压域，提供由所述第六节点向所述第四节点传输所述监测信号的第二传输路径。
  13. 如权利要求12所述的监测电路，其中，所述第一驱动电路包括：
    第二电平转换单元，连接所述第五节点，且工作在所述第一电压域，接收所述监测信号并输出监测反相信号，所述监测反相信号与所述监测信号互为反相信号；
    第八反相器，工作在所述第一电压域，所述第八反相器的输入端接收所述监测反相信号，所述第八反相器的输出端作为所述第六节点。
  14. 如权利要求12所述的监测电路，其中，所述第二驱动电路包括：
    偶数个级联的第九反相器，所述第九反相器均工作在所述第二电压域，处于首级的所述第九反相器的输入端连接所述第六节点，处于尾级的所述第九反相器的输出端作为所述第四节点。
  15. 一种存储系统，包括：
    电源网络，所述电源网络具有所述第一电压域、所述第二电压域以及所述第三电压域；
    如权利要求1-14任一项所述的监测电路。
PCT/CN2022/124145 2022-08-19 2022-10-09 监测电路以及存储系统 WO2024036725A1 (zh)

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JP2000075940A (ja) * 1998-08-31 2000-03-14 Hitachi Ltd 半導体装置
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CN108649939A (zh) * 2018-04-16 2018-10-12 芯原微电子(上海)有限公司 电源检测电路及方法
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000075940A (ja) * 1998-08-31 2000-03-14 Hitachi Ltd 半導体装置
CN207817562U (zh) * 2017-12-22 2018-09-04 北京时代民芯科技有限公司 一种多电源上电监控电路结构
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