WO2024031848A1 - 三维堆叠封装结构及其形成方法 - Google Patents

三维堆叠封装结构及其形成方法 Download PDF

Info

Publication number
WO2024031848A1
WO2024031848A1 PCT/CN2022/128970 CN2022128970W WO2024031848A1 WO 2024031848 A1 WO2024031848 A1 WO 2024031848A1 CN 2022128970 W CN2022128970 W CN 2022128970W WO 2024031848 A1 WO2024031848 A1 WO 2024031848A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory chip
bonding pad
lead
memory
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2022/128970
Other languages
English (en)
French (fr)
Inventor
季宏凯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to US18/547,152 priority Critical patent/US20250006702A1/en
Publication of WO2024031848A1 publication Critical patent/WO2024031848A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/20—Conductive package substrates serving as an interconnection, e.g. metal plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/823—Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/953—Materials of bond pads not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a three-dimensional stacked packaging structure and a method of forming the same.
  • LPDDR Low Power Double Data Rate, Low Power Double Data Rate
  • multiple storage blocks Ranks
  • Soldering pads are provided on the packaging substrate.
  • the block is connected to the soldering pad on the packaging substrate through a connecting wire, and external control signals are transmitted to the storage block through the soldering pad and the connecting wire.
  • the wires can be wound inside the memory block or within the packaging substrate.
  • the internal winding of the storage block will increase the size of the storage block, occupy too much space of the semiconductor product, reduce the space utilization of the semiconductor product, and is prone to signal crosstalk.
  • the internal winding of the packaging substrate will increase the complexity of the internal circuit of the packaging substrate, increase the size of the packaging substrate, and cause signal crosstalk to easily occur inside the packaging substrate.
  • Some embodiments of the present disclosure provide a three-dimensional stacked packaging structure and a forming method thereof, which are used to reduce the crosstalk between signal lines while reducing signal delays between different memory blocks, thereby improving the performance and yield of the packaging structure.
  • the present disclosure provides a three-dimensional stacked packaging structure, including:
  • a packaging substrate includes a substrate body, a through hole penetrating the substrate body along a first direction, a first bonding pad located on a first surface of the substrate body, and a second soldering pad located on a second surface of the substrate body. Welding pad, the first surface and the second surface are relatively distributed along the first direction, and the first direction is perpendicular to the first surface;
  • a stacked structure located on the first surface of the substrate body, the stacked structure including a second storage block and a first storage block located above the second storage block;
  • connection lead includes a first lead and a second lead of equal length.
  • the first lead is located above the packaging substrate, and one end of the first lead is electrically connected to the first bonding pad, and the other end is electrically connected to the In the first storage block, the second lead passes through the through hole, and one end of the second lead is electrically connected to the second bonding pad, and the other end is electrically connected to the second storage block.
  • the thickness of the stacked structure along the first direction is equal to the thickness of the substrate body along the first direction.
  • the packaging substrate further includes:
  • connection post is located in the substrate body, one end of the connection post is electrically connected to the first soldering pad, and the other end is electrically connected to the third soldering pad.
  • the first storage block includes:
  • a plurality of memory chips are stacked along the first direction, and adjacent memory chips are electrically connected, and the first lead is connected to the topmost memory chip in the first memory block. Chip electrical connections.
  • the first memory block includes a first memory chip and a second memory chip located above the first memory chip along a first direction, and a top surface of the first memory chip is in contact with the first memory chip. top surface bond connection of the second memory chip;
  • the bottom surface of the second memory chip is electrically connected to the first lead.
  • the top surface of the first memory chip has a first bonding pad
  • the top surface of the second memory chip has a second bonding pad
  • the first bonding pad is connected to the second bonding pad. bond pad electrical connections
  • the second memory chip also includes a first connection pad located on the bottom surface of the second memory chip and a first signal plug penetrating the second memory chip along the first direction.
  • the first signal plug One end of the plug is electrically connected to the second bonding pad, the other end is electrically connected to the first connection pad, and the first lead is electrically connected to the first connection pad.
  • the first memory chip further includes:
  • a first conductive bump is located on a surface of the first bonding pad facing away from the first signal plug, and the first conductive bump is bonded and connected to the second bonding pad.
  • the first storage block further includes:
  • the first adhesive layer fills the gap between the first memory chip and the second memory chip, and is used to bond the first memory chip and the second memory chip.
  • the stacked structure further includes:
  • a second adhesive layer is located between the second storage block and the packaging substrate.
  • the second adhesive layer includes a groove penetrating the second adhesive layer along the first direction, so The trench is aligned with the through hole along the first direction, and the second lead passes through the trench and the through hole.
  • the second storage block includes:
  • a plurality of memory chips are stacked along the first direction, and adjacent memory chips are electrically connected, and the second lead is connected to the memory at the bottom of the second memory block. Chip electrical connections.
  • the second memory block includes a third memory chip and a fourth memory chip located above the third memory chip along the first direction, and a top surface of the third memory chip is in contact with the third memory chip. Top surface bonding connection of the fourth memory chip;
  • the bottom surface of the third memory chip is electrically connected to the second lead.
  • the third memory chip has a third bonding pad on its top surface
  • the fourth memory chip has a fourth bonding pad on its top surface
  • the third bonding pad is connected to the fourth bonding pad. Bond pads bond electrical connections;
  • the third memory chip also includes a second connection pad located on the bottom surface of the third memory chip, and a second signal plug penetrating the third memory chip along the first direction.
  • the second signal plug One end of the plug is electrically connected to the third bonding pad, the other end is electrically connected to the second connection pad, the second lead is electrically connected to the second connection pad, and at least one of the second connection pads is connected to the second connection pad.
  • the through holes are aligned along the first direction.
  • the present disclosure also provides a method for forming a three-dimensional stacked packaging structure, including the following steps:
  • the packaging substrate includes a substrate body, a through hole penetrating the substrate body along a first direction, a first bonding pad located on a first surface of the substrate body, and a second pad located on the substrate body. a second bonding pad on the surface, the first surface and the second surface are relatively distributed along the first direction, and the first direction is perpendicular to the first surface;
  • the stacked structure including a second storage block and a first storage block located above the second storage block;
  • first lead located above the package substrate and electrically connecting the first storage block and the first bonding pad, and forming a through hole through the through hole and electrically connecting the second storage block and the The second lead of the second bonding pad.
  • specific steps of forming the packaging substrate include:
  • the first soldering pad located on the first surface of the substrate body, the second soldering pad and the third soldering pad located on the second surface of the substrate body are formed, and the first soldering pad located on the second surface of the substrate body is formed.
  • the connection post is inside the substrate body and electrically connects the first bonding pad and the third bonding pad.
  • the specific steps of forming a stacked structure on the first surface of the substrate body include:
  • first storage block Forming a first storage block, the first storage block including a plurality of memory chips stacked along the first direction, and adjacent memory chips in the first storage block are electrically connected;
  • the second storage block includes a plurality of memory chips stacked along the first direction, and adjacent memory chips in the first storage block are electrically connected;
  • the second storage block is fixed on the first surface of the substrate body, and the first storage block is fixed above the second storage block along the first direction.
  • the specific steps of forming the first storage block include:
  • a first memory chip and a second memory chip are formed, the first memory chip has a first bonding pad on its top surface, the second memory chip has a second bonding pad on its top surface, and the second memory chip further It includes a first connection pad located on the bottom surface of the second memory chip and a first signal plug penetrating the second memory chip along the first direction. One end of the first signal plug is electrically connected to the The other end of the second bonding pad is electrically connected to the first connection pad;
  • the first memory chip and the second memory chip are bonded in such a manner that the first bonding pad and the second bonding pad face each other.
  • the second memory chip further includes a first conductive bump located on a surface of the second bonding pad facing away from the first signal plug; with the first bonding pad and the first signal plug.
  • a first adhesive layer filling the gap between the first memory chip and the second memory chip is formed.
  • the specific steps of forming the second storage block include:
  • a third memory chip and a fourth memory chip are formed, the top surface of the third memory chip has a third bonding pad, the top surface of the fourth memory chip has a fourth bonding pad, and the third memory chip further It includes a second connection pad located on the bottom surface of the third memory chip and a second signal plug penetrating the third memory chip along the first direction. One end of the second signal plug is electrically connected to the The other end of the third bonding pad is electrically connected to the second connection pad;
  • the third memory chip and the fourth memory chip are bonded in such a manner that the third bonding pad and the fourth bonding pad face each other.
  • the second storage block is fixed on the first surface of the substrate body, and the first storage block is fixed on the second storage block along the first direction.
  • the third memory chip in the second memory block is bonded to the first surface of the substrate body through a second adhesive layer, and the second adhesive layer has a structure along the first direction. a trench penetrating the second adhesive layer and aligned with the through hole along the first direction, at least one of the second connection pads aligned with the through hole along the first direction;
  • the first memory chip and the fourth memory chip in the first memory block are bonded through a third adhesive layer.
  • a first lead is formed above the packaging substrate and electrically connected to the first storage block and the first bonding pad, and a first lead is formed through the through hole and electrically connected to the second
  • the specific steps of storing the second lead of the block and the second bonding pad include:
  • the second lead is formed through the through hole and the trench and electrically connects the second connection pad and the second bonding pad.
  • the three-dimensional stacked packaging structure and the forming method thereof provided by some embodiments of the present disclosure, by forming a through hole penetrating the packaging substrate along the first direction inside the packaging substrate, so that the second storage block on the packaging substrate passes through the through hole.
  • the second lead of the hole is electrically connected to the packaging substrate, and the first storage block located above the second storage block is electrically connected to the packaging substrate through the first lead located above the packaging substrate, thereby eliminating the need to pass
  • the length of the first lead and the length of the second lead can be equalized, thereby reducing the signal between different storage blocks.
  • Figure 1 is a schematic diagram of a three-dimensional stacked packaging structure in a specific embodiment of the present disclosure
  • Figure 2 is a schematic diagram of a stacked structure in a specific embodiment of the present disclosure
  • FIG. 3 is a flow chart of a method for forming a three-dimensional stacked packaging structure in a specific embodiment of the present disclosure
  • FIGS. 4 to 10 are schematic diagrams of the main process structures in the process of forming a three-dimensional stacked packaging structure according to specific embodiments of the present disclosure.
  • FIG. 1 is a schematic diagram of the three-dimensional stacked packaging structure in a specific embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of the stacked structure in a specific embodiment of the present disclosure.
  • the three-dimensional stacked packaging structure includes:
  • the packaging substrate includes a substrate body 10 , a through hole 36 penetrating the substrate body 10 along the first direction D1 , a first bonding pad 11 located on the first surface of the substrate body 10 , and a first bonding pad 11 located on the first surface of the substrate body 10 .
  • the second bonding pad 12 on the second surface, the first surface and the second surface are relatively distributed along the first direction D1, and the first direction D1 is perpendicular to the first surface;
  • a stacked structure located on the first surface of the substrate body 10, the stacked structure includes a second storage block R0 and a first storage block R1 located above the second storage block R0;
  • connection leads include a first lead 15 and a second lead 16 of equal length.
  • the first lead 15 is located above the packaging substrate, and one end of the first lead 15 is electrically connected to the first bonding pad 11 and the other end.
  • One end of the second lead 16 is electrically connected to the first memory block R1, the second lead 16 passes through the through hole 36, and one end of the second lead 16 is electrically connected to the second bonding pad 12, and the other end is electrically connected to the The second storage block R0.
  • the three-dimensional stacked packaging structure described in this specific embodiment may be, but is not limited to, LPDDR.
  • the packaging substrate may be but is not limited to PCB (Printed Circuit Board).
  • the packaging substrate has the through hole 36 that penetrates the substrate body 10 along the first direction D1, and the two opposite surfaces of the substrate body 10 along the first direction D1 are respectively provided with the through holes 36 .
  • the stacked structure is located on the first surface of the substrate body 10 and covers the through hole 36 .
  • Each of the first memory block R1 and the second memory block R0 in the stacked structure includes a plurality of memory chips.
  • the plurality of memory chips in the first storage block R1 and the plurality of memory chips in the second storage block R0 are of the same type, for example, both are DRAM (Dynamic Random Access Memory, dynamic random access memory). memory) chip.
  • the plurality mentioned in this specific embodiment refers to two or more.
  • the second storage block R0 and the first storage block R1 in the stacked structure are stacked along the first direction D1, and the first storage block R1 is located in the second storage block R0 Above, that is, along the first direction D1, the distance between the first memory block R1 and the packaging substrate is greater than the distance between the second memory block R0 and the packaging substrate.
  • connection leads are used to electrically connect the packaging substrate and the stacked structure to transmit control signals from the outside through the packaging substrate to the first storage block R1 and the stacked structure.
  • the connection leads include the first lead 15 and the second lead 16 .
  • the first lead 15 electrically connecting the first memory block R1 and the first bonding pad 11 is located above the packaging substrate, and electrically connecting the second memory block R0 and the second bonding pad 11 .
  • the second lead 16 of the pad 12 passes through the through hole 36 and is electrically connected to the second bonding pad 12 .
  • the length of the first lead 15 and the second lead 16 can be equal, There is no need to perform wiring design in the first memory block R1 and the second memory block R2, nor in the wiring layer inside the packaging substrate.
  • the circuit design inside the first storage block R1, the second storage block R0, and the packaging substrate can also be simplified.
  • Crosstalk between signal lines is reduced, thereby improving the yield and performance of the three-dimensional stacked packaging structure, without causing an increase in the complexity of the internal circuits of the three-dimensional stacked packaging structure, thereby helping to control the cost of the three-dimensional stacked packaging structure. .
  • the three-dimensional stacked packaging structure further includes a plastic encapsulation layer 17 that covers at least the stacked structure, the first lead 15 and the second lead 16 , and the plastic encapsulation layer 17 17 is filled with the through holes 36 to prevent external factors from affecting the stacked structure, the first lead 15 and the second lead 16 .
  • the material of the plastic sealing layer 17 may be resin material.
  • the aperture of the through hole 36 can adjust the aperture of the through hole 36 according to actual needs, as long as it can ensure that the second lead 16 can pass through the through hole 36, which is not limited in this specific embodiment.
  • Those skilled in the art can adjust the thickness of the substrate body 10 along the first direction D1, the position and thickness of the first bonding pad 11 on the first surface, and the location of the second bonding pad 12.
  • the position and thickness on the second surface, the height of the stacked structure along the first direction D1 and other factors are used to further adjust the lengths of the first lead 15 and the second lead 16, as long as the The lengths of the first lead 15 and the second lead 16 only need to be equal.
  • the first lead 15 and the second lead 16 are made of the same material, and the diameter of the first lead 15 and the second lead 16 are the same, thereby further reducing the first The signal delay between the storage block R1 and the second storage block R0.
  • the thickness of the stacked structure along the first direction D1 is equal to the thickness of the substrate body 10 along the first direction D1.
  • the length of the first lead 15 mainly depends on The thickness of the stacked structure along the first direction D1. Since the second lead 16 passes through the through hole 36 penetrating the substrate body 10 and connects the second bonding pad 12 and the second memory block R0, the second lead 16 The length mainly depends on the thickness of the substrate body 10 along the first direction D1. In this specific embodiment, by setting the thickness of the substrate body 10 along the first direction D1 to be equal to the thickness of the stacked structure along the first direction D1, the first lead can be more easily realized.
  • the length of 15 is equal to the length of the second lead 16, which simplifies the manufacturing process of the three-dimensional stacked packaging structure.
  • the thickness of the stacked structure along the first direction D1 and the thickness of the substrate body 10 along the first direction D1 are both 300 ⁇ m.
  • the packaging substrate further includes:
  • the third bonding pad 13 is located on the second surface
  • connection post 14 is located in the substrate body 10 .
  • One end of the connection post 14 is electrically connected to the first bonding pad 11 , and the other end is electrically connected to the third bonding pad 13 .
  • connection pillar 14 penetrating the substrate body 10 along the first direction D1 in the substrate body 10 , the first bonding pad 11 and the first bonding pad 11 are electrically connected through the connection pillar 14 .
  • the external control signal is transmitted to the first memory block R1 through the third bonding pad 13 , the connection post 14 , the first bonding pad 11 and the first lead 15 .
  • the first bonding pad 11 , the second bonding pad 12 , the third bonding pad 13 and the connection post 14 may be made of the same material, for example, they may all be conductive materials such as metal tungsten or metal copper.
  • solder balls 37 (such as tin solder balls) are also provided on the surface of the third solder pad 13 .
  • the first storage block R1 includes:
  • a plurality of memory chips are stacked along the first direction D1, and adjacent memory chips are electrically connected.
  • the first lead 15 is connected to the topmost memory chip in the first memory block R1.
  • the memory chips are electrically connected.
  • the first storage area R1 block includes a first memory chip 34 and a second memory chip 24 located above the first memory chip 34 along the first direction D1.
  • the first memory chip 34 The top surface (front surface) is bonded and connected to the top surface (front surface) of the second memory chip 24;
  • the bottom surface (rear surface) of the second memory chip 24 is electrically connected to the first lead 15 .
  • the first memory chip 34 has a first bonding pad 22 on its top surface
  • the second memory chip 24 has a second bonding pad 20 on its top surface.
  • the first bonding pad 22 Electrically connected to the second bonding pad 20;
  • the second memory chip 24 further includes a first connection pad 18 located on the bottom surface of the second memory chip 24 and a first signal plug 19 penetrating the second memory chip 24 along the first direction D1.
  • One end of the first signal plug 19 is electrically connected to the second bonding pad 20 and the other end is electrically connected to the first connection pad 18 .
  • the first lead 15 is electrically connected to the first connection pad 18 .
  • the first memory chip R1 further includes:
  • the first conductive bump 21 is located on the surface of the first bonding pad 22 away from the first signal plug 19 , and the first conductive bump 21 is bonded to the second bonding pad 20 .
  • the first memory chip 34 includes a top surface and a bottom surface relatively distributed along the first direction D1
  • the second memory chip 24 also includes a top surface and a bottom surface relatively distributed along the first direction D1.
  • the second memory chip 24 and the first memory chip 34 are bonded face to face, that is, the first conductive bump 21 on the top surface of the second memory chip 24 and the first memory chip 34
  • the first bonding pads 22 on the top surface are bonded and connected, and the first leads 15 are in direct contact and electrical connection with the first connection pads 18 on the bottom surface of the second memory chip 24 .
  • the first control signal from the outside is transmitted to the first connection pad 18 on the bottom surface of the second memory chip 24 through the first bonding pad 11 and the first lead 15 .
  • the first control signal is transmitted to the semiconductor structure on the top surface of the second memory chip 24 through the first connection pad 18, the first signal plug 19 and the second bonding pad 20, And the first control signal also passes through the first connection pad 18, the first signal plug 19, the second bonding pad 20, the first conductive bump 21 and the first bonding
  • the pad 22 is transferred to the semiconductor structure on the top surface of the first memory chip 34, thereby reducing the gap between the first memory chip 34 and the second memory chip 24 inside the first memory block R1.
  • the signal delay improves the electrical performance of the first memory block R1 and the three-dimensional stacked packaging structure.
  • the number of the first bonding pads 22 is multiple, and the multiple first bonding pads 22 are arranged at intervals along the second direction D2. There are also a plurality of second bonding pads 20 , and the plurality of second bonding pads 20 are electrically connected to the plurality of first bonding pads 22 in a one-to-one correspondence.
  • the second direction D2 is parallel to the first surface.
  • the first storage block R1 Also included:
  • the first adhesive layer 25 fills the gap between the first memory chip 34 and the second memory chip 24 and is used to bond the first memory chip 34 and the second memory chip 24 .
  • the material of the first adhesive layer 25 may be underfill.
  • the stacked structure further includes:
  • the second adhesive layer 30 is located between the second memory block R0 and the packaging substrate.
  • the second adhesive layer 30 includes a second adhesive layer that penetrates the second adhesive layer 30 along the first direction D1.
  • the groove 301 is aligned with the through hole 36 along the first direction D1, and the second lead 16 passes through the groove 301 and the through hole 36.
  • the second storage block R0 is fixed to the first surface of the substrate body 10 through the second adhesive layer 30 to strengthen the connection between the second storage block R0 and the packaging substrate. connection stability.
  • the first storage area R1 may be fixed above the second storage block R0 through a third adhesive layer 33 to enhance the connection between the first storage block R1 and the second storage block R0 stability.
  • the material of the second adhesive layer 30 and the third adhesive layer 33 are the same, for example, both are insulating adhesive materials.
  • the material of the second adhesive layer 30 and the third adhesive layer 33 are both die attach film (Die Attach Film, DAF).
  • the groove 301 aligned with the through hole 36 is provided in the second adhesive layer 30, so that the second lead 16 can pass through all the holes in sequence from the bottom of the second memory block R0.
  • the trench 301 and the through hole 36 are then electrically connected to the second bonding pad 12 .
  • the second adhesive layer 30 is in contact with the second contact pad 29 and the third adhesive layer 33 is in contact with the back side of the memory chip, whereby the second adhesive layer 30 is exposed to more heat, thereby
  • the thermal expansion coefficient of the second adhesive layer 30 can be made smaller than the thermal expansion coefficient of the third adhesive layer 33 . Since the thermal expansion coefficient of the second adhesive layer 30 is relatively small, the thermal expansion difference between the memory chip and the substrate can be reduced. In some embodiments, for example, by increasing the concentration of silica in the second adhesive layer 30, the linear expansion coefficient of the silica filler is smaller, thereby increasing the thermal expansion coefficient of the second adhesive layer 30.
  • the second storage block R0 includes:
  • a plurality of memory chips are stacked along the first direction D1, and adjacent memory chips are electrically connected.
  • the second lead 16 is connected to the bottom layer of the second memory block R0.
  • the memory chips are electrically connected.
  • the second memory block R0 includes a third memory chip 35 and a fourth memory chip 26 located above the third memory chip 35 along the first direction D1.
  • the third memory chip 35 The top surface is bonded and connected to the top surface of the fourth memory chip 26;
  • the bottom surface of the third memory chip 35 is electrically connected to the second lead 16 .
  • the third memory chip 35 has a third bonding pad 27 on its top surface
  • the fourth memory chip 26 has a fourth bonding pad 32 on its top surface.
  • the third bonding pad 27 Bonding and electrical connection with the fourth bonding pad 32;
  • the third memory chip 35 further includes a second connection pad 29 located on the bottom surface of the third memory chip 35 and a second signal plug 28 penetrating the third memory chip 35 along the first direction D1.
  • One end of the second signal plug 28 is electrically connected to the third bonding pad 27, and the other end is electrically connected to the second connection pad 29.
  • the second lead 16 is electrically connected to the second connection pad 29, and At least one of the second connection pads 29 is aligned with the through hole 36 along the first direction D1.
  • the third memory chip 35 includes a top surface and a bottom surface relatively distributed along the first direction D1
  • the fourth memory chip 26 also includes a top surface and a bottom surface relatively distributed along the first direction D1.
  • the top surface of the third memory chip 35 includes a third bonding pad 27 and a second conductive bump 31 located on the surface of the third bonding pad 27 .
  • the third memory chip 35 and the fourth memory chip 26 are bonded face to face, that is, the second conductive bump 31 on the top surface of the third memory chip 35 and the fourth memory chip 26
  • the fourth bonding pad 32 on the top surface is bonded and connected, and the second lead 16 passing through the through hole 36 and the trench 301 is connected to the third bonding pad 32 on the bottom surface of the third memory chip 35 .
  • the two connection pads 29 are in direct contact for electrical connection.
  • the second control signal from the outside is transmitted to the second connection pad 29 on the bottom surface of the third memory chip 35 through the second bonding pad 12 and the second lead 16 .
  • the second control signal is transmitted to the semiconductor structure on the top surface of the third memory chip 35 through the second connection pad 29, the second signal plug 28 and the third bonding pad 27,
  • the second control signal also passes through the second connection pad 29, the second signal plug 28, the third bonding pad 27, the second conductive bump 31 and the fourth bonding
  • the pad 32 is transferred to the semiconductor structure on the top surface of the fourth memory chip 26, thereby reducing the gap between the third memory chip 35 and the fourth memory chip 26 inside the second memory block R0.
  • the signal delay improves the electrical performance of the second memory block R0 and the three-dimensional stacked packaging structure.
  • the second storage block R0 Also included:
  • the fourth adhesive layer 37 fills the gap between the third memory chip 35 and the fourth memory chip 26 and is used to bond the third memory chip 35 and the fourth memory chip 26 .
  • the material of the fourth adhesive layer 37 may be underfill.
  • FIG. 3 is a flow chart of a method for forming a three-dimensional stacked packaging structure in the specific embodiment of the present disclosure.
  • Figures 4 to 10 are specific embodiments of the present disclosure. Schematic diagram of the main process structure in the process of forming a three-dimensional stacked packaging structure. The schematic diagram of the three-dimensional stacked packaging structure formed in this specific embodiment can be seen in Figures 1 and 2. As shown in Figures 1-10, the method for forming the three-dimensional stacked packaging structure includes the following steps:
  • Step S40 forming a packaging substrate, which includes a substrate body 10, a through hole 36 penetrating the substrate body 10 along the first direction D1, a first bonding pad 11 located on the first surface of the substrate body 10, and a second bonding pad 12 located on the second surface of the substrate body 10.
  • the first surface and the second surface are relatively distributed along the first direction D1, and the first direction D1 is in contact with the second surface.
  • One surface is vertical;
  • Step S41 Form a stacked structure on the first surface of the substrate body 10.
  • the stacked structure includes a second memory block R0 and a first memory block R1 located above the second memory block R0. ;
  • Step S42 Form a first lead 15 located above the package substrate and electrically connected to the first memory block R1 and the first bonding pad 11, and form a first lead 15 passing through the through hole 36 and electrically connected to the first bonding pad 11.
  • the second memory block R0 and the second lead 16 of the second bonding pad 12 The length of the first lead 15 may be equal to the length of the second lead 16 .
  • specific steps of forming the packaging substrate include:
  • the first soldering pad 11 located on the first surface of the substrate body 10 , the second soldering pad 12 and the third soldering pad 13 located on the second surface of the substrate body 10 are formed.
  • the preset thickness of the subsequently preformed stacked structure can be obtained according to the preset design.
  • the thickness of the substrate body 10 is adjusted according to the preset thickness, so that the thickness of the substrate body 10 is equal to the thickness of the stacked structure to be formed subsequently.
  • a circuit structure is formed on the substrate body 10 .
  • the circuit structure includes the first bonding pad 11 located on the first surface of the substrate body 10 , the third soldering pad 11 located on the substrate body 10 .
  • the second bonding pad 12 and the third bonding pad 13 on both surfaces, and the connection posts 14 located in the substrate body 10 and electrically connecting the first bonding pad 11 and the third bonding pad 13 .
  • the specific steps of forming a stacked structure on the first surface of the substrate body 10 include:
  • the first storage block R1 includes a plurality of memory chips stacked along the first direction D1, and adjacent memory chips in the first storage block R1 are electrically connected;
  • the second storage area R0 contains a plurality of memory chips stacked along the first direction D1, and adjacent memory chips in the first storage block R1 are electrically connected;
  • the specific steps of forming the first storage block R1 include:
  • a first memory chip 34 and a second memory chip 24 are formed.
  • the first memory chip 34 has a first bonding pad 22 on its top surface
  • the second memory chip 24 has a second bonding pad 20 on its top surface.
  • the second memory chip 24 also includes a first connection pad 18 located on the bottom surface of the second memory chip 24, and a first signal plug 19 penetrating the second memory chip 24 along the first direction D1, so One end of the first signal plug 19 is electrically connected to the second bonding pad 20, and the other end is electrically connected to the first connection pad 18;
  • the first memory chip 34 and the second memory chip 24 are bonded in such a manner that the first bonding pad 22 and the second bonding pad 20 face each other.
  • the second memory chip 24 further includes a first conductive bump 21 located on a surface of the second bonding pad 20 facing away from the first signal plug 19; with the first key
  • the first adhesive layer 25 filling the gap between the first memory chip 34 and the second memory chip 24 is formed.
  • the first conductive bump 21 and the first memory chip are bonded.
  • Bonding pads 22 are used to realize the bonding connection between the first memory chip 34 and the second memory chip 24 .
  • an insulating adhesive such as underfill glue is filled between the first memory chip 34 and the second memory chip 24 to enhance the connection between the first memory chip 34 and the second memory chip 24 .
  • Connection strength may both be DRAM chips.
  • the first bonding pad 22 , the second bonding pad 20 , the first connection pad 18 and the first signal plug 19 may be made of the same material, for example, NiAu alloy material.
  • the material of the first conductive bump 21 may be any one of Cu, Ni, Sn, Ag, or an alloy material composed of two or more materials.
  • the material of the first conductive bump 21 is Cu/Ni/Sn/Ag (that is, an alloy material composed of Cu, Ni, Sn and Ag), Cu/Sn/Ag (that is, Cu, Sn and Ag alloy material composed of Ni/Sn/Ag (i.e. alloy material composed of Ni, Sn and Ag).
  • the specific steps of forming the second storage block R0 include:
  • a third memory chip 35 (shown in Figure 6) and a fourth memory chip 26 (shown in Figure 7) are formed.
  • the top surface of the third memory chip 35 has a third bonding pad 27.
  • the fourth memory chip 35 has a third bonding pad 27 on its top surface.
  • the top surface of the chip 26 has a fourth bonding pad 32.
  • the third memory chip 35 also includes a second connection pad 29 located on the bottom surface of the third memory chip 35 and a second connection pad 29 extending through the first direction D1.
  • the second signal plug 28 of the third memory chip 35, one end of the second signal plug 28 is electrically connected to the third bonding pad 27, and the other end is electrically connected to the second connection pad 29;
  • the third memory chip 35 and the fourth memory chip 26 are bonded in such a manner that the third bonding pad 27 and the fourth bonding pad 32 face each other.
  • the third memory chip 35 further includes a second conductive bump 31 located on the surface of the third bonding pad 27, and the second conductive bump 31 is bonded to the fourth bonding pad through Together, the third memory chip 35 and the fourth memory chip 26 are connected.
  • the second storage block R0 is fixed on the first surface of the substrate body 10 and the first storage block R1 is fixed on the first surface along the first direction D1.
  • the specific steps above the second memory block R0 include:
  • the third memory chip 35 in the second memory block R0 is bonded to the first surface of the substrate body 10 through a second adhesive layer 30 , which has an edge along the
  • the trench 301 penetrates the second adhesive layer 30 in the first direction D1 and is aligned with the through hole 36 along the first direction D1.
  • At least one of the second connection pads 29 is aligned with the through hole 36. 36 aligned along the first direction D1;
  • the first memory chip 34 and the fourth memory chip 26 in the first memory block R1 are bonded through the third adhesive layer 33 .
  • the third memory chip 35 is fixed on the first surface of the substrate body 10 of the packaging substrate through the second adhesive layer 30 , so that the third memory chip 35
  • the at least one second connection pad 29 is aligned with the through hole 36 along the first direction D1.
  • the second adhesive layer 30 has a groove 301 penetrating the second adhesive layer 30 along the first direction D1, and the groove 301 is aligned with the through hole 36, and at least one of the The position of the second connection pads 29 is aligned with the position of the groove 301 , that is, at least one of the second connection pads 29 is exposed through the groove 301 .
  • the second conductive bump 31 in the third memory chip 35 and the fourth bonding pad 32 in the fourth memory chip 26 are bonded through a bonding process to form a structure as shown in FIG. 8 Structure.
  • a fourth adhesive layer 37 is formed that fills the gap between the third memory chip 35 and the fourth memory chip 26 .
  • the formed first memory block R1 is connected to the bottom surface of the fourth memory chip 26 through the third adhesive layer 33 to form a structure as shown in FIG. 9 .
  • the first memory chip 34 and the fourth memory chip 26 can be fixedly connected through the third adhesive layer 33 first, and then The second memory chip 24 and the first memory chip 34 are bonded through a bonding process.
  • a first lead 15 is formed above the package substrate and electrically connected to the first memory block R1 and the first bonding pad 11 , and is formed through the through hole 36 and electrically connected.
  • the specific steps of the second memory block R0 and the second lead 16 of the second bonding pad 12 include:
  • the second lead 16 is formed through the through hole 36 and the trench 301 and electrically connects the second connection pad 29 and the second bonding pad 12 , as shown in FIG. 10 .
  • the plastic packaging layer 17 covering at least the stacked structure, the first lead 15 and the second lead 16 may be formed through a plastic packaging process, And the plastic sealing layer 17 fills the through holes 36 to prevent external factors from affecting the stacked structure, the first lead 15 and the second lead 16 .
  • solder balls 37 can also be formed on the surface of the third soldering pad 13 to form an LPDDR product.
  • the plastic encapsulation layer 17 may include an epoxy material and a filler dispersed in the epoxy material, such as silicon dioxide.
  • the fourth adhesive layer 37 may include epoxy resin and fillers dispersed in the epoxy resin, such as silica. Since the gap between the third memory chip 26 and the fourth memory chip 35 is small, the fluidity of the fourth adhesive layer 37 can be improved, thereby avoiding the existence of a gap between the third memory chip 26 and the fourth memory chip 35 .
  • the bubbles for example, make the filler content in the fourth adhesive layer 37 lower than the filler content in the plastic sealing layer 17 , thereby improving the filling effect of the fourth adhesive layer 37 .
  • the volume of the filler in the fourth adhesive layer 37 can also be made smaller than the volume of the filler in the plastic sealing layer 17 . Since the volume of the filler is smaller, the fluidity of the fourth adhesive layer 37 is stronger, thereby improving the quality of the fourth adhesive layer 37 . filling effect.
  • the three-dimensional stacked packaging structure and its formation method provided by some embodiments of this specific embodiment form a through hole penetrating the packaging substrate along the first direction inside the packaging substrate, so that the second storage block on the packaging substrate passes through all the through holes.
  • the second lead of the through hole is electrically connected to the packaging substrate, and the first storage block located above the second storage block is electrically connected to the packaging substrate through the first lead located above the packaging substrate, thereby enabling
  • the length of the first lead and the length of the second lead can be equalized without winding wires inside the first memory block, the second memory block or the packaging substrate, thereby reducing the cost of different memory blocks.

Landscapes

  • Semiconductor Memories (AREA)
  • Wire Bonding (AREA)

Abstract

本公开涉及一种三维堆叠封装结构及其形成方法。三维堆叠封装结构包括：封装基板，包括基板本体、沿贯穿基板本体的通孔、位于基板本体的第一表面上的第一焊垫、以及位于基板本体的第二表面上的第二焊垫；堆叠结构，位于基板本体的第一表面上，堆叠结构包括第二存储区块、以及位于第二存储区块上方的第一存储区块；连接引线，包括长度相等的第一引线和第二引线，第一引线位于封装基板上方，且第一引线的一端电连接第一焊垫、另一端电连接第一存储区块，第二引线穿过通孔，且第二引线的一端电连接第二焊垫、另一端电连接第二存储区块。本公开在降低不同存储区块之间信号延迟的同时，减少了引线等信号线之间的串扰。

Description

三维堆叠封装结构及其形成方法
相关申请引用说明
本申请要求于2022年08月08日递交的中国专利申请号202210944874.7、申请名为“三维堆叠封装结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种三维堆叠封装结构及其形成方法。
背景技术
在LPDDR(Low Power Double Data Rate，低功耗双倍速率)存储器等半导体产品中，多个存储区块(Rank)在封装基板上依次堆叠，所述封装基板上设置有焊垫，所述存储区块通过连接线与所述封装基板上的焊垫连接，外部控制信号通过所述焊垫和所述连接线传输至所述存储区块。但是，由于多个存储区块的高度不同，不同存储区块与所述封装基板的距离不同，导致不同存储区块与所述封装基板之间连接线的长度不同，从而产生不同存储区块之间的信号延迟等问题。为了解决这一问题，可以在存储区块内部进行绕线或者在封装基板内进行绕线。但是，存储区块内部绕线会增大存储区块的体积，占用半导体产品过多的空间，降低了半导体产品的空间利用率，而且还易发生信号的串扰。封装基板内部绕线会增加封装基板内部电路的复杂性，且增大封装基板的尺寸，且导致封装基板内部易发生信号的串扰。
因此，如何在降低不同存储区块之间信号延迟的同时，减少信号线之间的串扰，从而提高封装结构的性能和良率，是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供一种三维堆叠封装结构及其形成方法，用于在降低不同存储区块之间信号延迟的同时，减少信号线之间的串扰，从而提高封装结构的性能和良率。
根据一些实施例，本公开提供了一种三维堆叠封装结构，包括：
封装基板，包括基板本体、沿第一方向贯穿所述基板本体的通孔、位于所述基板本体的第一表面上的第一焊垫、以及位于所述基板本体的第二表面上的第二焊垫，所述第一表面与所述第二表面沿所述第一方向相对分布，所述第一方向与所述第一表面垂直；
堆叠结构，位于所述基板本体的所述第一表面上，所述堆叠结构包括第二存储区块、以及位于所述第二存储区块上方的第一存储区块；
连接引线，包括长度相等的第一引线和第二引线，所述第一引线位于所述封装基板上方，且所述第一引线的一端电连接所述第一焊垫、另一端电连接所述第一存储区块，所述第二引线穿过所述通孔，且所述第二引线的一端电连接所述第二焊垫、另一端电连接所述第二存储区块。
在一些实施例中，所述堆叠结构沿所述第一方向的厚度与所述基板本体沿所述第一方向的厚度相等。
在一些实施例中，所述封装基板还包括：
第三焊垫，位于所述第二表面上；
连接柱，位于所述基板本体内，所述连接柱的一端与所述第一焊垫电连接、另一端与所述第三焊垫电连接。
在一些实施例中，所述第一存储区块包括：
多个存储芯片，多个所述存储芯片沿所述第一方向堆叠，且相邻的所述存储芯片电连接，所述第一引线与所述第一存储区块中最顶层的所述存储芯片电连接。
在一些实施例中，所述第一存储区块包括第一存储芯片、以及沿第一方向位于所述第一存储芯片上方的第二存储芯片，所述第一存储芯片的顶面与所述第二存储芯片的顶面键合连接；
所述第二存储芯片的底面与所述第一引线电连接。
在一些实施例中，所述第一存储芯片的顶面具有第一键合垫，所述第二存储芯片的顶 面具有第二键合垫，所述第一键合垫与所述第二键合垫电连接；
所述第二存储芯片还包括位于所述第二存储芯片的底面的第一连接垫、以及沿所述第一方向贯穿所述第二存储芯片的第一信号插塞，所述第一信号插塞的一端电连接所述第二键合垫、另一端电连接所述第一连接垫，所述第一引线电连接所述第一连接垫。
在一些实施例中，所述第一存储芯片还包括：
第一导电凸块，位于所述第一键合垫背离所述第一信号插塞的表面，所述第一导电凸块与所述第二键合垫键合连接。
在一些实施例中，所述第一存储区块中还包括：
第一粘结层，填充满所述第一存储芯片和所述第二存储芯片之间的间隙，用于粘结所述第一存储芯片和所述第二存储芯片。
在一些实施例中，所述堆叠结构还包括：
第二粘结层，位于所述第二存储区块与所述封装基板之间，所述第二粘结层中包括沿所述第一方向贯穿所述第二粘结层的沟槽，所述沟槽与所述通孔沿所述第一方向对准，所述第二引线穿过所述沟槽和所述通孔。
在一些实施例中，所述第二存储区块包括：
多个存储芯片，多个所述存储芯片沿所述第一方向堆叠，且相邻的所述存储芯片电连接，所述第二引线与所述第二存储区块中最底层的所述存储芯片电连接。
在一些实施例中，所述第二存储区块包括第三存储芯片、以及沿第一方向位于所述第三存储芯片上方的第四存储芯片，所述第三存储芯片的顶面与所述第四存储芯片的顶面键合连接；
所述第三存储芯片的底面与所述第二引线电连接。
在一些实施例中，所述第三存储芯片的顶面具有第三键合垫，所述第四存储芯片的顶面具有第四键合垫，所述第三键合垫与所述第四键合垫键合电连接；
所述第三存储芯片还包括位于所述第三存储芯片的底面的第二连接垫、以及沿所述第一方向贯穿所述第三存储芯片的第二信号插塞，所述第二信号插塞的一端电连接所述第三键合垫、另一端电连接所述第二连接垫，所述第二引线电连接所述第二连接垫，且至少一个所述第二连接垫与所述通孔沿所述第一方向对准。
根据另一些实施例，本公开还提供了一种三维堆叠封装结构的形成方法，包括如下步骤：
形成封装基板，所述封装基板包括基板本体、沿第一方向贯穿所述基板本体的通孔、位于所述基板本体的第一表面上的第一焊垫、以及位于所述基板本体的第二表面上的第二焊垫，所述第一表面与所述第二表面沿所述第一方向相对分布，所述第一方向与所述第一表面垂直；
于所述基板本体的所述第一表面上形成堆叠结构，所述堆叠结构包括第二存储区块、以及位于所述第二存储区块上方的第一存储区块；
形成位于所述封装基板上方且电连接所述第一存储区块和所述第一焊垫的第一引线、并形成穿过所述通孔且电连接所述第二存储区块和所述第二焊垫的第二引线。
在一些实施例中，形成封装基板的具体步骤包括：
获取所述堆叠结构的预设厚度；
形成基板本体，且使得所述基板本体沿所述第一方向的厚度与所述预设厚度相等；
形成位于所述基板本体的所述第一表面上的所述第一焊垫、位于所述基板本体的所述第二表面上的所述第二焊垫和第三焊垫、以及位于所述基板本体内且电连接所述第一焊垫和所述第三焊垫的连接柱。
在一些实施例中，于所述基板本体的所述第一表面上形成堆叠结构的具体步骤包括：
形成第一存储区块，所述第一存储区块包括沿所述第一方向堆叠的多个存储芯片，且所述第一存储区块中相邻的存储芯片电连接；
形成第二存储区块，所述第二存储区块沿所述第一方向堆叠的多个存储芯片，且所述第一存储区块中相邻的存储芯片电连接；
固定所述第二存储区块于所述基板本体的所述第一表面上、并沿所述第一方向固定所述第一存储区块于所述第二存储区块上方。
在一些实施例中，形成第一存储区块的具体步骤包括：
形成第一存储芯片和第二存储芯片，所述第一存储芯片的顶面具有第一键合垫，所述第二存储芯片的顶面具有第二键合垫，所述第二存储芯片还包括位于所述第二存储芯片的底面的第一连接垫、以及沿所述第一方向贯穿所述第二存储芯片的第一信号插塞，所述第一信号插塞的一端电连接所述第二键合垫、另一端电连接所述第一连接垫；
以所述第一键合垫和所述第二键合垫相对的方式键合所述第一存储芯片和所述第二存储芯片。
在一些实施例中，所述第二存储芯片还包括位于所述第二键合垫背离所述第一信号插塞的表面上的第一导电凸块；以所述第一键合垫和所述第二键合垫相对的方式键合所述第一存储芯片和所述第二存储芯片的具体步骤包括：
键合所述第一导电凸块和所述第一键合垫；
形成填充满所述第一存储芯片和所述第二存储芯片之间的间隙的第一粘结层。
在一些实施例中，形成第二存储区块的具体步骤包括：
形成第三存储芯片和第四存储芯片，所述第三存储芯片的顶面具有第三键合垫，所述第四存储芯片的顶面具有第四键合垫，所述第三存储芯片还包括位于所述第三存储芯片的底面的第二连接垫、以及沿所述第一方向贯穿所述第三存储芯片的第二信号插塞，所述第二信号插塞的一端电连接所述第三键合垫、另一端电连接所述第二连接垫；
以所述第三键合垫和所述第四键合垫相对的方式键合所述第三存储芯片和所述第四存储芯片。
在一些实施例中，固定所述第二存储区块于所述基板本体的所述第一表面上、并沿所述第一方向固定所述第一存储区块于所述第二存储区块上方的具体步骤包括：
通过第二粘结层粘结所述第二存储区块中的所述第三存储芯片与所述基板本体的所述第一表面，所述第二粘结层中具有沿所述第一方向贯穿所述第二粘结层且与所述通孔沿所述第一方向对准的沟槽，至少一个所述第二连接垫与所述通孔沿所述第一方向对准；
通过第三粘结层粘结所述第一存储区块中的所述第一存储芯片和所述第四存储芯片。
在一些实施例中，形成位于所述封装基板上方且电连接所述第一存储区块和所述第一焊垫的第一引线、并形成穿过所述通孔且电连接所述第二存储区块和所述第二焊垫的第二引线的具体步骤包括：
形成位于所述封装基板上方且电连接所述第一连接垫和所述第一焊垫的所述第一引线；
形成穿过所述通孔和所述沟槽、且电连接所述第二连接垫和所述第二焊垫的所述第二引线。
本公开一些实施例提供的三维堆叠封装结构及其形成方法，通过在封装基板的内部形成沿第一方向贯穿封装基板的通孔，使得封装基板上的第二存储区块通过穿过所述通孔的第二引线与封装基板电连接，位于所述第二存储区块上方的第一存储区块通过位于所述封装基板上方的第一引线与所述封装基板电连接，从而能够使得无需通过在第一存储区块、第二存储区块或者所述封装基板内部绕线即可实现所述第一引线的长度与所述第二引线的长度相等，进而在降低不同存储区块之间信号延迟的同时，减少了引线等信号线之间的串扰，从而改善了三维堆叠封装结构的良率和性能，且不会造成三维堆叠封装结构内部线路复杂度的增加，从而有助于控制所述三维堆叠封装结构的成本。
附图说明
附图1是本公开具体实施方式中三维堆叠封装结构的示意图；
附图2是本公开具体实施方式中堆叠结构的示意图；
附图3是本公开具体实施方式中三维堆叠封装结构的形成方法流程图；
附图4-附图10是本公开具体实施方式在形成三维堆叠封装结构的过程中主要的工艺结构示意图。
具体实施方式
下面结合附图对本公开提供的三维堆叠封装结构及其形成方法的具体实施方式做详细说明。
本公开提供了一种三维堆叠封装结构，附图1是本公开具体实施方式中三维堆叠封装结构的示意图，附图2是本公开具体实施方式中堆叠结构的示意图。如图1和图2所示，所述三维堆叠封装结构，包括：
封装基板，包括基板本体10、沿第一方向D1贯穿所述基板本体10的通孔36、位于所述基板本体10的第一表面上的第一焊垫11、以及位于所述基板本体10的第二表面上的第二焊垫12，所述第一表面与所述第二表面沿所述第一方向D1相对分布，所述第一方向D1与所述第一表面垂直；
堆叠结构，位于所述基板本体10的所述第一表面上，所述堆叠结构包括第二存储区块R0、以及位于所述第二存储区块R0上方的第一存储区块R1；
连接引线，包括长度相等的第一引线15和第二引线16，所述第一引线15位于所述封装基板上方，且所述第一引线15的一端电连接所述第一焊垫11、另一端电连接所述第一存储区块R1，所述第二引线16穿过所述通孔36，且所述第二引线16的一端电连接所述第二焊垫12、另一端电连接所述第二存储区块R0。
本具体实施方式中所述的三维堆叠封装结构可以是但不限于LPDDR。具体来说，所述封装基板可以是但不限于PCB(Printed Circuit Board，印刷电路板)。所述封装基板中具有沿所述第一方向D1贯穿所述基板本体10的所述通孔36，且所述基板本体10沿所述第一方向D1相对的两个表面上分别设置有所述第一焊垫11和所述第二焊垫12。所述堆叠结构位于所述基板本体10的所述第一表面上，且所述堆叠结构覆盖所述通孔36。所述堆叠结构中的所述第一存储区块R1和所述第二存储区块R0均包括多个存储芯片。在一示例中，所述第一存储区块R1中的多个存储芯片与所述第二存储区块R0中的多个存储芯片的种类相同，例如均为DRAM(Dynamic Random Access Memory，动态随机存储器)芯片。本具体实施方式中所述的多个是指两个以上。所述堆叠结构中的所述第二存储区块R0和所述第一存储区块R1沿所述第一方向D1堆叠，且所述第一存储区块R1位于所述第二存储区块R0上方，即在沿所述第一方向D1上，所述第一存储区块R1与所述封装基板之间的距离大于所述第二存储区块R0与所述封装基板之间的距离。
所述连接引线用于电连接所述封装基板与所述堆叠结构，以将来自于外界的控制信号通过所述封装基板传输至所述堆叠结构中的所述第一存储区块R1和所述第二存储区块R0。所述连接引线包括所述第一引线15和所述第二引线16。其中，电连接所述第一存储区块R1和所述第一焊垫11的所述第一引线15位于所述封装基板上方，电连接所述第二存储区块R0和所述第二焊垫12的所述第二引线16穿过所述通孔36与所述第二焊垫12电连接。通过在所述封装基板中设置所述通孔36、且使得所述第二引线16穿过所述通孔36，即可实现所述第一引线15和所述第二引线16长度的相等，无需在所述第一存储区块R1和所述第二存储区块R2中进行绕线设计，也无需在所述封装基板内部的布线层中进行绕线设计，在减小所述第一存储区块R1与所述第二存储区块R0之间信号延迟的同时，也能简化所述第一存储区块R1、所述第二存储区块R0、以及所述封装基板内部的电路设计，减少了信号线之间的串扰，从而改善了三维堆叠封装结构的良率和性能，且不会造成三维堆叠封装结构内部线路复杂度的增加，从而有助于控制所述三维堆叠封装结构的成本。
在一些实施例中，所述三维堆叠封装结构还包括塑封层17，所述塑封层17至少包覆所述堆叠结构、所述第一引线15和所述第二引线16，且所述塑封层17填充满所述通孔36， 以避免外界因素对所述堆叠结构、所述第一引线15和所述第二引线16造成影响。在一示例中，所述塑封层17的材料可以为树脂材料。
本领域技术人员可以根据实际需要调整所述通孔36的孔径，只要能确保所述第二引线16能够穿过所述通孔36即可，本具体实施方式对此不做限定。本领域技术人员可以通过调整所述基板本体10沿所述第一方向D1的厚度、所述第一焊垫11在所述第一表面上的位置和厚度、所述第二焊垫12在所述第二表面上的位置和厚度、所述堆叠结构沿所述第一方向D1的高度等因素，来进一步调整所述第一引线15和所述第二引线16的长度，只要使得所述第一引线15和所述第二引线16的长度相等即可。在一示例中，所述第一引线15和所述第二引线16的材料相同，且所述第一引线15的直径和所述第二引线16的直径相同，从而进一步减小所述第一存储区块R1与所述第二存储区块R0之间的信号延迟。
在一些实施例中，所述堆叠结构沿所述第一方向D1的厚度与所述基板本体10沿所述第一方向D1的厚度相等。
具体来说，由于所述第一引线15位于所述封装基板的上部、且连接所述第一焊垫11和所述第一存储区块R1，因此，所述第一引线15的长度主要取决于所述堆叠结构沿所述第一方向D1的厚度。由于所述第二引线16穿过贯穿所述基板本体10的所述通孔36、且连接所述第二焊垫12和所述第二存储区块R0，因此，所述第二引线16的长度主要取决于所述基板本体10沿所述第一方向D1的厚度。本具体实施方式通过将所述基板本体10沿所述第一方向D1的厚度设置为与所述堆叠结构沿所述第一方向D1的厚度相等，从而可以更为简便的实现所述第一引线15的长度与所述第二引线16的长度相等，简化所述三维堆叠封装结构的制造工艺。举例来说，所述堆叠结构沿所述第一方向D1的厚度和所述基板本体10沿所述第一方向D1的厚度均为300μm。
在一些实施例中，所述封装基板还包括：
第三焊垫13，位于所述第二表面上；
连接柱14，位于所述基板本体10内，所述连接柱14的一端与所述第一焊垫11电连接、另一端与所述第三焊垫13电连接。
具体来说，通过在所述基板本体10内设置沿所述第一方向D1贯穿所述基板本体10的所述连接柱14，通过所述连接柱14电连接所述第一焊垫11和所述第三焊垫13，外界控制信号经所述第三焊垫13、所述连接柱14、所述第一焊垫11和所述第一引线15传输至所述第一存储区块R1。其中，所述第一焊垫11、所述第二焊垫12、所述第三焊垫13和所述连接柱14的材料可以相同，例如均为金属钨或者金属铜等导电材料。在一示例中，所述第三焊垫13表面还设置有焊球37(例如锡焊球)。
为了进一步简化所述三维堆叠封装结构的电路，且减小所述第一存储区块R1内部各存储芯片之间的信号延迟，在一些实施例中，所述第一存储区块R1包括：
多个存储芯片，多个所述存储芯片沿所述第一方向D1堆叠，且相邻的所述存储芯片电连接，所述第一引线15与所述第一存储区块R1中最顶层的所述存储芯片电连接。
在一些实施例中，所述第一存储区R1块包括第一存储芯片34、以及沿第一方向D1位于所述第一存储芯片34上方的第二存储芯片24，所述第一存储芯片34的顶面(正面)与所述第二存储芯片24的顶面(正面)键合连接；
所述第二存储芯片24的底面(背面)与所述第一引线15电连接。
在一些实施例中，所述第一存储芯片34的顶面具有第一键合垫22，所述第二存储芯片24的顶面具有第二键合垫20，所述第一键合垫22与所述第二键合垫20电连接；
所述第二存储芯片24还包括位于所述第二存储芯片24的底面的第一连接垫18、以及沿所述第一方向D1贯穿所述第二存储芯片24的第一信号插塞19，所述第一信号插塞19的一端电连接所述第二键合垫20、另一端电连接所述第一连接垫18，所述第一引线15电连接所述第一连接垫18。
在一些实施例中，所述第一存储芯片R1还包括：
第一导电凸块21，位于所述第一键合垫22背离所述第一信号插塞19的表面，所述第一导电凸块21与所述第二键合垫20键合连接。
具体来说，所述第一存储芯片34包括沿所述第一方向D1相对分布的顶面和底面，所述第二存储芯片24也包括沿所述第一方向D1相对分布的顶面和底面。所述第二存储芯片24和所述第一存储芯片34以面对面的方式键合，即所述第二存储芯片24顶面上的所述第一导电凸块21与所述第一存储芯片34顶面上的所述第一键合垫22键合连接，所述第一引线15与所述第二存储芯片24底面上的所述第一连接垫18直接接触电连接。来自于外界的第一控制信号通过所述第一焊垫11和所述第一引线15传输至所述第二存储芯片24底面上的所述第一连接垫18。之后，所述第一控制信号通过所述第一连接垫18、所述第一信号插塞19和所述第二键合垫20传输至所述第二存储芯片24顶面的半导体结构中，且所述第一控制信号还通过所述第一连接垫18、所述第一信号插塞19、所述第二键合垫20、所述第一导电凸块21和所述第一键合垫22传输至所述第一存储芯片34顶面的半导体结构中，从而减小了所述第一存储区块R1内部的所述第一存储芯片34与所述第二存储芯片24之间的信号延迟，改善了所述第一存储区块R1、以及所述三维堆叠封装结构的电性能。
在一示例中，所述第一键合垫22的数量为多个，且多个所述第一键合垫22沿第二方向D2间隔排布。所述第二键合垫20的数量也为多个，且多个所述第二键合垫20与多个所述第一键合垫22一一对应电连接。所述第二方向D2与所述第一表面平行。
为了增强所述第一存储区块R1内所述第一存储芯片34与所述第二存储芯片24之间的连接强度，同时避免所述第一存储芯片34和所述第二存储芯片24之间残留的空气等气体对所述第一键合垫22、所述第二键合垫20以及所述第一导电凸块21的影响，在一些实施例中，所述第一存储区块R1中还包括：
第一粘结层25，填充满所述第一存储芯片34和所述第二存储芯片24之间的间隙，用于粘结所述第一存储芯片34和所述第二存储芯片24。在一示例中，所述第一粘结层25的材料可以为底部填充胶(underfill)。
在一些实施例中，所述堆叠结构还包括：
第二粘结层30，位于所述第二存储区块R0与所述封装基板之间，所述第二粘结层30中包括沿所述第一方向D1贯穿所述第二粘结层30的沟槽301，所述沟槽301与所述通孔36沿所述第一方向D1对准，所述第二引线16穿过所述沟槽301和所述通孔36。
具体来说，所述第二存储区块R0通过所述第二粘结层30固定于所述基板本体10的所述第一表面，以增强所述第二存储区块R0与所述封装基板之间的连接稳定性。所述第一存储区域R1可以通过第三粘结层33固定于所述第二存储区块R0上方，以增强所述第一存储区块R1与所述第二存储区块R0之间的连接稳定性。在一示例中，所述第二粘结层30的材料与所述第三粘结层33的材料相同，例如均为绝缘粘结材料。在一示例中，所述第二粘结层30的材料和所述第三粘结层33的材料均为芯片粘合膜(Die Attach Film，DAF)。所述第二粘结层30中设置有与所述通孔36对齐的所述沟槽301，从而能够使得所述第二引线16能够自所述第二存储区块R0的底部依次穿过所述沟槽301和所述通孔36之后与所述第二焊垫12电连接。
在一些实施例中，第二粘结层30与第二接触垫29接触，第三粘结层33与存储芯片的背面接触，由此第二粘结层30会接触更多的热量，由此可以使得第二粘结层30的热膨胀系数小于第三粘结层33的热膨胀系数，由于第二粘结层30的热膨胀系数相对较小，由此可以降低存储芯片与基板之间的热膨胀差。在一些实施例中，例如提高第二粘结层30中二氧化硅的浓度，二氧化硅填料的线膨胀系数较小，由此可以提高第二粘结层30的热膨胀系数。
为了进一步简化所述三维堆叠封装结构的电路，且减小所述第二存储区块R0内部各存储芯片之间的信号延迟，在一些实施例中，所述第二存储区块R0包括：
多个存储芯片，多个所述存储芯片沿所述第一方向D1堆叠，且相邻的所述存储芯片电 连接，所述第二引线16与所述第二存储区块R0中最底层的所述存储芯片电连接。
在一些实施例中，所述第二存储区块R0包括第三存储芯片35、以及沿第一方向D1位于所述第三存储芯片35上方的第四存储芯片26，所述第三存储芯片35的顶面与所述第四存储芯片26的顶面键合连接；
所述第三存储芯片35的底面与所述第二引线16电连接。
在一些实施例中，所述第三存储芯片35的顶面具有第三键合垫27，所述第四存储芯片26的顶面具有第四键合垫32，所述第三键合垫27与所述第四键合垫32键合电连接；
所述第三存储芯片35还包括位于所述第三存储芯片35的底面的第二连接垫29、以及沿所述第一方向D1贯穿所述第三存储芯片35的第二信号插塞28，所述第二信号插塞28的一端电连接所述第三键合垫27、另一端电连接所述第二连接垫29，所述第二引线16电连接所述第二连接垫29，且至少一个所述第二连接垫29与所述通孔36沿所述第一方向D1对准。
具体来说，所述第三存储芯片35包括沿所述第一方向D1相对分布的顶面和底面，所述第四存储芯片26也包括沿所述第一方向D1相对分布的顶面和底面。所述第三存储芯片35的顶面上包括第三键合垫27、以及位于所述第三键合垫27表面的第二导电凸块31。所述第三存储芯片35与所述第四存储芯片26以面对面的方式键合，即所述第三存储芯片35顶面上的所述第二导电凸块31与所述第四存储芯片26顶面上的所述第四键合垫32键合连接，穿过所述通孔36和所述沟槽301的所述第二引线16与所述第三存储芯片35底面上的所述第二连接垫29直接接触电连接。
来自于外界的第二控制信号通过所述第二焊垫12和所述第二引线16传输至所述第三存储芯片35底面上的所述第二连接垫29。之后，所述第二控制信号通过所述第二连接垫29、所述第二信号插塞28和所述第三键合垫27传输至所述第三存储芯片35顶面的半导体结构中，且所述第二控制信号还通过所述第二连接垫29、所述第二信号插塞28、所述第三键合垫27、所述第二导电凸块31和所述第四键合垫32传输至所述第四存储芯片26顶面的半导体结构中，从而减小了所述第二存储区块R0内部的所述第三存储芯片35与所述第四存储芯片26之间的信号延迟，改善了所述第二存储区块R0、以及所述三维堆叠封装结构的电性能。
为了增强所述第二存储区块R0内所述第三存储芯片35与所述第四存储芯片26之间的连接强度，同时避免所述第三存储芯片35和所述第四存储芯片26之间残留的空气等气体对所述第三键合垫37、所述第四键合垫32以及所述第二导电凸块31的影响，在一些实施例中，所述第二存储区块R0中还包括：
第四粘结层37，填充满所述第三存储芯片35和所述第四存储芯片26之间的间隙，用于粘结所述第三存储芯片35和所述第四存储芯片26。在一示例中，所述第四粘结层37的材料可以为底部填充胶(underfill)。
本具体实施方式还提供了一种三维堆叠封装结构的形成方法，附图3是本公开具体实施方式中三维堆叠封装结构的形成方法流程图，附图4-附图10是本公开具体实施方式在形成三维堆叠封装结构的过程中主要的工艺结构示意图。本具体实施方式形成的三维堆叠封装结构的示意图可以参见图1和图2。如图1-图10所示，所述三维堆叠封装结构的形成方法，包括如下步骤：
步骤S40，形成封装基板，所述封装基板包括基板本体10、沿第一方向D1贯穿所述基板本体10的通孔36、位于所述基板本体10的第一表面上的第一焊垫11、以及位于所述基板本体10的第二表面上的第二焊垫12，所述第一表面与所述第二表面沿所述第一方向D1相对分布，所述第一方向D1与所述第一表面垂直；
步骤S41，于所述基板本体10的所述第一表面上形成堆叠结构，所述堆叠结构包括第二存储区块R0、以及位于所述第二存储区块R0上方的第一存储区块R1；
步骤S42，形成位于所述封装基板上方且电连接所述第一存储区块R1和所述第一焊垫 11的第一引线15、并形成穿过所述通孔36且电连接所述第二存储区块R0和所述第二焊垫12的第二引线16。第一引线15的长度可以等于第二引线16的长度。
在一些实施例中，形成封装基板的具体步骤包括：
获取所述堆叠结构的预设厚度；
形成基板本体10，且使得所述基板本体10沿所述第一方向D1的厚度与所述预设厚度相等；
形成位于所述基板本体10的所述第一表面上的所述第一焊垫11、位于所述基板本体10的所述第二表面上的所述第二焊垫12和第三焊垫13、以及位于所述基板本体10内且电连接所述第一焊垫11和所述第三焊垫13的连接柱14。
具体来说，可以根据预先设计获取后续预形成的所述堆叠结构的预设厚度。接着，根据所述预设厚度调整所述基板本体10的厚度，使得所述基板本体10的厚度与后续所要形成的所述堆叠结构的厚度相等。之后，于所述基板本体10上形成电路结构，所述电路结构包括位于所述基板本体10的所述第一表面上的所述第一焊垫11、位于所述基板本体10的所述第二表面上的所述第二焊垫12和第三焊垫13、以及位于所述基板本体10内且电连接所述第一焊垫11和所述第三焊垫13的连接柱14。本具体实施方式是以在所述基板本体10内形成所述连接柱14为了进行说明。在其他具体实施方式中，本领域技术人员还可以根据实际需要在所述基板本体10内部形成布线层，通过所述布线层连接所述第一焊垫11和所述第三焊垫13。
在一些实施例中，于所述基板本体10的所述第一表面上形成堆叠结构的具体步骤包括：
形成第一存储区块R1，所述第一存储区块R1包括沿所述第一方向D1堆叠的多个存储芯片，且所述第一存储区块R1中相邻的存储芯片电连接；
形成第二存储区块R0，所述第二存储区R0块沿所述第一方向D1堆叠的多个存储芯片，且所述第一存储区块R1中相邻的存储芯片电连接；
固定所述第二存储区块R0于所述基板本体10的所述第一表面上、并沿所述第一方向D1固定所述第一存储区块R1于所述第二存储区块R0上方。
在一些实施例中，形成第一存储区块R1的具体步骤包括：
形成第一存储芯片34和第二存储芯片24，所述第一存储芯片34的顶面具有第一键合垫22，所述第二存储芯片24的顶面具有第二键合垫20，所述第二存储芯片24还包括位于所述第二存储芯片24的底面的第一连接垫18、以及沿所述第一方向D1贯穿所述第二存储芯片24的第一信号插塞19，所述第一信号插塞19的一端电连接所述第二键合垫20、另一端电连接所述第一连接垫18；
以所述第一键合垫22和所述第二键合垫20相对的方式键合所述第一存储芯片34和所述第二存储芯片24。
在一些实施例中，所述第二存储芯片24还包括位于所述第二键合垫20背离所述第一信号插塞19的表面上的第一导电凸块21；以所述第一键合垫22和所述第二键合垫20相对的方式键合所述第一存储芯片34和所述第二存储芯片24的具体步骤包括：
键合所述第一导电凸块21和所述第一键合垫22；
形成填充满所述第一存储芯片34和所述第二存储芯片24之间的间隙的第一粘结层25。
举例来说，在形成如图4所示的所述第一存储芯片34和如图5所示的所述第二存储芯片24之后，键合所述第一导电凸块21和所述第一键合垫22，以实现所述第一存储芯片34和所述第二存储芯片24之间的键合连接。之后，填充底部填充胶等绝缘粘结剂于所述第一存储芯片34和所述第二存储芯片24之间，以增强所述第一存储芯片34与所述第二存储芯片24之间的连接强度。其中，所述第一存储芯片34和所述第二存储芯片24可以均为DRAM芯片。所述第一键合垫22、所述第二键合垫20、所述第一连接垫18、以及所述第一信号插塞19的材料可以相同，例如均为NiAu合金材料。所述第一导电凸块21的材料可以为Cu、Ni、Sn、Ag中的任一种或者两种以上的材料组成的合金材料。在一示例中，所述第一导电 凸块21的材料为Cu/Ni/Sn/Ag(即Cu、Ni、Sn和Ag组成的合金材料)、Cu/Sn/Ag(即Cu、Sn和Ag组成的合金材料)或者Ni/Sn/Ag(即Ni、Sn和Ag组成的合金材料)。
在一些实施例中，形成第二存储区块R0的具体步骤包括：
形成第三存储芯片35(如图6所示)和第四存储芯片26(如图7所示)，所述第三存储芯片35的顶面具有第三键合垫27，所述第四存储芯片26的顶面具有第四键合垫32，所述第三存储芯片35还包括位于所述第三存储芯片35的底面的第二连接垫29、以及沿所述第一方向D1贯穿所述第三存储芯片35的第二信号插塞28，所述第二信号插塞28的一端电连接所述第三键合垫27、另一端电连接所述第二连接垫29；
以所述第三键合垫27和所述第四键合垫32相对的方式键合所述第三存储芯片35和所述第四存储芯片26。
在一示例中，所述第三存储芯片35还包括位于所述第三键合垫27表面的第二导电凸块31，通过所述第二导电凸块31与所述第四键合垫键合来连接所述第三存储芯片35和所述第四存储芯片26。
在一些实施例中，固定所述第二存储区块R0于所述基板本体10的所述第一表面上、并沿所述第一方向D1固定所述第一存储区块R1于所述第二存储区块R0上方的具体步骤包括：
通过第二粘结层30粘结所述第二存储区块R0中的所述第三存储芯片35与所述基板本体10的所述第一表面，所述第二粘结层30中具有沿所述第一方向D1贯穿所述第二粘结层30且与所述通孔36沿所述第一方向D1对准的沟槽301，至少一个所述第二连接垫29与所述通孔36沿所述第一方向D1对准；
通过第三粘结层33粘结所述第一存储区块R1中的所述第一存储芯片34和所述第四存储芯片26。
具体来说，通过所述第二粘结层30将所述第三存储芯片35固定于所述封装基板的所述基板本体10的所述第一表面上，且使得所述第三存储芯片35中的所述至少一个所述第二连接垫29与所述通孔36沿所述第一方向D1对准。所述第二粘结层30中具有沿所述第一方向D1贯穿所述第二粘结层30的沟槽301，且所述沟槽301与所述通孔36对准，至少一个所述第二连接垫29的位置与所述沟槽301的位置对准，即至少一个所述第二连接垫29通过所述沟槽301暴露。之后，通过键合工艺键合所述第三存储芯片35中的所述第二导电凸块31与所述第四存储芯片26中的所述第四键合垫32，形成如图8所示的结构。之后，形成填充满所述第三存储芯片35与所述第四存储芯片26之间间隙的第四粘结层37。接着，将已形成的所述第一存储区块R1通过第三粘结层33与所述第四存储芯片26的底面连接，形成如图9所示的结构。
在其他具体实施方式中，还可以在形成如图8所示的结构之后，先通过所述第三粘结层33固定连接所述第一存储芯片34和所述第四存储芯片26，之后再通过键合工艺键合所述第二存储芯片24与所述第一存储芯片34。
在一些实施例中，形成位于所述封装基板上方且电连接所述第一存储区块R1和所述第一焊垫11的第一引线15、并形成穿过所述通孔36且电连接所述第二存储区块R0和所述第二焊垫12的第二引线16的具体步骤包括：
形成位于所述封装基板上方且电连接所述第一连接垫18和所述第一焊垫11的所述第一引线15；
形成穿过所述通孔36和所述沟槽301、且电连接所述第二连接垫29和所述第二焊垫12的所述第二引线16，如图10所示。
在形成所述第一引线15和所述第二引线16之后，可以通过塑封工艺形成至少包覆所述堆叠结构、所述第一引线15和所述第二引线16的所述塑封层17，且所述塑封层17填充满所述通孔36，以避免外界因素对所述堆叠结构、所述第一引线15和所述第二引线16造成影响。之后，还可以在所述第三焊垫13的表面形成焊球37，以构成LPDDR产品。
在一些实施例中，塑封层17可包括环氧材料以及分散在环氧材料中的填料，填料例如为二氧化硅。第四粘结层37可包括环氧树脂以及分散在环氧树脂中的填料，填料例如为二氧化硅。由于第三存储芯片26与第四存储芯片35之间的间隙较小，由此可以提高第四粘结层37的流动性，从而避免在第三存储芯片26与第四存储芯片35之间存在气泡，例如使得第四粘结层37内的填料的含量低于塑封层17中填料的含量，从而提高第四粘结层37的填充效果。当然，也可以使得第四粘结层37中填料的体积小于塑封层17中填料的体积，由于填料体积较小，第四粘结层37的流动性较强，从而提高第四粘结层37的填充效果。
本具体实施方式一些实施例提供的三维堆叠封装结构及其形成方法，通过在封装基板的内部形成沿第一方向贯穿封装基板的通孔，使得封装基板上的第二存储区块通过穿过所述通孔的第二引线与封装基板电连接，位于所述第二存储区块上方的第一存储区块通过位于所述封装基板上方的第一引线与所述封装基板电连接，从而能够使得无需通过在第一存储区块、第二存储区块或者所述封装基板内部绕线即可实现所述第一引线的长度与所述第二引线的长度相等，进而在降低不同存储区块之间信号延迟的同时，减少了引线等信号线之间的串扰，从而改善了三维堆叠封装结构的良率和性能，且不会造成三维堆叠封装结构内部线路复杂度的增加，从而有助于控制所述三维堆叠封装结构的成本。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (20)

  1. 一种三维堆叠封装结构，包括：
    封装基板，包括基板本体、沿第一方向贯穿所述基板本体的通孔、位于所述基板本体的第一表面上的第一焊垫、以及位于所述基板本体的第二表面上的第二焊垫，所述第一表面与所述第二表面沿所述第一方向相对分布，所述第一方向与所述第一表面垂直；
    堆叠结构，位于所述基板本体的所述第一表面上，所述堆叠结构包括第二存储区块、以及位于所述第二存储区块上方的第一存储区块；
    连接引线，包括长度相等的第一引线和第二引线，所述第一引线位于所述封装基板上方，且所述第一引线的一端电连接所述第一焊垫、另一端电连接所述第一存储区块，所述第二引线穿过所述通孔，且所述第二引线的一端电连接所述第二焊垫、另一端电连接所述第二存储区块。
  2. 根据权利要求1所述的三维堆叠封装结构，其中，所述堆叠结构沿所述第一方向的厚度与所述基板本体沿所述第一方向的厚度相等。
  3. 根据权利要求1所述的三维堆叠封装结构，其中，所述封装基板还包括：
    第三焊垫，位于所述第二表面上；
    连接柱，位于所述基板本体内，所述连接柱的一端与所述第一焊垫电连接、另一端与所述第三焊垫电连接。
  4. 根据权利要求1所述的三维堆叠封装结构，其中，所述第一存储区块包括：
    多个存储芯片，多个所述存储芯片沿所述第一方向堆叠，且相邻的所述存储芯片电连接，所述第一引线与所述第一存储区块中最顶层的所述存储芯片电连接。
  5. 根据权利要求4所述的三维堆叠封装结构，其中，所述第一存储区块包括第一存储芯片、以及沿第一方向位于所述第一存储芯片上方的第二存储芯片，所述第一存储芯片的顶面与所述第二存储芯片的顶面键合连接；
    所述第二存储芯片的底面与所述第一引线电连接。
  6. 根据权利要求5所述的三维堆叠封装结构，其中，所述第一存储芯片的顶面具有第一键合垫，所述第二存储芯片的顶面具有第二键合垫，所述第一键合垫与所述第二键合垫电连接；
    所述第二存储芯片还包括位于所述第二存储芯片的底面的第一连接垫、以及沿所述第一方向贯穿所述第二存储芯片的第一信号插塞，所述第一信号插塞的一端电连接所述第二键合垫、另一端电连接所述第一连接垫，所述第一引线电连接所述第一连接垫。
  7. 根据权利要求6所述的三维堆叠封装结构，其中，所述第一存储芯片还包括：
    第一导电凸块，位于所述第一键合垫背离所述第一信号插塞的表面，所述第一导电凸块与所述第二键合垫键合连接。
  8. 根据权利要求6所述的三维堆叠封装结构，其中，所述第一存储区块中还包括：
    第一粘结层，填充满所述第一存储芯片和所述第二存储芯片之间的间隙，用于粘结所述第一存储芯片和所述第二存储芯片。
  9. 根据权利要求1所述的三维堆叠封装结构，其中，所述堆叠结构还包括：
    第二粘结层，位于所述第二存储区块与所述封装基板之间，所述第二粘结层中包括沿所述第一方向贯穿所述第二粘结层的沟槽，所述沟槽与所述通孔沿所述第一方向对准，所述第二引线穿过所述沟槽和所述通孔。
  10. 根据权利要求9所述的三维堆叠封装结构，其中，所述第二存储区块包括：
    多个存储芯片，多个所述存储芯片沿所述第一方向堆叠，且相邻的所述存储芯片电连接，所述第二引线与所述第二存储区块中最底层的所述存储芯片电连接。
  11. 根据权利要求10所述的三维堆叠封装结构，其中，所述第二存储区块包括第三存储芯片、以及沿第一方向位于所述第三存储芯片上方的第四存储芯片，所述第三存储芯片的顶面与所述第四存储芯片的顶面键合连接；
    所述第三存储芯片的底面与所述第二引线电连接。
  12. 根据权利要求11所述的三维堆叠封装结构，其中，所述第三存储芯片的顶面具有第三键合垫，所述第四存储芯片的顶面具有第四键合垫，所述第三键合垫与所述第四键合垫键合电连接；
    所述第三存储芯片还包括位于所述第三存储芯片的底面的第二连接垫、以及沿所述第一方向贯穿所述第三存储芯片的第二信号插塞，所述第二信号插塞的一端电连接所述第三键合垫、另一端电连接所述第二连接垫，所述第二引线电连接所述第二连接垫，且至少一个所述第二连接垫与所述通孔沿所述第一方向对准。
  13. 一种三维堆叠封装结构的形成方法，包括如下步骤：
    形成封装基板，所述封装基板包括基板本体、沿第一方向贯穿所述基板本体的通孔、位于所述基板本体的第一表面上的第一焊垫、以及位于所述基板本体的第二表面上的第二焊垫，所述第一表面与所述第二表面沿所述第一方向相对分布，所述第一方向与所述第一表面垂直；
    于所述基板本体的所述第一表面上形成堆叠结构，所述堆叠结构包括第二存储区块、以及位于所述第二存储区块上方的第一存储区块；
    形成位于所述封装基板上方且电连接所述第一存储区块和所述第一焊垫的第一引线、并形成穿过所述通孔且电连接所述第二存储区块和所述第二焊垫的第二引线。
  14. 根据权利要求13所述的三维堆叠封装结构的形成方法，其中，形成封装基板的具体步骤包括：
    获取所述堆叠结构的预设厚度；
    形成基板本体，且使得所述基板本体沿所述第一方向的厚度与所述预设厚度相等；
    形成位于所述基板本体的所述第一表面上的所述第一焊垫、位于所述基板本体的所述第二表面上的所述第二焊垫和第三焊垫、以及位于所述基板本体内且电连接所述第一焊垫和所述第三焊垫的连接柱。
  15. 根据权利要求13所述的三维堆叠封装结构的形成方法，其中，于所述基板本体的所述第一表面上形成堆叠结构的具体步骤包括：
    形成第一存储区块，所述第一存储区块包括沿所述第一方向堆叠的多个存储芯片，且所述第一存储区块中相邻的存储芯片电连接；
    形成第二存储区块，所述第二存储区块沿所述第一方向堆叠的多个存储芯片，且所述第一存储区块中相邻的存储芯片电连接；
    固定所述第二存储区块于所述基板本体的所述第一表面上、并沿所述第一方向固定所述第一存储区块于所述第二存储区块上方。
  16. 根据权利要求15所述的三维堆叠封装结构的形成方法，其中，形成第一存储区块的具体步骤包括：
    形成第一存储芯片和第二存储芯片，所述第一存储芯片的顶面具有第一键合垫，所述第二存储芯片的顶面具有第二键合垫，所述第二存储芯片还包括位于所述第二存储芯片的底面的第一连接垫、以及沿所述第一方向贯穿所述第二存储芯片的第一信号插塞，所述第一信号插塞的一端电连接所述第二键合垫、另一端电连接所述第一连接垫；
    以所述第一键合垫和所述第二键合垫相对的方式键合所述第一存储芯片和所述第二存储芯片。
  17. 根据权利要求16所述的三维堆叠封装结构的形成方法，其中，所述第二存储芯片还包括位于所述第二键合垫背离所述第一信号插塞的表面上的第一导电凸块；以所述第一键合垫和所述第二键合垫相对的方式键合所述第一存储芯片和所述第二存储芯片的具体步骤包括：
    键合所述第一导电凸块和所述第一键合垫；
    形成填充满所述第一存储芯片和所述第二存储芯片之间的间隙的第一粘结层。
  18. 根据权利要求16所述的三维堆叠封装结构的形成方法，其中，形成第二存储区块的具 体步骤包括：
    形成第三存储芯片和第四存储芯片，所述第三存储芯片的顶面具有第三键合垫，所述第四存储芯片的顶面具有第四键合垫，所述第三存储芯片还包括位于所述第三存储芯片的底面的第二连接垫、以及沿所述第一方向贯穿所述第三存储芯片的第二信号插塞，所述第二信号插塞的一端电连接所述第三键合垫、另一端电连接所述第二连接垫；
    以所述第三键合垫和所述第四键合垫相对的方式键合所述第三存储芯片和所述第四存储芯片。
  19. 根据权利要求18所述的三维堆叠封装结构的形成方法，其中，固定所述第二存储区块于所述基板本体的所述第一表面上、并沿所述第一方向固定所述第一存储区块于所述第二存储区块上方的具体步骤包括：
    通过第二粘结层粘结所述第二存储区块中的所述第三存储芯片与所述基板本体的所述第一表面，所述第二粘结层中具有沿所述第一方向贯穿所述第二粘结层且与所述通孔沿所述第一方向对准的沟槽，至少一个所述第二连接垫与所述通孔沿所述第一方向对准；
    通过第三粘结层粘结所述第一存储区块中的所述第一存储芯片和所述第四存储芯片。
  20. 根据权利要求19所述的三维堆叠封装结构的形成方法，其中，形成位于所述封装基板上方且电连接所述第一存储区块和所述第一焊垫的第一引线、并形成穿过所述通孔且电连接所述第二存储区块和所述第二焊垫的第二引线的具体步骤包括：
    形成位于所述封装基板上方且电连接所述第一连接垫和所述第一焊垫的所述第一引线；
    形成穿过所述通孔和所述沟槽、且电连接所述第二连接垫和所述第二焊垫的所述第二引线。
PCT/CN2022/128970 2022-08-08 2022-11-01 三维堆叠封装结构及其形成方法 Ceased WO2024031848A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/547,152 US20250006702A1 (en) 2022-08-08 2022-11-01 Three-dimensional Stack Package Structure And Method Making The Same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210944874.7 2022-08-08
CN202210944874.7A CN117577634A (zh) 2022-08-08 2022-08-08 三维堆叠封装结构及其形成方法

Publications (1)

Publication Number Publication Date
WO2024031848A1 true WO2024031848A1 (zh) 2024-02-15

Family

ID=89850480

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/128970 Ceased WO2024031848A1 (zh) 2022-08-08 2022-11-01 三维堆叠封装结构及其形成方法

Country Status (3)

Country Link
US (1) US20250006702A1 (zh)
CN (1) CN117577634A (zh)
WO (1) WO2024031848A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020180057A1 (en) * 2001-05-31 2002-12-05 I-Tseng Lee Chip stack-type semiconductor package
CN2543206Y (zh) * 2002-03-26 2003-04-02 胜开科技股份有限公司 内存芯片堆栈构造
US20060284298A1 (en) * 2005-06-15 2006-12-21 Jae Myun Kim Chip stack package having same length bonding leads
US20110291295A1 (en) * 2010-05-27 2011-12-01 Elpida Memory, Inc. Semiconductor device
CN103943615A (zh) * 2014-05-13 2014-07-23 山东华芯半导体有限公司 一种dram双芯片堆叠封装结构和封装方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004063767A (ja) * 2002-07-29 2004-02-26 Renesas Technology Corp 半導体装置
JP2011258687A (ja) * 2010-06-08 2011-12-22 Renesas Electronics Corp 半導体装置およびその製造方法
KR20150085384A (ko) * 2014-01-15 2015-07-23 삼성전자주식회사 반도체 패키지 및 그 제조방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020180057A1 (en) * 2001-05-31 2002-12-05 I-Tseng Lee Chip stack-type semiconductor package
CN2543206Y (zh) * 2002-03-26 2003-04-02 胜开科技股份有限公司 内存芯片堆栈构造
US20060284298A1 (en) * 2005-06-15 2006-12-21 Jae Myun Kim Chip stack package having same length bonding leads
US20110291295A1 (en) * 2010-05-27 2011-12-01 Elpida Memory, Inc. Semiconductor device
CN103943615A (zh) * 2014-05-13 2014-07-23 山东华芯半导体有限公司 一种dram双芯片堆叠封装结构和封装方法

Also Published As

Publication number Publication date
CN117577634A (zh) 2024-02-20
US20250006702A1 (en) 2025-01-02

Similar Documents

Publication Publication Date Title
US7598617B2 (en) Stack package utilizing through vias and re-distribution lines
US20040070083A1 (en) Stacked flip-chip package
US9754927B2 (en) Method for fabricating multi-chip stack structure
KR102532205B1 (ko) 반도체 칩 및 그 반도체 칩을 포함한 반도체 패키지
US20050212114A1 (en) Semiconductor device
CN102790042A (zh) 半导体芯片堆叠构造
TW408467B (en) Semiconductor device having adhesive between lead and chip, and method of manufacture thereof
CN115472583A (zh) 一种硅基三维集成扇出型封装结构及其制造方法
US12170266B2 (en) Semiconductor package
CN101872749A (zh) 凹穴芯片封装结构及使用其的层叠封装结构
CN101452860B (zh) 多芯片堆叠结构及其制法
WO2024031848A1 (zh) 三维堆叠封装结构及其形成方法
TWI711131B (zh) 晶片封裝結構
CN101236962A (zh) 多芯片堆叠结构及其制法
CN217955850U (zh) 一种硅基三维集成扇出型封装结构
CN101452861B (zh) 多芯片堆叠结构及其制法
CN116169035A (zh) 倒装芯片与正装芯片的芯片间可互联堆叠结构的制备方法
CN101355040B (zh) 多芯片堆叠结构及其制法
CN101667545B (zh) 多芯片堆叠结构及其制法
CN203277377U (zh) 一种dram双芯片堆叠封装结构
CN118866828B (zh) 2.5d封装结构和2.5d封装方法
CN222838850U (zh) 芯片封装结构
CN105742283B (zh) 倒置堆叠封装件
CN103943615A (zh) 一种dram双芯片堆叠封装结构和封装方法
CN219393394U (zh) 基于双裸芯堆叠的dram模组封装结构

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 18547152

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22954788

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 22954788

Country of ref document: EP

Kind code of ref document: A1