WO2024026634A1 - 显示基板、其制作方法、中板及电子纸显示装置 - Google Patents

显示基板、其制作方法、中板及电子纸显示装置 Download PDF

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Publication number
WO2024026634A1
WO2024026634A1 PCT/CN2022/109500 CN2022109500W WO2024026634A1 WO 2024026634 A1 WO2024026634 A1 WO 2024026634A1 CN 2022109500 W CN2022109500 W CN 2022109500W WO 2024026634 A1 WO2024026634 A1 WO 2024026634A1
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Prior art keywords
transistor
electrostatic ring
transfer
electrically connected
test
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PCT/CN2022/109500
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English (en)
French (fr)
Inventor
程浩
池彦菲
刘承俊
林剑涛
林琳琳
刘耀
刘祖文
石常洪
王进
Original Assignee
京东方科技集团股份有限公司
福州京东方光电科技有限公司
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Priority to PCT/CN2022/109500 priority Critical patent/WO2024026634A1/zh
Publication of WO2024026634A1 publication Critical patent/WO2024026634A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a manufacturing method thereof, a mid-board and an electronic paper display device.
  • ETD Electronic paper
  • the embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, a mid-board, and an electronic paper display device.
  • the specific solutions are as follows:
  • embodiments of the present disclosure provide a display substrate, including:
  • a base substrate which includes a display area and a frame area located on at least one side of the display area;
  • a plurality of sub-test terminals located in the frame area including a common voltage sub-test terminal and a plurality of non-common voltage sub-test terminals;
  • a first electrostatic ring is located in the frame area, and the plurality of non-common voltage sub-test terminals are arranged in series and/or grounded through the first electrostatic ring.
  • the first electrostatic ring is electrically connected between two adjacent non-common voltage sub-test terminals.
  • the above display substrate provided by the embodiment of the present disclosure further includes a second electrostatic ring, the second electrostatic ring is electrically connected between the common voltage sub-test terminal and the adjacent non-common voltage between sub-test terminals;
  • Both the second electrostatic ring and the first electrostatic ring include a plurality of transistors electrically connected to each other, and the channel width-to-length ratio of the transistors included in the second electrostatic ring is smaller than the channel width-to-length ratio of the transistors included in the first electrostatic ring. Road width to length ratio.
  • the first electrostatic ring includes a first connection end and a second connection end
  • the first electrostatic ring includes four transistors, wherein the gate electrode of the first transistor, the first electrode of the first transistor, and the first electrode of the second transistor are electrically connected together as the first connection end;
  • the second terminal of the first transistor, the second terminal of the second transistor, the gate of the second transistor, the gate of the third transistor, the first terminal of the third transistor, the first terminal of the fourth transistor The gate electrode of the fourth transistor, the second electrode of the fourth transistor, and the second electrode of the third transistor are electrically connected together as the second connection end.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes a transfer electrode located on the layer where the first electrostatic ring is located, and the transfer electrode is connected to the second layer of the first transistor respectively.
  • pole, the second pole of the second transistor, the gate of the second transistor, the gate of the third transistor, the first pole of the third transistor, and the first pole of the fourth transistor are electrically connected.
  • the above display substrate provided by the embodiment of the present disclosure also includes a pixel electrode located on the layer where the first electrostatic ring is located, and the transfer electrode is in the same layer and material as the pixel electrode. set up.
  • the electrical connection between the plurality of transistors in the second electrostatic ring is different from the electrical connection between the plurality of transistors in the first electrostatic ring. Same way.
  • the above display substrate provided by the embodiment of the present disclosure further includes a plurality of first transfer terminals, and one first transfer terminal is electrically connected to one of the sub-test terminals.
  • the first electrostatic ring is electrically connected to the non-common voltage sub-test terminal through the first transfer terminal.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes a pixel electrode located on the layer where the first electrostatic ring is located, and the plurality of first transfer terminals are co-located with the pixel electrode. Layer, same material settings.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure also includes a ground wire located in the frame area, and each of the non-common voltage sub-test terminals is electrically connected to each of the non-common voltage sub-test terminals through the first electrostatic ring.
  • the ground wire located in the frame area, and each of the non-common voltage sub-test terminals is electrically connected to each of the non-common voltage sub-test terminals through the first electrostatic ring.
  • an embodiment of the present disclosure provides a midplane, which includes a plurality of display substrates.
  • the display substrates are the above-mentioned display substrates provided by the embodiments of the present disclosure.
  • the above-mentioned midplane provided by the embodiment of the present disclosure also includes: a plurality of test terminals and a third electrostatic ring located on one side of the area where the plurality of display substrates are located, wherein the plurality of test terminals
  • the terminals include a public voltage test terminal and a non-public voltage test terminal, the common voltage test terminal is electrically connected to the common voltage sub-test terminal, the non-public voltage test terminal is electrically connected to the non-common voltage sub-test terminal, so
  • the third electrostatic ring is electrically connected between the common voltage test terminal and the non-common voltage test terminal.
  • the number of the non-public voltage test terminals is multiple, and at least two of the non-public voltage test terminals are connected through the third electrostatic ring respectively. to the common voltage test terminal.
  • the structure of the third electrostatic ring is the same as the structure of the first electrostatic ring.
  • the plurality of test terminals and the plurality of sub-test terminals are arranged in the same layer and in the same material as the gates of the plurality of transistors.
  • the above-mentioned midplane provided by the embodiments of the present disclosure also includes a plurality of first connection lines, a plurality of second connection lines and a plurality of first transfer lines, wherein the plurality of first connection lines
  • the lines and the plurality of second connecting lines are arranged on the same layer and in the same material, the plurality of first connecting lines and the plurality of first connecting lines are arranged on different layers; one of the first connecting lines passes through one of the first connecting lines.
  • a transfer terminal is electrically connected to one of the sub-test terminals, one of the second connection lines is electrically connected to one of the test terminals, and one of the first transfer lines is electrically connected to one of the first connection lines and one of the test terminals. between the second connecting lines.
  • the above-mentioned midplane provided by the embodiment of the present disclosure also includes a plurality of second transfer lines, a plurality of third transfer lines and a fourth transfer line, and one of the non-public voltage test terminals passes through a
  • the second transfer wire is electrically connected to the corresponding second connection wire.
  • One of the second transfer wires is electrically connected to one of the third transfer wires through one of the third electrostatic rings.
  • the plurality of third transfer wires are electrically connected to each other.
  • the adapter wire is electrically connected to the fourth adapter wire, and the common voltage test terminal is electrically connected to the corresponding second connection wire through the fourth adapter wire.
  • the plurality of third patch cords and the fourth patch cords are integrally provided.
  • the above-mentioned midplane provided by embodiments of the present disclosure further includes a fourth electrostatic ring, and the plurality of third transfer lines are electrically connected to the fourth transfer lines through the fourth electrostatic ring.
  • the structure of the fourth electrostatic ring is the same as the structure of the first electrostatic ring.
  • the above-mentioned midplane provided by the embodiments of the present disclosure also includes a pixel electrode located on the layer where the first electrostatic ring is located, the first transfer line, the second transfer line, the The third transfer line and the fourth transfer line are arranged in the same layer and material as the pixel electrode.
  • the above-mentioned midplane provided by the embodiment of the present disclosure further includes a plurality of second transfer terminals, and one second transfer terminal is electrically connected to one of the test terminals.
  • the above-mentioned midplane provided by the embodiments of the present disclosure further includes a pixel electrode located on the layer where the first electrostatic ring is located, and the plurality of second transfer terminals are co-located with the pixel electrode. Layer, same material settings.
  • the above-mentioned midplane provided by the embodiment of the present disclosure further includes shorting rods and a plurality of high-resistance lines.
  • the high-resistance lines are located between the second transfer terminals.
  • One of the high-resistance lines is The resistance wire is provided integrally with one of the second transfer terminals, and one of the test terminals is electrically connected to the short-circuit rod through one of the high-resistance wires, and the short-circuit rod is arranged in the air.
  • embodiments of the present disclosure provide a method for manufacturing a display substrate, including:
  • the middle plate is cut to obtain the display substrate.
  • the display substrate includes a base substrate, which includes a display area and a frame area located on at least one side of the display area.
  • the frame area A plurality of sub-test terminals and a plurality of first electrostatic rings are provided, the plurality of sub-test terminals include a common voltage sub-test terminal and a plurality of non-common voltage sub-test terminals, the plurality of non-common voltage sub-test terminals pass through the first
  • An electrostatic ring is set in series and/or grounded.
  • embodiments of the present disclosure provide an electronic paper display device, including an opposite display substrate and a counter substrate, and an electrophoretic layer located between the display substrate and the counter substrate; wherein, the display The substrate is the above-mentioned display substrate provided by the embodiment of the present disclosure.
  • Figure 1 is a schematic diagram of anti-static in related technologies
  • Figure 2 is a schematic diagram of the circuit for chip induction to normally obtain the public voltage
  • Figure 3 is the circuit schematic diagram of the chip sensing abnormality to obtain the public voltage
  • Figure 4 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 5 is an anti-static schematic diagram provided by an embodiment of the present disclosure.
  • Figure 6 is another anti-static schematic diagram provided by an embodiment of the present disclosure.
  • Figure 7 is another structural schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • Figure 8 is a circuit diagram of an electrostatic ring provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic structural diagram of an electrostatic ring provided by an embodiment of the present disclosure.
  • Figure 10 is a cross-sectional view along the direction a-a’ in Figure 9;
  • Figure 11 is a cross-sectional view along the b-b’ direction in Figure 9;
  • Figure 12 is a cross-sectional view along the c-c’ direction in Figure 9;
  • Figure 13 is a schematic structural diagram of a sub-pixel in a display substrate provided by an embodiment of the present disclosure.
  • Figure 14 is a schematic diagram of anti-static on a display substrate provided by an embodiment of the present disclosure.
  • Figure 15 is an enlarged schematic diagram of the Z 1 area in Figure 14;
  • Figure 16 is a schematic structural diagram of a middle plate provided by an embodiment of the present disclosure.
  • Figure 17 is a schematic diagram of an anti-static device on the mid-board provided by an embodiment of the present disclosure.
  • Figure 18 is another anti-static schematic diagram of the mid-board provided by an embodiment of the present disclosure.
  • Figure 19 is an enlarged schematic diagram of the Z 2 area in Figure 18;
  • Figure 20 is an enlarged schematic diagram of the Z 3 area in Figure 19;
  • Figure 21 is another structural schematic diagram of the middle plate provided by an embodiment of the present disclosure.
  • FIG. 22 is a schematic connection diagram of the second connection line, the third connection line, and the fourth adapter line provided by the embodiment of the present disclosure.
  • the manufacturing process of display substrates included in electronic paper products includes the following steps: preparing multiple display substrates on large-size substrates to form large panels; cutting the large panels into multiple medium panels to facilitate shipment; to prevent the shipping process
  • the middle plate is scratched and a blue film is screen-printed on the middle plate; after cutting the middle plate, a display substrate of the target size can be obtained.
  • a sub-test terminal and a test transistor are provided on a display substrate.
  • the sub-test terminal is electrically connected to the first electrode (such as the source) of the test transistor, and the second electrode (such as the drain) of the test transistor is connected to the signal line.
  • the test terminals on the middle board provide test signals for the sub-test terminals, and control the test transistors to turn on through the chip to conduct electrical testing of the signal lines; during user use, the test transistors remain normally off and will not affect the normal display.
  • Static electricity is easily generated during the silk screen printing process and film tearing process of blue film.
  • the test transistor may be damaged due to static electricity and may turn on abnormally, thus affecting the normal operation of the electronic paper product.
  • each non-public voltage sub-test terminal such as ET SW , ET GE , ET GO
  • ER electrostatic ring
  • the common voltage line ( Vcom ) is integrated with the test terminal (ET Vcom).
  • the test terminals (such as ET SW , ET GE , ET GO ) must be connected to each non-common voltage sub-test terminal.
  • the electrostatic ring (ER) opens under the high voltage of static electricity, so that the static electricity can be released to the larger common voltage line (Vcom) through the electrostatic ring (ER), thereby dispersing the static electricity. influence to avoid abnormal turning on of the test transistor due to static electricity.
  • the common voltage of electronic paper products plays the role of offsetting ⁇ V pixel during the display process, so that the charged particles (such as microspheres) in the three colors of black, white and red can be at a normal target display voltage.
  • C gs represents the overlapping capacitance of the gate g and source s of the pixel transistor
  • V gh represents the gate turn-on voltage of the pixel transistor
  • V gl represents the gate turn-off voltage of the pixel transistor
  • C paper film represents the pixel electrode (P)
  • Cst represents the storage capacitance.
  • the common voltage of electronic paper products is obtained through chip sensing (IC Sensing).
  • the public voltage obtained through chip induction has problems such as being too large and fluctuating seriously.
  • the inventor has studied the chip sensing mechanism of electronic paper products and analyzed its influencing factors.
  • the research shows that during the chip sensing stage, as shown in Figure 2, the common electrode (Com) should be in the floating state ( Floating) state, but as shown in Figure 3, the non-common voltage sub-test terminals (such as ET SW , ET GE , ET GO ) have leakage to the common electrode (Com) through the electrostatic ring (ER), causing the common voltage induced by the chip
  • the C paper film becomes smaller and the ⁇ V pixel becomes larger, so the final common voltage used to offset the ⁇ V pixel during the display process is too large.
  • a display substrate as shown in Figures 4 to 7, including:
  • the base substrate 101 includes a display area AA and a frame area BB located on at least one side of the display area AA; optionally, the base substrate 101 can be a flexible substrate such as polyimide or glass, etc. rigid substrate;
  • Multiple sub-test terminals (such as ET DE , ET DO , ET GE , ET GO , ET SW , ET Vcom ) are located in the border area BB.
  • the multiple sub-test terminals include the common voltage sub-test terminal ET Vcom and multiple non-common voltage sub-tests.
  • Terminals such as ET DE , ET DO , ET GE , ET GO , ET SW
  • ET Vcom provides test signals for the common voltage line Vcom
  • ET DE provides test signals for the even-numbered column data lines
  • ET DO provides the odd-numbered column data lines
  • ET GE provides test signals for even-numbered row gate lines
  • ET GO provides test signals for odd-numbered row gate lines
  • ET SW provides test signals for the first pole of the test transistor;
  • the common voltage line Vcom is in the border area BB is set in the entire circle.
  • the common voltage line Vcom in order to reduce the resistance of the common voltage line Vcom, can be set as a double-layer wiring structure on the gate metal layer and the source-drain metal layer, and the common voltage line of the gate metal layer
  • the voltage line Vcom and the common voltage line Vcom of the source-drain metal layer can be connected through a via hole penetrating the gate insulating layer (GI);
  • the first electrostatic ring 102 is located in the frame area BB, and each non-common voltage sub-test terminal (such as ET DE , ET DO , ET GE , ET GO , ET SW ) is set in series and/or grounded through the first electrostatic ring 102; it can be Optionally, in Figures 4 to 6, the first electrostatic ring 102 is electrically connected between two adjacent non-common voltage sub-test terminals (such as ET DE , ET DO , ET GE , ET GO , ET SW ); in In FIG. 7 , the first electrostatic ring 102 is electrically connected between the non-common voltage sub-test terminals (eg ET DE , ET DO , ET GE , ET GO , ET SW ) and the ground wire 103 .
  • each non-common voltage sub-test terminal such as ET DE , ET DO , ET GE , ET GO , ET SW
  • each non-common voltage sub-test terminal (such as ET DE , ET DO , ET GE , ET GO , ET SW ) is arranged in series using the first electrostatic ring 102 and/or is grounded It is set so that when there is too much static electricity accumulated on each non-common voltage sub-test terminal (such as ET DE , ET DO , ET GE , ET GO , ET SW ), the first electrostatic ring 102 is opened under the high voltage of static electricity, and each non-common voltage test terminal A path is formed between the common voltage sub-test terminals (such as ET DE , ET DO , ET GE , ET GO , ET SW ), thus increasing the electrostatic transmission path, effectively dispersing static electricity, and reducing the risk of static electricity pairing with non-public voltage sub-tests.
  • each non-common voltage sub-test terminal such as ET DE , ET DO , ET GE , ET GO , ET SW
  • the terminal ET SW is electrically connected to the test transistor and improves the anti-static capability of the product.
  • the first electrostatic ring 102 is connected in series between the non-common voltage sub-test terminals (such as ET DE , ET DO , ET GE , ET GO , ET SW ), and/or, the first electrostatic ring 102 is connected Between the non-common voltage sub-test terminals (such as ET DE , ET DO , ET GE , ET GO , ET SW ) and the ground (such as the ground wire 103), therefore, it will not cause interference to the signal on the common electrode line Vcom , thereby preventing the common electrode (Com) electrically connected to the common electrode line Vcom from leaking through the first electrostatic ring 102, thereby ensuring the accuracy of the public voltage obtained through chip induction.
  • the non-common voltage sub-test terminals such as ET DE , ET DO , ET GE , ET GO , ET SW
  • a second electrostatic ring 104 may also be included.
  • the second electrostatic ring 104 is electrically connected between the common voltage sub-test terminal ET Vcom and the phase. Between adjacent non-common voltage sub-test terminals (such as any one of ET DE , ET DO , ET GE , ET GO , and ET SW ); the second electrostatic ring 104 and the first electrostatic ring 102 both include a plurality of electrically connected to each other.
  • the channel width to length ratio of each transistor included in the second electrostatic ring 104 is the same,
  • the channel width to length ratio of each transistor included in the first electrostatic ring 102 is the same, and the channel width to length ratio of the transistors included in the second electrostatic ring 104 is smaller than the channel width to length ratio of the transistors included in the first electrostatic ring 102 .
  • the second electrostatic ring 104 can be arranged such that there is no connection between the common voltage sub-test terminal ET Vcom and the adjacent non-common voltage sub-test terminal (such as any one of ET DE , ET DO , ET GE , ET GO and ET SW ).
  • the second electrostatic ring 104 When the static electricity accumulates too much, the second electrostatic ring 104 is opened under the high voltage of static electricity, thereby increasing the electrostatic release path and further reducing the impact of static electricity on the test transistor; and, because the second electrostatic ring 104 contains The channel width-to-length ratio of the transistor is smaller than the channel width-to-length ratio of the transistor included in the first electrostatic ring 102, which can make the leakage current of the transistor included in the second electrostatic ring 104 smaller, thereby reducing the leakage current of the second electrostatic ring 104 as much as possible. Effect on the public voltage obtained by chip induction.
  • the channel width to length ratio of the transistors included in the first electrostatic ring 102 is 15/28.5
  • the channel width to length ratio of the transistors included in the second electrostatic ring 104 is greater than 15/60 and less than 15/28.5, for example, the second The channel width to length ratio of the transistors included in the electrostatic ring 104 is 15/40.
  • the test signal voltage loaded on each sub-test terminal (such as ET DE , ET DO , ET GE , ET GO , ET SW , ET Vcom ) is much smaller than the blue film silk screen printing process or the tearing off process. Therefore, during the electrical test process, the first electrostatic ring 102 and the second electrostatic ring 104 can both remain closed, thereby effectively avoiding the need for different sub-test terminals (such as ET DE , ET DO , ET DE , ET DO , etc.) during the electrical test process.
  • ET GE , ET GO , ET SW , ET Vcom are short-circuited, that is, the first electrostatic ring 102 and the second electrostatic ring 104 will not affect the electrical test results.
  • the first electrostatic ring 102 includes a first connection end A and a second connection end B; in FIGS. 4 to 7 6, the first connection terminal A and the second connection terminal B of the first electrostatic ring 102 are respectively electrically connected to two adjacent non-common voltage sub-test terminals (such as ET DE , ET DO , ET GE , ET GO , ET SW ).
  • the first connection terminal A of the first electrostatic ring 102 is electrically connected to the non-common voltage sub-test terminals (such as ET DE , ET DO , ET GE , ET GO , ET SW ), and the second connection terminal B It is electrically connected to the ground wire 103.
  • the non-common voltage sub-test terminals such as ET DE , ET DO , ET GE , ET GO , ET SW
  • the number of transistors included in the first electrostatic ring 102 may be four, wherein the gate g of the first transistor T 1 , the gate electrode g of the first transistor T The first pole s of 1 and the first pole s of the second transistor T 2 are electrically connected together as the first connection terminal A; the second pole d of the first transistor T 1 and the second pole d of the second transistor T 2 The electrode d, the gate electrode g of the second transistor T 2 , the gate electrode g of the third transistor T 3 , the first electrode s of the third transistor T 3 , and the first electrode s of the fourth transistor T 4 are electrically connected together; the gate g of the fourth transistor T 4 , the second pole d of the fourth transistor T 4 , and the second pole d of the third transistor T 3 are electrically connected together as the second connection terminal B, so that The four transistors form a symmetrically arranged closed-loop circuit, which is conducive to rapid self-turning under
  • the first electrode s of the transistor may be the source electrode, and the second electrode d may be the drain electrode.
  • the first electrode s of the transistor may be the drain electrode, and the second electrode d may be the source electrode.
  • the first electrode s is used as the drain electrode.
  • the pole s is the source and the second pole d is the drain as an example.
  • the electrical connection method between the plurality of transistors in the second electrostatic ring 104 can be the same as the electrical connection method between the plurality of transistors in the first electrostatic ring 102 .
  • the same makes it easier for the first electrostatic ring 102 to conduct under the same electrostatic influence, improving the anti-static ability.
  • it can ensure that the off-state leakage current of the transistor contained in the second electrostatic ring 104 is small, thereby reducing the third electrostatic ring 104 as much as possible.
  • first connection terminal A of the second electrostatic ring 104 is electrically connected to the common voltage sub-test terminal ET Vcom
  • the second connection terminal B is connected to the non-public voltage sub-test terminals (such as ET DE , ET DO , ET GE , ET GO , ET SW ) are electrically connected.
  • the first transistor T 1 , the second transistor T 2 , the third transistor T 3 , and the fourth transistor T 4 provided by the present disclosure may be the same type of P-type transistor. Or N-type transistor.
  • the P-type transistor is turned on when the voltage difference V gs between its gate g and its first s and its threshold voltage V th satisfy the relationship V gs ⁇ V th , and between its gate g and its first electrode s
  • the voltage difference V gs and its threshold voltage V th satisfy the relationship V gs >V th and are cut off
  • the N-type transistor has a voltage difference V gs between its gate g and its first pole s and its threshold voltage V th satisfies the relationship V It is turned on when gs > V th , and turned off when the voltage difference V gs between its gate g and its first pole s and its threshold voltage V th satisfy the relationship V gs ⁇ V th .
  • the first transistor T 1 , the second transistor T 2 , the third transistor T 3 , and the fourth transistor T 4 may be amorphous silicon transistors, polysilicon transistors, oxide transistors, etc.
  • the leakage current of oxide transistors using metal oxide semiconductor materials such as indium gallium zinc oxide IGZO
  • the first transistor T 1 and the third transistor need to be kept
  • the two transistors T 2 , the third transistor T 3 , and the fourth transistor T 4 are turned off. Therefore, in order to reduce the leakage current in the off state, during specific implementation, it is advisable to set the first transistor T 1 and the second transistor T 2 , the third transistor T 3 and the fourth transistor T 4 are oxide transistors.
  • the gate electrode g, the first electrode s, and the second electrode d of the first transistor T 1 , the second transistor T 2 , the third transistor T 3 , and the fourth transistor T 4 are all made of materials. It can include metal materials or alloy materials, such as a single-layer metal structure or a multi-layer metal structure that can be formed of molybdenum, aluminum, titanium, etc., for example, the multi-layer metal structure is composed of a stacked titanium metal layer/aluminum metal layer/titanium Made of metal layers.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure may also include a transfer electrode 105 located on the layer where the first electrostatic ring 102 is located.
  • the transfer electrode 105 Respectively with the second electrode d of the first transistor T 1 , the second electrode d of the second transistor T 2 , the gate electrode g of the second transistor T 2 , the gate electrode g of the third transistor T 3 , the third electrode
  • the first pole s of the first transistor T 3 and the first pole s of the fourth transistor T 4 are electrically connected.
  • One electrode s is integrally provided, and the gate electrode g of the second transistor T 2 and the gate electrode g of the third transistor T 3 are integrally provided to facilitate electrical connection with the transfer electrode 105 .
  • the first transistor T 1 , the second transistor T 2 , the third transistor T 3 and the fourth transistor T 4 are bottom-gate transistors, and the transfer electrode 105 passes through the first insulating layer 106
  • the hole is electrically connected to the second pole d of the first transistor T 1 , the second pole d of the second transistor T 2 , the first pole s of the third transistor T 3 , and the first pole s of the fourth transistor T 4 . connected, and electrically connected to the gate g of the second transistor T 2 and the gate g of the third transistor T 3 through a via hole penetrating the first insulating layer 106 and the second insulating layer 107 .
  • the via holes penetrating the first insulating layer 106 and the via holes penetrating both the first insulating layer 106 and the second insulating layer 107 can be prepared through a single patterning process, thereby avoiding additional processing of the second insulating layer 107 Composition craftsmanship.
  • the second electrode d of the first transistor T 1 , the second electrode d of the second transistor T 2 , the gate electrode g of the second transistor T 2 , and the third transistor T 2 can also be used.
  • the gate g of T 3 , the first electrode s of the third transistor T 3 , and the first electrode s of the fourth transistor T 4 are electrically connected through a via hole penetrating the second insulating layer 107 , which is not limited here.
  • the materials of the first insulating layer 106 and the second insulating layer 107 include but are not limited to silicon oxide, silicon nitride, silicon oxynitride, etc.
  • the first insulating layer 106 and the second insulating layer 107 may have a single film layer structure or a stacked layer structure, which is not limited here.
  • the pixel transistor T and the pixel electrode 108 may also be electrically connected to each other, and the pixel electrode 108 is located on the layer where the pixel transistor T is located.
  • the pixel transistor T and the same functional film layers of the first transistor T 1 , the second transistor T 2 , the third transistor T 3 , and the fourth transistor T 4 are respectively arranged in the same layer and with the same material, that is, the pixel
  • the gate g of the transistor T is in the same layer and made of the same material as the gates g of the first transistor T 1 , the second transistor T 2 , the third transistor T 3 , and the fourth transistor T 4 .
  • the first pole s and the second pole d are on the same layer and in the same layer as the first pole s and the second pole d of the first transistor T 1 , the second transistor T 2 , the third transistor T 3 and the fourth transistor T 4
  • the active layer of the pixel transistor T is in the same layer and made of the same material as the active layers ac of the first transistor T 1 , the second transistor T 2 , the third transistor T 3 , and the fourth transistor T 4 .
  • the transfer electrode 105 can be provided in the same layer and with the same material as the pixel electrode 108, so that the transfer electrode 105 is formed at the same time as the pixel electrode 108 is patterned to avoid additional layers of the transfer electrode 105, and Composition craftsmanship.
  • the material of the pixel electrode 108 may include indium tin oxide (ITO), indium zinc oxide (IZO), or the like.
  • “same layer, same material” refers to a layer structure formed by using the same film formation process to form a film layer for making a specific pattern, and then using the same mask to form a patterning process. That is, one patterning process corresponds to one mask (also called photomask).
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous. These specific patterns may be at the same height or Have the same thickness, may be at different heights or have different thicknesses.
  • the pixel electrode 108 is electrically connected to the pixel transistor T through a via hole penetrating the first insulating layer 106 . Therefore, when the transfer electrode 105 and the pixel electrode 108 are arranged in the same layer and with the same material, , can also be formed simultaneously in the first insulating layer 106 and the second insulating layer 107 through a patterning process, and a via hole penetrating the first insulating layer 106 and used to electrically connect the pixel electrode 108 and the pixel transistor T can pass through the first insulating layer.
  • the 106 is used to electrically connect the transfer electrode 105 to the second pole d of the first transistor T 1 , the second pole d of the second transistor T 2 , the first pole s of the third transistor T 3 , and the fourth transistor.
  • the via hole of the first electrode s of T 4 as well as the via hole that penetrates the first insulating layer 106 and the second insulating layer 107 and is used to electrically connect the transfer electrode 105 and the gate electrode g of the second transistor T 2 and the third transistor T 3 via holes for the gate g, thereby avoiding the patterning process of additionally adding 105 related via holes for the transfer electrode.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure also includes a plurality of first transfer terminals 109, a first transfer terminal 109 and a sub-test terminal. (eg ET DE , ET DO , ET SW , ET Vcom ) are electrically connected.
  • the first electrostatic ring 102 is electrically connected to the non-common voltage sub-test terminals (eg ET DE , ET DO , ET SW ) through the first transfer terminal 109 .
  • the plurality of first transfer terminals 109 can be provided in the same layer and with the same material as the pixel electrode 108, so as to form the plurality of first transfer terminals 109 while patterning the pixel electrode 108 to avoid additional first transfer terminals 109.
  • the film layer of the transfer terminal 109 and the patterning process can be provided in the same layer and with the same material as the pixel electrode 108, so as to form the plurality of first transfer terminals 109 while patterning the pixel electrode 108 to avoid additional first transfer terminals 109.
  • an embodiment of the present disclosure provides a mid-board, as shown in FIG. 16 , including a plurality of the above-mentioned display substrates 201 provided by an embodiment of the present disclosure. Since the principle of the mid-plane to solve the problem is similar to the principle of the above-mentioned display substrate to solve the problem, the implementation of the mid-plane provided by the embodiment of the present disclosure can be referred to the implementation of the above-mentioned display substrate, and repeated details will not be repeated.
  • the above-mentioned midplane provided by the embodiments of the present disclosure also includes multiple test terminals (such as AT GO , AT GE , AT DO , AT DE , AT SW , AT Vcom ) and the third electrostatic ring 202, a plurality of test terminals (such as AT GO , AT GE , AT DO , AT DE , AT SW , AT Vcom ) including a common voltage test terminal AT Vcom and non-public voltage test terminals (such as AT GO , AT GE , AT DO , AT DE , AT SW ), the common voltage test terminal AT Vcom is electrically connected to the common voltage sub-test terminal ET Vcom , and the non-public voltage test terminals (such as AT GO , AT GE , AT DO , AT DE , AT SW ) are electrically connected to the non-common voltage sub-test terminals (such as ET GO , ET GE , ET DO , ET DE
  • non-common voltage test terminals such as ET GO , ET GE , ET DO , ET DE , ET SW
  • at least two non-common voltage test terminals such as ET GO , ET GE , ET DO , ET DE , ET SW
  • ET Vcom common voltage test terminal
  • each non-common voltage sub-test terminal (eg ET GO , ET GE , ET DO , ET DE , ET SW ) is connected to one non-common voltage test terminal (eg AT GO , ET GO , ET SW ) through a third electrostatic ring 202 AT GE , AT DO , AT DE , AT SW ) correspond to electrical connections.
  • the common voltage test terminal AT Vcom is electrically connected to the common voltage sub-test terminal ET Vcom
  • the non-public voltage test terminals such as AT GO , AT GE , AT DO , AT DE , AT SW
  • the non-common voltage sub-test terminals such as ET GO , ET GE , ET DO , ET DE , ET SW
  • each non-common voltage sub-test terminal such as ET GO , ET GE , ET DO , ET DE , ET SW
  • the static electricity accumulated on the common voltage sub-test terminal (ET Vcom ) is transferred to the corresponding electrically connected non-public voltage test terminals (such as AT GO , AT GE , AT DO , AT DE , AT SW ) and the common voltage
  • the test terminal AT Vcom and because there is a third electrostatic ring 202 electrically connected between the public voltage test terminal AT Vcom
  • the common voltage test terminal AT Vcom and the non-public voltage test terminals (such as AT GO , AT GE , AT DO , AT DE , AT SW ) and the third electrostatic ring 202 between them are cut off. Therefore, in the process of using chip induction to obtain the common voltage, it will not be affected by the leakage of the third electrostatic ring 202 and the public voltage can be accurately obtained. Voltage.
  • the structure of the third electrostatic ring 202 can be the same as the structure of the first electrostatic ring 102 , so that the third electrostatic ring 202 can be completed using the same process parameters. and the preparation of the first electrostatic ring 102, thereby simplifying the manufacturing process of the electrostatic ring. Furthermore, because the channel width-to-length ratio of the transistors included in the first electrostatic ring 102 is greater than the channel width-to-length ratio of the transistors included in the second electrostatic ring 104, the first electrostatic ring 102 is more susceptible to the influence of static electricity and turns on, accordingly. , the third electrostatic ring 202 with the same structure as the first electrostatic ring 102 is also easily affected by static electricity and conducts, which is beneficial to dispersing static electricity and improving the anti-static ability of the product.
  • multiple test terminals such as AT GO , AT GE , AT DO , AT DE , AT SW , AT Vcom
  • multiple sub-test terminals such as ET GO , ET GE , ET DO , ET DE , ET SW , ET Vcom
  • the electrodes are arranged in the same layer and with the same material, so that one conductive film layer can be used to prepare the gates of one transistor T 1 , the second transistor T 2 , the third transistor T 3 , and the fourth transistor T 4 to avoid Additional set up multiple test terminals (such as AT GO , AT GE , AT DO , AT DE , AT SW , AT Vcom ), and multiple sub-test terminals (such as ET GO , ET GE , ET DO , ET DE , ET SW , ET Vcom
  • the above-mentioned midplane provided by the embodiment of the present disclosure may also include a plurality of first connection lines 203 , a plurality of second connection lines 204 and a plurality of first transfer lines 205 , wherein the plurality of first connection lines 203 and the plurality of second connection lines 204 are arranged on the same layer and with the same material, and the plurality of first connection lines 203 and the plurality of first transfer lines 205 are arranged on different layers; one first connection line 203 Electrically connected to a sub-test terminal (such as ET GO , ET GE , ET DO , ET DE , ET SW , ET Vcom ), a second connection line 204 is connected to a test terminal (such as AT GO , AT GE , AT DO , AT DE , AT SW , AT Vcom ) are electrically connected, and a first adapter line 205 is electrically connected between a first connection line 203 and a second connection line 204
  • a sub-test terminal such as ET GO
  • first connection lines 203 and second connection lines 204 when there are multiple first connection lines 203 and second connection lines 204 arranged on the same layer and with the same material, the corresponding first connection lines 204 are connected through the first transfer lines 205 of different layers. 203 and the second connection line 204 are electrically connected together, which can not only effectively avoid short circuits between different first connection lines 203 but also effectively avoid short circuits between different second connection lines 204 .
  • the above-mentioned midplane provided by the embodiment of the present disclosure also includes a plurality of second transfer lines 206 , a plurality of third transfer lines 207 and a fourth transfer line. 208.
  • a non-public voltage test terminal (such as AT GO , AT GE , AT DO , AT DE , AT SW ) is electrically connected to the corresponding second connection line 204 through a second transfer line 206, and a second transfer line 206 passes through
  • a third electrostatic ring 202 is electrically connected to a third transfer wire 207, a plurality of third transfer wires 207 is electrically connected to a fourth transfer wire 208, and the common voltage test terminal AT Vcom is connected to the corresponding second transfer wire through the fourth transfer wire 208.
  • Line 204 is electrically connected. In some embodiments, as shown in FIG.
  • the third transfer wires 207 can be brought together and then connected to the fourth transfer wires 207 .
  • Adapter cable 208 can be electrically connected to the fourth adapter wire 208 respectively, which is not limited here.
  • the above-mentioned midplane provided by the embodiment of the present disclosure may also include a fourth electrostatic ring 209 , and the fourth electrostatic ring 209 is electrically connected between the third adapter line 207 and between the fourth adapter wires 208; or, as shown in FIG. 22, the third adapter wire 207 can be integrally provided with the fourth adapter wire 208.
  • the setting of the fourth electrostatic ring 209 can avoid mutual influence between different test terminals (such as AT GO , AT GE , AT DO , AT DE , AT SW , AT Vcom ) and improve test accuracy.
  • the structure of the fourth electrostatic ring 209 is the same as the structure of the first electrostatic ring 102 .
  • the fourth electrostatic ring 209 and the first electrostatic ring 102 can be prepared using the same process parameters, thereby simplifying the manufacturing process of the electrostatic ring.
  • the first electrostatic ring 102 is easily affected by static electricity and conducts
  • the fourth electrostatic ring 209 with the same structure as the first electrostatic ring 102 is also easily affected by static electricity and conducts, which is conducive to dispersing static electricity and improving the anti-static ability of the product. .
  • the first transfer line 205, the second transfer line 206, the third transfer line 207, and the fourth transfer line 208 are all in the same layer as the pixel electrode 108.
  • the same material is arranged, so that the first transfer line 205, the second transfer line 206, the third transfer line 207 and the fourth transfer line 208 are formed at the same time as the pixel electrode 108 is patterned to avoid additionally adding the first transfer line 205, the third transfer line 205 and the fourth transfer line 208.
  • the film layers and patterning process of the second transfer wire 206, the third transfer wire 207, and the fourth transfer wire 208 are all in the same layer as the pixel electrode 108.
  • the above-mentioned midplane provided by the embodiments of the present disclosure may also include a plurality of second transfer terminals 210 , and the plurality of second transfer terminals 210 are connected to a plurality of The test terminals (such as AT GO , AT GE , AT DO , AT DE , AT SW , AT Vcom ) are electrically connected so that during the electrical testing process, the second transfer terminal 210 can be used to connect the test terminals (such as AT GO , AT GE , AT DO , AT DE , AT SW , AT Vcom ) load signals.
  • the test terminals such as AT GO , AT GE , AT DO , AT DE , AT SW , AT Vcom
  • the plurality of second transfer terminals 210 and the pixel electrode 108 are arranged in the same layer and with the same material, so that the second transfer terminals 210 are formed simultaneously with the patterning of the pixel electrode 108 to avoid adding additional second transfer terminals 210 film layer, and patterning process.
  • the size of the second transfer terminal 210 is equal to the size of the test terminal (such as AT GO , AT GE , AT DO , AT DE , AT SW , AT Vcom ); in the vertical direction of the arrangement direction of each test terminal (such as AT GO , AT GE , AT DO , AT DE , AT SW , AT Vcom ) , the size of the second transfer terminal 210 is smaller than the size of the test terminals (such as AT GO , AT GE , AT DO , AT DE , AT SW , AT Vcom ), for example, in each test terminal (such as AT GO , AT GE , AT DO , AT DE , AT SW , AT Vcom ), the size of the second transfer terminal 210 is the same as the size of the test terminal (such as AT GO , AT GE , AT DO , AT DE , AT SW , AT Vcom ), the size of the second transfer terminal 210 is the same as the size of the test terminal (such as AT GO ,
  • the above-mentioned midplane provided by the embodiment of the present disclosure may also include shorting rods 211 and a plurality of high-resistance lines 212, and the high-resistance lines 212 are located at the second turn.
  • a high-impedance line 212 is integrally provided with a second transfer terminal 210, and a test terminal (such as AT GO , AT GE , AT DO , AT DE , AT SW , AT Vcom ) passes through a high-impedance line.
  • 212 is electrically connected to the shorting rod 211, and the shorting rod 211 is set in floating position.
  • the high-resistance line 212 may be a bent line spliced by multiple “U”-shaped line segments.
  • embodiments of the present disclosure provide a method for manufacturing a display substrate. Since the principle of solving the problem of this manufacturing method is similar to the principle of solving the problem of the above-mentioned mid-plane and display substrate, therefore, the implementation of the manufacturing method can be referred to the above. The embodiments of the middle plate and the display substrate will not be repeated again.
  • the method for manufacturing a display substrate may include the following steps:
  • the display substrate includes a base substrate.
  • the base substrate includes a display area and a frame area located on at least one side of the display area.
  • the frame area is provided with a plurality of sub-test terminals and a plurality of first static electricity.
  • the plurality of sub-test terminals include a common voltage sub-test terminal and a plurality of non-common voltage sub-test terminals, the plurality of non-common voltage sub-test terminals are arranged in series and/or grounded through the first electrostatic ring.
  • an electronic paper display device including an opposite display substrate and a counter substrate, and an electrophoretic layer (FPL) located between the display substrate and the counter substrate.
  • the display substrate is The above display substrate provided by embodiments of the present disclosure.
  • the opposite substrate includes a common electrode with a planar structure.
  • the common electrode is electrically connected to the common electrode line Vcom in the frame area BB.
  • the material of the common electrode may include indium tin oxide (ITO), indium zinc oxide (IZO), etc.
  • the electrophoretic layer includes a plurality of electrophoretic particles. Each electrophoretic particle may include: a particle body, and an electrophoretic liquid and charged particles located in the particle body.
  • the charged particles may include black particles and white particles, or the charged particles may include black particles, white particles, etc. Particles and colored particles (such as red particles, yellow particles, blue particles, etc.).
  • the electric field formed by the pixel electrode and the common electrode controls the up and down movement of black particles and white particles with different charges, or black particles, white particles, and colored particles (such as red particles, yellow particles, blue particles, etc.), which can display a black and white picture or Black and white red, black and white yellow, black and white blue and other color pictures.
  • the above-mentioned electronic paper products provided by the embodiments of the present disclosure may include, but are not limited to: radio frequency units, network modules, audio output & input units, sensors, display units, user input units, interface units, control chips and other components.
  • the control chip is a central processing unit, a digital signal processor, a system on chip (SoC), etc.
  • SoC system on chip
  • the control chip may also include a memory, a power module, etc., and realize power supply and signal input and output functions through additional wires, signal lines, etc.
  • the control chip may also include hardware circuits and computer executable codes.
  • Hardware circuits may include conventional very large scale integration (VLSI) circuits or gate arrays as well as existing semiconductors such as logic chips, transistors, or other discrete components; hardware circuits may also include field programmable gate arrays, programmable array logic, Programmable logic devices, etc.
  • VLSI very large scale integration
  • hardware circuits may also include field programmable gate arrays, programmable array logic, Programmable logic devices, etc.
  • the above structure does not constitute a limitation on the above display device provided by the embodiment of the present disclosure.
  • the above electronic paper provided by the embodiment of the present disclosure may include more or less of the above. components, or combinations of certain components, or different arrangements of components.
  • the embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, a mid-board and an electronic paper display device.
  • the present disclosure connects each non-public voltage sub-test terminal (such as ET DE , ET DO , ET GE , ET GO , ET SW ) adopts the first electrostatic ring 102 set in series and/or grounded, so that accumulation on each non-common voltage sub-test terminal (such as ET DE , ET DO , ET GE , ET GO , ET SW )
  • the first electrostatic ring 102 is opened under the high voltage of static electricity, and a path is formed between the non-common voltage sub-test terminals (such as ET DE , ET DO , ET GE , ET GO , ET SW ), thereby increasing the It eliminates the static electricity transmission path, effectively disperses static electricity, reduces the adverse effects of static electricity on the test transistor electrically connected to the non-common voltage sub-test terminal ET SW , and improves the anti
  • the second electrostatic ring 104 By arranging the second electrostatic ring 104 between the common voltage sub-test terminal ET Vcom and the adjacent non-common voltage sub-test terminal (such as any one of ET DE , ET DO , ET GE , ET GO , and ET SW ), it is possible to achieve When there is excessive static electricity accumulation on the common voltage sub-test terminal ET Vcom and the adjacent non-common voltage sub-test terminal (such as any one of ET DE , ET DO , ET GE , ET GO , ET SW ), the second The electrostatic ring 104 is opened under the high voltage of static electricity, thus increasing the electrostatic release path and further reducing the impact of static electricity on the test transistor; and, because the channel width-to-length ratio of the transistor contained in the second electrostatic ring 104 is smaller than that of the first electrostatic ring The channel width-to-length ratio of the transistors included in the ring 102 can make the leakage current of the transistors included in the second electrostatic ring 104 smaller, thereby minimizing
  • the third electrostatic ring 202 is turned on under the high voltage of static electricity, so that the non-public voltage test terminals (such as AT GO , AT GE , AT DO , AT DE , AT SW ), the first electrostatic ring 102, the public voltage test terminal AT Vcom , and the public voltage sub-test
  • the terminal ET Vcom and the common voltage line Vcom are connected in sequence, and static electricity can be released to the larger common voltage line Vcom through this path, thereby dispersing the influence of static electricity and preventing the test transistor from turning on abnormally due to static electricity and affecting the display effect.
  • the common voltage test terminal AT Vcom the non-public voltage test terminal (such as AT GO , AT GE , AT DO , AT DE , AT SW ) and the two The third electrostatic ring 202 in between is cut off, so that in the process of obtaining the common voltage using chip induction, it will not be affected by the leakage of the third electrostatic ring 202, so that the public voltage can be accurately obtained.

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Abstract

一种显示基板、其制作方法、中板及电子纸显示装置，其中显示基板包括：衬底基板（101），衬底基板（101）包括显示区（AA）、以及位于显示区（AA）至少一侧的边框区（BB）；多个子测试端子，位于边框区（BB），多个子测试端子包括公共电压子测试端子（ET Vcom）和多个非公共电压子测试端子；第一静电环（102），位于边框区（BB），多个非公共电压子测试端子通过第一静电环（102）串联设置和/或接地设置。

Description

显示基板、其制作方法、中板及电子纸显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、其制作方法、中板及电子纸显示装置。
背景技术
电子纸(EPD)产品是目前市场上常见的电子价签和电子阅读器产品，该产品显示效果接近于纸张，一次刷新可长时间显示，具有环保节能等优点，市场需求量巨大。
发明内容
本公开实施例提供的显示基板、其制作方法、中板及电子纸显示装置，具体方案如下：
一方面，本公开实施例提供了一种显示基板，包括：
衬底基板，所述衬底基板包括显示区、以及位于所述显示区至少一侧的边框区；
多个子测试端子，位于所述边框区，所述多个子测试端子包括公共电压子测试端子和多个非公共电压子测试端子；
第一静电环，位于所述边框区，所述多个非公共电压子测试端子通过所述第一静电环串联设置和/或接地设置。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一静电环电连接在相邻两个所述非公共电压子测试端子之间。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括第二静电环，所述第二静电环电连接在所述公共电压子测试端子与相邻的所述非公共电压子测试端子之间；
所述第二静电环和所述第一静电环均包括相互电连接的多个晶体管，所述第二静电环所含晶体管的沟道宽长比小于所述第一静电环所含晶体管的沟道宽长比。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一静电环包括第一连接端和第二连接端；
所述第一静电环包括四个晶体管，其中，第一个晶体管的栅极、第一个晶体管的第一极、第二个晶体管的第一极电连接在一起作为所述第一连接端；第一个晶体管的第二极、第二个晶体管的第二极、第二个晶体管的栅极、第三个晶体管的栅极、第三个晶体管的第一极、第四个晶体管的第一极电连接在一起；第四个晶体管的栅极、第四个晶体管的第二极、以及第三个晶体管的第二极电连接在一起作为所述第二连接端。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述第一静电环所在层之上的转接电极，所述转接电极分别与第一个晶体管的第二极、第二个晶体管的第二极、第二个晶体管的栅极、第三个晶体管的栅极、第三个晶体管的第一极、第四个晶体管的第一极电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述第一静电环所在层之上的像素电极，所述转接电极与所述像素电极同层、同材料设置。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第二静电环中多个晶体管之间的电连接方式与所述第一静电环中多个晶体管之间的电连接方式相同。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括多个第一转接端子，一个所述第一转接端子与一个所述子测试端子电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，所述第一静电环通过所述第一转接端子与所述非公共电压子测试端子电连接。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述第一静电环所在层之上的像素电极，所述多个第一转接端子与所述像素 电极同层、同材料设置。
在一些实施例中，在本公开实施例提供的上述显示基板中，还包括位于所述边框区的接地线，各所述非公共电压子测试端子分别通过所述第一静电环电连接至所述接地线。
另一方面，本公开实施例提供了一种中板，包括多个显示基板，所述显示基板为本公开实施例提供的上述显示基板。
在一些实施例中，在本公开实施例提供的上述中板中，还包括：位于所述多个显示基板所在区一侧的多个测试端子和第三静电环，其中，所述多个测试端子包括公共电压测试端子和非公共电压测试端子，所述公共电压测试端子与所述公共电压子测试端子电连接，所述非公共电压测试端子与所述非公共电压子测试端子电连接，所述第三静电环电连接在所述公共电压测试端子与所述非公共电压测试端子之间。
在一些实施例中，在本公开实施例提供的上述中板中，所述非公共电压测试端子的数量为多个，至少两个所述非公共电压测试端子分别通过所述第三静电环连接至所述公共电压测试端子。
在一些实施例中，在本公开实施例提供的上述中板中，所述第三静电环的结构与所述第一静电环的结构相同。
在一些实施例中，在本公开实施例提供的上述中板中，所述多个测试端子、以及所述多个子测试端子均与所述多个晶体管的栅极同层、同材料设置。
在一些实施例中，在本公开实施例提供的上述中板中，还包括多条第一连接线、多条第二连接线和多条第一转接线，其中，所述多条第一连接线与所述多条第二连接线同层、同材料设置，所述多条第一连接线与所述多条第一转接线异层设置；一条所述第一连接线通过一个所述第一转接端子与一个所述子测试端子对应电连接，一条所述第二连接线与一个所述测试端子电连接，一条所述第一转接线电连接在一条所述第一连接线与一条所述第二连接线之间。
在一些实施例中，在本公开实施例提供的上述中板中，还包括多条第二 转接线、多条第三转接线和一条第四转接线，一个所述非公共电压测试端子通过一条所述第二转接线与对应的所述第二连接线电连接，一条所述第二转接线通过一个所述第三静电环与一条所述第三转接线电连接，所述多条第三转接线与所述第四转接线电连接，所述公共电压测试端子通过所述第四转接线与对应的所述第二连接线电连接。
在一些实施例中，在本公开实施例提供的上述中板中，所述多条第三转接线与所述第四转接线一体设置。
在一些实施例中，在本公开实施例提供的上述中板中，还包括第四静电环，所述多条第三转接线通过所述第四静电环与所述第四转接线电连接。
在一些实施例中，在本公开实施例提供的上述中板中，所述第四静电环的结构与所述第一静电环的结构相同。
在一些实施例中，在本公开实施例提供的上述中板中，还包括位于所述第一静电环所在层之上的像素电极，所述第一转接线、所述第二转接线、所述第三转接线、以及所述第四转接线均与所述像素电极同层、同材料设置。
在一些实施例中，在本公开实施例提供的上述中板中，还包括多个第二转接端子，一个所述第二转接端子与一个所述测试端子对应电连接。
在一些实施例中，在本公开实施例提供的上述中板中，还包括位于所述第一静电环所在层之上的像素电极，所述多个第二转接端子与所述像素电极同层、同材料设置。
在一些实施例中，在本公开实施例提供的上述中板中，还包括短接棒和多条高阻线，所述高阻线位于所述第二转接端子之间，一条所述高阻线与一个所述第二转接端子一体设置，一个所述测试端子通过一条所述高阻线电连接至所述短接棒，所述短接棒浮空设置。
另一方面，本公开实施例提供了一种显示基板的制作方法，包括：
提供本公开实施例提供的上述中板；
对所述中板进行切割处理，获取所述显示基板，所述显示基板包括衬底基板，所述衬底基板包括显示区、以及位于所述显示区至少一侧的边框区， 所述边框区设置有多个子测试端子和多个第一静电环，所述多个子测试端子包括公共电压子测试端子和多个非公共电压子测试端子，所述多个非公共电压子测试端子通过所述第一静电环串联设置和/或接地设置。
另一方面，本公开实施例提供了一种电子纸显示装置，包括相对而置的显示基板和对向基板，以及位于所述显示基板和对向基板之间的电泳层；其中，所述显示基板为本公开实施例提供的上述显示基板。
附图说明
图1为相关技术中的防静电示意图；
图2为芯片感应正常获取公共电压的电路原理图；
图3为芯片感应异常获取公共电压的电路原理图；
图4为本公开实施例提供的显示基板的一种结构示意图；
图5为本公开实施例提供的一种防静电示意图；
图6为本公开实施例提供的又一种防静电示意图；
图7为本公开实施例提供的显示基板的又一种结构示意图；
图8为本公开实施例提供的静电环的电路图；
图9为本公开实施例提供的静电环的结构示意图；
图10为沿图9中a-a’方向的截面图；
图11为沿图9中b-b’方向的截面图；
图12为沿图9中c-c’方向的截面图；
图13为本公开实施例提供的显示基板中一个子像素的结构示意图；
图14为本公开实施例提供的显示基板上的防静电示意图；
图15为图14中Z 1区的放大示意图；
图16为本公开实施例提供的中板的一种结构示意图；
图17为本公开实施例提供的中板上的一种防静电示意图；
图18为本公开实施例提供的中板上的又一种防静电示意图；
图19为图18中Z 2区的放大示意图；
图20为图19中Z 3区的放大示意图；
图21为本公开实施例提供的中板的又一种结构示意图；
图22为本公开实施例提供的第二连接线、第三连接线、第四转接线的一种连接示意图。
附图标记：
101-衬底基板，102-第一静电环，103-接地线，104-第二静电环，105-转接电极，106-第一绝缘层，107-第二绝缘层，108-像素电极，109-第一转接端子，g-栅极，s-源极，d-漏极，ac-有源层，T 1-第一个晶体管，T 2-第二个晶体管，T 3-第三个晶体管，T 4-第四个晶体管，ET Vcom-公共电压子测试端子，ET GE、ET GO、ET DE、ET DO、ET SW-非公共电压子测试端子，201-显示基板，202-第三静电环，203-第一连接线，204-第二连接线，205-第一转接线，206-第二转接线，207-第三转接线，208-第四转接线，209-第四静电环，210-第二转接端子，211-短接棒，212-高阻线，AT Vcom-公共电压测试端子，AT GE、AT GO、AT DE、AT DO、AT SW-非公共电压测试端子。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置 关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
电子纸产品所含显示基板的制程包括以下步骤：在大尺寸衬底上制备多个显示基板，以形成大板；为便于出货，将大板切割为多个中板；为防止出货过程中划伤中板，在中板上丝印了蓝膜；对中板进行切割后即可获得目标尺寸的显示基板。相关技术中在显示基板上设置了子测试端子和测试晶体管，子测试端子与测试晶体管的第一极(例如源极)电连接，测试晶体管的第二极(例如漏极)与信号线连接，中板上的测试端子为子测试端子提供测试信号，并通过芯片控制测试晶体管开启，以对信号线进行电学检测；在用户使用过程中，测试晶体管保持常关，不会影响正常显示。
在蓝膜的丝印制程以及撕膜过程中较易产生静电(ESD)，测试晶体管受到静电影响发生损伤可能会异常开启，从而影响电子纸产品正常工作。为改善静电影响，如图1所示，相关技术中将显示基板的各个非公共电压子测试端子(例如ET SW、ET GE、ET GO)通过静电环(ER)分别电连接至与公共电压子测试端子(ET Vcom)一体设置的公共电压线(Vcom)，由于公共电压线(Vcom)的线宽较大，因此，在各个非公共电压子测试端子(例如ET SW、ET GE、ET GO)上积累的静电过多的情况下，静电环(ER)在静电的高压作用下开启，这样静电就可以通过静电环(ER)释放至面积较大的公共电压线(Vcom)上，从而分散静电的影响，避免测试晶体管因静电作用而异常开启。
电子纸产品的公共电压，在显示过程中起着抵消△V pixel，使黑白红三种颜色的带电粒子(例如微球)均能处在一个正常的目标显示电压下的作用，其中，
Figure PCTCN2022109500-appb-000001
C gs表示像素晶体管的栅极g与源极s的交叠电容，V gh表示像素晶体管的栅极开启电压，V gl表示像素晶体管的栅极关闭电压，C 纸膜表示像素电极(P)与公共电极(Com)之间的交叠电容，Cst表示存储电容。一般地，电子纸产品的公共电压通过芯片感应(IC Sensing)的方式获得。然而通过芯片感应获得的公共电压存在过大、波动严重等问题。 鉴于此，发明人对电子纸产品的芯片感应机理进行了研究并对其影响因素进行了分析，研究表明，在芯片感应阶段，如图2所示，公共电极(Com)本应处于浮空(Floating)状态，但如图3所示，非公共电压子测试端子(例如ET SW、ET GE、ET GO)通过静电环(ER)对公共电极(Com)存在漏电，导致芯片感应出的公共电压被拉动至低电平，C 纸膜变小，△V pixel变大，因此最终获得的用于抵消显示过程中△V pixel的公共电压偏大。
为了改善相关技术中存在的上述技术问题，本公开实施例提供了一种显示基板，如图4至图7所示，包括：
衬底基板101，衬底基板101包括显示区AA、以及位于显示区AA至少一侧的边框区BB；可选地，衬底基板101可以为聚酰亚胺等柔性基板，也可以为玻璃等刚性基板；
多个子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW、ET Vcom)，位于边框区BB，多个子测试端子包括公共电压子测试端子ET Vcom和多个非公共电压子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW)，其中，ET Vcom为公共电压线Vcom提供测试信号，ET DE为偶数列数据线提供测试信号，ET DO为奇数列数据线提供测试信号，ET GE为偶数行栅线提供测试信号，ET GO为奇数行栅线提供测试信号，ET SW为测试晶体管的第一极提供测试信号；可选地，公共电压线Vcom在边框区BB整圈设置，在一些实施例中，为降低公共电压线Vcom的电阻，可将公共电压线Vcom设置为在栅金属层和源漏金属层的双层走线结构，且栅金属层的公共电压线Vcom与源漏金属层的公共电压线Vcom可以经由贯穿栅绝缘层(GI)的过孔连接；
第一静电环102，位于边框区BB，各非公共电压子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW)通过第一静电环102串联设置和/或接地设置；可选地，在图4至图6中，第一静电环102电连接在相邻两个非公共电压子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW)之间；在图7中，第一静电环102电连接在非公共电压子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW)与接地线103之间。
在本公开实施例提供的上述显示基板中，通过将各非公共电压子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW)采用第一静电环102串联设置和/或接地设置，使得在各非公共电压子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW)上积累的静电过多时，第一静电环102在静电的高压作用下开启，各非公共电压子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW)之间形成通路，由此增加了静电传输路径，有效分散了静电，降低了静电对与非公共电压子测试端子ET SW电连接的测试晶体管造成的不良影响，提高了产品的抗静电能力。另一方面，本公开中第一静电环102串联在非公共电压子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW)之间，和/或，第一静电环102连接在非公共电压子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW)与地(例如接地线103)之间，因此，并不会对公共电极线Vcom上的信号造成干扰，从而避免了与公共电极线Vcom电连接的公共电极(Com)通过第一静电环102漏电，进而保证了通过芯片感应方式获取的公共电压的准确性。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图6所示，还可以包括第二静电环104，第二静电环104电连接在公共电压子测试端子ET Vcom与相邻的非公共电压子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW中的任一个)之间；第二静电环104和第一静电环102均包括相互电连接的多个晶体管(例如第一个晶体管T 1、第二个晶体管T 2、第三个晶体管T 3、第四个晶体管T 4)，第二静电环104所含各晶体管的沟道宽长比相同，第一静电环102所含各晶体管的沟道宽长比相同，第二静电环104所含晶体管的沟道宽长比小于第一静电环102所含晶体管的沟道宽长比。第二静电环104的设置，可以使得在公共电压子测试端子ET Vcom与相邻的非公共电压子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW中的任一个)上的静电积累过多的情况下，第二静电环104在静电的高压作用下开启，由此增加了静电释放路径，进一步降低了静电对测试晶体管的影响；并且，因第二静电环104所含晶体管的沟道宽长比小于第一静电环102所含晶体管的沟道宽长比，可以使得第二静电环104所含晶体管的漏电流较小，从而尽可能地降低了第二静电 环104对芯片感应获取的公共电压的影响。可选地，第一静电环102所含晶体管的沟道宽长比为15/28.5，第二静电环104所含晶体管的沟道宽长比大于15/60且小于15/28.5，例如第二静电环104所含晶体管的沟道宽长比为15/40。
应当理解的是，在电学测试过程中对各子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW、ET Vcom)加载的测试信号电压远小于蓝膜丝印过程或撕除过程中产生的静电电压，因此，在电学测试过程中第一静电环102、第二静电环104均可以保持关闭状态，从而可有效避免电学测试过程中不同子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW、ET Vcom)之间短接，即第一静电环102、第二静电环104不会影响电学测试结果。
在一些实施例中，在本公开实施例提供的上述中板中，如图4至图7所示，第一静电环102包括第一连接端A和第二连接端B；在图4至图6中，第一静电环102的第一连接端A和第二连接端B分别与相邻两个非公共电压子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW)电连接；在图7中，第一静电环102的第一连接端A与非公共电压子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW)电连接，第二连接端B与接地线103电连接。
在一些实施例中，如图8至图12所示，第一静电环102包括的多个晶体管的数量可以为四个，其中，第一个晶体管T 1的栅极g、第一个晶体管T 1的第一极s、第二个晶体管T 2的第一极s电连接在一起作为第一连接端A；第一个晶体管T 1的第二极d、第二个晶体管T 2的第二极d、第二个晶体管T 2的栅极g、第三个晶体管T 3的栅极g、第三个晶体管T 3的第一极s、第四个晶体管T 4的第一极s电连接在一起；第四个晶体管T 4的栅极g、第四个晶体管T 4的第二极d、以及第三个晶体管T 3的第二极d电连接在一起作为第二连接端B，使得四个晶体管形成一个对称设置的闭环电路，利于在静电的高压作用下快速自开启。可选地，晶体管的第一极s可以为源极，第二极d可以为漏极，或者，晶体管的第一极s为漏极，第二极d为源极，本公开中以第一极s为源极，第二极d为漏极为例进行示例说明。
在一些实施例中，在本公开实施例提供的上述显示基板中，第二静电环 104中多个晶体管之间的电连接方式可以与第一静电环102中多个晶体管之间的电连接方式相同，使得在相同的静电影响下，第一静电环102更容易导通，提高抗静电能力，同时可以保证第二静电环104所含晶体管的关态漏电流较小，从而尽可能地降低第二静电环104对芯片感应获取的公共电压的影响。另外，由图6可见，第二静电环104的第一连接端A与公共电压子测试端子ET Vcom电连接，第二连接端B与非公共电压子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW)电连接。
在一些实施例中，为简化制作工艺，本公开提供的第一个晶体管T 1、第二个晶体管T 2、第三个晶体管T 3、第四个晶体管T 4可以为相同类型的P型晶体管或N型晶体管。其中，P型晶体管在其栅极g与其第一s之间的电压差V gs与其阈值电压V th满足关系式V gs<V th时导通，在其栅极g与其第一极s之间的电压差V gs与其阈值电压V th满足关系式V gs＞V th时截止；N型晶体管在其栅极g与其第一极s之间的电压差V gs与其阈值电压V th满足关系式V gs＞V th时导通，在其栅极g与其第一极s之间的电压差V gs与其阈值电压V th满足关系式V gs＜V th时截止。
在一些实施例中，第一个晶体管T 1、第二个晶体管T 2、第三个晶体管T 3、第四个晶体管T 4可以为非晶硅晶体管、多晶硅晶体管、氧化物晶体管等。可选地，采用金属氧化物半导体材料(例如铟镓锌氧化物IGZO)作为有源层的氧化物晶体管的漏电流较小，而在用户使用过程中，需保持第一个晶体管T 1、第二个晶体管T 2、第三个晶体管T 3、第四个晶体管T 4关闭，因此为了降低关闭状态的漏电流，在具体实施时，宜设置第一个晶体管T 1、第二个晶体管T 2、第三个晶体管T 3、第四个晶体管T 4为氧化物晶体管。
在一些实施例中，第一个晶体管T 1、第二个晶体管T 2、第三个晶体管T 3、第四个晶体管T 4的栅极g、第一极s、第二极d的材料均可以包括金属材料或者合金材料，例如可以由钼、铝及钛等形成的单层金属结构或多层金属结构，示例性地，多层金属结构由层叠设置的钛金属层/铝金属层/钛金属层构成。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图9和图 10所示，还可以包括位于第一静电环102所在层之上的转接电极105，转接电极105分别与第一个晶体管T 1的第二极d、第二个晶体管T 2的第二极d、第二个晶体管T 2的栅极g、第三个晶体管T 3的栅极g、第三个晶体管T 3的第一极s、第四个晶体管T 4的第一极s电连接。在一些实施例中，第一个晶体管T 1的第二极d、第二个晶体管T 2的第二极d、第三个晶体管T 3的第一极s、第四个晶体管T 4的第一极s一体设置，第二个晶体管T 2的栅极g、第三个晶体管T 3的栅极g一体设置，以便于与转接电极105电连接。
可选地，第一个晶体管T 1、第二个晶体管T 2、第三个晶体管T 3、第四个晶体管T 4为底栅型晶体管，转接电极105通过贯穿第一绝缘层106的过孔与第一个晶体管T 1的第二极d、第二个晶体管T 2的第二极d、第三个晶体管T 3的第一极s、第四个晶体管T 4的第一极s电连接，并通过贯穿第一绝缘层106和第二绝缘层107的过孔与第二个晶体管T 2的栅极g、第三个晶体管T 3的栅极g电连接。在此情况下，仅贯穿第一绝缘层106的过孔、以及同时贯穿第一绝缘层106和第二绝缘层107的过孔可以通过一次构图工艺制备，避免了额外对第二绝缘层107进行构图工艺。当然，在一些实施例中，也可以使得第一个晶体管T 1的第二极d、第二个晶体管T 2的第二极d、第二个晶体管T 2的栅极g、第三个晶体管T 3的栅极g、第三个晶体管T 3的第一极s、第四个晶体管T 4的第一极s通过贯穿第二绝缘层107的过孔电连接，在此不做限定。在一些实施例中，第一绝缘层106、第二绝缘层107的材料包括但不限与氧化硅、氮化硅、氮氧化硅等。第一绝缘层106、第二绝缘层107可以为单膜层结构，也可以为叠层结构，在此不做限定。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图13所示，还可以相互电连接的像素晶体管T和像素电极108，且像素电极108位于像素晶体管T所在层之上。可选地，像素晶体管T与第一个晶体管T 1、第二个晶体管T 2、第三个晶体管T 3、第四个晶体管T 4的相同功能膜层分别同层、同材料设置，即像素晶体管T的栅极g与第一个晶体管T 1、第二个晶体管T 2、第三个晶体管T 3、第四个晶体管T 4的栅极g同层、同材料设置，像素晶体管T 的第一极s、第二极d与第一个晶体管T 1、第二个晶体管T 2、第三个晶体管T 3、第四个晶体管T 4的第一极s、第二极d同层、同材料设置，像素晶体管T的有源层与第一个晶体管T 1、第二个晶体管T 2、第三个晶体管T 3、第四个晶体管T 4的有源层ac同层、同材料设置。在一些实施例中，转接电极105可以与像素电极108同层、同材料设置，以使得在构图形成像素电极108的同时形成转接电极105，避免额外增加转接电极105的膜层、以及构图工艺。可选地，像素电极108的材料可以包括氧化铟锡(ITO)、氧化铟锌(IZO)等。
需要说明的是，在本公开中，“同层、同材料”指的是采用同一成膜工艺形成用于制作特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。即一次构图工艺对应一道掩模板(mask，也称光罩)。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而所形成层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形可能处于相同的高度或者具有相同的厚度、也可能处于不同的高度或者具有不同的厚度。
继续参见图13，可以看出，像素电极108通过贯穿第一绝缘层106的过孔与像素晶体管T电连接，因此，在将转接电极105与像素电极108同层、同材料设置的情况下，还可以通过一次构图工艺在第一绝缘层106和第二绝缘层107中同时形成，贯穿第一绝缘层106且用于电连接像素电极108与像素晶体管T的过孔，贯穿第一绝缘层106用于电连接转接电极105与第一个晶体管T 1的第二极d、第二个晶体管T 2的第二极d、第三个晶体管T 3的第一极s、第四个晶体管T 4的第一极s的过孔，以及贯穿第一绝缘层106和第二绝缘层107且用于电连接转接电极105与第二个晶体管T 2的栅极g、第三个晶体管T 3的栅极g的过孔，由此避免了额外增加转接电极的105相关过孔的构图工艺。
在一些实施例中，在本公开实施例提供的上述显示基板中，如图14和图15所示，还包括多个第一转接端子109，一个第一转接端子109与一个子测试端子(例如ET DE、ET DO、ET SW、ET Vcom)电连接。可选地，第一静电环102通过第一转接端子109与非公共电压子测试端子(例如ET DE、ET DO、ET SW) 电连接。在一些实施例中，多个第一转接端子109可以与像素电极108同层、同材料设置，以在构图形成像素电极108的同时形成多个第一转接端子109，避免额外增加第一转接端子109的膜层、以及构图工艺。
基于同一发明构思，本公开实施例提供了一种中板，如图16所示，包括多个本公开实施例提供的上述显示基板201。由于该中板解决问题的原理与上述显示基板解决问题的原理相似，因此，本公开实施例提供的该中板的实施可以参见上述显示基板的实施，重复之处不再赘述。
在一些实施例中，在本公开实施例提供的上述中板中，如图16和图17所示，还包括位于多个显示基板201所在区一侧的多个测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW、AT Vcom)和第三静电环202，多个测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW、AT Vcom)包括公共电压测试端子AT Vcom和非公共电压测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW)，公共电压测试端子AT Vcom与公共电压子测试端子ET Vcom电连接，非公共电压测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW)与非公共电压子测试端子(例如ET GO、ET GE、ET DO、ET DE、ET SW)电连接。
可选地，非公共电压子测试端子(例如ET GO、ET GE、ET DO、ET DE、ET SW)为多个，至少两个非公共电压测试端子(例如ET GO、ET GE、ET DO、ET DE、ET SW)分别通过第三静电环202连接至公共电压测试端子ET Vcom。在一些实施例中，每个非公共电压子测试端子(例如ET GO、ET GE、ET DO、ET DE、ET SW)通过一个第三静电环202与一个非公共电压测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW)对应电连接。
在本公开实施例提供的上述中板中，公共电压测试端子AT Vcom与公共电压子测试端子ET Vcom电连接，非公共电压测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW)与非公共电压子测试端子(例如ET GO、ET GE、ET DO、ET DE、ET SW)电连接，可以使得各个非公共电压子测试端子(例如ET GO、ET GE、ET DO、ET DE、ET SW)、以及公共电压子测试端子(ET Vcom)上积累的静电传递至对应电连接的非公共电压测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW)和公 共电压测试端子AT Vcom上，且因在公共电压测试端子AT Vcom与非公共电压测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW)之间电连接有第三静电环202，可以使得第三静电环202在静电的高压作用下开启，这样非公共电压测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW)、第一静电环102、公共电压测试端子AT Vcom、公共电压子测试端子ET Vcom、公共电压线Vcom之间依次连通，静电就可以通过该通路释放至面积较大的公共电压线Vcom上，从而分散静电的影响，避免测试晶体管因静电作用而异常开启。并且，如图4和图7所示，由于在将中板切割为目标尺寸的显示基板201之后，公共电压测试端子AT Vcom、非公共电压测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW)以及二者之间的第三静电环202均被切割掉，因此在采用芯片感应获取公共电压的过程中，不会受到第三静电环202的漏电影响，从而可准确获得公共电压。
在一些实施例中，在本公开实施例提供的上述显示基板中，第三静电环202的结构可以与第一静电环102的结构相同，这样就可以利用相同的工艺参数完成第三静电环202和第一静电环102的制备，由此可简化静电环的制作工艺。并且，因第一静电环102所含晶体管的沟道宽长比大于第二静电环104所含晶体管的沟道宽长比，使得第一静电环102更容易受静电影响而导通，相应地，与第一静电环102结构相同的第三静电环202也容易受静电影响而导通，利于疏散静电，提高产品的抗静电能力。
在一些实施例中，在本公开实施例提供的上述中板中，多个测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW、AT Vcom)、以及多个子测试端子(例如ET GO、ET GE、ET DO、ET DE、ET SW、ET Vcom)与可以与第一个晶体管T 1、第二个晶体管T 2、第三个晶体管T 3、第四个晶体管T 4的栅极同层、同材料设置，这样就可以采用一个导电膜层，制备出以及一个晶体管T 1、第二个晶体管T 2、第三个晶体管T 3、第四个晶体管T 4的栅极，避免额外设置多个测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW、AT Vcom)、以及多个子测试端子(例如ET GO、ET GE、ET DO、ET DE、ET SW、ET Vcom)的膜层，且节约了单独制作多个 测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW、AT Vcom)、以及多个子测试端子(例如ET GO、ET GE、ET DO、ET DE、ET SW、ET Vcom)的工艺。
在一些实施例中，在本公开实施例提供的上述中板中，如图16所示，还可以包括多条第一连接线203、多条第二连接线204和多条第一转接线205，其中，多条第一连接线203与多条第二连接线204同层、同材料设置，多条第一连接线203与多条第一转接线205异层设置；一条第一连接线203与一个子测试端子(例如ET GO、ET GE、ET DO、ET DE、ET SW、ET Vcom)电连接，一条第二连接线204与一个测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW、AT Vcom)电连接，一条第一转接线205电连接在一条第一连接线203与一条第二连接线204之间，使得子测试端子(例如ET GO、ET GE、ET DO、ET DE、ET SW、ET Vcom)依次通过第一连接线203、第一转接线205、第二连接线204与测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW、AT Vcom)电连接。由图16可见，同层、同材料设置的第一连接线203和第二连接线204为一一对应的多条的情况下，通过异层的第一转接线205将相应的第一连接线203与第二连接线204电连接在一起，不仅可有效避免不同第一连接线203之间短接、还可有效避免不同第二连接线204之间短接。
在一些实施例中，在本公开实施例提供的上述中板中，如图18至图20所示，还包括多条第二转接线206、多条第三转接线207和一条第四转接线208，一个非公共电压测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW)通过一条第二转接线206与对应的第二连接线204电连接，一条第二转接线206通过一个第三静电环202与一条第三转接线207电连接，多条第三转接线207与第四转接线208电连接，公共电压测试端子AT Vcom通过第四转接线208与对应的第二连接线204电连接。在一些实施例中，如图20所示，为便于实现各第三转接线207与第四转接线208之间的电连接，可将各第三转接线207汇聚在一起后再连接至第四转接线208。当然，在另一些实施例中，各第三转接线207也可以分别与第四转接线208电连接，在此不做限定。
在一些实施例中，在本公开实施例提供的上述中板中，如图19至图21 所示，还可以包括第四静电环209，第四静电环209电连接在第三转接线207与第四转接线208之间；或者，如图22所示，第三转接线207可以与第四转接线208一体设置。第四静电环209的设置可以避免不同的测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW、AT Vcom)之间相互影响，提高测试准确性。可选地，第四静电环209的结构与第一静电环102的结构相同。这样就可以利用相同的工艺参数完成第四静电环209和第一静电环102的制备，由此可简化静电环的制作工艺。并且，因第一静电环102易受静电影响而导通，所以与第一静电环102结构相同的第四静电环209也容易受静电影响而导通，利于疏散静电，提高产品的抗静电能力。
在一些实施例中，在本公开实施例提供的上述中板中，第一转接线205、第二转接线206、第三转接线207、以及第四转接线208均与像素电极108同层、同材料设置，以使得在构图形成像素电极108的同时形成第一转接线205、第二转接线206、第三转接线207、以及第四转接线208，避免额外增加第一转接线205、第二转接线206、第三转接线207、以及第四转接线208的膜层、以及构图工艺。
在一些实施例中，在本公开实施例提供的上述中板中，如图15和图16所示，还可以包括多个第二转接端子210，多个第二转接端子210与多个测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW、AT Vcom)电连接，以便于在电学测试过程中通过第二转接端子210为测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW、AT Vcom)加载信号。可选地，多个第二转接端子210与像素电极108同层、同材料设置，以使得在构图形成像素电极108的同时形成第二转接端子210，避免额外增加第二转接端子210的膜层、以及构图工艺。在一些实施例中，在各测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW、AT Vcom)的排列方向上，第二转接端子210的尺寸等于测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW、AT Vcom)的尺寸；在各测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW、AT Vcom)的排列方向的垂直方向上，第二转接端子210的尺寸小于测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW、AT Vcom)的尺寸，例 如在各测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW、AT Vcom)的排列方向的垂直方向上，第二转接端子210的尺寸与测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW、AT Vcom)的尺寸之比大于等于1/2且小于等于2/3。
在一些实施例中，在本公开实施例提供的上述中板中，如图18和图19所示，还可以包括短接棒211和多条高阻线212，高阻线212位于第二转接端子210之间，一条高阻线212与一个第二转接端子210一体设置，一个测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW、AT Vcom)通过一条高阻线212电连接至短接棒211，短接棒211浮空设置。以避免电学测试过程中，不同测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW、AT Vcom)之间的信号相互干扰。可选地，高阻线212可以为由多个“U”型线段拼接成的弯折线。
基于同一发明构思，本公开实施例提供了一种显示基板的制作方法，由于该制作方法解决问题的原理与上述中板和显示基板解决问题的原理相似，因此，该制作方法的实施可以参见上述中板和显示基板的实施例，重复之处不再赘述。
在一些实施例中，本公开实施例提供的显示基板的制作方法可以包括以下步骤：
提供本公开实施例提供的上述中板；
对中板进行切割处理，获取显示基板，显示基板包括衬底基板，衬底基板包括显示区、以及位于显示区至少一侧的边框区，边框区设置有多个子测试端子和多个第一静电环，多个子测试端子包括公共电压子测试端子和多个非公共电压子测试端子，多个非公共电压子测试端子通过第一静电环串联设置和/或接地设置。
基于同一发明构思，本公开实施例提供了一种电子纸显示装置，包括相对而置的显示基板和对向基板，以及位于显示基板与对向基板之间的电泳层(FPL)，显示基板为本公开实施例提供的上述显示基板。可选地，对向基板包括面状结构的公共电极，公共电极在边框区BB与公共电极线Vcom电连接，公共电极的材料可以包括氧化铟锡(ITO)、氧化铟锌(IZO)等。电泳层包括 多个电泳粒子，每个电泳粒子可以包括：粒子本体，以及位于该粒子本体内的电泳液和带电粒子，带电粒子可以包括黑粒子和白粒子，或者带电粒子可以包括黑粒子、白粒子和彩色粒子(例如红粒子、黄粒子、蓝粒子等)。通过像素电极与公共电极形成的电场控制不同电荷的黑粒子、白粒子，或者黑粒子、白粒子、彩粒子(例如红粒子、黄粒子、蓝粒子等)的升降移动，可以显示出黑白画面或黑白红、黑白黄、黑白蓝等色彩画面。
在一些实施例中，本公开实施例提供的上述电子纸产品可以包括但不限于：射频单元、网络模块、音频输出&输入单元、传感器、显示单元、用户输入单元、接口单元以及控制芯片等部件。可选地，控制芯片为中央处理器、数字信号处理器、系统芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、信号线等实现供电以及信号输入输出功能。例如，控制芯片还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可编程逻辑设备等。并且，本领域技术人员可以理解的是，上述结构并不构成对本公开实施例提供的上述显示装置的限定，换言之，在本公开实施例提供的上述电子纸中可以包括上述更多或更少的部件，或者组合某些部件，或者不同的部件布置。
综上所述，本公开实施例提供的显示基板、其制作方法、中板及电子纸显示装置，本公开在显示基板上，将各非公共电压子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW)采用第一静电环102串联设置和/或接地设置，使得在各非公共电压子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW)上积累的静电过多时，第一静电环102在静电的高压作用下开启，各非公共电压子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW)之间形成通路，由此增加了静电传输路径，有效分散了静电，降低了静电对与非公共电压子测试端子ET SW电连接的测试晶体管造成的不良影响，提高了产品的抗静电能力。通过在公共电压子测试端子ET Vcom与相邻的非公共电压子测试端子(例如ET DE、 ET DO、ET GE、ET GO、ET SW中的任一个)设置第二静电环104，可以使得在公共电压子测试端子ET Vcom与相邻的非公共电压子测试端子(例如ET DE、ET DO、ET GE、ET GO、ET SW中的任一个)上的静电积累过多的情况下，第二静电环104在静电的高压作用下开启，由此增加了静电释放路径，进一步降低了静电对测试晶体管的影响；并且，因第二静电环104所含晶体管的沟道宽长比小于第一静电环102所含晶体管的沟道宽长比，可以使得第二静电环104所含晶体管的漏电流较小，从而尽可能地降低了第二静电环104对芯片感应获取的公共电压的影响。
另外，通过在中板的公共电压测试端子AT Vcom与非公共电压测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW)间设置第三静电环202，可以使得第三静电环202在静电的高压作用下开启，这样非公共电压测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW)、第一静电环102、公共电压测试端子AT Vcom、公共电压子测试端子ET Vcom、公共电压线Vcom之间依次连通，静电就可以通过该通路释放至面积较大的公共电压线Vcom上，从而分散静电的影响，避免测试晶体管因静电作用而异常开启而影响显示效果。并且，由于在将中板切割为目标尺寸的显示基板201之后，公共电压测试端子AT Vcom、非公共电压测试端子(例如AT GO、AT GE、AT DO、AT DE、AT SW)以及二者之间的第三静电环202均被切割掉，因此在采用芯片感应获取公共电压的过程中，不会受到第三静电环202的漏电影响，从而可准确获得公共电压。
尽管本公开已描述了优选实施例，但应当理解的是，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (27)

  1. 一种显示基板，其中，包括：
    衬底基板，所述衬底基板包括显示区、以及位于所述显示区至少一侧的边框区；
    多个子测试端子，位于所述边框区，所述多个子测试端子包括公共电压子测试端子和多个非公共电压子测试端子；
    第一静电环，位于所述边框区，所述多个非公共电压子测试端子通过所述第一静电环串联设置和/或接地设置。
  2. 如权利要求1所述的显示基板，其中，所述第一静电环电连接在相邻两个所述非公共电压子测试端子之间。
  3. 如权利要求2所述的显示基板，其中，还包括第二静电环，所述第二静电环电连接在所述公共电压子测试端子与相邻的所述非公共电压子测试端子之间；
    所述第二静电环和所述第一静电环均包括相互电连接的多个晶体管，所述第二静电环所含晶体管的沟道宽长比小于所述第一静电环所含晶体管的沟道宽长比。
  4. 如权利要求1～3任一项所述的显示基板，其中，所述第一静电环包括第一连接端和第二连接端；
    所述第一静电环中包括四个晶体管，其中，第一个晶体管的栅极、第一个晶体管的第一极、第二个晶体管的第一极电连接在一起作为所述第一连接端；第一个晶体管的第二极、第二个晶体管的第二极、第二个晶体管的栅极、第三个晶体管的栅极、第三个晶体管的第一极、第四个晶体管的第一极电连接在一起；第四个晶体管的栅极、第四个晶体管的第二极、以及第三个晶体管的第二极电连接在一起作为所述第二连接端。
  5. 如权利要求4所述的显示基板，其中，还包括位于所述第一静电环所在层之上的转接电极，所述转接电极分别与第一个晶体管的第二极、第二个 晶体管的第二极、第二个晶体管的栅极、第三个晶体管的栅极、第三个晶体管的第一极、第四个晶体管的第一极电连接。
  6. 如权利要求5所述的显示基板，其中，还包括位于所述第一静电环所在层之上的像素电极，所述转接电极与所述像素电极同层、同材料设置。
  7. 如权利要求3所述的显示基板，其中，所述第二静电环中多个晶体管之间的电连接方式与所述第一静电环中多个晶体管之间的电连接方式相同。
  8. 如权利要求1～7任一项所述的显示基板，其中，还包括多个第一转接端子，一个所述第一转接端子与一个所述子测试端子电连接。
  9. 如权利要求8所述的显示基板，其中，所述第一静电环通过所述第一转接端子与所述非公共电压子测试端子电连接。
  10. 如权利要求8或9所述的显示基板，其中，还包括位于所述第一静电环所在层之上的像素电极，所述多个第一转接端子与所述像素电极同层、同材料设置。
  11. 如权利要求1～10任一项所述的显示基板，其中，还包括位于所述边框区的接地线，各所述非公共电压子测试端子分别通过所述第一静电环电连接至所述接地线。
  12. 一种中板，其中，包括多个显示基板，所述显示基板为如权利要求1～11任一项所述的显示基板。
  13. 如权利要求12所述的中板，其中，还包括：位于所述多个显示基板所在区一侧的多个测试端子和第三静电环，其中，所述多个测试端子包括公共电压测试端子和非公共电压测试端子，所述公共电压测试端子与所述公共电压子测试端子电连接，所述非公共电压测试端子与所述非公共电压子测试端子电连接，所述第三静电环电连接在所述公共电压测试端子与所述非公共电压测试端子之间。
  14. 如权利要求13所述的中板，其中，所述非公共电压测试端子的数量为多个，至少两个所述非公共电压测试端子分别通过所述第三静电环连接至所述公共电压测试端子。
  15. 如权利要求14所述的中板，其中，所述第三静电环的结构与所述第一静电环的结构相同。
  16. 如权利要求13～15任一项所述的中板，其中，所述多个测试端子、以及所述多个子测试端子均与所述多个晶体管的栅极同层、同材料设置。
  17. 如权利要求16所述的中板，其中，还包括多条第一连接线、多条第二连接线和多条第一转接线，其中，所述多条第一连接线与所述多条第二连接线同层、同材料设置，所述多条第一连接线与所述多条第一转接线异层设置；一条所述第一连接线通过一个所述第一转接端子与一个所述子测试端子对应电连接，一条所述第二连接线与一个所述测试端子电连接，一条所述第一转接线电连接在一条所述第一连接线与一条所述第二连接线之间。
  18. 如权利要求17所述的中板，其中，还包括多条第二转接线、多条第三转接线和一条第四转接线，一个所述非公共电压测试端子通过一条所述第二转接线与对应的所述第二连接线电连接，一条所述第二转接线通过一个所述第三静电环与一条所述第三转接线电连接，所述多条第三转接线与所述第四转接线电连接，所述公共电压测试端子通过所述第四转接线与对应的所述第二连接线电连接。
  19. 如权利要求18所述的中板，其中，所述多条第三转接线与所述第四转接线一体设置。
  20. 如权利要求18所述的中板，其中，还包括第四静电环，所述多条第三转接线通过所述第四静电环与所述第四转接线电连接。
  21. 如权利要求20所述的中板，其中，所述第四静电环的结构与所述第一静电环的结构相同。
  22. 如权利要求18～21任一项所述的中板，其中，还包括位于所述第一静电环所在层之上的像素电极，所述第一转接线、所述第二转接线、所述第三转接线、以及所述第四转接线均与所述像素电极同层、同材料设置。
  23. 如权利要求16～22任一项所述的中板，其中，还包括多个第二转接端子，一个所述第二转接端子与一个所述测试端子对应电连接。
  24. 如权利要求23所述的中板，其中，还包括位于所述第一静电环所在层之上的像素电极，所述多个第二转接端子与所述像素电极同层、同材料设置。
  25. 如权利要求23或24所述的中板，其中，还包括短接棒和多条高阻线，所述高阻线位于所述第二转接端子之间，一条所述高阻线与一个所述第二转接端子一体设置，一个所述测试端子通过一条所述高阻线电连接至所述短接棒，所述短接棒浮空设置。
  26. 一种显示基板的制作方法，其中，包括：
    提供如权利要求12～25任一项所述的中板；
    对所述中板进行切割处理，获取所述显示基板，所述显示基板包括衬底基板，所述衬底基板包括显示区、以及位于所述显示区至少一侧的边框区，所述边框区设置有多个子测试端子和多个第一静电环，所述多个子测试端子包括公共电压子测试端子和多个非公共电压子测试端子，所述多个非公共电压子测试端子通过所述第一静电环串联设置和/或接地设置。
  27. 一种电子纸显示装置，其中，包括相对而置的显示基板和对向基板，以及位于所述显示基板和对向基板之间的电泳层；其中，所述显示基板为如权利要求1～11任一项所述的显示基板。
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CN103676345A (zh) * 2012-09-20 2014-03-26 上海中航光电子有限公司 一种防静电显示面板
CN105070712A (zh) * 2015-07-10 2015-11-18 合肥鑫晟光电科技有限公司 显示基板及其制作方法、显示面板、显示装置
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