WO2023000352A1 - 显示面板及其制备方法、显示装置 - Google Patents

显示面板及其制备方法、显示装置 Download PDF

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Publication number
WO2023000352A1
WO2023000352A1 PCT/CN2021/108400 CN2021108400W WO2023000352A1 WO 2023000352 A1 WO2023000352 A1 WO 2023000352A1 CN 2021108400 W CN2021108400 W CN 2021108400W WO 2023000352 A1 WO2023000352 A1 WO 2023000352A1
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Prior art keywords
gate
layer
pattern
light
source
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PCT/CN2021/108400
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English (en)
French (fr)
Inventor
罗传宝
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/438,999 priority Critical patent/US12004374B2/en
Publication of WO2023000352A1 publication Critical patent/WO2023000352A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133371—Cells with varying thickness of the liquid crystal layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G02F1/13312—Circuits comprising photodetectors for purposes other than feedback
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
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    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
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    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • the present application relates to the field of display technology, in particular to an OLED display panel and an OLED display device.
  • the fingerprint sensor In order to increase the screen-to-body ratio of the display device, the fingerprint sensor will be placed under the display screen. Because oxide thin film transistors have higher electron mobility and stability than amorphous silicon thin film transistors, existing fingerprint sensors use oxide thin film transistors, such as indium gallium zinc oxide thin film transistors. However, due to the high bandwidth of the indium gallium zinc oxide thin film transistor, it only absorbs ultraviolet light with a shorter wavelength. According to the test of the oxide thin film transistor, its leakage current is lower than that of light with a wavelength lower than 468 nanometers.
  • the oxide thin film transistor still has a large amount of visible light that cannot be sensed, resulting in fingerprint sensors with indium gallium zinc oxide thin film transistors unable to recognize finger clicks, and the fingerprint recognition effect is poor Difference.
  • the existing display device has the technical problem that the light-sensing range of the oxide thin film transistor is relatively small, resulting in poor recognition effect of the fingerprint sensor.
  • Embodiments of the present application provide a display panel, a manufacturing method thereof, and a display device, so as to alleviate the technical problem of poor recognition effect of a fingerprint sensor caused by a small photosensitive range of an oxide thin film transistor in an existing display device.
  • An embodiment of the present application provides a display panel, the display panel includes an array substrate, and the array substrate includes:
  • a first gate disposed on one side of the substrate
  • a second gate disposed on a side of the active pattern away from the first gate
  • the array substrate further includes a first source and a first drain, the first gate, the first source, the first drain, the second gate and the active
  • the pattern forms a first thin film transistor
  • the second gate, the photosensitive pattern and the electrode plate form a capacitor.
  • the first gate and the first source are arranged in the same layer, and the first gate and the first source are insulated, and the first gate and the first source are insulated.
  • a drain is provided in the same layer, and the first gate is insulated from the first drain.
  • the array substrate further includes a second source, a third gate and a first light-shielding pattern, the second source, the first drain, the third gate and the
  • the active pattern forms a second thin film transistor, the first light-shielding pattern is arranged corresponding to the active pattern of the second thin film transistor, and the first light-shielding pattern is connected to the first gate, the first source and the first light-shielding pattern.
  • the first drain is disposed on the same layer, and the first light-shielding pattern is insulated from the first gate, the first source, and the first drain.
  • the array substrate further includes a pixel electrode layer, the pixel electrode layer is disposed on a side of the photosensitive pattern away from the second gate, the pixel electrode layer includes a pixel electrode and an electrode plate, And the pole plate is insulated from the pixel electrode.
  • the array substrate further includes a transparent conductive layer and a pixel electrode layer, the transparent conductive layer is disposed between the pixel electrode layer and the photosensitive pattern, the transparent conductive layer is formed with an electrode plate, And the electrode plate is insulated from the pixel electrode layer.
  • the array substrate further includes a second light-shielding pattern, and the second light-shielding pattern is correspondingly disposed on the second thin film transistor.
  • the second gate and the third gate are arranged in the same layer.
  • the material of the photosensitive pattern includes at least one of amorphous silicon and thiophene-based organic materials.
  • the array substrate also includes:
  • a light-shielding layer disposed on one side of the substrate, and the light-shielding layer forms a first light-shielding pattern
  • a buffer layer disposed on a side of the light-shielding layer away from the substrate
  • a metal layer, the metal layer is formed with a first gate, the first source and the first drain.
  • the array substrate also includes:
  • a light-shielding layer disposed on one side of the substrate, and the light-shielding layer forms a first light-shielding pattern
  • a buffer layer disposed on a side of the light-shielding layer away from the substrate
  • a first metal layer disposed on a side of the buffer layer away from the light-shielding layer
  • a first gate insulating layer disposed on a side of the first metal layer away from the buffer layer;
  • a second gate insulating layer disposed on a side of the active layer away from the first metal layer
  • a second metal layer disposed on a side of the second gate insulating layer away from the active layer, the second metal layer is formed with the second gate;
  • the first metal layer is formed with the first gate, the first source and the first drain.
  • an embodiment of the present application provides a display device, the display device includes a display panel and electronic components, the display panel includes an array substrate, and the array substrate includes:
  • a first gate disposed on one side of the substrate
  • a second gate disposed on a side of the active pattern away from the first gate
  • the array substrate further includes a first source and a first drain, the first gate, the first source, the first drain, the second gate and the active
  • the pattern forms a first thin film transistor
  • the second gate, the photosensitive pattern and the electrode plate form a capacitor.
  • the electronic component includes an under-display camera.
  • the display panel includes a liquid crystal display panel or an OLED display panel.
  • the first gate and the first source are arranged in the same layer, and the first gate and the first source are insulated, and the first gate and the first source are insulated.
  • a drain is provided in the same layer, and the first gate is insulated from the first drain.
  • the array substrate further includes a second source, a third gate and a first light-shielding pattern, the second source, the first drain, the third gate and the
  • the active pattern forms a second thin film transistor, the first light-shielding pattern is arranged corresponding to the active pattern of the second thin film transistor, and the first light-shielding pattern is connected to the first gate, the first source and the first light-shielding pattern.
  • the first drain is disposed on the same layer, and the first light-shielding pattern is insulated from the first gate, the first source, and the first drain.
  • the array substrate further includes a pixel electrode layer, the pixel electrode layer is disposed on a side of the photosensitive pattern away from the second gate, the pixel electrode layer includes a pixel electrode and an electrode plate, And the pole plate is insulated from the pixel electrode.
  • the array substrate further includes a transparent conductive layer and a pixel electrode layer, the transparent conductive layer is disposed between the pixel electrode layer and the photosensitive pattern, the transparent conductive layer is formed with an electrode plate, And the electrode plate is insulated from the pixel electrode layer.
  • the array substrate further includes a second light-shielding pattern, and the second light-shielding pattern is correspondingly disposed on the second thin film transistor.
  • the second gate and the third gate are arranged in the same layer.
  • the embodiment of the present application provides a method for manufacturing a display panel, the method for manufacturing a display panel includes:
  • first metal layer on the substrate, and processing the first metal layer to form a first gate, a first source, a first drain, a second source, and a second drain;
  • An electrode plate is formed on the side of the photosensitive pattern away from the second gate; the first gate, the first source, the second gate and the active pattern form a first thin film transistor , the second grid, the photosensitive pattern and the electrode plate form a capacitor.
  • the present application provides a display panel, its preparation method, and a display device.
  • the array substrate includes a substrate, a first grid, an active pattern, a second grid, a photosensitive pattern, and an electrode plate, and the first grid is arranged on the substrate.
  • the active pattern is arranged on the side of the first gate away from the substrate
  • the second gate is arranged on the side of the active pattern away from the first gate
  • the photosensitive pattern is arranged on the side of the second gate away from the active pattern
  • the electrode plate is arranged on the side of the photosensitive pattern away from the second gate
  • the array substrate further includes a first source and a first drain, the first gate, the first source, the first drain, the second
  • the second gate and the active pattern form the first thin film transistor, and the second gate, the photosensitive pattern and the plate form a capacitor.
  • a capacitor is arranged in the array substrate, the capacitor is connected to the first thin film transistor, and the photosensitive pattern in the capacitor is exposed to light, so that when the light changes, the change of the charge amount of the photosensitive pattern of the capacitor drives the current change of the first thin film transistor,
  • the photosensitivity of the photosensitive pattern is better than that of the active pattern of the thin film transistor, thereby improving the photosensitive characteristic of the first thin film transistor and improving the fingerprint recognition effect, and using the second grid as a capacitor plate reduces the sensitivity of the array substrate. thickness.
  • FIG. 1 is a first schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a circuit diagram of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a second schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 4 is a third schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 5 is a first flow chart of a method for manufacturing a display panel provided in an embodiment of the present application.
  • FIG. 6 is a second flow chart of the method for manufacturing a display panel provided by the embodiment of the present application.
  • FIG. 7 is a first schematic diagram of a display panel corresponding to each step of the method for manufacturing a display panel provided in the embodiment of the present application.
  • FIG. 8 is a second schematic diagram of a display panel corresponding to each step of the method for manufacturing a display panel provided in the embodiment of the present application.
  • FIG. 9 is a third schematic diagram of a display panel corresponding to each step of the method for manufacturing a display panel provided in the embodiment of the present application.
  • FIG. 10 is a fourth schematic diagram of a display panel corresponding to each step of the method for manufacturing a display panel provided in the embodiment of the present application.
  • FIG. 11 is a schematic diagram of a display device provided by an embodiment of the present application.
  • the embodiment of the present application aims at the technical problem that the photosensitive range of the oxide thin film transistor is small in the existing display device, resulting in poor recognition effect of the fingerprint sensor, and provides an array substrate and its preparation method, and a display panel to alleviate the above technical problems .
  • an embodiment of the present application provides a display panel 1, the display panel 1 includes an array substrate, and the array substrate includes:
  • the first gate 112 is disposed on one side of the substrate 11;
  • the second gate 151 is disposed on a side of the active pattern 13 away from the first gate 112;
  • the photosensitive pattern 16 is arranged on the side of the second gate 151 away from the active pattern 13;
  • An electrode plate 181 is disposed on a side of the photosensitive pattern 16 away from the second grid 151;
  • the array substrate further includes a first source 111 and a first drain 113, the first gate 112, the first source 111, the first drain 113, the second gate 151 and the active pattern 13 form a first thin film transistor 22 , and the second gate 151 , the photosensitive pattern 16 and the electrode plate 181 form a capacitor 21 .
  • An embodiment of the present application provides a display panel.
  • the display panel includes an array substrate.
  • the array substrate connects the capacitor to the first thin film transistor by setting a capacitor, and receives light through the photosensitive pattern in the capacitor, so that when the light changes, the photosensitive
  • the change of the charge amount of the pattern drives the current change of the first thin film transistor, and the photosensitive characteristic of the photosensitive pattern is better than that of the active pattern of the thin film transistor, thereby improving the photosensitive characteristic of the first thin film transistor and improving the fingerprint recognition effect, and will
  • the second grid acts as a capacitor plate, which reduces the thickness of the array substrate.
  • the first gate and the first source are arranged in the same layer, and the first gate and the first source are insulated, and the first gate and the first source are insulated.
  • the first drain is arranged in the same layer, and the first gate is insulated from the first drain.
  • the first gate, the first source and the first drain By arranging the first gate, the first source and the first drain on the same layer, there is no need to arrange two layers of metal to form the first gate, the first source and the first drain respectively, reducing the thickness of the array substrate , and because the first gate is arranged on the same layer as the first source and the first drain, there is no need to set multiple masks to form metal layers and dig holes, reducing the complexity of the array substrate preparation process.
  • the array substrate further includes a second source 115, a third gate 152 and a first light-shielding pattern 114, the second source 115, the first drain
  • the electrode 113, the third gate 152 and the active pattern 13 are formed with the second thin film transistor 23, the first light-shielding pattern 114 is set corresponding to the active pattern 13 of the second thin film transistor 23, and the The first light-shielding pattern 114 is set on the same layer as the first gate 112, the first source 111 and the first drain 113, and the first light-shielding pattern 114 is connected to the first gate, the first drain 113, and The first source and the first drain are insulated.
  • the first light-shielding pattern By arranging the first light-shielding pattern on the same layer as the first source, the first drain and the first gate, only one metal layer needs to be provided, and there is no need to separately form the metal layer corresponding to the first light-shielding pattern and the first gate.
  • the metal layer corresponding to the electrode, the metal layer corresponding to the first source electrode and the first drain electrode, and the insulating layer between the metal layers reduce the thickness of the display panel, and in the formation process of the metal layer, there is no need to set more
  • Each metal layer and each insulating layer is formed by using a mask plate, which simplifies the formation process of the display panel.
  • the source and drain of the first thin film transistor and the second thin film transistor are arranged on the same layer, which reduces the thickness of the array substrate, And the first drain of the first thin film transistor is shared with the second drain of the second thin film transistor, which reduces the occupation area of the first thin film transistor and the second thin film transistor, and can increase the area of the display area of the array substrate, correspondingly Improve the resolution or brightness of the display panel, and improve the display effect of the display panel.
  • the first light-shielding pattern corresponding to the third grid the impact of external light on the thin film transistor is avoided.
  • the second gate of the first thin film transistor as a plate of the capacitor, direct control of the first thin film transistor can be realized, and at the same time, the upper part uses a transparent conductive layer or a pixel electrode layer to form another plate of the capacitor.
  • the one polar plate makes the influence of the coupling between the capacitor and other capacitors of the array substrate less, improves the signal-to-noise ratio of the fingerprint sensor, and improves the effect of fingerprint identification.
  • the active pattern of the first thin film transistor is connected to the active pattern of the second thin film transistor.
  • the active patterns of the first thin film transistor and the active patterns of the second thin film transistor are connected to realize the connection between the first thin film transistor and the second thin film transistor.
  • the series connection of thin film transistors can output current between the first thin film transistor and the second thin film transistor to realize the fingerprint identification function.
  • the array substrate further includes a pixel electrode layer 18, and the pixel electrode layer 18 is disposed on a side of the photosensitive pattern 16 away from the second gate.
  • the pixel electrode layer 18 includes a pixel electrode 182 and a pole plate 181 , and the pole plate 181 is insulated from the pixel electrode 182 .
  • the photosensitive pattern in the region corresponding to the pixel electrode can be etched when forming the photosensitive pattern and the second passivation layer, so that after the pixel electrode layer is formed, the pixel electrode will It is arranged on the first passivation layer, and the electrode plate is arranged on the second passivation layer, so that the same film layer is used to form the pixel electrode and the electrode plate respectively, reducing the preparation process of the display panel and reducing the thickness of the display panel.
  • the array substrate further includes a transparent conductive layer 183 and a pixel electrode layer 18, and the transparent conductive layer 183 is disposed between the pixel electrode layer 18 and the photosensitive pattern 16.
  • the transparent conductive layer 183 is formed with an electrode plate, and the electrode plate is insulated from the pixel electrode layer 18 .
  • the transparent conductive layer can also be arranged in the array substrate to form the polar plate through the transparent conductive layer, so as to prevent the polar plate from affecting the setting of the pixel electrode layer.
  • a third passivation layer 184 is provided between the transparent conductive layer 183 and the pixel electrode layer 18 , and the transparent conductive layer and the pixel electrode layer are insulated through the third passivation layer.
  • the display panel further includes a third source 101, a third drain 103, a fourth gate 102, a fifth gate 104, a third source 101, a third drain 103 , the fourth gate 102, the fifth gate 104 and the active pattern form a third thin film transistor, the third source 101 is connected to the pixel electrode 182, and the third thin film transistor is used to drive the organic light emitting device to emit light.
  • the second gate and the third gate are arranged in the same layer.
  • the third gate and the second gate are arranged on the same layer, there is no need to separately arrange the metal layer corresponding to the second gate and the metal layer corresponding to the third gate, thereby reducing the thickness of the array substrate.
  • the array substrate further includes a second light-shielding pattern 19 , and the second light-shielding pattern 19 is correspondingly disposed on the second thin film transistor 23 .
  • the second light-shielding pattern can shield the external light, so as to prevent the external light from affecting the second thin film transistor, resulting in poor fingerprint recognition effect.
  • the working process of the fingerprint sensor is illustrated with a partial circuit diagram of the array substrate, and the high potential voltage terminal +HV is used to indicate that the capacitance C changes with the change of light, that is, the voltage of the high potential voltage terminal +HV changes with the change of light change, one end of the capacitor C is connected to the high potential voltage end +HV, the other end of the capacitor C is connected to the second gate of the first thin film transistor T1, the first gate of the first thin film transistor T1 is connected to the scanning line Scan, and the first thin film transistor
  • the first source of T1 is connected to the first power supply terminal Vdd
  • the first drain of the first thin film transistor T1 is connected to the second source of the second thin film transistor T2
  • the first drain of the first thin film transistor T1 is connected to the voltage output terminal Vout
  • the second drain of the second thin film transistor T2 is connected to the second power supply terminal Vss
  • the third gate of the second thin film transistor T2 is connected to the scan line.
  • the photosensitive range of the photosensitive pattern improves the effect of fingerprint recognition.
  • the array substrate further includes:
  • a light-shielding layer disposed on one side of the substrate, and the light-shielding layer forms a first light-shielding pattern
  • a buffer layer disposed on a side of the light-shielding layer away from the substrate
  • a metal layer, the metal layer is formed with a first gate, the first source and the first drain.
  • the array substrate further includes:
  • a light-shielding layer disposed on one side of the substrate, and the light-shielding layer forms a first light-shielding pattern
  • a buffer layer disposed on a side of the light-shielding layer away from the substrate
  • a first metal layer disposed on a side of the buffer layer away from the light-shielding layer
  • a first gate insulating layer disposed on a side of the first metal layer away from the buffer layer;
  • a second gate insulating layer disposed on a side of the active layer away from the first metal layer
  • a second metal layer disposed on a side of the second gate insulating layer away from the active layer, the second metal layer is formed with the second gate;
  • the first metal layer is formed with the first gate, the first source and the first drain.
  • the first metal layer forms the first gate, the first source and the first drain, reducing the thickness of the array substrate, and because the first gate, the first source and the first drain
  • the electrode and the first light-shielding pattern are arranged in different layers, which can reduce the area occupied by the thin film transistor in the array substrate.
  • the second gate and the first source are provided on the same layer, and the second gate is insulated from the first source, and the second gate and the The first drain is arranged in the same layer, and the second gate is insulated from the first drain.
  • the material of the photosensitive pattern includes at least one of amorphous silicon and thiophene-based organic materials. Since amorphous silicon and thiophene-based organic materials have a large photosensitive range and can sense all visible light, the fingerprint recognition function can be realized through the capacitor, the first thin film transistor and the second thin film transistor, which can improve the recognition effect of the fingerprint sensor.
  • the array substrate further includes a buffer layer 12 disposed on a side of the light shielding layer 24 away from the substrate 11 .
  • the array substrate further includes a gate insulating layer 14 disposed on a side of the active pattern 13 away from the buffer layer 12 .
  • the array substrate further includes a gate layer 15, and the gate layer 15 is disposed on a side of the gate insulating layer 14 away from the active pattern 13,
  • the gate layer 15 is patterned with a second gate 151 and a third gate 152 .
  • the array substrate further includes a first passivation layer 20, and the first passivation layer 20 is disposed on the gate layer 15 away from the gate insulating layer 14. side.
  • the array substrate further includes a second passivation layer 17, and the second passivation layer 17 is disposed on the photosensitive pattern 16 away from the first passivation layer 20. side.
  • the material of the light-shielding layer includes one of molybdenum and molybdenum-copper laminates.
  • the material of the buffer layer includes one of silicon oxide and silicon nitride/silicon oxide stack.
  • the material of the active layer includes one of indium gallium zinc oxide, indium gallium zinc tin oxide, and indium gallium tin oxide.
  • the material of the first passivation layer includes silicon oxide, silicon oxide/silicon nitride stack.
  • the material of the second passivation layer includes one of silicon oxide, silicon oxide/silicon nitride stack, and silicon oxide/silicon nitride/alumina stack.
  • the material of the transparent conductive layer includes one of indium tin oxide and indium zinc oxide.
  • the embodiment of the present application provides a method for manufacturing a display panel, and the method for manufacturing an array substrate includes:
  • An embodiment of the present application provides a method for preparing a display panel.
  • the display panel prepared by the method for preparing a display panel is provided with a capacitor, connected to the first thin film transistor, and is exposed to light through the photosensitive pattern in the capacitor, so that when the light changes, the capacitance of the capacitor.
  • the change of the charge amount of the photosensitive pattern drives the current change of the first thin film transistor, and the photosensitive characteristic of the photosensitive pattern is better than that of the active pattern of the thin film transistor, thereby improving the photosensitive characteristic of the first thin film transistor and improving the fingerprint recognition effect, and
  • Using the second grid as a capacitor plate reduces the thickness of the array substrate.
  • the embodiment of the present application provides a method for manufacturing a display panel, the method for manufacturing a display panel includes:
  • the capacitor includes the first pole plate, the second pole plate, and a The photosensitive pattern; the photosensitive range of the photosensitive pattern is larger than the photosensitive range of the active pattern of the first thin film transistor; the structure of the display panel corresponding to this step is shown in (b) in FIG. 10 ;
  • the step of forming a buffer layer on the metal layer and etching the buffer layer to form the first via hole includes: performing the High temperature annealing treatment for 2 hours to 3 hours.
  • an embodiment of the present application provides a display device, the display device includes a display panel and electronic components, the display panel includes an array substrate, and the array substrate includes:
  • the first gate 112 is disposed on one side of the substrate 11;
  • the second gate 151 is disposed on a side of the active pattern 13 away from the first gate 112;
  • the photosensitive pattern 16 is arranged on the side of the second gate 151 away from the active pattern 13;
  • An electrode plate 181 is disposed on a side of the photosensitive pattern 16 away from the second grid 151;
  • the array substrate further includes a first source 111 and a first drain 113, the first gate 112, the first source 111, the first drain 113, the second gate 151 and the active pattern 13 form a first thin film transistor 22 , and the second gate 151 , the photosensitive pattern 16 and the electrode plate 181 form a capacitor 21 .
  • An embodiment of the present application provides a display device, the display device includes a display panel, the display panel includes an array substrate, the array substrate is provided with a capacitor, the capacitor is connected to the first thin film transistor, and the photosensitive pattern in the capacitor is exposed to light, so that in When the light changes, the change of the charge amount of the photosensitive pattern of the capacitor drives the current change of the first thin film transistor, and the photosensitive characteristic of the photosensitive pattern is better than that of the active pattern of the thin film transistor, thereby improving the photosensitive characteristic of the first thin film transistor, The fingerprint identification effect is improved, and the second grid is used as a capacitor plate, which reduces the thickness of the array substrate.
  • the electronic component includes an under-display camera.
  • the display panel includes a liquid crystal display panel. As shown in FIG. 11 , the liquid crystal display panel further includes a liquid crystal layer 41 , a common electrode layer 421 , a color resist layer 422 and a black matrix layer 423 .
  • the display panel includes an OLED (Organic Light-Emitting Diode, Organic Light-Emitting Diode) display panel.
  • OLED Organic Light-Emitting Diode, Organic Light-Emitting Diode
  • the first gate and the first source are arranged in the same layer, and the first gate and the first source are insulated, and the first The gate is arranged in the same layer as the first drain, and the first gate is insulated from the first drain.
  • the array substrate further includes a second source, a third gate and a first light-shielding pattern, the second source, the first drain, the first The tri-gate and the active pattern form a second thin film transistor, the first light-shielding pattern is set corresponding to the active pattern of the second thin-film transistor, the first light-shielding pattern is connected with the first gate, the The first source and the first drain are arranged in the same layer, and the first light-shielding pattern is insulated from the first gate, the first source and the first drain.
  • the array substrate further includes a pixel electrode layer, the pixel electrode layer is disposed on the side of the photosensitive pattern away from the second gate, and the pixel electrode layer includes A pixel electrode and a pole plate, and the pole plate is insulated from the pixel electrode.
  • the array substrate further includes a transparent conductive layer and a pixel electrode layer, the transparent conductive layer is arranged between the pixel electrode layer and the photosensitive pattern, and the transparent conductive layer An electrode plate is formed in the layer, and the electrode plate is insulated from the pixel electrode layer.
  • the array substrate further includes a second light-shielding pattern, and the second light-shielding pattern is correspondingly disposed on the second thin film transistor.
  • the second gate and the third gate are arranged in the same layer.
  • Embodiments of the present application provide a display panel, a manufacturing method thereof, and a display device.
  • the display panel includes an array substrate, and the array substrate includes a substrate, a first grid, an active pattern, a second grid, a photosensitive pattern, and an electrode plate.
  • the first gate is disposed on one side of the substrate
  • the active pattern is disposed on the side of the first gate away from the substrate
  • the second gate is disposed on the side of the active pattern away from the first gate
  • the photosensitive pattern is disposed on the side of the first gate
  • the second gate is away from the side of the active pattern
  • the electrode plate is arranged on the side of the photosensitive pattern away from the second gate
  • the array substrate further includes a first source and a first drain, the first gate, the first The source, the first drain, the second gate and the active pattern form a first thin film transistor
  • the second gate, the photosensitive pattern and the plate form a capacitor.
  • a capacitor is arranged in the array substrate, the capacitor is connected to the first thin film transistor, and the photosensitive pattern in the capacitor is exposed to light, so that when the light changes, the change of the charge amount of the photosensitive pattern of the capacitor drives the current change of the first thin film transistor,
  • the photosensitivity of the photosensitive pattern is better than that of the active pattern of the thin film transistor, thereby improving the photosensitive characteristic of the first thin film transistor and improving the fingerprint recognition effect, and using the second grid as a capacitor plate reduces the sensitivity of the array substrate. thickness.

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Abstract

一种显示面板（1）及其制备方法、显示装置；其中，显示面板（1）通过设置电容（21），使电容（21）与第一薄膜晶体管（22）连接，通过电容（21）中的感光图案（16）感光，使得在光照变化时，电容（21）的感光图案（16）的电荷量变化带动第一薄膜晶体管（22）的电流变化，提高了第一薄膜晶体管（22）的感光特性，提高指纹识别效果，且将第二栅极（151）作为电容（21）极板，降低了阵列基板的厚度。

Description

显示面板及其制备方法、显示装置 技术领域
本申请涉及显示技术领域，尤其是涉及一种OLED显示面板和OLED显示装置。
 背景技术
显示器件为了提高屏占比，会将指纹传感器设置在显示屏下。由于氧化物薄膜晶体管相较于非晶硅薄膜晶体管具有更高的电子迁移率和稳定性，现有指纹传感器会采用氧化物薄膜晶体管，例如氧化铟镓锌薄膜晶体管。但氧化铟镓锌薄膜晶体管由于具有较高的带宽，导致其只对波长较短的紫外光进行吸收，根据对氧化物薄膜晶体管进行测试可知，其漏电流在波长低于468纳米的光线下有明显的响应，但相较于400纳米至760纳米的可见光，氧化物薄膜晶体管仍然有大量的可见光无法感应到，导致具有氧化铟镓锌薄膜晶体管的指纹传感器无法识别手指点击处，指纹识别效果较差。
所以，现有显示器件存在氧化物薄膜晶体管的感光范围较小，导致指纹传感器识别效果较差的技术问题。
 技术问题
本申请实施例提供一种显示面板及其制备方法、显示装置，用以缓解现有显示器件存在氧化物薄膜晶体管的感光范围较小所导致的指纹传感器识别效果较差的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种显示面板，该显示面板包括阵列基板，该阵列基板包括：
衬底；
第一栅极，设置于所述衬底一侧；
有源图案，设置于所述第一栅极远离所述衬底的一侧；
第二栅极，设置于所述有源图案远离所述第一栅极的一侧；
感光图案，设置于所述第二栅极远离所述有源图案的一侧；
极板，设置于所述感光图案远离所述第二栅极的一侧；
其中，所述阵列基板还包括第一源极和第一漏极，所述第一栅极、所述第一源极、所述第一漏极、所述第二栅极和所述有源图案形成第一薄膜晶体管，所述第二栅极、所述感光图案和所述极板形成电容。
在一些实施例中，所述第一栅极与所述第一源极同层设置，且所述第一栅极与所述第一源极绝缘设置，所述第一栅极与所述第一漏极同层设置，且所述第一栅极与所述第一漏极绝缘设置。
在一些实施例中，所述阵列基板还包括第二源极、第三栅极和第一遮光图案，所述第二源极、所述第一漏极、所述第三栅极和所述有源图案形成第二薄膜晶体管，所述第一遮光图案对应于所述第二薄膜晶体管的有源图案设置，所述第一遮光图案与所述第一栅极、所述第一源极和所述第一漏极同层设置，且所述第一遮光图案与所述第一栅极、所述第一源极和所述第一漏极绝缘设置。
在一些实施例中，所述阵列基板还包括像素电极层，所述像素电极层设置于所述感光图案远离所述第二栅极的一侧，所述像素电极层包括像素电极和极板，且所述极板与所述像素电极绝缘设置。
在一些实施例中，所述阵列基板还包括透明导电层和像素电极层，所述透明导电层设置于所述像素电极层与所述感光图案之间，所述透明导电层形成有极板，且所述极板与所述像素电极层绝缘设置。
在一些实施例中，所述阵列基板还包括第二遮光图案，所述第二遮光图案对应设置于所述第二薄膜晶体管上。
在一些实施例中，所述第二栅极与所述第三栅极同层设置。
在一些实施例中，所述感光图案的材料包括非晶硅和噻吩系有机材料中的至少一种。
在一些实施例中，所述阵列基板还包括：
遮光层，设置于所述衬底一侧，所述遮光层形成第一遮光图案；
缓冲层，设置于所述遮光层远离所述衬底的一侧；
金属层，所述金属层形成有第一栅极、所述第一源极和所述第一漏极。
在一些实施例中，所述阵列基板还包括：
遮光层，设置于所述衬底一侧，所述遮光层形成第一遮光图案；
缓冲层，设置于所述遮光层远离所述衬底的一侧；
第一金属层，设置于所述缓冲层远离所述遮光层的一侧；
第一栅极绝缘层，设置于所述第一金属层远离所述缓冲层的一侧；
有源层，设置于所述第一栅极绝缘层远离所述第一金属层的一侧；
第二栅极绝缘层，设置于所述有源层远离所述第一金属层的一侧；
第二金属层，设置于所述第二栅极绝缘层远离所述有源层的一侧，所述第二金属层形成有所述第二栅极；
其中，所述第一金属层形成有所述第一栅极、所述第一源极和所述第一漏极。
同时，本申请实施例提供一种显示装置，该显示装置包括显示面板和电子元件，所述显示面板包括阵列基板，所述阵列基板包括：
衬底；
第一栅极，设置于所述衬底一侧；
有源图案，设置于所述第一栅极远离所述衬底的一侧；
第二栅极，设置于所述有源图案远离所述第一栅极的一侧；
感光图案，设置于所述第二栅极远离所述有源图案的一侧；
极板，设置于所述感光图案远离所述第二栅极的一侧；
其中，所述阵列基板还包括第一源极和第一漏极，所述第一栅极、所述第一源极、所述第一漏极、所述第二栅极和所述有源图案形成第一薄膜晶体管，所述第二栅极、所述感光图案和所述极板形成电容。
在一些实施例中，所述电子元件包括屏下摄像头。
在一些实施例中，所述显示面板包括液晶显示面板或者OLED显示面板。
在一些实施例中，所述第一栅极与所述第一源极同层设置，且所述第一栅极与所述第一源极绝缘设置，所述第一栅极与所述第一漏极同层设置，且所述第一栅极与所述第一漏极绝缘设置。
在一些实施例中，所述阵列基板还包括第二源极、第三栅极和第一遮光图案，所述第二源极、所述第一漏极、所述第三栅极和所述有源图案形成第二薄膜晶体管，所述第一遮光图案对应于所述第二薄膜晶体管的有源图案设置，所述第一遮光图案与所述第一栅极、所述第一源极和所述第一漏极同层设置，且所述第一遮光图案与所述第一栅极、所述第一源极和所述第一漏极绝缘设置。
在一些实施例中，所述阵列基板还包括像素电极层，所述像素电极层设置于所述感光图案远离所述第二栅极的一侧，所述像素电极层包括像素电极和极板，且所述极板与所述像素电极绝缘设置。
在一些实施例中，所述阵列基板还包括透明导电层和像素电极层，所述透明导电层设置于所述像素电极层与所述感光图案之间，所述透明导电层形成有极板，且所述极板与所述像素电极层绝缘设置。
在一些实施例中，所述阵列基板还包括第二遮光图案，所述第二遮光图案对应设置于所述第二薄膜晶体管上。
在一些实施例中，所述第二栅极与所述第三栅极同层设置。
同时，本申请实施例提供一种显示面板制备方法，该显示面板制备方法包括：
提供衬底；
在所述衬底上形成第一金属层，并对所述第一金属层进行处理，形成第一栅极、第一源极、第一漏极、第二源极和第二漏极；
在所述第一金属层远离所述衬底的一侧形成第二栅极；
在所述第二栅极远离所述第一金属层的一侧形成感光图案；
在所述感光图案远离所述第二栅极的一侧形成极板；所述第一栅极、所述第一源极、所述第二栅极和所述有源图案形成第一薄膜晶体管，所述第二栅极、所述感光图案和所述极板形成电容。
 有益效果
本申请提供一种显示面板及其制备方法、显示装置，该阵列基板包括衬底、第一栅极、有源图案、第二栅极、感光图案和极板，第一栅极设置于衬底一侧，有源图案设置于第一栅极远离衬底的一侧，第二栅极设置于有源图案远离第一栅极的一侧，感光图案设置于第二栅极远离有源图案的一侧，极板设置于感光图案远离第二栅极的一侧，其中，阵列基板还包括第一源极和第一漏极，第一栅极、第一源极、第一漏极、第二栅极和有源图案形成第一薄膜晶体管，第二栅极、感光图案和极板形成电容。本申请通过在阵列基板中设置电容，使电容与第一薄膜晶体管连接，通过电容中的感光图案感光，使得在光照变化时，电容的感光图案的电荷量变化带动第一薄膜晶体管的电流变化，而感光图案的感光特性优于薄膜晶体管的有源图案的感光特性，从而提高了第一薄膜晶体管的感光特性，提高指纹识别效果，且将第二栅极作为电容极板，降低了阵列基板的厚度。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的显示面板的第一种示意图。
图2为本申请实施例提供的显示面板的电路图。
图3为本申请实施例提供的显示面板的第二种示意图。
图4为本申请实施例提供的显示面板的第三种示意图。
图5为本申请实施例提供的显示面板制备方法的第一种流程图。
图6为本申请实施例提供的显示面板制备方法的第二种流程图。
图7为本申请实施例提供的显示面板制备方法的各步骤对应的显示面板的第一种示意图。
图8为本申请实施例提供的显示面板制备方法的各步骤对应的显示面板的第二种示意图。
图9为本申请实施例提供的显示面板制备方法的各步骤对应的显示面板的第三种示意图。
图10为本申请实施例提供的显示面板制备方法的各步骤对应的显示面板的第四种示意图。
图11为本申请实施例提供的显示装置的示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例针对现有显示器件存在氧化物薄膜晶体管的感光范围较小，导致指纹传感器识别效果较差的技术问题，提供一种阵列基板及其制备方法、显示面板，用以缓解上述技术问题。
如图1所示，本申请实施例提供一种显示面板1，该显示面板1包括阵列基板，该阵列基板包括：
衬底11；
第一栅极112，设置于所述衬底11一侧；
有源图案13，设置于所述第一栅极112远离所述衬底11的一侧；
第二栅极151，设置于所述有源图案13远离所述第一栅极112的一侧；
感光图案16，设置于所述第二栅极151远离所述有源图案13的一侧；
极板181，设置于所述感光图案16远离所述第二栅极151的一侧；
其中，所述阵列基板还包括第一源极111和第一漏极113，所述第一栅极112、所述第一源极111、所述第一漏极113、所述第二栅极151和所述有源图案13形成第一薄膜晶体管22，所述第二栅极151、所述感光图案16和所述极板181形成电容21。
本申请实施例提供一种显示面板，该显示面板包括阵列基板，该阵列基板通过设置电容，使电容与第一薄膜晶体管连接，通过电容中的感光图案感光，使得在光照变化时，电容的感光图案的电荷量变化带动第一薄膜晶体管的电流变化，而感光图案的感光特性优于薄膜晶体管的有源图案的感光特性，从而提高了第一薄膜晶体管的感光特性，提高指纹识别效果，且将第二栅极作为电容极板，降低了阵列基板的厚度。
针对薄膜晶体管的源漏极与栅极设置在不同层会导致阵列基板的厚度较大，阵列基板的制备工艺较为复杂。在一种实施例中，所述第一栅极与所述第一源极同层设置，且所述第一栅极与所述第一源极绝缘设置，所述第一栅极与所述第一漏极同层设置，且所述第一栅极与所述第一漏极绝缘设置。通过将第一栅极与第一源极和第一漏极设置在同层，则无需设置两层金属分别形成第一栅极、第一源极和第一漏极，减小阵列基板的厚度，且由于第一栅极与第一源极和第一漏极设置在同层，无需设置多个掩模版形成金属层和挖孔，降低阵列基板的制备工艺的复杂性。
在一种实施例中，如图1所示，所述阵列基板还包括第二源极115、第三栅极152和第一遮光图案114，所述第二源极115、所述第一漏极113、所述第三栅极152和所述有源图案13形成有第二薄膜晶体管23，所述第一遮光图案114对应于所述第二薄膜晶体管23的有源图案13设置，所述第一遮光图案114与所述第一栅极112、所述第一源极111和所述第一漏极113同层设置，且所述第一遮光图案114与所述第一栅极、所述第一源极和所述第一漏极绝缘设置。通过将第一遮光图案与第一源极、第一漏极和第一栅极同层设置，使得仅需要设置一层金属层，而无需分别形成第一遮光图案对应的金属层、第一栅极对应的金属层、第一源极和第一漏极对应的金属层，以及各金属层之间的绝缘层，减小了显示面板的厚度，且在金属层的形成过程中，无需设置多个掩模板形成各金属层和各绝缘层，简化了显示面板的形成工艺。而通过将第一薄膜晶体管的第一漏极作为第二薄膜晶体管的第二漏极，使第一薄膜晶体管和第二薄膜晶体管的源漏极设置在同层，减小了阵列基板的厚度，且第一薄膜晶体管的第一漏极和第二薄膜晶体管的第二漏极共用，减小了第一薄膜晶体管和第二薄膜晶体管的占用面积，则可以提高阵列基板的显示区域的面积，相应的提高显示面板的分辨率或者亮度，提高显示面板的显示效果。通过将第一遮光图案对应第三栅极设置，避免外部光线对薄膜晶体管产生影响。
在本申请实施例中，通过将第一薄膜晶体管的第二栅极作为电容的一极板，可以实现对第一薄膜晶体管的直接控制，同时上部采用透明导电层或者像素电极层形成电容的另一极板，使得电容与阵列基板的其他电容之间的耦合影响较小，提高指纹传感器的信噪比，提高指纹识别的效果。
在本申请实施例中，第一薄膜晶体管的有源图案与第二薄膜晶体管的有源图案连接。在第一薄膜晶体管的第一漏极和第二薄膜晶体管的第二源极共同时，第一薄膜晶体管的有源图案和第二薄膜晶体管的有源图案连接，实现第一薄膜晶体管和第二薄膜晶体管的串联，则可以通过第一薄膜晶体管和第二薄膜晶体管之间输出电流，实现指纹识别功能。
针对指纹传感器的信噪比较低，指纹识别功能的效果较差。在一种实施例中，如图3所示，所述阵列基板还包括像素电极层18，所述像素电极层18设置于所述感光图案16远离所述第二栅极的一侧，所述像素电极层18包括像素电极182和极板181，且所述极板181与所述像素电极182绝缘设置。通过采用像素电极层形成电容的极板，使得在光照变化时，电容能够根据光照的变化相应的变化电容的大小，使第一薄膜晶体管的电流变化，从而可以实现指纹识别功能。
具体的，在像素电极层形成像素电极和极板时，可以在形成感光图案、第二钝化层时，将对应像素电极的区域的感光图案蚀刻，从而在形成像素电极层后，像素电极会设置在第一钝化层上，而极板设置在第二钝化层上，从而采用同一膜层分别形成像素电极和极板，减少显示面板的制备工艺，降低显示面板的厚度。
在一种实施例中，如图4所示，所述阵列基板还包括透明导电层183和像素电极层18，所述透明导电层183设置于所述像素电极层18与所述感光图案16之间，所述透明导电层183形成有极板，且所述极板与所述像素电极层18绝缘设置。在设置极板时，还可以通过在阵列基板中设置透明导电层，通过透明导电层形成极板，避免极板影响像素电极层的设置。
具体的，如图4所示，透明导电层183和像素电极层18之间设有第三钝化层184，通过第三钝化层将透明导电层和像素电极层绝缘设置。
具体的，如图3所示，所述显示面板还包括第三源极101、第三漏极103、第四栅极102、第五栅极104，第三源极101、第三漏极103、第四栅极102、第五栅极104和有源图案形成第三薄膜晶体管，第三源极101与像素电极182连接，第三薄膜晶体管用于驱动有机发光器件发光。
在一种实施例中，所述第二栅极与所述第三栅极同层设置。通过将第三栅极与第二栅极同层设置，无需分别设置第二栅极对应的金属层和第三栅极对应的金属层，减小了阵列基板的厚度。
针对非感光薄膜晶体管受到光照时，会导致薄膜晶体管的性能变化。在一种实施例中，如图1所示，所述阵列基板还包括第二遮光图案19，所述第二遮光图案19对应设置于所述第二薄膜晶体管23上。通过将第二遮光图案设置在第二薄膜晶体管上，使第二遮光图案遮光外界光线，避免外界光线对第二薄膜晶体管产生影响，导致指纹识别效果较差。
如图2所示，以阵列基板的部分电路图说明指纹传感器的工作过程，以高电位电压端+HV表示电容C随光照的变化而变化，即高电位电压端+HV的电压随光照的变化而变化，电容C的一端连接高电位电压端+HV，电容C的另一端连接第一薄膜晶体管T1的第二栅极，第一薄膜晶体管T1的第一栅极连接扫描线Scan，第一薄膜晶体管T1的第一源极连接第一电源端Vdd，第一薄膜晶体管T1的第一漏极连接第二薄膜晶体管T2的第二源极，第一薄膜晶体管T1的第一漏极连接电压输出端Vout，第二薄膜晶体管T2的第二漏极连接第二电源端Vss，第二薄膜晶体管T2的第三栅极连接扫描线。
在光照变化时，电容C的电荷量变化，从而导致第一薄膜晶体管T1的电流变化，电压输出端Vout的电位变化，实现指纹识别的功能，且由于感光图案的感光范围大于第一薄膜晶体管的有源图案的感光范围，提高了指纹识别的效果。
在一种实施例中，所述阵列基板还包括：
遮光层，设置于所述衬底一侧，所述遮光层形成第一遮光图案；
缓冲层，设置于所述遮光层远离所述衬底的一侧；
金属层，所述金属层形成有第一栅极、所述第一源极和所述第一漏极。
在一种实施例中，所述阵列基板还包括：
遮光层，设置于所述衬底一侧，所述遮光层形成第一遮光图案；
缓冲层，设置于所述遮光层远离所述衬底的一侧；
第一金属层，设置于所述缓冲层远离所述遮光层的一侧；
第一栅极绝缘层，设置于所述第一金属层远离所述缓冲层的一侧；
有源层，设置于所述第一栅极绝缘层远离所述第一金属层的一侧；
第二栅极绝缘层，设置于所述有源层远离所述第一金属层的一侧；
第二金属层，设置于所述第二栅极绝缘层远离所述有源层的一侧，所述第二金属层形成有所述第二栅极；
其中，所述第一金属层形成有所述第一栅极、所述第一源极和所述第一漏极。通过设置第一金属层，使第一金属层形成第一栅极、第一源极和第一漏极，减小阵列基板的厚度，且由于第一栅极、第一源极和第一漏极与第一遮光图案设置在不同层，可以减小阵列基板中薄膜晶体管占用的面积。
上述实施例对源漏极与有源层底接触进行了详细描述。在一种实施例中，所述第二栅极与所述第一源极同层设置，且所述第二栅极与所述第一源极绝缘设置，所述第二栅极与所述第一漏极同层设置，且所述第二栅极与所述第一漏极绝缘设置。通过将第一源极和第一漏极与第二栅极同层设置，使源漏极与有源层顶接触，且第一源极和第一漏极与第二栅极同层设置，可以减小阵列基板的厚度。
在一种实施例中，所述感光图案的材料包括非晶硅和噻吩系有机材料中的至少一种。由于非晶硅和噻吩系有机材料的感光范围较大，对于各可见光均可以感应，则通过电容、第一薄膜晶体管和第二薄膜晶体管实现指纹识别功能，可以提高指纹传感器的识别效果。
在一种实施例中，如图1所示，所述阵列基板还包括缓冲层12，所述缓冲层12设置于所述遮光层24远离所述衬底11的一侧。
在一种实施例中，如图1所示，所述阵列基板还包括栅极绝缘层14，所述栅极绝缘层14设置于所述有源图案13远离所述缓冲层12的一侧。
在一种实施例中，如图1所示，所述阵列基板还包括栅极层15，所述栅极层15设置于所述栅极绝缘层14远离所述有源图案13的一侧，所述栅极层15图案化形成有第二栅极151和第三栅极152。
在一种实施例中，如图1所示，所述阵列基板还包括第一钝化层20，所述第一钝化层20设置于所述栅极层15远离所述栅极绝缘层14的一侧。
在一种实施例中，如图1所示，所述阵列基板还包括第二钝化层17，所述第二钝化层17设置于所述感光图案16远离所述第一钝化层20的一侧。
在一种实施例中，所述遮光层的材料包括钼、钼铜叠层中的一种。
在一种实施例中，所述缓冲层的材料包括氧化硅、氮化硅/氧化硅叠层中的一种。
在一种实施例中，所述有源层的材料包括铟镓锌氧化物、铟镓锌锡氧化物、铟镓锡氧化物中的一种。
在一种实施例中，所述第一钝化层的材料包括氧化硅、氧化硅/氮化硅叠层。
在一种实施例中，所述第二钝化层的材料包括氧化硅、氧化硅/氮化硅叠层、氧化硅/氮化硅/氧化铝叠层中的一种。
在一种实施例中，所述透明导电层的材料包括氧化铟锡、氧化铟锌中的一种。
如图5所示，本申请实施例提供一种显示面板制备方法，该阵列基板制备方法包括：
S1，提供衬底；
S2，在所述衬底上形成第一金属层，并对所述第一金属层进行处理，形成第一栅极、第一源极、第一漏极、第二源极和第二漏极；
S3，在所述第一金属层远离所述衬底的一侧形成第二栅极；
S4，在所述第二栅极远离所述第一金属层的一侧形成感光图案；
S5，在所述感光图案远离所述第二栅极的一侧形成极板；所述第一栅极、所述第一源极、所述第二栅极和所述有源图案形成第一薄膜晶体管，所述第二栅极、所述感光图案和所述极板形成电容。
本申请实施例提供一种显示面板制备方法，该显示面板制备方法制备的显示面板通过设置电容，使电容与第一薄膜晶体管连接，通过电容中的感光图案感光，使得在光照变化时，电容的感光图案的电荷量变化带动第一薄膜晶体管的电流变化，而感光图案的感光特性优于薄膜晶体管的有源图案的感光特性，从而提高了第一薄膜晶体管的感光特性，提高指纹识别效果，且将第二栅极作为电容极板，降低了阵列基板的厚度。
如图6所示，本申请实施例提供一种显示面板制备方法，该显示面板制备方法包括：
S1，提供衬底；此步骤对应的显示面板的结构如图7中的（a）所示；
S2，在所述衬底上形成金属层，并刻蚀遮光层形成第一栅极、第一源极、第一漏极、第二源极、第二漏极和第一遮光图案；此步骤对应的显示面板的结构如图7中的（a）所示；
S3，在所述遮光层上形成缓冲层，并刻蚀所述缓冲层形成第一过孔；此步骤对应的显示面板的结构如图7中的（b）所示；
S4，在所述缓冲层上形成有源层，并刻蚀所述有源层形成有源图案；所述有源层填充至所述第一过孔内；此步骤对应的显示面板的结构如图8中的（a）所示；
S5，在所述有源层上形成栅极绝缘层，并图案化所述栅极绝缘层；此步骤对应的显示面板的结构如图8中的（b）所示；
S6，在所述栅极绝缘层上形成栅极层，并刻蚀所述栅极层形成第二栅极、第三栅极和第一极板；第一薄膜晶体管包括所述第一栅极、所述第二栅极、所述第一源极和所述第一漏极，第二薄膜晶体管包括所述第三栅极、所述第二源极和所述第二漏极；此步骤对应的显示面板的结构如图8中的（b）所示；
S7，在所述栅极层上形成第一钝化层，并刻蚀所述第一钝化层形成第二过孔；此步骤对应的显示面板的结构如图9中的（a）所示；
S8，在所述第一钝化层上形成感光层，并刻蚀所述感光层形成感光图案；所述感光图案填充至所述第二过孔；此步骤对应的显示面板的结构如图9中的（b）所示；
S9，在所述感光层上形成第二钝化层；此步骤对应的显示面板的结构如图10中的（a）所示；
S10，在所述第二钝化层上形成第二极板；电容包括所述第一极板、所述第二极板，以及位于所述第一极板和所述第二极板之间的所述感光图案；所述感光图案的感光范围大于所述第一薄膜晶体管的有源图案的感光范围；此步骤对应的显示面板的结构如图10中的（b）所示；
S11，在所述第一钝化层上形成第二遮光图案；所述第二遮光图案对应所述第二薄膜晶体管设置；得到的显示面板的结构如图1所示。
在一种实施例中，所述在所述金属层上形成缓冲层，并刻蚀所述缓冲层形成第一过孔的步骤，包括：在温度为300摄氏度至400摄氏度下，对缓冲层进行高温退火处理2小时至3小时。
同时，如图11所示，本申请实施例提供一种显示装置，该显示装置包括显示面板和电子元件，该显示面板包括阵列基板，所述阵列基板包括：
衬底11；
第一栅极112，设置于所述衬底11一侧；
有源图案13，设置于所述第一栅极112远离所述衬底11的一侧；
第二栅极151，设置于所述有源图案13远离所述第一栅极112的一侧；
感光图案16，设置于所述第二栅极151远离所述有源图案13的一侧；
极板181，设置于所述感光图案16远离所述第二栅极151的一侧；
其中，所述阵列基板还包括第一源极111和第一漏极113，所述第一栅极112、所述第一源极111、所述第一漏极113、所述第二栅极151和所述有源图案13形成第一薄膜晶体管22，所述第二栅极151、所述感光图案16和所述极板181形成电容21。
本申请实施例提供一种显示装置，该显示装置包括显示面板，该显示面板包括阵列基板，该阵列基板通过设置电容，使电容与第一薄膜晶体管连接，通过电容中的感光图案感光，使得在光照变化时，电容的感光图案的电荷量变化带动第一薄膜晶体管的电流变化，而感光图案的感光特性优于薄膜晶体管的有源图案的感光特性，从而提高了第一薄膜晶体管的感光特性，提高指纹识别效果，且将第二栅极作为电容极板，降低了阵列基板的厚度。
在一种实施例中，所述电子元件包括屏下摄像头。
在一种实施例中，所述显示面板包括液晶显示面板，如图11所示，所述液晶显示面板还包括液晶层41、公共电极层421、色阻层422和黑色矩阵层423。
在一种实施例中，所述显示面板包括OLED（Organic Light-Emitting Diode，有机发光二极管）显示面板。
在一种实施例中，在显示装置中，所述第一栅极与所述第一源极同层设置，且所述第一栅极与所述第一源极绝缘设置，所述第一栅极与所述第一漏极同层设置，且所述第一栅极与所述第一漏极绝缘设置。
在一种实施例中，在显示装置中，所述阵列基板还包括第二源极、第三栅极和第一遮光图案，所述第二源极、所述第一漏极、所述第三栅极和所述有源图案形成第二薄膜晶体管，所述第一遮光图案对应于所述第二薄膜晶体管的有源图案设置，所述第一遮光图案与所述第一栅极、所述第一源极和所述第一漏极同层设置，且所述第一遮光图案与所述第一栅极、所述第一源极和所述第一漏极绝缘设置。
在一种实施例中，在显示装置中，所述阵列基板还包括像素电极层，所述像素电极层设置于所述感光图案远离所述第二栅极的一侧，所述像素电极层包括像素电极和极板，且所述极板与所述像素电极绝缘设置。
在一种实施例中，在显示装置中，所述阵列基板还包括透明导电层和像素电极层，所述透明导电层设置于所述像素电极层与所述感光图案之间，所述透明导电层形成有极板，且所述极板与所述像素电极层绝缘设置。
在一种实施例中，在显示装置中，所述阵列基板还包括第二遮光图案，所述第二遮光图案对应设置于所述第二薄膜晶体管上。
在一种实施例中，在显示装置中，所述第二栅极与所述第三栅极同层设置。
根据以上实施例可知：
本申请实施例提供一种显示面板及其制备方法、显示装置，该显示面板包括阵列基板，该阵列基板包括衬底、第一栅极、有源图案、第二栅极、感光图案和极板，第一栅极设置于衬底一侧，有源图案设置于第一栅极远离衬底的一侧，第二栅极设置于有源图案远离第一栅极的一侧，感光图案设置于第二栅极远离有源图案的一侧，极板设置于感光图案远离第二栅极的一侧，其中，阵列基板还包括第一源极和第一漏极，第一栅极、第一源极、第一漏极、第二栅极和有源图案形成第一薄膜晶体管，第二栅极、感光图案和极板形成电容。本申请通过在阵列基板中设置电容，使电容与第一薄膜晶体管连接，通过电容中的感光图案感光，使得在光照变化时，电容的感光图案的电荷量变化带动第一薄膜晶体管的电流变化，而感光图案的感光特性优于薄膜晶体管的有源图案的感光特性，从而提高了第一薄膜晶体管的感光特性，提高指纹识别效果，且将第二栅极作为电容极板，降低了阵列基板的厚度。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板及其制备方法、显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，包括阵列基板，其中，所述阵列基板包括：
    衬底；
    第一栅极，设置于所述衬底一侧；
    有源图案，设置于所述第一栅极远离所述衬底的一侧；
    第二栅极，设置于所述有源图案远离所述第一栅极的一侧；
    感光图案，设置于所述第二栅极远离所述有源图案的一侧；
    极板，设置于所述感光图案远离所述第二栅极的一侧；
    其中，所述阵列基板还包括第一源极和第一漏极，所述第一栅极、所述第一源极、所述第一漏极、所述第二栅极和所述有源图案形成第一薄膜晶体管，所述第二栅极、所述感光图案和所述极板形成电容。
  2. 如权利要求1所述的显示面板，其中，所述第一栅极与所述第一源极同层设置，且所述第一栅极与所述第一源极绝缘设置，所述第一栅极与所述第一漏极同层设置，且所述第一栅极与所述第一漏极绝缘设置。
  3. 如权利要求2所述的显示面板，其中，所述阵列基板还包括第二源极、第三栅极和第一遮光图案，所述第二源极、所述第一漏极、所述第三栅极和所述有源图案形成第二薄膜晶体管，所述第一遮光图案对应于所述第二薄膜晶体管的有源图案设置，所述第一遮光图案与所述第一栅极、所述第一源极和所述第一漏极同层设置，且所述第一遮光图案与所述第一栅极、所述第一源极和所述第一漏极绝缘设置。
  4. 如权利要求3所述的显示面板，其中，所述阵列基板还包括像素电极层，所述像素电极层设置于所述感光图案远离所述第二栅极的一侧，所述像素电极层包括像素电极和极板，且所述极板与所述像素电极绝缘设置。
  5. 如权利要求3所述的显示面板，其中，所述阵列基板还包括透明导电层和像素电极层，所述透明导电层设置于所述像素电极层与所述感光图案之间，所述透明导电层形成有极板，且所述极板与所述像素电极层绝缘设置。
  6. 如权利要求3所述的显示面板，其中，所述阵列基板还包括第二遮光图案，所述第二遮光图案对应设置于所述第二薄膜晶体管上。
  7. 如权利要求3所述的显示面板，其中，所述第二栅极与所述第三栅极同层设置。
  8. 如权利要求1所述的显示面板，其中，所述感光图案的材料包括非晶硅和噻吩系有机材料中的至少一种。
  9. 如权利要求1所述的显示面板，其中，所述阵列基板还包括：
    遮光层，设置于所述衬底一侧，所述遮光层形成第一遮光图案；
    缓冲层，设置于所述遮光层远离所述衬底的一侧；
    金属层，所述金属层形成有第一栅极、所述第一源极和所述第一漏极。
  10. 如权利要求1所述的显示面板，其中，所述阵列基板还包括：
    遮光层，设置于所述衬底一侧，所述遮光层形成第一遮光图案；
    缓冲层，设置于所述遮光层远离所述衬底的一侧；
    第一金属层，设置于所述缓冲层远离所述遮光层的一侧；
    第一栅极绝缘层，设置于所述第一金属层远离所述缓冲层的一侧；
    有源层，设置于所述第一栅极绝缘层远离所述第一金属层的一侧；
    第二栅极绝缘层，设置于所述有源层远离所述第一金属层的一侧；
    第二金属层，设置于所述第二栅极绝缘层远离所述有源层的一侧，所述第二金属层形成有所述第二栅极；
    其中，所述第一金属层形成有所述第一栅极、所述第一源极和所述第一漏极。
  11. 一种显示装置，其包括显示面板和电子元件，所述显示面板包括阵列基板，所述阵列基板包括：
    衬底；
    第一栅极，设置于所述衬底一侧；
    有源图案，设置于所述第一栅极远离所述衬底的一侧；
    第二栅极，设置于所述有源图案远离所述第一栅极的一侧；
    感光图案，设置于所述第二栅极远离所述有源图案的一侧；
    极板，设置于所述感光图案远离所述第二栅极的一侧；
    其中，所述阵列基板还包括第一源极和第一漏极，所述第一栅极、所述第一源极、所述第一漏极、所述第二栅极和所述有源图案形成第一薄膜晶体管，所述第二栅极、所述感光图案和所述极板形成电容。
  12. 如权利要求11所述的显示装置，其中，所述电子元件包括屏下摄像头。
  13. 如权利要求11所述的显示装置，其中，所述显示面板包括液晶显示面板或者OLED显示面板。
  14. 如权利要求11所述的显示装置，其中，所述第一栅极与所述第一源极同层设置，且所述第一栅极与所述第一源极绝缘设置，所述第一栅极与所述第一漏极同层设置，且所述第一栅极与所述第一漏极绝缘设置。
  15. 如权利要求14所述的显示装置，其中，所述阵列基板还包括第二源极、第三栅极和第一遮光图案，所述第二源极、所述第一漏极、所述第三栅极和所述有源图案形成第二薄膜晶体管，所述第一遮光图案对应于所述第二薄膜晶体管的有源图案设置，所述第一遮光图案与所述第一栅极、所述第一源极和所述第一漏极同层设置，且所述第一遮光图案与所述第一栅极、所述第一源极和所述第一漏极绝缘设置。
  16. 如权利要求15所述的显示装置，其中，所述阵列基板还包括像素电极层，所述像素电极层设置于所述感光图案远离所述第二栅极的一侧，所述像素电极层包括像素电极和极板，且所述极板与所述像素电极绝缘设置。
  17. 如权利要求15所述的显示装置，其中，所述阵列基板还包括透明导电层和像素电极层，所述透明导电层设置于所述像素电极层与所述感光图案之间，所述透明导电层形成有极板，且所述极板与所述像素电极层绝缘设置。
  18. 如权利要求15所述的显示装置，其中，所述阵列基板还包括第二遮光图案，所述第二遮光图案对应设置于所述第二薄膜晶体管上。
  19. 如权利要求15所述的显示装置，其中，所述第二栅极与所述第三栅极同层设置。
  20. 一种显示面板制备方法，其包括：
    提供衬底；
    在所述衬底上形成第一金属层，并对所述第一金属层进行处理，形成第一栅极、第一源极、第一漏极、第二源极和第二漏极；
    在所述第一金属层远离所述衬底的一侧形成第二栅极；
    在所述第二栅极远离所述第一金属层的一侧形成感光图案；
    在所述感光图案远离所述第二栅极的一侧形成极板；所述第一栅极、所述第一源极、所述第二栅极和所述有源图案形成第一薄膜晶体管，所述第二栅极、所述感光图案和所述极板形成电容。
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