WO2024020931A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2024020931A1
WO2024020931A1 PCT/CN2022/108577 CN2022108577W WO2024020931A1 WO 2024020931 A1 WO2024020931 A1 WO 2024020931A1 CN 2022108577 W CN2022108577 W CN 2022108577W WO 2024020931 A1 WO2024020931 A1 WO 2024020931A1
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WIPO (PCT)
Prior art keywords
common voltage
display
voltage line
display substrate
sub
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Application number
PCT/CN2022/108577
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English (en)
French (fr)
Inventor
张亚东
李挺
王春华
廖政
赵泽
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/108577 priority Critical patent/WO2024020931A1/zh
Priority to CN202280002425.9A priority patent/CN117795409A/zh
Publication of WO2024020931A1 publication Critical patent/WO2024020931A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • Display devices usually have a built-in (In-cell) or external (On-cell) touch structure to implement touch functions.
  • the built-in touch structure is integrated inside the display substrate of the display device, which is beneficial to the narrow frame and thin and light design of the display device.
  • TDDI Touch and Display Driver Integration
  • At least one embodiment of the present disclosure provides a display substrate, which has a display area and a peripheral area surrounding the display area, and has a touch function.
  • the display substrate includes a first common voltage line and a second common voltage line. and an integrated circuit; a first common voltage line is disposed in the peripheral area and at least partially surrounds the display area; a second common voltage line is disposed in the peripheral area, located away from the first common voltage line and away from the display area one side of the display area, and at least partially surrounds the display area; the integrated circuit is disposed in the peripheral area, and is located on a first side of the display area, and is configured to provide power to the first common voltage line and the third common voltage line during the display phase.
  • the two common voltage lines provide a first signal that is the same as the display signal.
  • a second signal that is the same as the touch signal is provided to the first common voltage line and the second common voltage line. The first signal is different from the second signal.
  • the display area includes a plurality of sub-pixels
  • the display substrate further includes a touch structure and a plurality of third common voltage lines
  • the touch structure is disposed in the display area and at least one of the peripheral areas, including a plurality of touch electrodes configured to implement the touch function
  • a plurality of third common voltage lines provided in the peripheral area and the display area, configured to electrically connect all the plurality of sub-pixels and the plurality of touch electrodes
  • the integrated circuit is further configured to provide the display signal to the plurality of sub-pixels through the plurality of third common voltage lines during the display stage, in the In the touch phase, the touch signals are provided to the plurality of touch electrodes through the plurality of third common voltage lines.
  • the display signal is a DC voltage
  • the touch signal is a pulse voltage
  • the DC voltage includes a first DC voltage signal
  • the pulse voltage has a highest potential and a lowest potential
  • the potential of the first DC voltage signal is higher than the highest potential. Potential.
  • the DC voltage further includes a second DC voltage signal
  • the potential of the first DC voltage signal is higher than the potential of the second DC voltage signal
  • the potential of the third DC voltage signal is higher than the potential of the second DC voltage signal.
  • the potential of the two DC voltage signals is lower than the lowest potential.
  • each of the plurality of third common voltage lines is electrically connected to one of the plurality of touch electrodes and one of the plurality of sub-pixels.
  • N sub-pixels, N is a positive integer greater than 1.
  • the first common voltage line includes a first connection end and a second connection end
  • the second common voltage line includes a third connection end and a fourth connection end
  • the first connection end is electrically connected to the third connection end
  • the second connection end is electrically connected to the fourth connection end to electrically connect the first common voltage line and the second common voltage line. connect.
  • the integrated circuit includes first and second binding terminals arranged at intervals and third and fourth binding terminals arranged at intervals, so The first binding end is electrically connected to the third binding end, the second binding end is electrically connected to the fourth binding end; the first connection end is electrically connected to the first binding end.
  • the third binding end is electrically connected to the third connection end, the second connection end is electrically connected to the second binding end, and the fourth binding end is electrically connected to the fourth connection end, to The first common voltage line and the second common voltage line are electrically connected.
  • the display substrate provided by at least one embodiment of the present disclosure further includes: a circuit board disposed in the peripheral area and at least partially disposed on a side of the integrated circuit away from the display area, wherein the third connection The terminal and the fourth connection terminal are electrically connected to the third binding terminal and the fourth binding terminal respectively through the circuit board.
  • the integrated circuit includes a first sub-integrated circuit and a second sub-integrated circuit arranged side by side on the first side of the display area, and the first binding terminal and the third binding terminal is disposed at an end of the first sub-integrated circuit away from the second sub-integrated circuit, and the second binding terminal and the fourth binding terminal are disposed at the second One end of the sub-integrated circuit away from the first sub-integrated circuit.
  • the first sub-integrated circuit further includes a fifth binding terminal disposed at an end of the first sub-integrated circuit close to the second sub-integrated circuit, so
  • the second sub-integrated circuit further includes a sixth binding terminal disposed at an end of the second sub-integrated circuit close to the first sub-integrated circuit, and the fifth binding terminal and the sixth binding terminal are at A display signal is input during the display phase, the touch signal is input during the touch phase, and the fifth binding terminal and the sixth binding terminal are floating.
  • the first sub-integrated circuit further includes a plurality of seventh binding terminals disposed between the first binding terminal and the fifth binding terminal.
  • the second sub-integrated circuit further includes a plurality of eighth binding terminals disposed between the second binding terminal and the sixth binding terminal, and the plurality of third common voltage lines are electrically connected respectively. to the plurality of seventh binding ends and the plurality of eighth binding ends.
  • the first common voltage line and the second common voltage line surround the display substrate at least on the second side, the third side and the fourth side of the display substrate. display area, and is electrically connected to the integrated circuit on a first side of the display area, the first side being opposite to the second side, and the third side being opposite to the fourth side.
  • the first common voltage line and the second common voltage line are respectively in a grid shape.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a substrate substrate, each of the plurality of sub-pixels includes a pixel drive circuit disposed on the substrate substrate, the pixel drive circuit includes a thin film transistor, so The thin film transistor includes a gate electrode and a source and drain electrode, and the first common voltage line and the second common voltage line are arranged in the same layer as the gate electrode.
  • the display substrate further includes a plurality of gate leads disposed on the base substrate, and the plurality of gate leads are respectively connected to the plurality of sub-pixels.
  • the gate electrode of the thin film transistor is electrically connected, and the plurality of gate electrode leads are respectively arranged in the same layer as the gate electrode or the source and drain electrode.
  • the plurality of gate leads extend to the peripheral area, and are located at the first common voltage line and the second common voltage line in at least part of the peripheral area. between common voltage lines.
  • the plurality of touch electrodes are located on a side of the pixel driving circuit away from the base substrate.
  • the plurality of touch electrodes and the plurality of third common voltage lines are arranged in the same layer.
  • the thin film transistor further includes an active layer, and in a direction perpendicular to the base substrate, the active layer is connected to the plurality of touch electrodes and The plurality of third common voltage lines do not overlap.
  • the display substrate provided by at least one embodiment of the present disclosure further includes: a ground line, disposed in the peripheral area, located on a side of the second common voltage line away from the display area, and at least partially surrounding the display area.
  • the ground line and the gate electrode are arranged in the same layer.
  • the display substrate provided by at least one embodiment of the present disclosure further includes: a test line provided in the peripheral area, located on a side of the ground line away from the display area, and located between the display area and the The second side opposite the first side.
  • test line and the gate electrode are arranged on the same layer.
  • At least one embodiment of the present disclosure also provides a display device.
  • the display device includes a display substrate, a counter substrate and a liquid crystal layer provided by embodiments of the present disclosure; the counter substrate is opposite to the display substrate, and the liquid crystal layer is located on the display screen. between the substrate and the counter substrate.
  • Figure 1 is a signal waveform diagram of a display stage and a touch stage in a display substrate provided by at least one embodiment of the present disclosure
  • Figure 2 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure
  • Figure 3 is a schematic plan view of another display substrate provided by at least one embodiment of the present disclosure.
  • Figure 4 is a schematic plan view of yet another display substrate provided by at least one embodiment of the present disclosure.
  • Figure 5 is a partial circuit layout diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • Figure 6 is a partial circuit layout diagram at four corners of a display substrate provided by at least one embodiment of the present disclosure
  • Figure 7 is a partial circuit layout diagram at four corners of another display substrate provided by at least one embodiment of the present disclosure.
  • Figure 8 is a schematic cross-sectional view of a display substrate provided by at least one embodiment of the present disclosure.
  • Figure 9 is a schematic cross-sectional view of a display device provided by at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic plan view of an opposing substrate of a display device according to at least one embodiment of the present disclosure.
  • FIG. 11 is a signal waveform diagram of a first common voltage signal line, a second common voltage signal line, and a third common voltage signal line in a display substrate according to at least one embodiment of the present disclosure.
  • the same integrated circuit can be used to provide display signals and touch signals in a time-sharing manner through the same signals.
  • the integrated circuit provides a common voltage signal V1 to multiple sub-pixels in the display area through signal lines.
  • the common voltage signal V1 may be a DC voltage signal;
  • the integrated circuit provides a pulse voltage signal V2 with high-frequency flipping to the touch structure through a signal line to identify the capacitance change caused by the operating object, such as a finger touching.
  • the high-frequency pulse voltage signal V2 of the touch signal often causes coupling disturbance to other signal lines on the display substrate, resulting in inaccurate signal transmission by the signal lines.
  • the GOA signal can be used to flip at high frequency along with the touch signal to reduce coupling disturbance; however, for Gate IC+TDDI products where the gate scan driver circuit is integrated into the IC, this coupling Disturbance cannot be avoided.
  • At least one embodiment of the present disclosure provides a display substrate and a display device.
  • the display substrate has a display area and a peripheral area surrounding the display area and has a touch function.
  • the display substrate includes a first common voltage line, a second common voltage line and Integrated circuit; a first common voltage line is provided in the peripheral area and at least partially surrounds the display area; a second common voltage line is provided in the peripheral area, located on a side of the first common voltage line away from the display area, and at least partially surrounds the display area;
  • the integrated circuit is disposed in the peripheral area and located on the first side of the display area, and is configured to provide a first signal that is the same as the display signal to the first common voltage line and the second common voltage line during the display phase, and to provide the first signal to the first common voltage line during the touch phase.
  • the common voltage line and the second common voltage line provide a second signal that is the same as the touch signal, and the first signal is different from the second signal.
  • the integrated circuit uses a time-sharing method to provide the same electrical signal to the first common voltage line and the second common voltage line located in the peripheral area at the same time during the display stage and the touch stage. This can make the signals transmitted by the first common voltage line and the second common voltage line consistent, without signal coupling disturbance, to avoid the phenomenon of inaccurate signal transmission by the signal line, and improve the display quality and touch effect of the display substrate.
  • FIG. 2 shows a schematic plan view of the display substrate.
  • the display substrate has a display area AA and a peripheral area NA surrounding the display area AA, and has a touch screen. control function.
  • the display substrate includes a first common voltage line C1, a second common voltage line C2 and an integrated circuit IC; the first common voltage line C1 is provided in the peripheral area NA and at least partially surrounds the display area AA; the second common voltage line C2 is provided in the peripheral area NA is located on the side of the first common voltage line C1 away from the display area AA and at least partially surrounds the display area AA; the integrated circuit IC is disposed in the peripheral area NA and is located on the first side of the display area AA (shown in Figure 2 is the lower side of the display area AA), configured to provide the same first signal as the display signal to the first common voltage line C1 and the second common voltage line C2 during the display phase, and to provide the first common voltage line C1 and the second common voltage line C2 during the touch phase.
  • the second common voltage line C2 provides a second signal that is the same as the touch signal, and the first signal is different from the second signal.
  • the first signal is a common voltage signal, such as a DC voltage signal
  • the second signal is a pulse voltage signal.
  • the display area AA includes a plurality of sub-pixels SP, and the display substrate also includes a touch structure (described in detail later) and a plurality of third common voltage lines C3 (shown in FIG. 2 Take a third common voltage line C3 as an example).
  • the touch structure is provided in at least one of the display area AA and the peripheral area NA, includes a plurality of touch electrodes T, and is configured to implement a touch function.
  • multiple touch electrodes T may be disposed in the display area AA, the peripheral area NA, or simultaneously in the display area AA and the peripheral area NA to implement touch functions at corresponding positions.
  • a plurality of third common voltage lines C3 are provided in the peripheral area NA and the display area AA, that is, extend in the peripheral area NA and the display area AA, and are configured to electrically connect the plurality of sub-pixels SP and the plurality of touch electrodes T.
  • the integrated circuit IC is also configured to provide display signals, such as a common voltage signal, such as a DC voltage signal, to the plurality of sub-pixels SP through a plurality of third common voltage lines C3 during the display stage, and through a plurality of third common voltage lines during the touch stage.
  • C3 provides touch signals, such as pulse voltage signals, to multiple touch electrodes T.
  • the waveforms of the display signal (first signal) and the touch signal (second signal) can be seen in FIG. 1 .
  • the touch structure may be a self-capacitive touch structure or a mutual-capacitive touch structure.
  • the embodiments of the present disclosure are introduced by taking a self-capacitive touch structure as an example.
  • the self-capacitive touch structure usually includes multiple touch electrodes, such as multiple block-shaped touch electrodes, that is, the above-mentioned touch electrodes T.
  • the operating body such as a finger
  • touches the screen due to the electric field of the human body, the finger and the touch position
  • the touch electrode will form a coupling capacitance, causing the original capacitance of the touch electrode to change.
  • the touch position can be obtained.
  • the plurality of third common voltage lines C3 are simultaneously used as the common voltage lines of the plurality of sub-pixels SP and the touch signal lines of the plurality of touch electrodes T.
  • the integrated circuit IC adopts a time-sharing manner to provide A third common voltage line C3 provides display signals or touch signals, which can reduce the number of signal lines on the display substrate, making the structure and wiring arrangement of the display substrate simpler, which is conducive to the narrow border of the display substrate. Thin design.
  • a third common voltage line C3 is connected to a touch electrode T to provide a touch signal for the touch electrode T, and a third common voltage line C3 is connected to N sub-pixels (N is greater than A positive integer of 1), thereby providing a display signal for the N sub-pixels.
  • N is greater than A positive integer of 1
  • one touch electrode T can correspond to 2000-8000 sub-pixels, such as 3000, 4000, 5000, 6000 or 7000 sub-pixels, etc., that is, N is 2000-8000
  • a third common voltage line C3 may connect 2000-8000 sub-pixels to provide display signals, such as a common voltage signal, for the 2000-8000 sub-pixels.
  • FIG. 3 shows a schematic plan view of another display substrate provided by at least one embodiment of the present disclosure.
  • the first common voltage line C1 includes a first connection terminal N1 and a second connection terminal N2
  • the second common voltage line C2 includes a third connection terminal N3 and a fourth connection terminal N4
  • the first connection terminal N1 is electrically connected to the third connection terminal N3, and the second connection terminal N2 is electrically connected to the fourth connection terminal N4, so as to electrically connect the first common voltage line C1 and the second common voltage line C2.
  • the signal transmission of the first common voltage line C1 and the second common voltage line C2 can be more synchronized.
  • the integrated circuit IC includes a first bonding terminal B1 and a second bonding terminal B2 arranged at intervals and a third bonding terminal B3 and a fourth bonding terminal arranged at intervals.
  • B3 the first binding terminal B1 is electrically connected to the third binding terminal B3, the second binding terminal B2 is electrically connected to the fourth binding terminal B4; the first connection terminal N1 is electrically connected to the first binding terminal B1, and the third binding terminal B3 is electrically connected.
  • the binding terminal B3 is electrically connected to the third connection terminal N3, the second connection terminal N2 is electrically connected to the second binding terminal B2, and the fourth binding terminal B4 is electrically connected to the fourth connection terminal N4 to connect the first common voltage line C1 and the third connection terminal N4.
  • the two common voltage lines C2 are electrically connected through the integrated circuit IC.
  • the display substrate also includes a circuit board F.
  • the circuit board F includes a flexible circuit board (Flexible Printed Circuit, FPC) and a printed circuit board (Printed Circuit Board, PCB). At least one of (the flexible circuit board FPC is shown as an example in the figure), the circuit board F is disposed in the peripheral area NA and at least partially disposed on a side of the integrated circuit IC away from the display area AA.
  • the third connection terminal N3 and the fourth connection terminal N4 are electrically connected to the third binding terminal B3 and the fourth binding terminal B4 respectively through the circuit board F.
  • the third connection terminal N3 and the fourth connection terminal N4 are respectively bound. After arriving at the circuit board F, it is bound to the third binding terminal B3 and the fourth binding terminal B4 at the other end of the circuit board F through the lines on the circuit board F.
  • the first common voltage line C1 is directly connected to the first binding terminal B1 of the integrated circuit IC, and then connected to the first binding terminal B1 through the circuit board F (for example, through the flexible circuit board and the printed circuit board in sequence).
  • Two common voltage lines C2 so that the first common voltage line C1 and the second common voltage line C2 are connected at the remote end.
  • This connection method is more beneficial to shielding electro-static discharge (ESD).
  • the first binding terminal B1, the second binding terminal B2, and the third and fourth binding terminals B3 and B3 may respectively include one, two or more binding pins. , to ensure that the first common voltage line C1 and the second common voltage line C2 are effectively bound to the integrated circuit IC.
  • FIG. 4 shows a schematic plan view of yet another display substrate provided by at least one embodiment of the present disclosure.
  • integrated circuits IC may be included and arranged side by side on the first side of the display area AA.
  • the first sub-integrated circuit IC1 is the main IC
  • the second sub-integrated circuit IC2 is the auxiliary IC.
  • the first sub-integrated circuit IC1 and the second sub-integrated circuit IC2 can be configured to provide sub-pixels SP or touch electrodes T in different areas. Provides driving signals.
  • the first binding terminal B1 and the third binding terminal B3 are provided at an end of the first sub-integrated circuit IC1 away from the second sub-integrated circuit IC2, that is, the left end in the figure; the second binding terminal The fixed terminal B2 and the fourth binding terminal B4 are provided at an end of the second sub-integrated circuit IC2 away from the first sub-integrated circuit IC1, that is, the right end in the figure, so that the first binding terminal B1 and the second binding terminal B2 is separated by a certain distance.
  • the first sub-integrated circuit IC1 further includes a fifth binding disposed at an end of the first sub-integrated circuit IC1 close to the second sub-integrated circuit IC2 (the right end in the figure).
  • Terminal B5 the second sub-integrated circuit IC2 also includes a sixth binding terminal B6 disposed at an end of the second sub-integrated circuit IC2 close to the first sub-integrated circuit IC1 (the left end in the figure), a fifth binding terminal B5 and a third binding terminal B5.
  • the sixth binding terminal B6 is input with a display signal during the display phase, and is input with a touch signal during the touch phase.
  • the fifth binding terminal B5 and the sixth binding terminal B6 are floating, that is, the fifth binding terminal B5 and the sixth binding terminal B6 are input.
  • the sixth binding terminal B6 is not connected to the signal line.
  • the right end of the first sub-integrated circuit IC1 and the right end of the second sub-integrated circuit IC2 are both proximal ends inside the IC, and the left end of the first sub-integrated circuit IC1 and the left end of the second sub-integrated circuit IC2 Both are remote ends inside the IC.
  • the signal transmission between the near end and the far end inside the IC is not synchronized, for example, the signal is first given to the near end inside the IC and then to the far end inside the IC. Therefore, by comparing the distance between The fifth binding terminal B5 and the sixth binding terminal B6 have a floating design, which can prevent the touch signals they transmit from being asynchronous and causing interference between the asynchronous signals, which is beneficial to the touch Improvement of control performance.
  • the fifth binding terminal B5 and the sixth binding terminal B6 may also include one, two or more binding pins respectively to be consistent with the settings of the first binding terminal B1 and the second binding terminal B2. .
  • the first sub-integrated circuit IC1 further includes a plurality of seventh bonding terminals B7 disposed between the first bonding terminal B1 and the fifth bonding terminal B5.
  • the second sub-integrated circuit IC2 also includes a plurality of eighth binding terminals B8 disposed between the second binding terminal B2 and the sixth binding terminal B6, and a plurality of third common voltage lines C3 are electrically connected to a plurality of seventh binding terminals respectively.
  • the seventh binding terminal B7 and the eighth binding terminal B8 may also include one, two or more binding pins respectively, which are not specifically limited in the embodiments of the present disclosure.
  • the above-mentioned plurality of seventh binding terminals B7 and the plurality of eighth binding terminals B8 are configured to provide display signals to the plurality of sub-pixels SP through the plurality of third common voltage lines C3 during the display stage.
  • a common voltage signal such as a DC voltage signal
  • touch signals such as pulse voltage signals
  • the terminal B7 and the plurality of eighth binding terminals B8 are binding terminals that transmit effective driving signals and are used to implement display functions and touch functions.
  • the first common voltage line C1 and the second common voltage line C2 are also applied with display signals and transmit display signals during the display phase, and are applied with touch signals and transmit touch signals during the touch phase.
  • control signal but this signal is not used to control display operations and touch operations. It is only used to surround the display area AA in the peripheral area NA and transmit signals consistent with the third common voltage line C3 to prevent signal crosstalk. etc.
  • the first common voltage line C1 is arranged on the inner circle of the display substrate relative to the second common voltage line C2, so that the signal of the display area AA can be shielded on the side close to the display area AA; the second common voltage line C2 is arranged relative to the third common voltage line C2.
  • a common voltage line C1 is provided on the outer circle of the display substrate, thereby preventing external static electricity on the outer circle of the display substrate and achieving an electrostatic shielding effect.
  • the binding end B8 is basically the same in structure, and the signals being transmitted are also the same, thus ensuring the consistency of signal transmission.
  • the first binding terminal B1, the second binding terminal B2, the fifth binding terminal B5 and the sixth binding terminal B6 are not used to connect sub-pixels and touch electrodes, they may also It's called the dummy end.
  • the plurality of seventh bonding terminals B7 in the first sub-integrated circuit IC1 are located between the first binding terminal B1 and the fifth binding terminal B5, and the plurality of seventh bonding terminals B7 in the second sub-integrated circuit IC2
  • the eighth bonding terminal B8 is located between the second bonding terminal B2 and the sixth bonding terminal B6. Therefore, in each sub-integrated circuit, the bonding terminals used to transmit effective driving signals are located between the dummy terminals. , which can further prevent the binding end used for transmitting effective driving signals and the corresponding signal lines from being interfered with.
  • the flexible circuit board FPC has a binding terminal B, and the third connection terminal N3 of the second common voltage line C2 is connected to the flexible circuit board FPC through at least one pin of the binding terminal
  • the circuit in the binding terminal is connected to the third binding terminal B3 through at least another pin of the binding terminal, and the fourth connection terminal N4 is connected to the third connection terminal N3 in a similar manner.
  • the binding end of the flexible circuit board FPC also includes multiple DC voltage output pins configured to be input with DC voltage signals; at this time, the multiple DC voltage output pins It can be short-circuited through the signal line Vcom, so that it is not used to provide an effective driving signal.
  • FIG. 11 shows a signal waveform diagram of the first common voltage line, the second common voltage line and the third common voltage line of the display substrate provided by at least one embodiment of the present disclosure.
  • the waveforms of the first common voltage line C1, the second common voltage line C2, and the third common voltage line C3 are shown in the bottom thick solid line in Figure 11.
  • the first common voltage line C1, the second common voltage line C2 and the third common voltage line C3 are applied with the first DC voltage signal V11 or the second DC voltage signal V12 (that is, the above-mentioned first signal).
  • the potential of the DC voltage signal V11 is higher than the potential of the second DC voltage signal V12; during the touch phase TU, the first common voltage line C1, the second common voltage line C2 and the third common voltage line C3 are applied with pulse signals (also That is, the above-mentioned second signal), such as a pulse voltage, the pulse voltage has a highest potential V21 and a lowest potential V22.
  • the potential of the first DC voltage signal V11 is higher than the highest potential V21 of the pulse voltage
  • the potential of the second DC voltage signal V12 is lower than the lowest potential V22 of the pulse voltage, thereby meeting the signal requirements at different stages.
  • FIG. 11 also shows a partial waveform G of the gate scan driving circuit.
  • the gate scanning driving circuit can, for example, control the provision of scanning voltages to the gates of the thin film transistors of the pixel driving circuit of multiple sub-pixels during the display stage. Its specific waveform is You can refer to related technologies and will not go into details here.
  • the first common voltage line C1 and the second common voltage line C2 are at least on the second side (eg, the upper side of the display substrate) and the third side (eg, the upper side of the display substrate).
  • the left side of the substrate) and the fourth side surround the display area AA and are electrically connected to the integrated circuit IC on the first side of the display area AA, the first side being opposite to the second side, and the third side side opposite to the fourth side.
  • the first common voltage line C1 may also surround the display area AA on the first side of the display area AA to prevent signal interference around the display area AA.
  • the second common voltage line C2 can also surround the display area AA on the first side of the display area AA to fully prevent signal interference around the display area AA. .
  • FIG. 5 shows a partial circuit arrangement diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 6 shows a partial circuit layout diagram at four corners of a display substrate provided by at least one embodiment of the present disclosure.
  • the first common voltage line C1 and the second common voltage line C2 are respectively in a grid shape, so that the voltage drop can be reduced and the first common voltage line C1 and the second common voltage line C2 can be improved.
  • FIG. 7 shows a partial circuit layout diagram at four corners of another display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate may further include a gate scan driving circuit GOA disposed on the third side and the fourth side of the display area AA adjacent to the first side, that is, forming a GOA (Gate on Array) display substrate, at this time, the transmission signal of the gate scan driving circuit can be configured to be consistent with the touch signal during the touch stage to reduce the coupling disturbance of the signal.
  • the first common voltage line C1 and the second common voltage line C2 may be provided on a side of the gate scan driving circuit GOA away from the display area AA to prevent signal interference at the outer periphery. effect.
  • FIG. 8 shows a schematic cross-sectional view of a display substrate provided by at least one embodiment of the present disclosure.
  • the display substrate further includes a base substrate 110 , and each of the plurality of sub-pixels SP includes a pixel driving circuit disposed on the base substrate 110 .
  • the pixel driving circuit includes a thin film transistor TFT.
  • the transistor TFT includes an active layer 121, a gate electrode 122, source and drain electrodes 123 and 124 and other structures.
  • the thin film transistor TFT shown in FIG. 8 is a bottom-gate type.
  • the gate electrode 122 is provided on a side of the active layer 121 close to the base substrate 110 , and a gate insulating layer 126 is provided on the gate electrode 122 .
  • the thin film transistor TFT may also be a top-gate type, and the gate 122 is disposed on a side of the active layer 121 away from the base substrate 110.
  • the embodiments disclosed in this disclosure are specific to the specific form of the thin film transistor TFT. No restrictions.
  • the first common voltage line C1 and the second common voltage line C2 are arranged in the same layer as the gate electrode 122, which can simplify the preparation process of the display substrate and facilitate the thin design of the display substrate.
  • “same layer arrangement” means that two (or more) functional layers or structural layers are formed on the same layer and with the same material in the hierarchical structure of the display substrate, that is, during the preparation process , the two (or more) functional layers or structural layers can be formed from the same material layer, and the required patterns and structures can be formed through the same patterning process.
  • the display substrate further includes a plurality of gate leads 125 disposed on the base substrate 110 , and the plurality of gate leads 125 are respectively connected to the thin film transistors TFT of the multiple sub-pixels SP.
  • the gate 122 is electrically connected and configured to provide a gate scan signal to the gate 122 .
  • the plurality of gate leads 125 are arranged in the same layer as the gate electrode 122 or the source and drain electrodes 123 and 124 respectively.
  • a part of the plurality of gate leads 125 is arranged in the same layer as the gate electrode 122.
  • the gate lead 125 can be integrally connected with the gate 122, and another part of the plurality of gate leads 125 is in the same layer as the source and drain electrodes 123 and 124.
  • Layer setting at this time, the gate lead 125 can be connected to the gate 122 through a via hole. Since there are a large number of gate leads 125 on the display substrate, the gate leads 125 can be simplified by distributing the plurality of gate leads 125 in two layers, namely the layer where the gate electrode 122 is located and the layer where the source and drain electrodes 123 and 124 are located. The arrangement difficulty in each layer can be avoided, and problems such as signal crosstalk or short circuit caused by excessive arrangement density of multiple gate leads 125 can be avoided.
  • the plurality of gate leads 125 extend to the peripheral area NA and are located between the first common voltage line C1 and the second common voltage line C2 in at least a portion of the peripheral area NA. .
  • the plurality of gate leads 125 extend on the lower right part of the display substrate, for example, to the integrated circuit IC, so that the integrated circuit IC can provide gate scanning signals for the plurality of gate leads 125; at this time , the distribution width of the first common voltage line C1 and the second common voltage line C2 on both sides of the plurality of gate leads 125 is small to avoid arrangement space for the plurality of gate leads 125 .
  • a plurality of touch electrodes T are located on a side of the pixel driving circuit away from the base substrate 110 .
  • multiple touch electrodes T are multiplexed as common electrodes of the sub-pixel SP to provide a common voltage for the sub-pixel SP.
  • the display substrate further includes a pixel electrode P electrically connected to the source and drain electrodes 124 of the thin film transistor TFT.
  • the pixel electrode P is configured to be applied with a high-level voltage
  • the common electrode is configured to be applied with a low-level voltage. flat voltage.
  • the display substrate further includes a passivation layer 127 disposed on the pixel electrode P to insulate the pixel electrode P from the common electrode.
  • a plurality of touch electrodes T and a plurality of third common voltage lines C3 are arranged in the same layer to simplify the preparation process of the display substrate and facilitate the thin design of the display substrate.
  • the active layer 121 does not overlap with the plurality of touch electrodes T and the plurality of third common voltage lines C3, that is,
  • the orthographic projection of the active layer 121 on the base substrate 110 does not overlap with the orthographic projections of the plurality of touch electrodes T and the plurality of third common voltage lines C3 on the base substrate 110 , thereby avoiding multiple touches.
  • the signals transmitted on the electrode T and the plurality of third common voltage lines C3 affect the conductivity of the active layer 121, thereby affecting the normal operation of the thin film transistor.
  • the pixel electrode P, the plurality of touch electrodes T and the plurality of third common voltage lines C3 may be made of transparent metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), etc. , to increase its transparency.
  • transparent metal oxide materials such as indium tin oxide (ITO), indium zinc oxide (IZO), etc.
  • the display substrate may further include a ground line G.
  • the ground line G is provided in the peripheral area NA, located on a side of the second common voltage line C2 away from the display area AA, and at least Partially surrounds display area AA.
  • the ground line G surrounds the display area AA on the second, third and fourth sides of the display substrate and is connected to the integrated circuit IC on the first side of the display substrate.
  • the ground line G is configured to be applied with a ground voltage, such as zero voltage, to provide signal shielding at the periphery of the display substrate.
  • the ground line G and the gate electrode 122 are provided in the same layer to simplify the preparation process of the display substrate and facilitate the thin design of the display substrate.
  • the display substrate may further include a test line S.
  • the test line S is disposed in the peripheral area NA, is located on a side of the ground line G away from the display area AA, and is located in the display area AA. a second side opposite the first side (shown as the upper side in the figure).
  • the test line S is electrically connected to at least part of the plurality of sub-pixels SP to perform a lighting test before the display substrate leaves the factory to test whether at least part of the plurality of sub-pixels SP can display normally.
  • the test line S does not participate in the display operation of the display substrate.
  • test line S and the gate electrode 122 are arranged on the same layer to simplify the preparation process of the display substrate and facilitate the thin design of the display substrate.
  • the base substrate 110 may be a rigid substrate such as glass or quartz or a flexible substrate such as polyimide (PI).
  • the materials of the active layer 121 include but are not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (hexathiophene, polycrystalline silicon, etc.). Thiophene, etc.).
  • silicon-based materials amorphous silicon a-Si, polycrystalline silicon p-Si, etc.
  • metal oxide semiconductors IGZO, ZnO, AZO, IZTO, etc.
  • organic materials hexathiophene, polycrystalline silicon, etc.
  • Thiophene, etc. During the preparation process, part of the semiconductor material of the active layer 121 is conductive to have good electrical conductivity.
  • the gate electrode 122 and the source and drain electrodes 123 and 124 may be made of copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), titanium (Ti), tungsten (W) or other metal materials or alloy materials.
  • the gate electrode 122 and the source and drain electrodes 123 and 124 may be a single-layer or multi-layer structure, such as a multi-layer metal structure such as Ti/Al/Ti or Mo/Al/Mo.
  • the gate insulating layer 126 and the passivation layer 127 may be inorganic insulating layers, for example, made of inorganic insulating materials such as silicon oxide (SiOx), silicon nitride (SiNy), or silicon oxynitride (SiOxNy).
  • inorganic insulating materials such as silicon oxide (SiOx), silicon nitride (SiNy), or silicon oxynitride (SiOxNy).
  • a gate material layer may first be formed on the base substrate using a process such as sputtering or deposition, and then a first mask may be used to perform a patterning process on the gate material layer to form a gate.
  • Extreme 122 the sequential patterning process includes photoresist formation, exposure, development, etching and other processes, which will not be described again in the embodiments of the present disclosure.
  • the gate insulating layer 126 is formed on the gate electrode 122 using a process such as deposition, and then an active material layer is formed on the gate insulating layer 126 using a process such as sputtering or deposition, and then a third process is used.
  • the second mask performs a patterning process on the active material layer to form a pattern of the active layer 121 .
  • a doping process may be performed on a portion of the active layer 121 to make the connection positions of the source and drain electrodes 123 and 124 conductive.
  • a pixel electrode material layer is formed on the active layer 121 and the gate insulating layer 126 using a process such as sputtering or deposition, and then a third mask is used to perform a patterning process on the pixel electrode material layer. , to form the pixel electrode P.
  • a source-drain electrode material layer is formed on the pixel electrode P using a process such as sputtering or deposition, and then a fourth mask is used to pattern the source-drain electrode material layer to form a source-drain electrode material layer.
  • Pole 123 and 124 Pole 123 and 124.
  • a passivation material layer is formed on the source and drain electrodes 123 and 124 using a process such as sputtering or deposition, and then a fifth mask is used to pattern the passivation material layer.
  • a passivation material layer is formed on the source and drain electrodes 123 and 124 using a process such as sputtering or deposition, and then a fifth mask is used to pattern the passivation material layer.
  • a common electrode material layer is formed on the passivation layer 127 using a process such as sputtering or deposition, and then a sixth mask is used to pattern the common electrode material layer to form a common electrode. layer, which is also the touch structure layer.
  • FIG. 9 shows a schematic structural diagram of the display device.
  • the display device includes a display substrate 10 provided by an embodiment of the present disclosure, a counter substrate 20 and The liquid crystal layer 30 and the opposite substrate 20 are opposite to the display substrate 10, and the liquid crystal layer 30 is located between the display substrate 10 and the opposite substrate 20, so that the display device is implemented as a liquid crystal display device.
  • the opposing substrate 20 may be a color filter substrate.
  • FIG. 10 shows a schematic plan view of the color filter substrate.
  • the color filter substrate includes a black matrix layer BM and a plurality of color filter patterns CF.
  • the black matrix layer BM includes a plurality of sub-pixel openings BM1 corresponding to a plurality of sub-pixels SP, and a plurality of color filter patterns CF are respectively disposed in the plurality of sub-pixel openings BM1 to process the light emitted from the plurality of sub-pixel openings BM1. Filter color.
  • the plurality of color filter patterns CF include a red color filter pattern, a green color filter pattern, and a blue color filter pattern to achieve full-color display.
  • the plurality of color filter patterns CF may also have other colors, which are not specifically limited in the embodiments of the present disclosure.
  • the opposing substrate 20 may also include other structures in addition to the above-mentioned structures.
  • other structures in addition to the above-mentioned structures.

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Abstract

一种显示基板和显示装置，该显示基板具有显示区域(AA)和围绕显示区域(AA)的周边区域(NA)，并具有触控功能，显示基板包括第一公共电压线(C1)、第二公共电压线(C2)以及集成电路(IC)；第一公共电压线(C1)设置在周边区域(NA)且至少部分围绕显示区域(AA)；第二公共电压线(C2)设置在周边区域(NA)，位于第一公共电压线(C1)的远离显示区域(AA)的一侧，且至少部分围绕显示区域(AA)；集成电路(IC)设置在周边区域(NA)，且位于显示区域(AA)的第一侧，配置为在显示阶段向第一公共电压线(C1)和第二公共电压线(C2)提供与显示信号相同的第一信号，在触控阶段向第一公共电压线(C1)和第二公共电压线(C2)提供与触控信号相同的第二信号，第一信号与第二信号不同。该显示基板的第一公共电压线(C1)和第二公共电压线(C2)传输的信号一致，不会发生信号耦合扰动，从而可以提高显示基板的显示质量和触控效果。

Description

显示基板和显示装置 技术领域
本公开的实施例涉及一种显示基板和显示装置。
背景技术
显示装置通常具有内置式(In-cell)或者外挂式(On-cell)的触控结构，以实现触控功能。内置式触控结构集成在显示装置的显示基板的内部，有利于显示装置的窄边框、轻薄化设计。结合TDDI(Touch and Display Driver Integration)方案，也即触控和显示驱动一体化的方案，可以进一步实现显示装置的窄边框、轻薄化设计。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板具有显示区域和围绕所述显示区域的周边区域，并具有触控功能，所述显示基板包括第一公共电压线、第二公共电压线以及集成电路；第一公共电压线设置在所述周边区域且至少部分围绕所述显示区域；第二公共电压线设置在所述周边区域，位于所述第一公共电压线的远离所述显示区域的一侧，且至少部分围绕所述显示区域；集成电路设置在所述周边区域，且位于所述显示区域的第一侧，配置为在显示阶段向所述第一公共电压线和所述第二公共电压线提供与显示信号相同的第一信号，在触控阶段向所述第一公共电压线和所述第二公共电压线提供与触控信号相同的第二信号，所述第一信号与所述第二信号不同。
例如，本公开至少一实施例提供的显示基板中，所述显示区域包括多个子像素，所述显示基板还包括触控结构以及多条第三公共电压线；触控结构设置在所述显示区域和所述周边区域中的至少一个，包括多个触控电极，配置为实现所述触控功能；多条第三公共电压线设置在所述周边区域和所述显示区域，配置为电连接所述多个子像素和所述多个触控电极；所述集成电路还配置为在所述显示阶段通过所述多条第三公共电压线向所述多个子像素提供所述显示信号，在所述触控阶段通过所述多条第三公共电压线向所述多个触控电极提供所述触控信号。
例如，本公开至少一实施例提供的显示基板中，所述显示信号为直流电压，所述触控信号为脉冲电压。
例如，本公开至少一实施例提供的显示基板中，所述直流电压包括第一直流电压信号，所述脉冲电压具有最高电位和最低电位，所述第一直流电压信号的电位高于所述最高电位。
例如，本公开至少一实施例提供的显示基板中，所述直流电压还包括第二直流电压信号，所述第一直流电压信号的电位高于所述第二直流电压信号的电位，所述第二直流电压信号的电位低于所述最低电位。
例如，本公开至少一实施例提供的显示基板中，所述多条第三公共电压线中的每个电连接所述多个触控电极中的一个触控电极以及所述多个子像素中的N个子像素，N为大于1的正整数。
例如，本公开至少一实施例提供的显示基板中，所述第一公共电压线包括第一连接端和第二连接端，所述第二公共电压线包括第三连接端和第四连接端，所述第一连接端与所述第三连接端电连接，所述第二连接端与所述第四连接端电连接，以将所述第一公共电压线和所述第二公共电压线电连接。
例如，本公开至少一实施例提供的显示基板中，所述集成电路包括间隔设置的第一绑定端和第二绑定端以及间隔设置的第三绑定端和第四绑定端，所述第一绑定端和所述第三绑定端电连接，所述第二绑定端与所述第四绑定端电连接；所述第一连接端电连接所述第一绑定端，所述第三绑定端电连接所述第三连接端，所述第二连接端电连接所述第二绑定端，所述第四绑定端电连接所述第四连接端，以将所述第一公共电压线和所述第二公共电压线电连接。
例如，本公开至少一实施例提供的显示基板还包括：电路板，设置在所述周边区域且至少部分设置在所述集成电路的远离所述显示区域的一侧，其中，所述第三连接端和所述第四连接端分别通过所述电路板与所述第三绑定端和所述第四绑定端电连接。
例如，本公开至少一实施例提供的显示基板中，所述集成电路包括在所述显示区域的第一侧并列设置的第一子集成电路和第二子集成电路，所述第一绑定端和所述第三绑定端设置在所述第一子集成电路的远离所述第二子集成电路的一端，所述第二绑定端和所述第四绑定端设置 在所述第二子集成电路的远离所述第一子集成电路的一端。
例如，本公开至少一实施例提供的显示基板中，所述第一子集成电路还包括设置在所述第一子集成电路的靠近所述第二子集成电路一端的第五绑定端，所述第二子集成电路还包括设置在所述第二子集成电路的靠近所述第一子集成电路一端的第六绑定端，所述第五绑定端和所述第六绑定端在所述显示阶段被输入显示信号，在所述触控阶段被输入所述触控信号，所述第五绑定端和所述第六绑定端浮置。
例如，本公开至少一实施例提供的显示基板中，所述第一子集成电路还包括设置在所述第一绑定端和所述第五绑定端之间的多个第七绑定端，所述第二子集成电路还包括设置在所述第二绑定端和所述第六绑定端之间的多个第八绑定端，所述多条第三公共电压线分别电连接至所述多个第七绑定端和所述多个第八绑定端。
例如，本公开至少一实施例提供的显示基板中，所述第一公共电压线和所述第二公共电压线至少在所述显示基板的第二侧、第三侧和第四侧围绕所述显示区域，并在所述显示区域的第一侧电连接到所述集成电路，所述第一侧与所述第二侧相对，所述第三侧与所述第四侧相对。
例如，本公开至少一实施例提供的显示基板中，所述第一公共电压线和所述第二公共电压线分别呈网格状。
例如，本公开至少一实施例提供的显示基板还包括衬底基板，所述多个子像素的每个包括设置在所述衬底基板上的像素驱动电路，所述像素驱动电路包括薄膜晶体管，所述薄膜晶体管包括栅极以及源漏电极，所述第一公共电压线和所述第二公共电压线与所述栅极同层设置。
例如，本公开至少一实施例提供的显示基板中，所述显示基板还包括设置在所述衬底基板上的多条栅极引线，所述多条栅极引线分别与所述多个子像素的薄膜晶体管的栅极电连接，所述多条栅极引线分别与所述栅极或者所述源漏电极同层设置。
例如，本公开至少一实施例提供的显示基板中，所述多条栅极引线延伸至所述周边区域，且在所述周边区域的至少部分位于所述第一公共电压线和所述第二公共电压线之间。
例如，本公开至少一实施例提供的显示基板中，所述多个触控电极位于所述像素驱动电路的远离所述衬底基板的一侧。
例如，本公开至少一实施例提供的显示基板中，所述多个触控电极与多条第三公共电压线同层设置。
例如，本公开至少一实施例提供的显示基板中，所述薄膜晶体管还包括有源层，在垂直于所述衬底基板的方向上，所述有源层与所述多个触控电极和所述多条第三公共电压线不交叠。
例如，本公开至少一实施例提供的显示基板还包括：接地线，设置在所述周边区域，位于所述第二公共电压线的远离所述显示区域的一侧，且至少部分围绕所述显示区域。
例如，本公开至少一实施例提供的显示基板中，所述接地线与所述栅极同层设置。
例如，本公开至少一实施例提供的显示基板还包括：测试线，设置在所述周边区域，位于所述接地线的远离所述显示区域的一侧，且位于所述显示区域的与所述第一侧相对的第二侧。
例如，本公开至少一实施例提供的显示基板中，所述测试线与所述栅极同层设置。
本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施例提供的显示基板、对置基板以及液晶层；对置基板与所述显示基板对置，液晶层位于所述显示基板与所述对置基板之间。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一实施例提供的显示基板中显示阶段与触控阶段的信号波形图；
图2为本公开至少一实施例提供的显示基板的平面示意图；
图3为本公开至少一实施例提供的另一显示基板的平面示意图；
图4为本公开至少一实施例提供的再一显示基板的平面示意图；
图5为本公开至少一实施例提供的显示基板的部分电路排布图；
图6为本公开至少一实施例提供的显示基板在四个边角位置的部分电路排布图；
图7为本公开至少一实施例提供的另一显示基板在四个边角位置的部分电路排布图；
图8为本公开至少一实施例提供的显示基板的截面示意图；
图9为本公开至少一实施例提供的显示装置的截面示意图；
图10为本公开至少一实施例提供的显示装置的对置基板的平面示意图；以及
图11为本公开至少一实施例提供的显示基板中第一公共电压信号线、第二公共电压信号线和第三公共电压信号线的信号波形图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在TDDI方案中，可以采用相同的集成电路(Integrated Circuit，IC)通过相同的信号以分时的方式提供显示信号和触控信号。例如，在一些实施例中，如图1所示，在显示阶段DA，集成电路通过信号线给显示区域的多个子像素提供公共电压信号V1，公共电压信号V1可以为直流电压信号；在触控阶段TU，集成电路通过信号线给触控结构提供具有高频翻转的脉冲电压信号V2，以识别操作体，例如手指进行触控时导致的电容变化。但是，触控信号的高频脉冲电压信号V2往往会对显示基板上其他信号线产生耦合 扰动，造成信号线传输信号不准确。
例如，在GOA(Gate on Array)产品中，可以采用GOA信号随着触控信号一起高频翻转，以减轻耦合扰动；但是对于栅扫描驱动电路集成于IC的Gate IC+TDDI产品，这种耦合扰动无法避免。
本公开至少一实施例提供一种显示基板和显示装置，该显示基板具有显示区域和围绕显示区域的周边区域，并具有触控功能，显示基板包括第一公共电压线、第二公共电压线以及集成电路；第一公共电压线设置在周边区域且至少部分围绕显示区域；第二公共电压线设置在周边区域，位于第一公共电压线的远离显示区域的一侧，且至少部分围绕显示区域；集成电路设置在周边区域，且位于显示区域的第一侧，配置为在显示阶段向第一公共电压线和第二公共电压线提供与显示信号相同的第一信号，在触控阶段向第一公共电压线和第二公共电压线提供与触控信号相同的第二信号，第一信号与第二信号不同。
在本公开实施例提供的上述显示基板中，集成电路采用分时的方式在显示阶段以及触控阶段同时为位于周边区域的第一公共电压线和第二公共电压线提供相同的电信号，由此可以使得第一公共电压线和第二公共电压线传输的信号一致，不会发生信号耦合扰动，以避免信号线传输信号不准确的现象，提高显示基板的显示质量和触控效果。
下面，通过几个具体的实施例来详细介绍本公开实施例提供的显示基板和显示装置。
本公开至少一实施例提供一种显示基板，图2示出了该显示基板的平面示意图，如图2所示，该显示基板具有显示区域AA和围绕显示区域AA的周边区域NA，并具有触控功能。
显示基板包括第一公共电压线C1、第二公共电压线C2以及集成电路IC；第一公共电压线C1设置在周边区域NA且至少部分围绕显示区域AA；第二公共电压线C2设置在周边区域NA，位于第一公共电压线C1的远离显示区域AA的一侧，且至少部分围绕显示区域AA；集成电路IC设置在周边区域NA，且位于显示区域AA的第一侧(图2中示出为显示区域AA的下侧)，配置为在显示阶段向第一公共电压线C1和第二公共电压线C2提供与显示信号相同的第一信号，在触控阶段向第一公共电压线C1和第二公共电压线C2提供与触控信号相同的第二信 号，第一信号与第二信号不同。例如，在一些实施例中，第一信号为公共电压信号，例如直流电压信号；第二信号为脉冲电压信号。
例如，在一些实施例中，如图2所示，显示区域AA包括多个子像素SP，显示基板还包括触控结构(稍后详细介绍)以及多条第三公共电压线C3(图2中示出一条第三公共电压线C3作为示例)。触控结构设置在显示区域AA和周边区域NA中的至少一个，包括多个触控电极T，配置为实现触控功能。例如，多个触控电极T可以设置在显示区域AA中，周边区域NA中，或者同时设置在显示区域AA和周边区域NA中，以在相应的位置实现触控功能。
例如，多条第三公共电压线C3设置在周边区域NA和显示区域AA，也即在周边区域NA和显示区域AA延伸，配置为电连接多个子像素SP和多个触控电极T。集成电路IC还配置为在显示阶段通过多条第三公共电压线C3向多个子像素SP提供显示信号，例如公共电压信号，例如直流电压信号，并在触控阶段通过多条第三公共电压线C3向多个触控电极T提供触控信号，例如脉冲电压信号。例如，显示信号(第一信号)和触控信号(第二信号)的波形可以参见图1。
例如，在一些实施例中，触控结构可以为自容式触控结构或者互容式触控结构等。本公开的实施例以自容式触控结构为例进行介绍。自容式触控结构通常包括多个触控电极，例如多个块状的触控电极，也即上述触控电极T，当操作体，例如手指触摸屏幕时，由于人体电场，手指和触摸位置的触控电极会形成一个耦合电容，导致该触控电极的原有电容发生变化，通过检测出发生变化的触控电极的位置，即可得出触控位置。
例如，在上述实施例中，多条第三公共电压线C3同时用作多个子像素SP的公共电压线以及多个触控电极T的触控信号线，集成电路IC采用分时的方式向多条第三公共电压线C3提供显示信号或者触控信号，由此可以减少显示基板上信号线的数量，使显示基板的结构、走线排布更简单，由此有利于显示基板的窄边框、薄型化设计。
例如，在一些实施例中，一个第三公共电压线C3连接一个触控电极T，从而为该一个触控电极T提供触控信号，一个第三公共电压线C3连接N个子像素(N为大于1的正整数)，从而为该N个子像素提 供显示信号。例如，根据触控电极T的大小，一个触控电极T可以对应2000-8000个子像素，例如3000个、4000个、5000个、6000个或者7000个子像素等，也即，N为2000-8000，一个第三公共电压线C3可以连接2000-8000个子像素，以为该2000-8000个子像素提供显示信号，例如公共电压信号。
例如，图3示出了本公开至少一实施例提供的另一显示基板的平面示意图。如图3所示，在一些实施例中，第一公共电压线C1包括第一连接端N1和第二连接端N2，第二公共电压线C2包括第三连接端N3和第四连接端N4，第一连接端N1与第三连接端N3电连接，第二连接端N2与第四连接端N4电连接，以将第一公共电压线C1和第二公共电压线C2电连接。由此可以使第一公共电压线C1和第二公共电压线C2的信号传输更同步。
例如，在一些实施例中，如图3所示，集成电路IC包括间隔设置的第一绑定端B1和第二绑定端B2以及间隔设置的第三绑定端B3和第四绑定端B3，第一绑定端B1和第三绑定端B3电连接，第二绑定端B2与第四绑定端B4电连接；第一连接端N1电连接第一绑定端B1，第三绑定端B3电连接第三连接端N3，第二连接端N2电连接第二绑定端B2，第四绑定端B4电连接第四连接端N4，以将第一公共电压线C1和第二公共电压线C2通过集成电路IC电连接。
例如，在一些实施例中，如图3所示，显示基板还包括电路板F，例如，电路板F包括柔性电路板(Flexible Printed Circuit，FPC)和印刷电路板(Printed Circuit Board，PCB)中的至少一个(图中示出柔性电路板FPC作为示例)，电路板F设置在周边区域NA且至少部分设置在集成电路IC的远离显示区域AA的一侧。例如，第三连接端N3和第四连接端N4分别通过电路板F与第三绑定端B3和第四绑定端B4电连接，例如第三连接端N3和第四连接端N4分别绑定到电路板F后，通过电路板F上的线路，在电路板F的另一端与第三绑定端B3和第四绑定端B4绑定。
由此，在上述实施例中，第一公共电压线C1直接接入集成电路IC的第一绑定端B1，然后经电路板F(例如依次经过柔性电路板和印刷电路板)再连接到第二公共电压线C2，这样使第一公共电压线C1和第 二公共电压线C2在远端进行了连接，这样的连接方式对屏蔽静电释放(Electro-Static discharge，ESD)更有利。
例如，在一些实施例中，第一绑定端B1、第二绑定端B2以及第三绑定端B3和第四绑定端B3可以分别包括一个、两个或更多个绑定引脚，以确保第一公共电压线C1和第二公共电压线C2被有效绑定于集成电路IC。
例如，在一些实施例中，图4示出了本公开至少一实施例提供的再一显示基板的平面示意图，如图4所示，集成电路IC可以包括在显示区域AA的第一侧并列设置的第一子集成电路IC1和第二子集成电路IC2。例如，第一子集成电路IC1为主IC，第二子集成电路IC2为辅IC，第一子集成电路IC1和第二子集成电路IC2可以配置为向不同区域的子像素SP或者触控电极T提供驱动信号。
例如，如图4所示，第一绑定端B1和第三绑定端B3设置在第一子集成电路IC1的远离第二子集成电路IC2的一端，也即图中的左端；第二绑定端B2和第四绑定端B4设置在第二子集成电路IC2的远离第一子集成电路IC1的一端，也即图中的右端，由此第一绑定端B1和第二绑定端B2相隔一定的距离。
例如，在一些实施例中，如图4所示，第一子集成电路IC1还包括设置在第一子集成电路IC1的靠近第二子集成电路IC2一端(图中的右端)的第五绑定端B5，第二子集成电路IC2还包括设置在第二子集成电路IC2的靠近第一子集成电路IC1一端(图中的左端)的第六绑定端B6，第五绑定端B5和第六绑定端B6在显示阶段被输入显示信号，在触控阶段被输入触控信号，例如，第五绑定端B5和第六绑定端B6浮置，也即第五绑定端B5和第六绑定端B6不连接信号线。
例如，在上述实施例中，第一子集成电路IC1的右端和第二子集成电路IC2的右端均为IC内部的近端，第一子集成电路IC1的左端和第二子集成电路IC2的左端同为IC内部的远端，考虑到IC内部近端和远端的信号传输不同步，例如，信号先给到IC内部的近端，之后给到IC内部的远端，因此，通过对距离较近的第五绑定端B5和第六绑定端B6进行了Floating设计，也即浮置设计，可以防止其传输的触控信号不同步使得不同步信号之间发生干扰，由此有利于触控性能的提升。
例如，第五绑定端B5和第六绑定端B6也可以分别包括一个、两个或更多个绑定引脚，以与第一绑定端B1和第二绑定端B2的设置一致。
例如，在一些实施例中，如图4所示，第一子集成电路IC1还包括设置在第一绑定端B1和第五绑定端B5之间的多个第七绑定端B7，第二子集成电路IC2还包括设置在第二绑定端B2和第六绑定端B6之间的多个第八绑定端B8，多条第三公共电压线C3分别电连接至多个第七绑定端B7和多个第八绑定端B8。
例如，第七绑定端B7和第八绑定端B8也可以分别包括一个、两个或更多个绑定引脚，本公开的实施例对此不作具体限定。
例如，在本公开的实施例中，上述多个第七绑定端B7和多个第八绑定端B8配置为在显示阶段通过多条第三公共电压线C3向多个子像素SP提供显示信号，例如公共电压信号，例如直流电压信号，并在触控阶段通过多条第三公共电压线C3向多个触控电极T提供触控信号，例如脉冲电压信号；也即多个第七绑定端B7和多个第八绑定端B8为传输有效驱动信号的绑定端，用于实现显示功能和触控功能。
例如，在本公开的实施例中，第一公共电压线C1和第二公共电压线C2虽然也在显示阶段被施加显示信号并传输显示信号，并在触控阶段被施加触控信号并传输触控信号，但是该信号并不用于控制显示操作以及触控操作，仅用作在周边区域NA围绕显示区域AA，并通过传输与第三公共电压线C3相一致的信号，以起到防信号串扰等作用。
例如，第一公共电压线C1相对于第二公共电压线C2设置在显示基板的内圈，从而可以在靠近显示区域AA的一侧屏蔽显示区域AA的信号；第二公共电压线C2相对于第一公共电压线C1设置在显示基板的外圈，从而可以在显示基板的外圈起到防止外侧静电，起到静电屏蔽的效果。
例如，在一些实施例中，上述第一绑定端B1、第二绑定端B2、第五绑定端B5、第六绑定端B6、多个第七绑定端B7和多个第八绑定端B8在结构上基本相同，并且被传输的信号的也相同，由此可以保证信号传输的一致性。例如，在一些实施例中，由于第一绑定端B1、第二绑定端B2、第五绑定端B5和第六绑定端B6并不用于连接子像素和触 控电极，因此也可以叫做虚设(Dummy)端。
例如，如图4所示，第一子集成电路IC1中的多个第七绑定端B7位于第一绑定端B1和第五绑定端B5之间，第二子集成电路IC2中的多个第八绑定端B8位于第二绑定端B2和第六绑定端B6之间，由此，在每个子集成电路中，用于传输有效驱动信号的绑定端均位于虚设端之间，由此还可以进一步避免用于传输有效驱动信号的绑定端以及相应的信号线被干扰。
例如，在一些实施例中，如图4所示，柔性电路板FPC具有绑定端B，第二公共电压线C2的第三连接端N3通过绑定端的至少一个引脚连接到柔性电路板FPC中的电路，并通过绑定端的至少另一个引脚与第三绑定端B3，第四连接端N4与第三连接端N3的连接方式类似。
例如，在一些实施例中，如图4所示，柔性电路板FPC的绑定端还包括多个直流电压输出引脚，配置为被输入直流电压信号；此时，多个直流电压输出引脚可以通过信号线Vcom短接，从而并不用于提供有效的驱动信号。
例如，图11示出了本公开至少一实施例提供的显示基板的第一公共电压线、第二公共电压线和第三公共电压线的信号波形图。如图11所示，在一些实施例中，第一公共电压线C1、第二公共电压线C2和第三公共电压线C3的波形如图11中最下方的粗实线所示。在显示阶段DA，第一公共电压线C1、第二公共电压线C2和第三公共电压线C3被施加第一直流电压信号V11或者第二直流电压信号V12(也即上述第一信号)，第一直流电压信号V11的电位高于第二直流电压信号V12的电位；在触控阶段TU，第一公共电压线C1、第二公共电压线C2和第三公共电压线C3被施加脉冲信号(也即上述第二信号)，例如脉冲电压，该脉冲电压具有最高电位V21以及最低电位V22。例如，第一直流电压信号V11的电位高于脉冲电压的最高电位V21，第二直流电压信号V12的电位低于脉冲电压的最低电位V22，由此满足不同阶段的信号要求。
例如，图11还示出了栅扫描驱动电路的部分波形G，该栅扫描驱动电路例如可以在显示阶段DA控制向多个子像素的像素驱动电路的薄膜晶体管的栅极提供扫描电压，其具体波形可以参见相关技术，这里 不再赘述。
例如，在一些实施例中，如图4所示，第一公共电压线C1和第二公共电压线C2至少在显示基板的第二侧(例如显示基板的上侧)、第三侧(例如显示基板的左侧)和第四侧(例如显示基板的右侧)围绕显示区域AA，并在显示区域AA的第一侧电连接到集成电路IC，上述第一侧与第二侧相对，第三侧与第四侧相对。
例如，在一些实施例中，如图4所示，第一公共电压线C1还可以在显示区域AA的第一侧围绕显示区域AA，以在显示区域AA的四周起到防信号干扰的作用。例如，在一些实施例中，如图3所示，第二公共电压线C2也可以在显示区域AA的第一侧围绕显示区域AA，以在显示区域AA的四周充分起到防信号干扰的作用。
例如，图5示出了本公开至少一实施例提供的显示基板的部分电路排布图，为示出清楚，图5中仅示出了第一公共电压线C1以及第一子集成电路IC1和第二子集成电路IC2的部分结构作为示例。图6示出了本公开至少一实施例提供的显示基板在四个边角位置的部分电路排布图。如图5和图6所示，在一些实施例中，第一公共电压线C1和第二公共电压线C2分别呈网格状，从而可以减小压降，提高第一公共电压线C1和第二公共电压线C2的信号传输一致性。
例如，图7示出了本公开至少一实施例提供的另一显示基板在四个边角位置的部分电路排布图。如图7所示，在一些实施例中，显示基板还可以包括设置在显示区域AA的与第一侧相邻的第三侧和第四侧的栅扫描驱动电路GOA，也即形成GOA(Gate on Array)显示基板，此时，栅扫描驱动电路的传输信号在触控阶段可以被配置为与触控信号一致，以减轻信号的耦合扰动。例如，在图7的实施例中，第一公共电压线C1和第二公共电压线C2可以设置在栅扫描驱动电路GOA的远离显示区域AA的一侧，以在更外围起到防信号干扰的作用。
例如，图8示出了本公开至少一实施例提供的显示基板的截面示意图。在一些实施例中，如图8所示，显示基板还包括衬底基板110，多个子像素SP的每个包括设置在衬底基板110上的像素驱动电路，像素驱动电路包括薄膜晶体管TFT，薄膜晶体管TFT包括有源层121、栅极122以及源漏电极123和124等结构。
例如，图8中示出的薄膜晶体管TFT为底栅型，栅极122设置在有源层121的靠近衬底基板110的一侧，栅极122上设置有栅绝缘层126。例如，在其他实施例中，薄膜晶体管TFT也可以为顶栅型，栅极122设置在有源层121的远离衬底基板110的一侧，本公布开的实施例对薄膜晶体管TFT的具体形式不做限定。
例如，在一些实施例中，第一公共电压线C1和第二公共电压线C2与栅极122同层设置，由此可以简化显示基板的制备工艺，并利于显示基板的薄型化设计。
需要注意的是，在本公开的实施例中，“同层设置”为两个(或更多个)功能层或结构层在显示基板的层级结构中同层且同材料形成，即在制备工艺中，该两个(或更多个)功能层或结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构。
例如，在一些实施例中，如图6所示，显示基板还包括设置在衬底基板110上的多条栅极引线125，多条栅极引线125分别与多个子像素SP的薄膜晶体管TFT的栅极122电连接，配置为向栅极122提供栅扫描信号。例如，在一些实施例中，多条栅极引线125分别与栅极122或者源漏电极123和124同层设置。
例如，多条栅极引线125的一部分与栅极122同层设置，此时，栅极引线125可以与栅极122一体连接，多条栅极引线125的另一部分与源漏电极123和124同层设置，此时，栅极引线125可以与栅极122通过过孔连接。由于显示基板上栅极引线125的数量较多，通过将多条栅极引线125分布在两个层，也即栅极122所在层以及源漏电极123和124所在层，可以简化栅极引线125在每一层的排布难度，并且可以避免多条栅极引线125的排布密度过高造成信号串扰或者短路等问题。
例如，在一些实施例中，如图6所示，多条栅极引线125延伸至周边区域NA，且在周边区域NA的至少部分位于第一公共电压线C1和第二公共电压线C2之间。
例如，如图6所示，多条栅极引线125在显示基板的右下部分延伸，例如延伸至集成电路IC，以使得集成电路IC可以为多条栅极引线125提供栅扫描信号；此时，多条栅极引线125两侧的第一公共电压线C1和第二公共电压线C2的分布宽度较小，以为多条栅极引线125避让排 布空间。
例如，如图8所示，多个触控电极T位于像素驱动电路的远离衬底基板110的一侧。例如，多个触控电极T复用做子像素SP的公共电极，用于为子像素SP提供公共电压。
例如，如图8所示，显示基板还包括与薄膜晶体管TFT的源漏电极124电连接的像素电极P，例如，像素电极P配置为被施加高电平电压，公共电极配置为被施加低电平电压。当显示基板用于液晶显示装置时，液晶可以在像素电极P与公共电极形成的电压差的驱动下进行不同程度的偏转，进而实现显示。
例如，在一些实施例中，如图8所示，显示基板还包括设置在像素电极P上的钝化层127，以将像素电极P与公共电极绝缘。
例如，在一些实施例中，多个触控电极T与多条第三公共电压线C3同层设置，以简化显示基板的制备工艺，并利于显示基板的薄型化设计。
例如，在垂直于衬底基板110的方向上，也即图8中的竖直方向上，有源层121与多个触控电极T和多条第三公共电压线C3不交叠，也即有源层121在衬底基板110上的正投影与多个触控电极T和多条第三公共电压线C3在衬底基板110上的正投影不交叠，由此可以避免多个触控电极T和多条第三公共电压线C3上传输的信号影响有源层121的导电性，进而影响薄膜晶体管的正常工作。
例如，在一些实施例中，像素电极P、多个触控电极T与多条第三公共电压线C3可以采用透明金属氧化物材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)等，以提高其透明度。
例如，在一些实施例中，如图6所示，显示基板还可以包括接地线G，接地线G设置在周边区域NA，位于第二公共电压线C2的远离显示区域AA的一侧，且至少部分围绕显示区域AA。例如，接地线G在显示基板的第二侧、第三侧和第四侧围绕显示区域AA，并在显示基板的第一侧连接到集成电路IC。例如，接地线G配置为被施加接地电压，例如零电压，以在显示基板的外围提供信号屏蔽作用。
例如，在一些实施例中，接地线G与栅极122同层设置，以简化显示基板的制备工艺，并利于显示基板的薄型化设计。
例如，在一些实施例中，如图6所示，显示基板还可以包括测试线S，测试线S设置在周边区域NA，位于接地线G的远离显示区域AA的一侧，且位于显示区域AA的与第一侧相对的第二侧(图中示出为上侧)。例如，在一些示例中，测试线S与多个子像素SP中的至少部分电连接，以在显示基板出厂前进行点灯测试，测试多个子像素SP中的至少部分是否可以正常显示，但是在显示基板出厂后，测试线S并不参与显示基板的显示操作。
例如，在一些实施例中，测试线S与栅极122同层设置，以简化显示基板的制备工艺，并利于显示基板的薄型化设计。
例如，在本公开的实施例中，衬底基板110可以采用玻璃、石英等刚性基板或者聚酰亚胺(PI)等柔性基板。有源层121的材料包括但不限于硅基材料(非晶硅a-Si，多晶硅p-Si等)、金属氧化物半导体(IGZO，ZnO，AZO，IZTO等)以及有机物材料(六噻吩，聚噻吩等)。在制备过程中，有源层121的部分半导体材料被导体化，以具有良好的导电性。例如，栅极122以及源漏电极123和124可以采用铜(Cu)、铝(Al)、钼(Mo)、镁(Mg)、钛(Ti)、钨(W)等金属材料或者合金材料。例如，栅极122以及源漏电极123和124可以为单层或者多层结构，例如Ti/Al/Ti或者Mo/Al/Mo等多层金属结构。
例如，栅绝缘层126和钝化层127可以为无机绝缘层，例如采用氧化硅(SiOx)、氮化硅(SiNy)或者氮氧化硅(SiOxNy)等无机绝缘材料制作。
例如，在上述显示基板的制备过程中，可以首先在衬底基板上采用例如溅射或者沉积等工艺形成栅极材料层，然后利用第一掩模版对栅极材料层进行构图工艺，以形成栅极122。例如，依次构图工艺包括光刻胶的形成、曝光、显影以及刻蚀等工艺，本公开的实施例对此不再赘述。
例如，在栅极122制备完成后，在栅极122上采用例如沉积等工艺形成栅绝缘层126，然后在栅绝缘层126上采用例如溅射或者沉积等工艺形成有源材料层，然后利用第二掩模板对有源材料层进行构图工艺，以形成有源层121的图案。例如，有源层121的图案形成后，还可以对其部分区域进行掺杂工艺，以在源漏电极123和124的连接位置被导体化。
例如，在有源层121制备完成后，在有源层121以及栅绝缘层126上采用例如溅射或者沉积等工艺形成像素电极材料层，然后利用第三掩模板对像素电极材料层进行构图工艺，以形成像素电极P。
例如，在像素电极P制备完成后，在像素电极P上采用例如溅射或者沉积等工艺形成源漏电极材料层，然后利用第四掩模板对源漏电极材料层进行构图工艺，以形成源漏电极123和124。
例如，在源漏电极123和124制备完成后，在源漏电极123和124上采用例如溅射或者沉积等工艺形成钝化材料层，然后利用第五掩模板对钝化材料层进行构图工艺，以形成钝化层127。
例如，在钝化层127制备完成后，在钝化层127上采用例如溅射或者沉积等工艺形成公共电极材料层，然后利用第六掩模板对公共电极材料层进行构图工艺，以形成公共电极层，也是触控结构层。
由此，可以利用六张掩模板(Mask)完成对图8所示的显示基板的制备，该制备过程更简单易行。
本公开至少一实施例还提供一种显示装置，图9示出了该显示装置的结构示意图，如图9所示，该显示装置包括本公开实施例提供的显示基板10、对置基板20以及液晶层30；对置基板20与显示基板10对置，液晶层30位于显示基板10与对置基板20之间，由此该显示装置实现为液晶显示装置。
例如，在一些实施例中，对置基板20可以为彩膜基板，例如，图10示出了该彩膜基板的平面示意图。例如，如图10所示，该彩膜基板包括黑矩阵层BM以及多个彩膜图案CF。例如，黑矩阵层BM包括对应于多个子像素SP的多个子像素开口BM1，多个彩膜图案CF分别设置在该多个子像素开口BM1中，以对从多个子像素开口BM1中发出的光进行滤色。
例如，多个彩膜图案CF包括红色彩膜图案、绿色彩膜图案以及蓝色彩膜图案，以实现全彩显示。或者，在其他实施例中，多个彩膜图案CF也可以具有其他颜色，本公开的实施例对此不作具体限定。
例如，对置基板20还可以包括除上述结构以外的其他结构，具体可以参考相关技术，本公开的实施例不再赘述。
还有以下几点需要说明：
(1)本公开实施例的附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (25)

  1. 一种显示基板，具有显示区域和围绕所述显示区域的周边区域，并具有触控功能，所述显示基板包括：
    第一公共电压线，设置在所述周边区域且至少部分围绕所述显示区域；
    第二公共电压线，设置在所述周边区域，位于所述第一公共电压线的远离所述显示区域的一侧，且至少部分围绕所述显示区域；以及
    集成电路，设置在所述周边区域，且位于所述显示区域的第一侧，配置为在显示阶段向所述第一公共电压线和所述第二公共电压线提供与显示信号相同的第一信号，在触控阶段向所述第一公共电压线和所述第二公共电压线提供与触控信号相同的第二信号，
    所述第一信号与所述第二信号不同。
  2. 根据权利要求1所述的显示基板，其中，所述显示区域包括多个子像素，所述显示基板还包括：
    触控结构，设置在所述显示区域和所述周边区域中的至少一个，包括多个触控电极，配置为实现所述触控功能；以及
    多条第三公共电压线，设置在所述周边区域和所述显示区域，配置为电连接所述多个子像素和所述多个触控电极；
    所述集成电路还配置为在所述显示阶段通过所述多条第三公共电压线向所述多个子像素提供所述显示信号，在所述触控阶段通过所述多条第三公共电压线向所述多个触控电极提供所述触控信号。
  3. 根据权利要求1或2所述的显示基板，其中，所述显示信号为直流电压，所述触控信号为脉冲电压。
  4. 根据权利要求3所述的显示基板，其中，所述直流电压包括第一直流电压信号，所述脉冲电压具有最高电位和最低电位，
    所述第一直流电压信号的电位高于所述最高电位。
  5. 根据权利要求4所述的显示基板，其中，所述直流电压还包括第二直流电压信号，所述第一直流电压信号的电位高于所述第二直流电压信号的电位，
    所述第二直流电压信号的电位低于所述最低电位。
  6. 根据权利要求2所述的显示基板，其中，所述多条第三公共电 压线中的每个电连接所述多个触控电极中的一个触控电极以及所述多个子像素中的N个子像素，N为大于1的正整数。
  7. 根据权利要求1-6任一所述的显示基板，其中，所述第一公共电压线包括第一连接端和第二连接端，所述第二公共电压线包括第三连接端和第四连接端，
    所述第一连接端与所述第三连接端电连接，所述第二连接端与所述第四连接端电连接，以将所述第一公共电压线和所述第二公共电压线电连接。
  8. 根据权利要求7所述的显示基板，其中，所述集成电路包括间隔设置的第一绑定端和第二绑定端以及间隔设置的第三绑定端和第四绑定端，所述第一绑定端和所述第三绑定端电连接，所述第二绑定端与所述第四绑定端电连接；
    所述第一连接端电连接所述第一绑定端，所述第三绑定端电连接所述第三连接端，所述第二连接端电连接所述第二绑定端，所述第四绑定端电连接所述第四连接端，以将所述第一公共电压线和所述第二公共电压线电连接。
  9. 根据权利要求8所述的显示基板，还包括：
    电路板，设置在所述周边区域且至少部分设置在所述集成电路的远离所述显示区域的一侧，
    其中，所述第三连接端和所述第四连接端分别通过所述电路板与所述第三绑定端和所述第四绑定端电连接。
  10. 根据权利要求8或9所述的显示基板，其中，所述集成电路包括在所述显示区域的第一侧并列设置的第一子集成电路和第二子集成电路，
    所述第一绑定端和所述第三绑定端设置在所述第一子集成电路的远离所述第二子集成电路的一端，所述第二绑定端和所述第四绑定端设置在所述第二子集成电路的远离所述第一子集成电路的一端。
  11. 根据权利要求10所述的显示基板，其中，所述第一子集成电路还包括设置在所述第一子集成电路的靠近所述第二子集成电路一端的第五绑定端，所述第二子集成电路还包括设置在所述第二子集成电路的靠近所述第一子集成电路一端的第六绑定端，
    所述第五绑定端和所述第六绑定端在所述显示阶段被输入显示信号，在所述触控阶段被输入所述触控信号，所述第五绑定端和所述第六绑定端浮置。
  12. 根据权利要求10所述的显示基板，其中，所述第一子集成电路还包括设置在所述第一绑定端和所述第五绑定端之间的多个第七绑定端，所述第二子集成电路还包括设置在所述第二绑定端和所述第六绑定端之间的多个第八绑定端，
    所述多条第三公共电压线分别电连接至所述多个第七绑定端和所述多个第八绑定端。
  13. 根据权利要求1-12任一所述的显示基板，其中，所述第一公共电压线和所述第二公共电压线至少在所述显示基板的第二侧、第三侧和第四侧围绕所述显示区域，
    并在所述显示区域的第一侧电连接到所述集成电路，
    所述第一侧与所述第二侧相对，所述第三侧与所述第四侧相对。
  14. 根据权利要求1-13任一所述的显示基板，其中，所述第一公共电压线和所述第二公共电压线分别呈网格状。
  15. 根据权利要求2所述的显示基板，还包括衬底基板，所述多个子像素的每个包括设置在所述衬底基板上的像素驱动电路，所述像素驱动电路包括薄膜晶体管，所述薄膜晶体管包括栅极以及源漏电极，
    所述第一公共电压线和所述第二公共电压线与所述栅极同层设置。
  16. 根据权利要求15所述的显示基板，其中，所述显示基板还包括设置在所述衬底基板上的多条栅极引线，所述多条栅极引线分别与所述多个子像素的薄膜晶体管的栅极电连接，
    所述多条栅极引线分别与所述栅极或者所述源漏电极同层设置。
  17. 根据权利要求16所述的显示基板，其中，所述多条栅极引线延伸至所述周边区域，且在所述周边区域的至少部分位于所述第一公共电压线和所述第二公共电压线之间。
  18. 根据权利要求15-17任一所述的显示基板，其中，所述多个触控电极位于所述像素驱动电路的远离所述衬底基板的一侧。
  19. 根据权利要求15-17任一所述的显示基板，其中，所述多个触控电极与多条第三公共电压线同层设置。
  20. 根据权利要求19所述的显示基板，其中，所述薄膜晶体管还包括有源层，
    在垂直于所述衬底基板的方向上，所述有源层与所述多个触控电极和所述多条第三公共电压线不交叠。
  21. 根据权利要求15-20任一所述的显示基板，还包括：
    接地线，设置在所述周边区域，位于所述第二公共电压线的远离所述显示区域的一侧，且至少部分围绕所述显示区域。
  22. 根据权利要求21所述的显示基板，其中，所述接地线与所述栅极同层设置。
  23. 根据权利要求21或22所述的显示基板，还包括：
    测试线，设置在所述周边区域，位于所述接地线的远离所述显示区域的一侧，且位于所述显示区域的与所述第一侧相对的第二侧。
  24. 根据权利要求23所述的显示基板，其中，所述测试线与所述栅极同层设置。
  25. 一种显示装置，包括：
    权利要求1-24任一所述的显示基板，
    对置基板，与所述显示基板对置，以及
    液晶层，位于所述显示基板与所述对置基板之间。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107065365A (zh) * 2017-06-16 2017-08-18 厦门天马微电子有限公司 显示面板以及显示装置
CN111045549A (zh) * 2019-11-28 2020-04-21 武汉天马微电子有限公司 显示面板及其驱动方法和显示装置
CN112987424A (zh) * 2017-03-25 2021-06-18 厦门天马微电子有限公司 阵列基板、触控显示面板和触控显示装置
CN113835259A (zh) * 2021-11-09 2021-12-24 京东方科技集团股份有限公司 显示基板及显示装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112987424A (zh) * 2017-03-25 2021-06-18 厦门天马微电子有限公司 阵列基板、触控显示面板和触控显示装置
CN107065365A (zh) * 2017-06-16 2017-08-18 厦门天马微电子有限公司 显示面板以及显示装置
CN111045549A (zh) * 2019-11-28 2020-04-21 武汉天马微电子有限公司 显示面板及其驱动方法和显示装置
CN113835259A (zh) * 2021-11-09 2021-12-24 京东方科技集团股份有限公司 显示基板及显示装置

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