WO2024022172A1 - 显示基板以及显示装置 - Google Patents

显示基板以及显示装置 Download PDF

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Publication number
WO2024022172A1
WO2024022172A1 PCT/CN2023/107944 CN2023107944W WO2024022172A1 WO 2024022172 A1 WO2024022172 A1 WO 2024022172A1 CN 2023107944 W CN2023107944 W CN 2023107944W WO 2024022172 A1 WO2024022172 A1 WO 2024022172A1
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WO
WIPO (PCT)
Prior art keywords
edge
line
display area
voltage
area
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Application number
PCT/CN2023/107944
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English (en)
French (fr)
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WO2024022172A9 (zh
Inventor
王梦奇
于子阳
蒋志亮
胡明
陈飞
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2024022172A1 publication Critical patent/WO2024022172A1/zh
Publication of WO2024022172A9 publication Critical patent/WO2024022172A9/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements

Definitions

  • At least one embodiment of the present disclosure relates to a display substrate and a display device.
  • organic light-emitting diode (OLED) display products Compared with traditional liquid crystal displays (LCDs), organic light-emitting diode (OLED) display products have the advantages of self-illumination, wide color gamut, high contrast, and thinness, making them widely used in mobile phones, tablets, etc. field.
  • LCDs liquid crystal displays
  • OLED organic light-emitting diode
  • At least one embodiment of the present disclosure provides a display substrate, which includes: a display area, a non-display area, a first power supply voltage lead, and a first power voltage line.
  • the display area is provided with sub-pixels and has a lower edge extending in a transverse direction and a left edge extending in a longitudinal direction.
  • the transverse direction intersects the longitudinal direction.
  • a dividing line extending along the longitudinal direction divides the display area into a left display area. and a right display area.
  • the left display area includes a first edge display area extending along the left edge and a first middle display area located in the first edge display area and close to the right display area;
  • the non-display area includes a frame area surrounding at least part of the display area;
  • a first power supply voltage lead is configured to provide a first power supply voltage and is located within the frame area;
  • the first power supply voltage lead includes a first power supply voltage lead along the lower edge corresponding to a first a portion of the lower lead that extends along the edge of the display area and does not correspond to a portion of the first middle display area along the lower edge Extension;
  • the first power supply voltage line includes an edge voltage line located along the first edge display area and an intermediate voltage line located along the first middle display area;
  • the edge voltage line is directly connected to the lower lead to provide
  • the sub-pixel located in the first edge display area provides the first power supply voltage, and the intermediate voltage line is spaced apart from the lower lead.
  • the first power supply voltage line includes a longitudinal voltage line extending along the longitudinal direction and a transverse voltage line extending along the transverse direction, and the longitudinal voltage line is related to the The transverse voltage lines are arranged in different layers; the longitudinal voltage lines include edge longitudinal voltage lines located in the first edge display area, and the transverse voltage lines include edge vertical voltage lines located in the first edge display area and connected to the edge longitudinal voltage lines.
  • the edge longitudinal voltage line and the edge transverse voltage line constitute the edge voltage line;
  • the first power supply voltage lead also includes a left lead extending along the left edge of the display area, so The edge vertical voltage line is directly connected to the lower lead, and the edge transverse voltage line is directly connected to the left lead.
  • the sub-pixel includes: a driving transistor, a light-emitting device and a data transistor, the driving transistor is configured to control the size of the driving current flowing through the light-emitting device, so The light-emitting device is configured to receive the driving current and be driven by the driving current to emit light, the data transistor is configured to write a data signal to the gate of the driving transistor in response to a first control signal, and the data line is configured to In order to transmit the data signal to the sub-pixel; the display area includes a lower display area and an upper display area, the lower display area is close to the lower edge, and the upper display area is located vertically in the lower display area.
  • the lower display area includes a first area and a second area
  • the first area includes a first sub-area close to the left edge in the transverse direction and a first sub-area away from the left edge.
  • the data line passing through the first sub-region and the second region includes a first connection line extending along the longitudinal direction in the first sub-region and a first connection line extending along the longitudinal direction in the first sub-region and the second sub-region.
  • the first connection line and the second connection line of the data line are electrically connected through a first connection hole; the first sub-region is located in the first middle display area, and the second area is at least partially located in the In the middle display area; the first sub-area has a left endpoint closest to the left edge of the display area in the transverse direction, and a straight line extending along the longitudinal direction and passing through the left endpoint is the first sub-area.
  • the dividing line passes through the second area and divides the second area into a first sub-area close to the left edge of the display area and a first sub-area away from the left edge of the display area.
  • the lower display area It also includes a third area, which is located in the first edge display area and is located on a side of the second area away from the first area in the lateral direction;
  • the edge lateral voltage line includes a The lower edge transverse voltage line of the third region, the edge longitudinal voltage line passes through the third region, and intersects with the lower edge transverse voltage line at a first intersection point, the left end of the lower edge transverse voltage line Electrically connected to the left lead, the right end of the lower edge transverse voltage line opposite to its left end is disconnected from the second connection line in the second area through a first break;
  • the vertical voltage line includes multiple The edge longitudinal voltage lines and the edge lateral voltage lines are interlaced with each other into a grid, and the grid includes a plurality of edge lateral voltage lines.
  • the plurality of edge vertical voltage lines are electrically connected to the plurality of edge lateral voltage lines through a plurality of the first via holes, and the plurality of first The planar pattern formed by the positions of the via holes is a connecting line segment located in the third area, and the extending direction of the connecting line segment intersects both the first direction and the second direction.
  • the third area is composed of a second side of the second area close to the left edge in the transverse direction, the left edge and the The corner area defined by the lower edge.
  • the frame area includes a frame corner area surrounding the corner area, and an auxiliary first power supply voltage line in a grid shape is provided in the frame corner area
  • the grid-shaped auxiliary first power supply voltage lines include a plurality of longitudinal auxiliary voltage lines and a plurality of transverse auxiliary voltage lines.
  • a plurality of longitudinal auxiliary voltage lines extend along the longitudinal direction and are arranged on the same layer as the longitudinal voltage lines. The first end of each of the plurality of longitudinal auxiliary voltage lines in the longitudinal direction is connected to the first power supply voltage.
  • the leads are directly connected, and the second end of each of the plurality of longitudinal auxiliary voltage lines in the longitudinal direction opposite to its first end is connected to one of the edge longitudinal voltage lines passing through the corner area.
  • a plurality of transverse auxiliary voltage lines extend along the transverse direction and are arranged on the same layer as the plurality of longitudinal auxiliary voltage lines, and one end of each of the plurality of transverse auxiliary voltage lines in the transverse direction is connected to the The first power supply voltage lead is directly connected, and a second end of each of the plurality of transverse auxiliary voltage lines opposite to its first end in the transverse direction is electrically connected to one of the edge longitudinal voltage lines.
  • the display area includes a pixel array
  • the pixel array includes a plurality of pixel rows extending along the transverse direction and a plurality of pixel columns extending along the longitudinal direction;
  • the plurality of pixel rows include a plurality of edge pixel rows close to the lower edge;
  • the plurality of lateral auxiliary voltage lines correspond to the plurality of edge pixel rows, and each of the plurality of edge pixel rows
  • the edge pixel row includes an edge sub-pixel closest to the left edge
  • the plurality of edge longitudinal voltage lines includes an edge-most longitudinal voltage line passing through the edge sub-pixel of each edge pixel row;
  • the plurality of lateral auxiliary voltage lines The second end of each of the voltage lines is electrically connected to the edgemost longitudinal voltage line passing through the corresponding edge pixel row, and is connected to the edge passing through the corresponding edge pixel row through a first edge via hole.
  • Lateral voltage lines are electrically connected.
  • the lateral voltage lines further include a plurality of first lateral voltage lines, and the plurality of first lateral voltage lines are arranged in the longitudinal direction and are located in the upper display area. ;
  • the left end of the first lateral voltage line is electrically connected to the left lead.
  • the edge lateral voltage line also includes an upper edge lateral voltage line located in the upper display area.
  • the upper edge lateral voltage line serves as one of the A part of the first transverse voltage line;
  • the longitudinal voltage line also includes a plurality of intermediate longitudinal voltage lines, arranged in the transverse direction, passing through part of the first middle display area and passing through the upper display along the longitudinal direction.
  • the plurality of middle longitudinal voltage lines, the plurality of edge longitudinal voltage lines and the plurality of first transverse voltage lines are interwoven into a grid; the plurality of edge longitudinal voltage lines and the plurality of first transverse voltage lines are interwoven into a grid;
  • the voltage lines intersect at a plurality of auxiliary intersection points in the first edge display area. At each position of a part of the auxiliary intersection points among the plurality of auxiliary intersection points, one of the edge longitudinal voltage lines is connected to one of the auxiliary intersection points through an auxiliary via hole.
  • the first transverse voltage lines are electrically connected, and the plurality of edge longitudinal voltage lines are electrically connected to the plurality of first transverse voltage lines through a plurality of the auxiliary via holes; a plane formed by the positions of the plurality of auxiliary via holes
  • the pattern is an auxiliary line segment located in the first edge display area.
  • the extending direction of the auxiliary line segments is the same as the extending direction of the connecting line segments; the display substrate includes a plurality of the auxiliary line segments, the connecting line segments, and the connecting line segments.
  • the plurality of auxiliary line segments are arranged at intervals from each other along the longitudinal direction.
  • the display area further includes an upper edge opposite to the lower edge
  • the first power supply voltage lead further includes an upper lead extending along the upper edge
  • the upper lead is electrically connected to the left lead
  • the upper end of the edge longitudinal voltage line is connected to the upper lead
  • the lower end of the edge longitudinal voltage line opposite to its upper end is directly connected to the lower lead
  • the longitudinal The voltage lines include a middle vertical voltage line located in the first middle display area, and the middle vertical voltage line includes: a first vertical voltage line and a second vertical voltage line.
  • a first longitudinal voltage line sequentially passes through the upper display area and at least part of the second area along the longitudinal direction. The upper end of the first longitudinal voltage line is electrically connected to the upper lead.
  • the first longitudinal voltage line The lower end opposite to its upper end is disconnected from the first connection line in the first sub-region through a second break; the second longitudinal voltage line sequentially passes through the upper display area and the third along the longitudinal direction.
  • the transverse voltage line includes an intermediate transverse voltage line located in the first region, the intermediate transverse voltage line is disconnected from the second connection line in the second region through a third break, and the second The longitudinal voltage line intersects the middle lateral voltage line at a second intersection point, and the second longitudinal voltage line is electrically connected to the middle lateral voltage line through a second via hole at the second intersection point.
  • the plurality of first lateral voltage lines and the plurality of second longitudinal voltage lines intersect at a plurality of third intersection points, and, at the plurality of third intersection points, At each position of at least a part of the third intersection points among the three intersection points, one of the first transverse voltage lines is electrically connected to one of the second longitudinal voltage lines through a third via hole.
  • the display area further includes a right edge opposite to the left edge
  • the first power lead further includes a right lead extending along the right edge, so The right lead is electrically connected to the upper lead; each line of the plurality of first lateral voltage lines runs through the upper display area along the lateral direction, and each line of the plurality of first lateral voltage lines is connected to the upper display area.
  • the right end opposite the left end is electrically connected to the right lead.
  • the plurality of intermediate longitudinal voltage lines and the plurality of first lateral voltage lines intersect each other at a plurality of fourth intersection points in the upper display area, at At each position of a portion of the plurality of fourth intersection points, one of the middle longitudinal voltage lines is electrically connected to one of the first transverse voltage lines through a fourth via hole; a plurality of the fourth via holes
  • the plane pattern formed by the position is a polyline.
  • the fold line includes a line from the The left edge extends to a plurality of sub-fold lines on the right edge, each of the plurality of sub-fold lines includes a plurality of polyline segments connected end to end;
  • the plurality of polyline segments include a first line segment extending along the first direction and a second line segment extending along a second direction, the first direction intersects the second direction, and both the first direction and the second direction intersect the transverse direction and the longitudinal direction, the first direction
  • the first end of the line segment intersects the first end of the second line segment at an upper vertex; a plurality of vertices of the plurality of sub-polylines are located on the second longitudinal voltage line, and the fourth vertex at the position of the vertex
  • the via holes are all the second via holes.
  • each of the plurality of sub-fold lines is W-shaped.
  • the W-shaped sub-fold line includes the first line segment, the second line segment, a third line segment and a fourth line segment, and the first line segment and the second line segment is located between the third line segment and the fourth line segment, the third line segment is connected to the first line segment, and the fourth line segment is connected to the second line segment; the first The line segment is substantially parallel to the fourth line segment, and the second line segment is substantially parallel to the third line segment.
  • the longitudinal direction is perpendicular to the lateral direction
  • the angle between the first line segment and the lateral direction is 45°
  • the angle between the second line segment and the lateral direction is 45°.
  • the included angle is 45°.
  • the auxiliary line segment is located between the third line segments of two adjacent sub-fold lines.
  • the connecting line segment, the auxiliary line segment and the third line segment are substantially parallel to each other.
  • the second longitudinal voltage line divides the first area into the first sub-area and the second sub-area, and the structure of the first sub-area
  • the structure of the second sub-region is substantially axially symmetrical with respect to the second longitudinal voltage line;
  • the lower display area includes a fourth region, and the structure of the fourth region and the structure of the second region are relative to the structure of the second sub-region.
  • the second longitudinal voltage line is substantially axially symmetrical;
  • the data line passing through the first region and the fourth region includes a third connection line extending along the longitudinal direction in the second sub-region and a third connection line extending along the longitudinal direction in the second sub-region.
  • the third connection line and the fourth connection line are electrically connected through the second connection hole; the right end of the intermediate lateral voltage line located in the first area opposite to its left end is connected to the right end of the middle lateral voltage line in the fourth area.
  • the fourth connecting wire is disconnected through the fourth break.
  • the display substrate includes a plurality of the first connection lines, a plurality of the second connection lines, a plurality of the third connection lines and a plurality of the The fourth connection line; the plurality of first connection lines and the plurality of second connection lines are electrically connected through a plurality of the first connection holes, and the plurality of third connection lines are electrically connected to the plurality of third connection lines.
  • Four connection lines are electrically connected through a plurality of second connection holes respectively; the planar pattern formed by the plurality of first connection holes is a fifth line segment, and the fifth line segment is the first area and the second area.
  • the planar pattern formed by the plurality of second connection holes is a sixth line segment, and the sixth line segment is the boundary between the first area and the fourth area;
  • the lower display area also includes a fifth area , the structure of the fifth region and the structure of the third region are substantially axially symmetrical with respect to the second longitudinal voltage line, and a plurality of first via holes in the fifth region are symmetrical to the first via holes.
  • the planar pattern of the fifth via hole is a seventh line segment; the connecting line segment, the fifth line segment, the sixth line segment and the seventh line segment are sequentially connected to the formed planar pattern and each of the plurality of sub-fold lines.
  • the flat patterns of the sliver fold lines are the same.
  • the planar shape of the first region is a first triangle
  • the planar shape of the second region is a second triangle
  • the planar shape of the first triangle is a second triangle.
  • the first side transversely close to the left edge at least partially coincides with the first side of the second triangle transversely away from the left edge of the display area; two lower vertices of the first triangle are located at On the lower edge of the display area, the left vertex of the two lower vertices of the first triangle close to the left edge is the left endpoint of the first sub-region;
  • the first triangle is an isosceles triangle, so
  • the second longitudinal voltage line is basically the mid-perpendicular to the base of the isosceles triangle.
  • the frame area includes a left frame area extending along the left edge, and a plurality of auxiliary connection lines extending along the lateral direction are provided in the left frame area. , the plurality of auxiliary connection lines and the edge longitudinal voltage lines are arranged in the same layer; the display area includes a pixel array, the pixel array includes a plurality of pixel rows extending along the transverse direction and a plurality of pixel rows extending along the longitudinal direction.
  • the plurality of pixel columns include an edge pixel column closest to the left edge, and the plurality of edge longitudinal voltage lines include outer edge longitudinal voltage lines passing through the edge pixel column; the plurality of auxiliary The left end of each connecting line in the lateral direction is electrically connected to the left lead, so The right end of each of the plurality of auxiliary connection lines opposite to its left end in the transverse direction is electrically connected to the outer edge longitudinal voltage line, and is connected to the corresponding left end of one of the first transverse voltage lines through the second edge. holes for electrical connections.
  • the right display area includes a second edge display area extending along the right edge and a second edge display area located in the second edge display area close to the left display area.
  • a second middle display area on one side; the second edge display area and the first edge display area are symmetrical with respect to the symmetry axis extending along the longitudinal direction, and the second middle display area is symmetrical with the first middle display area.
  • the zone is axially symmetrical with respect to the second longitudinal voltage line.
  • the display substrate further includes: a second power supply voltage line configured to provide a second power supply voltage different from the first power supply voltage to the sub-pixel;
  • the vertical voltage lines are arranged on the same layer as the data lines in the upper display area, and the horizontal voltage lines and the second power supply voltage lines are arranged on the same layer.
  • At least one embodiment of the present disclosure also provides a display device, including any display substrate provided by the embodiments of the present disclosure.
  • FIG. 1 is an overall plan view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 2 is a partial enlarged schematic diagram including the lower display area and part of the upper display area in FIG. 1 .
  • FIG. 3A is a partially enlarged schematic diagram of the region R1 in FIG. 2 .
  • FIGS. 3B-3D are schematic views of part of the film layer in region R3 in FIG. 2 .
  • FIG. 4 is a partial enlarged schematic diagram including the area R2 and the area R3 in FIG. 1 .
  • FIG. 5A is a partially enlarged schematic diagram of region R2 in FIG. 4 .
  • FIGS. 5B-5D are schematic diagrams of part of the film layer in region R2 in FIG. 4 .
  • FIG. 6A is a partially enlarged schematic diagram of region R3 in FIG. 4 .
  • FIGS. 6B-6D are schematic diagrams of part of the film layer in region R3 in FIG. 3 .
  • FIG. 7A is a partially enlarged schematic diagram of region R4 in FIG. 3 .
  • FIGS. 7B-7D are schematic views of part of the film layer in region R4 in FIG. 3 .
  • FIG. 8A is a partially enlarged schematic diagram of the region R5 in FIG. 3 .
  • 8B-8C are schematic diagrams of part of the film layer in region R5 in FIG. 3 .
  • FIG. 9 is a partially enlarged schematic diagram of region R6 in FIG. 3 .
  • FIG. 10 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure.
  • 11A-11H include schematic diagrams of different film layers in a pixel circuit.
  • Figure 11I is a schematic diagram of the film layer stacking shown in Figures 11A-11F.
  • FIG. 12 is a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • Characteristics such as “parallel”, “perpendicular” and “identical” used in this disclosure include “parallel”, “perpendicular”, “identical” and other characteristics in the strict sense, as well as “substantially parallel”, “substantially perpendicular”, “basically” "This is the same,” etc., includes certain errors, taking into account the errors associated with the measurement and measurement of the specific quantity (e.g., limitations of the measurement system), and means an acceptable deviation from a specific value as determined by one of ordinary skill in the art. Within a range. For example, “substantially” can mean within one or more standard deviations, or within 10% or 5% of the stated value.
  • the component can be one or more, or it can be understood as at least one. "At least one” means one or more, and “plurality” means at least two.
  • “Same layer” in the embodiment of the present disclosure refers to the relationship between multiple film layers formed of the same material after going through the same step (such as a one-step patterning process). "Same layer” here does not always mean that the thickness of multiple film layers is the same or that the height of the multiple film layers in the cross-sectional view is the same.
  • Words indicating directions such as “vertical”, “horizontal”, “upper”, “lower”, “left” and “right” used in this disclosure are only used to express relative positional relationships.
  • the relative positional relationship may also change accordingly, and is not limited to the directions shown in the drawings of the description.
  • the "upper edge”, “lower edge”, “left edge” and “right edge” are not limited to the upper, lower, left and right as shown in the drawings, as long as they satisfy the relative positional relationship defined therebetween.
  • the “left display area” and “right display area” are not limited to the left and right in the drawings of this application, as long as they satisfy the relative positional relationship defined therebetween.
  • the “upper display area” and the “lower display area” are not limited to the left and right in the drawings of this application, as long as they satisfy the relative positional relationship defined therebetween.
  • At least one embodiment of the present disclosure provides a display substrate, which includes: a display area, a non-display area, a first power supply voltage lead, and a first power voltage line.
  • the display area is provided with sub-pixels and has a lower edge extending in a transverse direction and a left edge extending in a longitudinal direction.
  • the transverse direction intersects the longitudinal direction.
  • a dividing line extending along the longitudinal direction divides the display area into a left display area. and a right display area.
  • the left display area includes a first edge display area extending along the left edge and a first middle display area located in the first edge display area and close to the right display area;
  • the non-display area includes a frame area surrounding at least part of the display area;
  • a first power supply voltage lead is configured to provide a first power supply voltage and is located within the frame area;
  • the first power supply voltage lead includes a first power supply voltage lead along the lower edge corresponding to a first a lower lead that partially extends along the edge display area but does not extend along the portion of the lower edge corresponding to the first middle display area;
  • the first power supply voltage line includes an edge voltage line located along the edge of the first edge display area and A middle voltage line located in the first middle display area; the edge voltage line is directly connected to the lower lead
  • the first power supply voltage is provided to the sub-pixels located in the first edge display area, and the intermediate voltage line is spaced apart from the lower lead.
  • At least one embodiment of the present disclosure also provides a display device, including any display substrate provided by the embodiments of the present disclosure.
  • FIG. 1 is an overall plan view of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a partially enlarged schematic view including the lower display area and part of the upper display area in FIG. 1
  • a display substrate 10 provided by at least one embodiment of the present disclosure includes: a display area 1 , a frame area 2 , a first power supply voltage lead 4 and a first power supply voltage line vss.
  • the display area 1 is provided with sub-pixels and has a lower edge 1a extending along the horizontal direction The vertical direction does not have to be vertical.
  • the display area 1 includes a left display area 11 and a right display area 12 arranged in the transverse direction X.
  • the dividing line ML extending along the longitudinal direction Y divides the display area 1 into a left display area 11 and a right display area 12.
  • the dividing line ML is the middle perpendicular line of the lower edge 1a, so that the left display area 11 and the right display area 12 are symmetrical.
  • the display effect of the entire display substrate 10 is uniform, but it is not limited to the case where the dividing line ML is the middle perpendicular line of the lower edge 1a.
  • the left display area 11 includes a first edge display area 11P extending along the left edge 1b and a first middle display area 11M located in the first edge display area 11P and close to the right display area 12;
  • the frame area 2 is a non-display area surrounding at least part of Display area 1.
  • the display substrate 10 may further include a soldering pad 3 located on a side of the lower edge 1a away from the display area 1; the first power supply voltage lead 4 is connected to the soldering pad 3 to be configured to provide the first power supply voltage VSS, and Located in the frame area 2; the first power supply voltage lead 4 includes a lower lead 41 extending along the portion of the lower edge 1a corresponding to the first edge display area 11P, but not along the portion of the lower edge 1a corresponding to the first middle display area 11M. Extension; the first power supply voltage line vss includes an edge voltage line LP located in the first edge display area 11P and a middle voltage line LM located in the first middle display area 11M.
  • the edge voltage line LP contacts the lower lead 41 to electrically connect the The sub-pixels of the first edge display area 11P provide the first power supply voltage VSS, and the middle voltage line LM is spaced apart from the lower lead 41 , that is, the middle voltage line LM is not directly connected to the lower lead 4 from the pad 3 .
  • the edge voltage line is in contact with the lower lead 41 and is electrically connected to provide a VSS signal to the sub-pixels of the first edge display area 11P, and the middle voltage line LM is spaced apart from the lower lead 41 That is, there is no contact, but a VSS signal is provided to the first middle display area 11M by being connected to the left lead 42 or the upper lead 43, or other first power supply voltage line vss, That is, the first power supply voltage lead 4 drawn from the pad 3 on the side of the lower edge 1a away from the display area is not directly connected to the first middle display area 11M, that is, the middle voltage line LM does not pass through the frame area.
  • the edge voltage line LP and the lower lead 41 are directly connected, that is, the edge voltage line LP and the lower lead 41 are in contact with each other, and there is no other structure between the edge voltage line LP and the lower lead 41 as a medium for connecting the two; for example , the edge voltage line LP and the lower lead 41 are arranged on the same layer and form a continuous integrated structure.
  • the edge voltage line LP and the lower lead 41 are made of the same material and can be formed through the same patterning process. In this way, it can Simplify the structure and manufacturing process of the display substrate.
  • the edge voltage line LP and the lower lead 41 can be arranged in different layers, and they are in contact with each other through via holes.
  • the term "direct connection” means that two structures connected to each other (for example, the edge voltage line LP and the lower lead 41 are directly connected, etc.) are in contact with each other, and there is no connection between the two structures connected to each other. Any other structure acts as a mediator between the two.
  • two structures directly connected to each other can be continuous one-piece structures.
  • the materials of the two structures directly connected to each other are the same, and the two structures can be formed through the same patterning process to simplify the manufacturing process of the display substrate;
  • the materials of the two structures directly connected to each other can also be different.
  • the two structures directly connected to each other are both conductive signal lines. Materials that match the functions of the two structures can be used to meet different needs. Performance requirements such as different conductivities.
  • the first power supply voltage line vss includes a longitudinal voltage line YL extending along the longitudinal direction Y and a transverse voltage line XL extending along the transverse direction X, and the longitudinal voltage line YL and the transverse voltage line XL are arranged in different layers;
  • the vertical voltage line YL includes an edge longitudinal voltage line YLP located in the first edge display area 11P
  • the lateral voltage line XL includes an edge lateral voltage line XLP located in the first edge display area 11P and intersecting the edge longitudinal voltage line YLP.
  • the edge longitudinal voltage line YLP and edge lateral voltage line Line XLP is directly connected to left lead 42.
  • the edge longitudinal voltage line YLP is at An edge display area 11P runs through the entire display area in the longitudinal direction to provide the first power supply voltage VSS to the sub-pixels of the entire first edge display area 11P.
  • the edge vertical voltage line YLP is directly connected to the lower lead 41 close to it, which can save space and help reduce the frame area outside the lower edge 1a.
  • the first power supply voltage pin 4a No. 1 is provided on the pad 3, the lower lead 41 is electrically connected to the first power supply voltage pin 4a, and the first power supply voltage pin 4a is located close to the pad 3 in the transverse direction X. Therefore, the first power supply voltage pin 4a, the lower lead 41 and the edge vertical voltage line YLP of the first edge display area 11P are directly connected in sequence, which can effectively reduce the running of the lower frame. line, reducing the frame area outside the lower edge 1a.
  • the first power supply voltage pin 4b No. 2 can also be provided on the pad 3, and the first power supply voltage pin 4b No. 2 is close to the right edge 1d, that is, located on the pad 3. Close to the second end of the lower second edge display area 12P in the transverse direction
  • the axis of symmetry is axially symmetrical, similar to the first power supply voltage pin 4a No. 1 and the first power supply voltage line vss in the first edge display area 11P, and the first power supply voltage pin 4b No. 2 and the first power supply voltage line vss in the second edge display area 12P.
  • the edge vertical voltage lines are directly connected to provide the first power supply voltage VSS to the sub-pixels of the second edge display area 12P.
  • FIG. 6A is a partially enlarged schematic diagram of the region R3 in FIG. 4
  • FIGS. 6B-6D are schematic diagrams of some film layers of the region R3 in FIG. 3 .
  • the lower end of the edge vertical voltage line YLP close to the lower lead 41 is directly connected to the lower lead 41 .
  • the upper end of the edge vertical voltage line YLP opposite to its lower end is directly connected to the upper lead 43 to more reliably provide the first power supply voltage VSS through the edge vertical voltage line YLP.
  • the display substrate 10 also includes a data line data
  • the sub-pixel includes: a driving transistor T3, a light-emitting element and a data transistor T4.
  • the driving transistor T3 is configured as controlling the size of the driving current flowing through the light-emitting element, the light-emitting element being configured to receive the driving current and being driven by the driving current to emit light, and the data transistor T4 being configured to write the data signal DATA into the gate of the driving transistor T3 in response to the first control signal
  • the data line data is configured to transmit the data signal DATA to the sub-pixel; the display area 1 includes a lower display area 14 and an upper display area 13.
  • the lower display area 14 is close to the lower edge 1a, and the upper display area 13 is located vertically between the lower display area 14 and the lower display area 14.
  • the side away from the lower edge 1a; the lower display area 14 includes a first area 1 and a second area 2.
  • a region 1 includes a first sub-region A close to the left edge 1b and a second sub-region B far away from the left edge 1b in the transverse direction X.
  • the data line data passing through the first sub-region A and the second region 2 is included in the first The first connection line DL1 extending along the longitudinal direction Y in the sub-region A, the second connection line DL2 extending along the transverse direction X in the second area 2, and the fifth connection line DL5 extending along the longitudinal direction Y in the upper display area 13,
  • the fifth connection line DL5 is arranged on the same layer as the first connection line DL1;
  • the first connection line DL1 is arranged on the same layer as the vertical voltage line YL
  • the second connection line DL2 is arranged on the same layer as the horizontal voltage line XL, and the same data line data
  • a connection line DL1 and a second connection line DL2 are electrically connected through the first connection hole VC1, and a fifth connection line DL5 of the same data line data is electrically connected to the third connection hole VC3 of the second connection line DL2.
  • a transmission channel for the data signal DATA is formed as indicated by the three arrows in Figure 1.
  • the plurality of data lines data are respectively connected to the pad 3 through a plurality of data signal leads CL, for example, are electrically connected to the integrated circuit IC in the pad 3 to provide the data signal DATA to the data line data.
  • the first sub-region A is located in the first middle display area 11M, and the second area 2 is at least partially located in the first middle display area 11M; the first sub-region A has a left edge 1b closest to the display area 1 in the transverse direction X.
  • the left end point PO of , the straight line extending along the longitudinal direction Y and passing through the left end point PO is the dividing line IL between the first edge display area 11P and the first middle display area 11M. That is, the area between the straight line and the left edge 1b is the first edge display area 11P.
  • the first sub-area A is located in the first middle display area 11M.
  • the dividing line IL passes through the second area 2 and divides the second area 2 into a first sub-area A close to the left edge 1b of the display area 1 and a left edge 1b away from the display area 1
  • the second sub-area B is located in the first edge display area 11P
  • the second sub-area B is located in the first middle display area 11M.
  • FIG. 3A is a partially enlarged schematic diagram of the region R1 in FIG. 2
  • FIGS. 3B-3D are schematic diagrams of some film layers of the region R3 in FIG. 2 .
  • the lower display area 14 also includes a third area 3, the third area 3 is located in the first edge display area 11P, and in the transverse direction X Located on the side of the second area 2 away from the first area 1;
  • the edge lateral voltage line XLP includes the lower edge lateral voltage line XLP1 located in the third area 3, and the edge longitudinal voltage line YLP passes through the third area 3 and is connected to the lower edge
  • the horizontal voltage line XLP1 intersects at the first intersection point P1.
  • the left end of the lower edge horizontal voltage line XLP1 is electrically connected to the left lead 42.
  • the lower edge horizontal voltage line XLP1 is electrically connected to the left lead 42.
  • the right end of the pressure line XLP1 opposite to its left end is disconnected from the second connection line DL2 in the second area 2 through the first break OP1.
  • the first fracture OP1 can be referred to Figures 1-2.
  • Figures 3A-3B are partial schematic diagrams, which only show a limited number of pixels. Therefore, the first fracture OP1 is not shown.
  • the longitudinal voltage line YL includes a plurality of edge longitudinal voltage lines YLP and a plurality of edge lateral voltage lines XLP.
  • the plurality of edge longitudinal voltage lines YLP and the plurality of edge lateral voltage lines XLP are interwoven into a grid, and the grid includes a plurality of first intersection points. P1; At each of a portion of the first intersection points P1, an edge longitudinal voltage line YLP is electrically connected to a lower edge lateral voltage line XLP1 through the first via hole V1, so that in the plurality of first intersection points P1 There are multiple first vias V1 at an intersection point P1.
  • the plurality of edge vertical voltage lines YLP and the plurality of lower edge lateral voltage lines XLP1 are electrically connected in the third area 3 to form a mesh structure, which can reduce the first power supply voltage line vss and transmit the first power voltage VSS in the third area 3
  • the resistance is low, and the voltage drop on the mesh-shaped first power voltage line vss composed of the edge vertical voltage line YLP and the lower edge lateral voltage line XLP1 in the third region 3 is low.
  • first insulating layer between the film layer shown in Figure 4B and the film layer shown in Figure 4C.
  • the first via hole V1 penetrates the first insulating layer, and the first connection structure C1 passes through the first via hole V1.
  • the edge longitudinal voltage line YLP and the lower edge transverse voltage line XLP1 are electrically connected.
  • first power voltage lines vss (vertical voltage lines YL) extending along the longitudinal direction Y in the display area 1 are arranged on the same layer as the data lines data in the upper display area 13, and the horizontal voltage lines located in the display area 1
  • the XL second power supply voltage lines are arranged on the same layer; all the first power supply voltage lines vss (lateral voltage lines XL) extending along the X direction are located on the side of the vertical voltage line YL close to the substrate.
  • the vertical voltage line YL is located in the underlying sixth conductive layer 580, and the lateral voltage line XL is located in the underlying fifth conductive layer 570.
  • 3A-3B show three first via holes V1 as an example, but the number of the first via holes V1 is not limited.
  • the plurality of edge vertical voltage lines YLP are electrically connected to the plurality of edge lateral voltage lines XLP through a plurality of first via holes V1, and the planar pattern formed by the positions of the plurality of first via holes V1 is located at the The connecting line segment SC in the third area 3 (the dotted line in the third area 3 in Figure 1 represents the connecting line segment SC), the extending direction of the connecting line segment SC intersects both the horizontal X and the longitudinal Y.
  • the "planar pattern composed of the positions of the first via holes V1" refers to the overall pattern formed by the positions of the plurality of first via holes V1 arranged.
  • the connecting line segment SC is a straight segment to be consistent with the shape of the W-shaped polyline below.
  • the connecting line segment SC may also be a curved segment.
  • the third area 3 is a corner area defined by the first side SL1 , the left edge 1b and the lower edge 1a of the second area 2 which are close to the left edge 1b in the transverse direction X.
  • the third area 3 is the corner area, which can float the first break OP1 in the corner area due to the design of the data line data passing through the second area 2 and the first area 1 (Fanout in pixel, FIP technology)
  • the first power supply voltage signal is connected to prevent signal interference caused by floating wires. For example, floating wires tend to accumulate static electricity and cause electrostatic interference.
  • the plan pattern of the plurality of third connection holes VC3 used to respectively connect the fifth connection line DL5 and the second connection line DL2 of the plurality of data lines data is a line segment, such as a straight segment, and the line segment serves as the first side SL1 of the second area 2 , also serves as the dividing line between the third area 3 and the second area 2.
  • the frame area 2 includes a frame corner area 20 surrounding the corner area 3.
  • a grid-shaped auxiliary first power supply voltage line vss is provided in the frame corner area 20. In this way, the first edge can be greatly reduced. The voltage drop of the first power low-voltage line in the display area 11P.
  • FIG. 4 is a partially enlarged schematic diagram including the area R2 and the area R3 in FIG. 1 , and the area R2 includes the frame corner area 20 ;
  • FIG. 5A is a partially enlarged schematic diagram of the area R2 in FIG. 4 , and
  • FIGS. 5B-5D are the areas in FIG. 4 Schematic diagram of part of the film layer of R2. 4 and 5A-5D, the grid-shaped auxiliary first power supply voltage line vss includes: a plurality of vertical auxiliary voltage lines YAL and a plurality of horizontal auxiliary voltage lines XAL.
  • the plurality of longitudinal auxiliary voltage lines YAL extend along the longitudinal direction Y and are arranged on the same layer as the longitudinal voltage lines YL, wherein the first end of each of the plurality of longitudinal auxiliary voltage lines YAL in the longitudinal direction Y is connected to the first power supply voltage lead 4 ( For example, the lower lead 41 or the corner lead connecting the lower lead 41 and the left lead 42) is directly connected, and the second end of each of the plurality of longitudinal auxiliary voltage lines YAL in the longitudinal direction YAL opposite to its first end is connected through the corner area 3
  • An edge longitudinal voltage line YLP is electrically connected, for example, directly connected; a plurality of transverse auxiliary voltage lines XAL extend along the transverse direction One end of the strip in the transverse direction line) are directly connected, and the second end of each of the plurality of transverse auxiliary voltage lines XAL in the transverse direction X opposite to its first end is electrically connected to an edge longitudinal voltage line YLP.
  • multiple vertical auxiliary voltage lines YAL and multiple horizontal auxiliary voltage lines are arranged on the same layer. For example, they are arranged on the same layer as the vertical voltage line YL.
  • the vertical auxiliary voltage lines YAL and the horizontal auxiliary voltage lines can be formed simultaneously through the same patterning process. line and the vertical voltage line YL to simplify the structure and manufacturing process of the display substrate.
  • the display area 1 includes a pixel array
  • the pixel array includes a plurality of pixel rows extending along the transverse direction X and a plurality of pixel columns extending along the longitudinal direction Y;
  • multiple horizontal auxiliary voltage lines XAL correspond to multiple edge pixel rows PXR one-to-one, each edge pixel row PXR in the multiple edge pixel rows PXR includes the edge sub-pixel P closest to the left edge 1b, multiple
  • the edge vertical voltage lines YLP include an edge-most vertical voltage line YLP0 that passes through the edge sub-pixel P of each edge pixel row PXR; the second end of each of the plurality of horizontal auxiliary voltage lines XAL passes through the corresponding edge pixel.
  • the edgemost longitudinal voltage line YLP0 of the row PXR is electrically connected, for example, directly connected; and the second end of each of the plurality of horizontal auxiliary voltage lines XAL passes through the first edge via VP1 and passes through the corresponding edge pixel row PXR.
  • the edge transverse voltage line XLP is electrically connected.
  • the second end of the lateral auxiliary voltage line XAL is electrically connected to the edge lateral voltage line XLP of the corresponding edge pixel row PXR through the first edge connection structure CP1 passing through the first insulating layer.
  • 5A-5D show a horizontal auxiliary voltage line XAL due to its corresponding connection relationship with an edge pixel row PXR closest to the lower edge 1a.
  • connection situation of other edge pixel rows PXR is the same, except that in this embodiment, the lengths of the lateral auxiliary voltage lines XAL corresponding to the respective edge pixel rows PXR are different. In other embodiments, if necessary, the length of the lateral auxiliary voltage line XAL of each edge pixel row PXR can also be designed to adapt to the pixel arrangement of the display substrate.
  • the second power supply voltage lead 4b-1 is located in the lower frame area surrounding the lower edge 1a, is electrically connected to the second power supply voltage pin 4b, and passes through the first power supply voltage pin 4b of the plurality of pixel columns.
  • the two power supply voltage lines are electrically connected to the second power supply voltage lead 4b-1, thereby providing the second power supply voltage VDD to the pixels of the plurality of pixel columns.
  • the horizontal voltage line XL also includes a plurality of first horizontal voltage lines XLU.
  • the plurality of first horizontal voltage lines XLU are arranged in the longitudinal direction Y and are located in the upper display area 13;
  • the left end is electrically connected to the left lead 42, and the edge horizontal voltage line XLP also includes a
  • the upper edge lateral voltage line XLP2 of the display area 13 is shown as a part of a first lateral voltage line XLU.
  • the longitudinal voltage line YL also includes a plurality of intermediate longitudinal voltage lines YLM.
  • a plurality of first transverse voltage lines XLU are arranged in the transverse direction X and pass through part of the first middle display area 11M and the upper display area 13 along the longitudinal direction Y;
  • the middle vertical voltage line YLM, the plurality of edge vertical voltage lines YLP and the plurality of first transverse voltage lines XLU are interwoven into a grid to reduce the resistance of the first power supply voltage line vss and reduce the voltage drop on the first power supply voltage line vss. .
  • the plurality of edge longitudinal voltage lines YLP and the plurality of first lateral voltage lines XLU intersect at a plurality of auxiliary intersection points AP in the first edge display area 11P, at each position of a part of the auxiliary intersection points AP among the plurality of auxiliary intersection points AP,
  • An edge vertical voltage line YLP is electrically connected to a first lateral voltage line XLU through an auxiliary via AV in the first edge display area 11P, and a plurality of edge vertical voltage lines YLP is connected to a plurality of first lateral voltage lines through a plurality of auxiliary vias AV.
  • the voltage line The hole pattern is connected to one end of the auxiliary line segment SA away from the left edge 1b.
  • the auxiliary line segment SA is different from the third line segment S3 of the W-shaped fold line below. In this way, the resistance of the first power supply voltage line vss in the first edge display area 11P can be further effectively reduced, and the voltage drop of the first power supply voltage line vss in the first edge display area 11P can be reduced.
  • an edge vertical voltage line YLP is electrically connected to a first lateral voltage line XLU through the auxiliary via AV in the first edge display area 11P.
  • the structure of the area R1 shown in FIGS. 3A-3D The same, please refer to Figures 3A-3D and will not be repeated here.
  • the extending direction of the auxiliary line segment SA is the same as the extending direction of the connecting line segment SC.
  • the lengths of the auxiliary line segment SA and the connecting line segment SC are also the same to maintain a uniform arrangement of the connection points connected through vias. properties to prevent mura defects in the display substrate.
  • the display substrate 10 includes a plurality of auxiliary line segments SA, the connecting line segments SC and the plurality of auxiliary line segments SA are arranged at intervals along the longitudinal direction Y.
  • the display area 1 also includes an upper edge 1 c opposite to the lower edge 1 a.
  • the first power supply voltage lead 4 also includes an upper lead 43 extending along the upper edge 1 c.
  • the upper lead 43 is electrically connected to the left lead 42 ;
  • the upper end of the edge vertical voltage line YLP is connected to the upper lead 43, and the lower end of the edge vertical voltage line YLP opposite to its upper end is directly connected to the lower lead 41.
  • Figure 7A is a partially enlarged schematic diagram of the area R4 in Figure 3, and Figures 7B-7D are the areas in Figure 3.
  • the vertical voltage line YL includes a middle vertical voltage line YLM located in the first middle display area 11M
  • the middle vertical voltage line YLM includes a first vertical voltage line YLM1 and a second vertical voltage line YML2.
  • the first longitudinal voltage line YLM1 sequentially passes through the upper display area 13 and at least part of the second area 2 along the longitudinal direction Y.
  • the upper end of the first vertical voltage line YLM1 is electrically connected to the upper lead 43, and the lower end of the first vertical voltage line YLM1 opposite to its upper end is connected to the first connection line DL1 in the first sub-region A.
  • the second fracture OP2 is disconnected, and the parts shown in FIGS. 7A and 7D illustrate the second two second fractures OP2 located in the area 2.
  • the second longitudinal voltage line YML2 passes through the upper display area 13 and the first area 1 in sequence along the longitudinal direction Y; the lateral voltage line XL includes an intermediate lateral voltage line XLM located in the first area 1, and the intermediate lateral voltage line
  • the second connection line DL2 is disconnected through the third fracture OP3.
  • the second vertical voltage line YML2 intersects with the middle horizontal voltage line XLM at the second intersection point P2.
  • the second vertical voltage line YML2 is electrically connected to the middle horizontal voltage line XLM through the second via V2 at the second intersection point P2.
  • the second longitudinal voltage line YML2 is electrically connected to the plurality of intermediate lateral voltage lines XLM arranged in the longitudinal direction through a plurality of second via holes V2 arranged in the longitudinal direction Y, respectively.
  • the part shown in Figures 7A-7D has three second via holes V2, but it does not mean that the display substrate only has three second via holes V2; for example, each of the multiple intermediate lateral voltage lines XLM passes through the second via hole V2 and the second vertical voltage line YML2 to transmit the first power supply voltage VSS to each pixel in the first area 1.
  • the second longitudinal voltage line YML2 and the middle lateral voltage line XLM are connected through the second connection structure C2 passing through the second via hole V2.
  • a plurality of first horizontal voltage lines XLU and a second longitudinal voltage line YML2 located in the upper display area 13 intersect at a plurality of third intersection points P3, and at least one of the plurality of third intersection points P3 At each position of a part of the third intersection point P3, a first horizontal voltage line XLU is electrically connected to the second vertical voltage line YML2 through the third via hole V3.
  • the second vertical voltage line YLM2 is electrically connected to the first lateral voltage line XLU through the third via V3, and the first lateral voltage line XLU is electrically connected to the first power supply voltage lead 4 (left lead 42). Therefore, the voltage line YLM2 is electrically connected to the first lateral voltage line XLU through the first lateral voltage line XLU.
  • the second vertical voltage line YML2 provides the first power supply voltage VSS
  • the second vertical voltage line YML2 provides the first power supply voltage VSS to the middle horizontal voltage line XLM, thereby providing the first power supply voltage VSS to the pixels in the first area 1.
  • the lower lead 41 is only directly connected to the edge vertical voltage line YLP located in the first edge display area 11P, but not to the first middle display area 11M and the second middle display area 12M. Inside the middle longitudinal voltage line YLM is connected.
  • the second via hole V2 and the third via hole V3 both penetrate the first insulating layer.
  • the first power supply voltage lead 4 and the longitudinal voltage line YLP are arranged on the same layer; for example, the first power supply voltage lead 4 and the longitudinal voltage line YLP are made of the same material and are a continuous one-piece structure. It can be formed through the same patterning process, which simplifies the structure and manufacturing process of the display substrate.
  • the display area 1 also includes a right edge 1d opposite to the left edge 1b, and the first power lead also includes a right lead 44 extending along the right edge 1d, and the right lead 44 is electrically connected to the upper lead 43;
  • Each of the first transverse voltage lines XLU runs through the upper display area 13 along the transverse direction
  • the left and right ends of the horizontal voltage line XLU transmit the first power supply voltage VSS to the display area 1, which increases the speed of signal transmission and is beneficial to improving the display quality of the display substrate.
  • the plurality of middle longitudinal voltage lines YLM and the plurality of first lateral voltage lines XLU in the upper display area 13 intersect each other at a plurality of fourth intersection points P4 in the upper display area 13 to be connected in a grid shape, which is conducive to reducing power consumption.
  • a middle longitudinal voltage line YLM is electrically connected to a first horizontal voltage line XLU through the fourth via hole V4, so that the middle edge of the upper display area 13
  • a plurality of first transverse voltage lines XLU extending in the transverse direction X and the middle longitudinal voltage line YLM extending in the longitudinal direction Y are connected in a grid shape to reduce the resistance of this part of the first power supply voltage line vss located in the upper display area 13. Reduce the voltage drop on the first supply voltage line vss.
  • the planar pattern formed by the positions of the plurality of fourth via holes V4 is a polyline (dashed line), which is connected with the boundary SL1 (dashed line) between the second area 2 and the third area 3, and the fourth area between the second area 2 and the first area 1.
  • the boundary of area 4 is the fifth line segment S5 (dashed line), the boundary between the first area 1 and the fourth area 4 is the sixth line segment S6 (dashed line), and the boundary SL3 (dashed line) between the fourth area 4 and the fifth area 5 is composed of
  • the shape of the W-shaped fold lines is consistent (at least they are all fold lines), which is beneficial to maintaining the uniformity of the arrangement trend of the connection points connected through via holes in the lower display area 14 and the connection points connected through via holes in the upper display area 13 , to prevent the display substrate from producing mura display defects.
  • the polyline includes a plurality of sub-polylines extending from the left edge 1b to the right edge 1d.
  • Each of the plurality of sub-polylines includes a plurality of polyline segments connected end to end; the plurality of polyline segments include segments along the first direction.
  • the first end of the first line segment S1 coincides with the first end of the second line segment S2, for example, the first end of the first line segment S1 and the first end of the second line segment S2 intersect at the upper vertex TP; multiple sub-polylines Multiple vertices are located on the second vertical voltage line YML2, and the fourth via holes V4 at the vertex positions are all second via holes V2.
  • each of the multiple sub-polylines is W-shaped.
  • a W-shaped dotted line in Figure 1 is a sub-polyline.
  • the W-shaped sub-polyline includes the first line segment S1 (dashed line) and the second line segment S2 (dashed line), the third line segment S3 (dashed line) and the fourth line segment S4 (dashed line).
  • the first line segment S1 and the second line segment S2 is located between the third line segment S3 and the fourth line segment S4.
  • the third line segment S3 is connected to the first line segment S1
  • the fourth line segment S4 is connected to the second line segment S2.
  • the first line segment S1 and the fourth line segment S4 are basically parallel.
  • the second line segment S2 and the third line segment S3 are substantially parallel.
  • the vertical voltage line YLM is connected to the first lateral voltage line XLU at more intersection points through the fourth via hole V4.
  • the auxiliary line segment SA is located between the third line segments S3 of two adjacent sub-polylines.
  • connection line segment SC, the auxiliary line segment SA and the third line segment S3 are substantially parallel to each other to maintain the uniformity of the arrangement trend of the connection points connected through via holes at various positions in the first edge display area 11P to prevent display
  • the substrate produces mura display failure.
  • the second longitudinal voltage line YML2 divides the first region 1 into a first sub-region A and a second sub-region B.
  • the structure of the first sub-region A and the structure of the second sub-region B are relative to each other.
  • the second longitudinal voltage line YML2 is basically axially symmetrical; the lower display area 14 includes a fourth area 4, and the structure of the fourth area 4 and the structure of the second area 2 are basically axially symmetrical with respect to the second longitudinal voltage line YML2; passing through the fourth area 4
  • the data lines data of the first area 1 and the fourth area 4 include the third connection line DL3 extending along the longitudinal direction Y in the second sub-area B, the fourth connection line DL4 extending along the lateral direction X in the fourth area 4, and the
  • the sixth connection line DL6 extending along the longitudinal direction Y in the upper display area 13 is arranged on the same layer as the first connection line DL1; the third connection line DL3 is arranged on the same layer as the vertical voltage line YL, and the fourth connection line DL4 Arranged on the same layer as the lateral voltage line XL, the third connection line DL3 and the fourth connection line DL4 of the same data line data are electrically connected through the second connection hole VC
  • the display substrate 10 includes a plurality of first connection lines DL1, a plurality of second connection lines DL2, a plurality of third connection lines DL3, and a plurality of fourth connection lines DL4; the plurality of first connection lines DL1 and a plurality of second connection lines DL4.
  • connection lines DL2 are electrically connected through a plurality of first connection holes VC1 respectively, the plurality of third connection lines DL3 and the plurality of fourth connection lines DL4 are respectively electrically connected through a plurality of second connection holes VC2; the plurality of first connection holes VC1 constitute The planar pattern is the fifth line segment S5, and the fifth line segment S5 is the boundary between the first area 1 and the second area 2; the planar pattern formed by the plurality of second connection holes VC2 is the sixth line segment S6, and the sixth line segment S6 is the first The boundary between area 1 and the fourth area 4; the lower display area 14 also includes a fifth area 5.
  • the structure of the fifth area 5 and the structure of the third area 3 are basically axially symmetrical with respect to the second longitudinal voltage line YML2.
  • the fifth area 5 The planar pattern of the plurality of fifth via holes V5 in 5 that is symmetrical with the plurality of first via holes V1 is the seventh line segment S7.
  • the connecting line segment SC dashed line
  • the fifth line segment S5 dashed line
  • the sixth line segment S6 dashex line
  • the seventh line segment S7 sequentially connect the formed plane pattern and each of the plurality of sub-polylines.
  • planar patterns of the sub-fold lines are the same to maintain the uniformity of the arrangement trend of the connection points connected through via holes in the lower display area 14 and the connection points connected through via holes in the upper display area 13 , to prevent the display substrate from producing mura display defects.
  • the dividing line between the second area 2 and the third area 3 is also the first side SL1 of the second area 2, and the angle between the first line segment S1 and the transverse direction X is smaller than the angle between the first side SL1 and the transverse direction X. angle.
  • the planar shape of the first area 1 is a first triangle
  • the planar shape of the second area 2 is a second triangle
  • the second area of the first triangle close to the left edge 1b in the transverse direction
  • the side i.e., the second connecting line SL2
  • the first side i.e., the second connecting line SL2
  • the two lower vertices of the first triangle DP1 and DP2 are located on the lower edge 1a of the display area 1.
  • the left vertex of the two lower vertices of the first triangle close to the left edge 1b is the left endpoint PO of the first sub-area A; the first triangle is an isosceles triangle, and the second The longitudinal voltage line YML2 is basically the perpendicular to the base of the isosceles triangle.
  • Such an arrangement can make the data lines and the first power supply voltage lines of the entire display area 1 uniformly arranged, thereby preventing mura defects on the display substrate.
  • FIG. 8A is a partially enlarged schematic diagram of the region R5 in FIG. 3
  • FIGS. 8B-8C are schematic diagrams of some film layers of the region R5 in FIG. 3
  • the frame area 2 includes a left frame area 2a extending along the left edge 1b, and a plurality of auxiliary connection lines ACL extending along the transverse direction X are provided in the left frame area 2.
  • the plurality of auxiliary connection lines ACL is placed on the same layer as the edge vertical voltage line YLP.
  • the display area 1 includes a pixel array, which includes a plurality of pixel rows extending along the transverse direction X and a plurality of pixel columns extending along the longitudinal direction Y.
  • the plurality of auxiliary connection lines ACL correspond to the plurality of first lateral voltage lines XLU on a one-to-one basis, and correspond to the plurality of pixel rows of the upper display area 13 on a one-to-one basis.
  • the plurality of pixel columns include the edge pixel column PXC0 closest to the left edge 1b
  • the plurality of edge longitudinal voltage lines YLP include the outer edge longitudinal voltage line YLP-1 passing through the edge pixel column PXC0;
  • each of the plurality of auxiliary connection lines ACL The left end in the transversal direction The left end of a first lateral voltage line XLU is electrically connected through the second edge via VP2.
  • auxiliary connection line ACL and the left lead 42 are arranged on the same layer.
  • they are made of the same material and are a continuous one-piece structure.
  • the materials of the two can also be different.
  • auxiliary connection lines ACL there are also multiple auxiliary connection lines ACL.
  • the connection mode of the right end of the voltage line XLU is the same as the auxiliary connection line ACL in the left frame area 2a
  • the connection method of the left end of the first transverse voltage line XLU is the same and will not be repeated here.
  • the right display area 12 includes a second edge display area 12P extending along the right edge 1d and a second middle display area 12M located on one side of the second edge display area 12P close to the left display area 11;
  • the edge display area 12P and the first edge display area 11P are symmetrical with respect to the symmetry axis extending along the longitudinal direction Y, and the second middle display area 12M and the first middle display area 11M are axially symmetrical with respect to the second longitudinal voltage line YML2.
  • the first middle display area 11M and the second middle display area 12M constitute a middle display area, the second sub-area B is located in the second middle display area 12M, and the first area 1 is located in the middle display area.
  • the first power supply voltage lead 4 further includes another lower lead 45 extending along the portion of the lower edge 1a corresponding to the second edge display area 12P, such as an edge voltage line that provides the first power supply voltage VSS to the second edge display area 12P.
  • another lower lead 45 for electrical connection for example, the two are directly connected, that is, the edge voltage line of the second edge display area 12P that provides the first power supply voltage VSS and the other lower lead 451 are in contact with each other, and the second edge display area 12P provides There is no other structure between the edge voltage line of the first power supply voltage VSS and another lower lead 45 as a medium for connecting the two; for example, the second edge display area 12P provides an edge voltage line of the first power supply voltage VSS and another lower lead 45 .
  • the leads 45 are arranged on the same layer and form a continuous one-piece structure.
  • the edge voltage line that provides the first power supply voltage VSS in the second edge display area 12P and the other lower lead 45 can be arranged in different layers, and the two are in contact with each other through via holes.
  • the display substrate 10 further includes a second power supply voltage line vdd (not shown in FIG. 1 ), the second power supply voltage line vdd is configured to provide a second power supply voltage different from the first power supply voltage VSS to the sub-pixel; for example, the first power supply voltage line vdd
  • the power supply voltage VSS has opposite polarity to the second power supply voltage VDD.
  • the first power supply voltage VSS is low level
  • the second power supply voltage VDD is high level.
  • the first power supply voltage VSS may be at a high level and the second power supply voltage VDD may be at a low level.
  • the vertical voltage line YL and the data line data in the upper display area 13 are arranged on the same layer, and the horizontal voltage line XL and the second power supply voltage line are arranged on the same layer.
  • FIG. 10 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIGS. 11A to 11H include schematic diagrams of different film layers in the pixel circuit.
  • FIG. 11I is a schematic diagram of the stacking of film layers shown in FIGS. 11A to 11F .
  • the dotted box in Figure 11A represents an area of one sub-pixel.
  • the display substrate further includes a plurality of sub-pixels, at least some of which The pixel includes a light-emitting element 120 and a pixel circuit 110 electrically connected to the light-emitting element 120 .
  • the pixel circuit includes a plurality of transistors and at least one capacitor.
  • the pixel circuit includes a second reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a second light emitting control transistor T5, a first light emitting control transistor T6, a first reset control transistor T7, and a third reset transistor T4.
  • the display substrate also includes reset power signal lines 561, 551, and 554, scan signal lines 552, 531, and 523, a second power supply voltage line vdd, reset control signal lines 522, 532, and 553, light emission control signal line 521 and data line 582.
  • the first electrode of the threshold compensation transistor T2 is electrically connected to the first electrode of the driving transistor T3, and the second electrode of the threshold compensation transistor T2 is electrically connected to the gate electrode of the driving transistor T3.
  • the gate electrode of the transistor T2 is electrically connected to the scan signal lines 531 and 552 to receive the compensation control signal; the first electrode of the first reset control transistor T7 is electrically connected to the reset power signal line 561 to receive the reset signal Vinit2.
  • the first reset control transistor T7 The second electrode of the first reset control transistor T7 is electrically connected to the first electrode of the light-emitting element (i.e., the N4 node), and the gate electrode of the first reset control transistor T7 is electrically connected to the reset control signal line 522 to receive the reset control signal Reset(N+1); the third The first electrode of the reset transistor T8 is electrically connected to the reset power signal line 551 to receive the reset signal Vref.
  • the second electrode of the third reset transistor T8 is electrically connected to the second electrode of the driving transistor T3.
  • the gate electrode of the third reset transistor T8 is connected to the reset power signal line 551 to receive the reset signal Vref.
  • the reset control signal line 522 is electrically connected; the first pole of the data writing transistor T4 is electrically connected to the second pole of the driving transistor T3, and the second pole of the data writing transistor T4 is electrically connected to the data line 200 (data line data) to receive Data signal Data, the gate of the data writing transistor T4 is electrically connected to the scanning signal line 523 to receive the scanning signal Gate; the first pole of the storage capacitor C is electrically connected to the second power supply voltage line vdd, and the second pole of the storage capacitor C is electrically connected to The gate of the driving transistor T3 is electrically connected; the first electrode of the second reset transistor T1 is electrically connected with the reset power signal line 554 to receive the reset signal Vinit1, and the second electrode of the second reset transistor T1 is electrically connected with the gate of the driving transistor T3 , the gate of the second reset transistor T1 is electrically connected to the reset control signal lines 553 and 532 to receive the reset control signal Reset(N); the gate of the first light emitting control transistor T6 is electrically connected to the
  • the first electrode of the first light-emitting control transistor T6 is electrically connected to the first electrode of the driving transistor T3, the second electrode of the first light-emitting control transistor T6 is electrically connected to the first electrode of the light-emitting element 120; the second light-emitting control transistor The first pole of T5 is electrically connected to the second power supply voltage line vdd to receive the first The power signal VDD, the second electrode of the second light-emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T3, the gate of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line 521 to receive the light-emitting control signal EM, and emits light.
  • the second electrode of the element 120 is electrically connected to the voltage terminal VSS (followed by the third signal line 600).
  • the above-mentioned power signal line refers to a signal line that outputs the voltage signal VDD, and can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.
  • each pixel circuit in addition to the 8T1C (ie, eight transistors and one capacitor) structure shown in FIG. 10 , each pixel circuit can also be a structure including other numbers of transistors, such as 7T1C. structure, 7T2C structure, 6T1C structure, 6T2C structure or 9T2C structure, the embodiments of the present disclosure are not limited to this.
  • Figure 11A shows active semiconductor pattern 510.
  • the active semiconductor pattern 510 can be used to fabricate the above-mentioned driving transistor T3, data writing transistor T4, second light emitting control transistor T5, first light emitting control transistor T6, first reset control transistor T7 and the third light emitting control transistor T7.
  • the active layer of the three-reset control transistor T8 is used to form the channel region of the above-mentioned transistor.
  • the active semiconductor pattern 510 includes the active layer pattern (channel region) and doping region pattern (source and drain region) of the above-mentioned transistor of each sub-pixel, and the active layer pattern and doping region of the above-mentioned transistor in the same pixel circuit Pattern integrated setting.
  • the active semiconductor pattern 510 may include an integrally formed low-temperature polysilicon layer, and the source region and the drain region may be conductive through doping or the like to achieve electrical connections between the structures.
  • the above-mentioned source region and drain region may be regions doped with p-type impurities.
  • FIG. 11B shows the first conductive layer pattern 520 located on the side of the active semiconductor pattern 510 away from the base substrate.
  • the first conductive layer pattern 520 includes a reset control signal line 522 , a scanning signal line 523 , a pole of the capacitor 524 and a light emission control signal line 521 .
  • the first conductive layer pattern 520 may include gates of the driving transistor T3, the data writing transistor T4, the second light emitting control transistor T5, the first light emitting control transistor T6, the first reset control transistor T7, and the third reset control transistor T8. .
  • each dotted rectangular frame in FIG. 11A shows each portion where the active semiconductor pattern 510 overlaps the first conductive layer pattern 520, that is, the channel region.
  • the active semiconductor layers on both sides of each channel region are conductive through processes such as ion doping to serve as the first pole and the second pole of each transistor.
  • the source and drain of a transistor can be symmetrical in structure, so its There may be no difference in physical structure between source and drain.
  • the third electrode of all or part of the transistors is The first and second poles are interchangeable as needed.
  • the gate electrode of the data writing transistor T4 may be a portion where the scanning signal line 523 overlaps the active semiconductor pattern 510 ;
  • the gate electrode of the first light emitting control transistor T6 may be a light emitting control signal
  • the first portion where the line 521 overlaps the active semiconductor pattern 510 and the gate electrode of the second light emission control transistor T5 may be the second portion where the light emission control signal line 521 overlaps the active semiconductor pattern 510 .
  • the gate of the third reset transistor T8 is the first portion where the reset control signal line 522 and the active semiconductor pattern 510 overlap.
  • the gate of the first reset control transistor T7 is the second portion where the reset control signal line 522 and the active semiconductor pattern 510 overlap. part.
  • the second conductive layer pattern 530 shows the second conductive layer pattern 530 on the side of the first conductive layer pattern 520 away from the base substrate.
  • the second conductive layer pattern 530 includes a scanning signal line 531 , a second pole 533 of the capacitor C, and a reset control signal line 532 .
  • the active layer pattern 540 includes channel regions of the second reset transistor T1 and the threshold compensation transistor T2.
  • the transistor using the oxide semiconductor has the characteristics of good hysteresis characteristics, low leakage current, and mobility. Therefore, oxide semiconductor transistors can be used to replace the low-temperature polysilicon material in the transistors to form a low-temperature polysilicon-oxide (LTPO) pixel circuit to achieve low leakage and help improve the stability of the gate voltage of the transistor.
  • LTPO low-temperature polysilicon-oxide
  • the gate electrode of the second reset transistor T1 may be a portion where the reset control signal line 532 overlaps the active layer pattern 540
  • the gate electrode of the threshold compensation transistor T2 may be a scan signal The portion where the line 531 overlaps the active layer pattern 540.
  • FIG. 11E shows the third conductive layer 550 on the side of the active layer pattern 540 away from the base substrate.
  • the third conductive layer 550 includes a reset power signal line 554 , a reset control signal line 553 , a scan signal line 552 and a reset power signal line 551 .
  • the reset control signal line 553 overlaps the channel region of the second reset transistor T1.
  • the second reset transistor T1 includes double gate, the second reset transistor T1 is a double-gate transistor; the scanning signal line 552 overlaps the channel region of the threshold compensation transistor T2, the threshold compensation transistor T2 includes double gates located on both sides of the active layer, and the threshold compensation transistor T2 is Dual gate transistor.
  • the second reset transistor T1 and the threshold compensation transistor T2 may be N-type transistors.
  • the data writing transistor T4, the second light emission control transistor T5, the first light emission control transistor T6, the first reset control transistor T7 and the third reset control transistor T8 may be P-type transistors.
  • FIG. 11F shows the fourth conductive layer 560 located on the side of the third conductive layer 550 away from the base substrate.
  • the fourth conductive layer 560 includes a reset power signal line 561, a connecting portion 568, a connecting portion 569, a connecting portion 563, a connecting portion 567, a connecting portion 562, a connecting portion 564, a connecting portion 565, and a connecting portion. 566.
  • connection part 568 are connected to the reset power signal line 551, and the middle part is connected to the first pole of the third reset transistor T8; the connection part 569 is connected to the data line data and the data writing transistor T4.
  • connection part 563 is used to electrically connect the first pole of the data writing transistor T4 and the second pole of the third reset transistor T8 to lead the reset signal Vref to the N2 node;
  • connection part 567 is used to electrically connect the driving transistor
  • the first pole of T3 is connected to the first pole of the threshold compensation transistor T2;
  • the middle of the connecting portion 562 is connected to the second power supply voltage line vdd (as shown in Figure 11H, that is, the second power supply voltage line vdd), and both ends of the connecting portion 562 are connected to the capacitor.
  • connection portion 564 is connected to the second pole 533 of the storage capacitor C, and the other end of the connection portion 564 is connected to the first pole of the second light-emitting control transistor T5; the connection portion 565 is used to electrically connect the third pole of the light-emitting element.
  • One electrode and the second electrode of the first light emitting control transistor T6; the connection portion 566 is used to electrically connect the reset power signal line 554 and the first electrode of the second reset transistor T1.
  • FIG. 11G shows the fifth conductive layer 570 located on the side of the fourth conductive layer 560 away from the base substrate.
  • the fifth conductive layer 570 includes a connection part 573, a connection part 575, a second power supply voltage line 572 (transmitting the second power supply voltage VDD), a connection part 574, a lateral voltage line XL (for example, a middle lateral voltage line Voltage line XLM, etc.).
  • the fifth conductive layer 570 further includes fourth connection lines.
  • connection portion 573 is used to electrically connect to the data line data.
  • the data line data is arranged in a different layer from the data line data through the connection portion 573 and some extending along the transverse direction X in the display area 1 .
  • the connection line is electrically connected to transmit the data signal DATA to the connection line;
  • the connection part 575 is a reserved pad.
  • the first connection line can be electrically connected to the second connection line through the reserved pad, or the vertical voltage line can be electrically connected to the lateral voltage line through the reserved pad.
  • connection portion 574 is electrically connected to the connection portion 565 to realize the electrical connection between the second electrode of the first light-emitting control transistor T6 and the first electrode of the light-emitting element.
  • the second power supply voltage line 572 is electrically connected to the second power supply voltage line vdd.
  • FIG. 11H shows the sixth conductive layer 580 located on the side of the fifth conductive layer 570 away from the base substrate.
  • the sixth conductive layer 580 includes the data line data, the second power supply voltage line vdd, the fifth connection line 450 , the connection part 584 and the connection part 585 .
  • the connecting portion 584 and the connecting portion 585 are electrically connected to first electrodes of different light-emitting elements.
  • the data line data includes a transfer pad 290 , and the data line data is connected to the connection portion 573 through the transfer pad 290 to connect with some of the data lines extending along the transverse direction X in the display area 1 .
  • the connection lines provided in different data layers are electrically connected to transmit the data signal DATA to the connection lines.
  • the vertical voltage lines YL each include an adapter pad 459, and the vertical voltage lines YL can pass through the adapter pad 459 and be electrically connected to the connection portion 575 through the corresponding adapter pad 459.
  • the connection portion 575 is electrically connected to the corresponding horizontal voltage line XL that needs to be electrically connected to the vertical voltage line YL, thereby realizing the electrical connection between the vertical voltage line YL and the horizontal voltage line XL.
  • At least one embodiment of the present disclosure also provides a display device 100 , including any display substrate 10 provided by at least one embodiment of the present disclosure.

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Abstract

一种显示基板和显示装置，该显示基板中，显示区具有沿横向延伸的下边缘和沿纵向延伸的左边缘，显示区包括左显示区和右显示区，左显示区包括沿左边缘延伸的第一边缘显示区和第一中间显示区，横向与纵向相交；边框区围绕至少部分显示区；第一电源电压引线提供第一电源电压且位于边框区内；第一电源电压引线包括沿下边缘的对应于第一边缘显示区的部分延伸的下引线，而不沿下边缘对应于第一中间显示区的部分延伸；第一电源电压线包括位于第一边缘显示区沿的边缘电压线和位于第一中间显示区的中间电压线；边缘电压线与下引线直接连接以给位于第一边缘显示区的子像素提供第一电源电压，中间电压线与下引线间隔开。

Description

显示基板以及显示装置
本申请要求于2022年07月28日递交的中国专利申请第202210898307.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开至少一实施例涉及一种显示基板以及显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示产品与传统的液晶显示器(LCD)相比，具有自发光、广色域、高对比度、轻薄等优点，使其广泛应用于手机、平板电脑等领域。
通常，需要将显示区的多种信号线例如数据线引出至从扇出区域(Fanout region)，然后经扇出区域连接至集成电路(IC)，从扇出区域(Fanout region)位于不执行显示功能的边框区。随着人们对显示产品视觉效果的不断追求，窄边框以及显示全面屏逐渐成为当前OLED显示产品发展的大趋势。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板包括：显示区、非显示区、第一电源电压引线和第一电源电压线。显示区设置有子像素，且具有沿横向延伸的下边缘和沿纵向延伸的左边缘，所述横向与所述纵向相交，沿所述纵向延伸的分隔线将所述显示区划分为左显示区和右显示区，所述左显示区包括沿所述左边缘延伸的第一边缘显示区和位于所述第一边缘显示区的靠近所述右显示区的第一中间显示区；非显示区包括围绕至少部分所述显示区的边框区；第一电源电压引线配置为提供第一电源电压，且位于所述边框区内；所述第一电源电压引线包括沿所述下边缘的对应于第一边缘显示区的部分延伸的下引线，而不沿所述下边缘对应于所述第一中间显示区的部分 延伸；第一电源电压线包括位于所述第一边缘显示区沿的边缘电压线和位于所述第一中间显示区的中间电压线；所述边缘电压线与所述下引线直接连接以给所述位于所述第一边缘显示区的子像素提供所述第一电源电压，并且，所述中间电压线与所述下引线间隔开。
例如，在本公开至少一实施例提供额显示基板中，所述第一电源电压线包括沿所述纵向延伸的纵向电压线和沿所述横向延伸的横向电压线，所述纵向电压线与所述横向电压线异层设置；所述纵向电压线包括位于所述第一边缘显示区的边缘纵向电压线，所述横向电压线包括位于所述第一边缘显示区且与所述边缘纵向电压线相交的边缘横向电压线，所述边缘纵向电压线与所述边缘横向电压线构成所述边缘电压线；所述第一电源电压引线还包括沿所述显示区的左边缘延伸的左引线，所述边缘纵向电压线与所述下引线直接连接，所述边缘横向电压线与所述左引线直接连接。
例如，在本公开至少一实施例提供额显示基板中，所述子像素包括：驱动晶体管、发光器件和数据晶体管，所述驱动晶体管配置为控制流经所述发光器件的驱动电流的大小，所述发光器件配置为接收所述驱动电流且被所述驱动电流驱动以发光，所述数据晶体管配置为响应于第一控制信号将数据信号写入所述驱动晶体管的栅极，所述数据线配置为给所述子像素传输所述数据信号；所述显示区域包括下显示区和上显示区，所述下显示区靠近所述下边缘，所述上显示区在纵向上位于所述下显示区的远离所述下边缘的一侧；所述下显示区包括第一区域和第二区域，所述第一区域包括在所述横向上靠近所述左边缘的第一子区域和远离所述左边缘的第二子区域，穿过所述第一子区域和所述第二区域的所述数据线包括在所述第一子区域内沿所述纵向延伸的第一连接线和在所述第二区域内沿所述横向延伸的第二连接线；所述第一连接线与所述纵向电压线同层设置，所述第二连接线与所述横向电压线同层设置，同一条所述数据线的所述第一连接线与所述第二连接线通过第一连接孔电连接；所述第一子区域位于所述第一中间显示区内，所述第二区域至少部分位于所述中间所述显示区内；所述第一子区域具有在所述横向上最靠近所述显示区的左边缘的左端点，沿所述纵向延伸且经过所述左端点的直线为所述第一边缘显示区与所述第一中间显示区的分界线。
例如，在本公开至少一实施例提供额显示基板中，所述分界线穿过所述第二区域且将所述第二区域分割成靠近所述显示区的左边缘的第一子区域和远离所述显示区的左边缘的第二子区域，所述第一子区域位于所述第一边缘显示区内，所述第二子区域位于所述第一中间显示区内；所述下显示区还包括第三区域，第三区域位于所述第一边缘显示区内，且在所述横向上位于所述第二区域的远离所述第一区域的一侧；所述边缘横向电压线包括位于所述第三区域的下部边缘横向电压线，所述边缘纵向电压线穿过所述第三区域，且与所述下部边缘横向电压线相交于第一交点，所述下部边缘横向电压线的左端与所述左引线电连接，所述下部边缘横向电压线的与其左端相对的右端与在所述第二区域中的所述第二连接线通过第一断口断开；所述纵向电压线包括多条所述边缘纵向电压线和多条所述边缘横向电压线，所述多条所述边缘纵向电压线和多条所述边缘横向电压线彼此交织成网格，所述网格包括多个所述第一交点；在所述多个第一交点中的一部分第一交点的每个的位置，一条所述边缘纵向电压线通过第一过孔与一条所述下部边缘横向电压线电连接。
例如，在本公开至少一实施例提供额显示基板中，所述多条边缘纵向电压线通过多个所述第一过孔与所述多条边缘横向电压线电连接，所述多个第一过孔的位置构成的平面图案为位于所述第三区域内的连接线段，所述连接线段的延伸方向与所述第一方向和所述第二方向均相交。
例如，在本公开至少一实施例提供额显示基板中，所述第三区域是由所述第二区域的在所述横向上靠近所述左边缘的第二边、所述左边缘以及所述下边缘所限定出的拐角区。
例如，在本公开至少一实施例提供额显示基板中，所述边框区包括围绕所述拐角区的边框角区域，所述边框角区域中设置有呈网格状的辅助第一电源电压线，所述网格状的辅助第一电源电压线包括多条纵向辅助电压线和多条横向辅助电压线。多条纵向辅助电压线沿所述纵向延伸，与所述纵向电压线同层设置，所述多条纵向辅助电压线中的每条在所述纵向上的第一端与所述第一电源电压引线直接连接，所述多条纵向辅助电压线的每条在所述纵向上的与其第一端相对的第二端与穿过所述拐角区的一条所述边缘纵向电压线 电连接；多条横向辅助电压线沿所述横向延伸，与所述多条纵向辅助电压线同层设置，所述多条横向辅助电压线中的每条在所述横向上的一端与所述第一电源电压引线直接连接，所述多条横向辅助电压线中的每条在所述横向上的与其第一端相对的第二端与一条所述边缘纵向电压线电连接。
例如，在本公开至少一实施例提供额显示基板中，所述显示区包括像素阵列，所述像素阵列包括沿所述横向延伸的多个像素行和沿所述纵向延伸的多个像素列；所述多个像素行包括靠近所述下边缘的多个边缘像素行；所述多条横向辅助电压线与所述多个边缘像素行一一对应，所述多个边缘像素行中的每个边缘像素行包括最靠近所述左边缘的边缘子像素，所述多条边缘纵向电压线包括穿过每个所述边缘像素行的边缘子像素的最边缘纵向电压线；所述多条横向辅助电压线中的每条的第二端与穿过对应的所述边缘像素行的最边缘纵向电压线电连接，且通过第一边缘过孔与穿过对应的所述边缘像素行的所述边缘横向电压线电连接。
例如，在本公开至少一实施例提供额显示基板中，所述横向电压线还包括多条第一横向电压线，多条第一横向电压线在所述纵向上排列，位于所述上显示区；所述第一横向电压线的左端与所述左引线电连接，所述边缘横向电压线还包括位于所述上显示区的上部边缘横向电压线，所述上部边缘横向电压线作为一条所述第一横向电压线的一部分；所述纵向电压线还包括多条中间纵向电压线，在所述横向上排列，沿所述纵向穿过部分所述第一中间显示区且穿过所述上显示区，所述多条中间纵向电压线、所述多条边缘纵向电压线与所述多条第一横向电压线交织成网格；所述多条边缘纵向电压线与所述多条第一横向电压线在所述第一边缘显示区内相交于多个辅助交点，在所述多个辅助交点中的一部分辅助交点的每个的位置，一条所述边缘纵向电压线通过辅助过孔与一条所述第一横向电压线电连接，所述多条边缘纵向电压线通过多个所述辅助过孔与所述多条第一横向电压线电连接；多个所述辅助过孔的位置构成的平面图案为位于所述第一边缘显示区内的辅助线段。
例如，在本公开至少一实施例提供额显示基板中，所述辅助线段的延伸方向与所述连接线段的延伸方向相同；所述显示基板包括多个所述辅助线段，所述连接线段、所述多个辅助线段沿所述纵向彼此间隔排列。
例如，在本公开至少一实施例提供额显示基板中，所述显示区还包括与所述下边缘相对的上边缘，所述第一电源电压引线还包括沿所述上边缘延伸的上引线，所述上引线与所述左引线电连接；所述边缘纵向电压线的上端与所述上引线连接，所述边缘纵向电压线的与其上端相对的下端与所述下引线直接连接；所述纵向电压线包括位于所述第一中间显示区的中间纵向电压线，所述中间纵向电压线包括：第一纵向电压线和第二纵向电压线。第一纵向电压线沿所述纵向依次穿过所述上显示区和至少部分所述第二区域，所述第一纵向电压线的上端与所述上引线电连接，所述第一纵向电压线的与其上端相对的下端与所述在第一子区域内的所述第一连接线通过第二断口断开；第二纵向电压线沿所述纵向依次穿过所述上显示区和所述第一区域；所述横向电压线包括位于所述第一区域的中间横向电压线，所述中间横向电压线与所述第二区域内的第二连接线通过第三断口断开，所述第二纵向电压线与所述中间横向电压线相交于第二交点，所述第二纵向电压线在所述第二交点处通过第二过孔与所述中间横向电压线电连接。
例如，在本公开至少一实施例提供额显示基板中，所述多条第一横向电压线与所述多条第二纵向电压线相交于多个第三交点，并且，在所述多个第三交点中的至少一部分第三交点的每个的位置，一条所述第一横向电压线通过第三过孔与一条所述第二纵向电压线电连接。
例如，在本公开至少一实施例提供额显示基板中，所述显示区还包括与所述左边缘相对的右边缘，所述第一电源引线还包括沿所述右边缘延伸的右引线，所述右引线与所述上引线电连接；所述多条第一横向电压线的每条线沿所述横向贯穿所述上显示区，且所述多条第一横向电压线的每条的与其左端相对的右端与所述右引线电连接。
例如，在本公开至少一实施例提供额显示基板中，所述多条中间纵向电压线与所述多条第一横向电压线在所述上显示区内彼此相交于多个第四交点，在所述多个第四交点中一部分第四交点的每个的位置，一条所述中间纵向电压线通过第四过孔与一条所述第一横向电压线电连接；多个所述第四过孔的位置构成的平面图案为折线。
例如，在本公开至少一实施例提供额显示基板中，所述折线包括从所述 左边缘延伸到所述右边缘的多条子折线，所述多条子折线中的每条子折线包括首尾相连的多个折线段；所述多个折线段包括沿第一方向延伸的第一线段和沿第二方向延伸的第二线段，所述第一方向与所述第二方向相交，且所述第一方向和所述第二方向均与所述横向和所述纵向相交，所述第一线段的第一端与所述第二线段的第一端相交于上顶点；所述多条子折线的多个所述顶点位于第二纵向电压线上，在所述顶点位置的所述第四过孔均为所述第二过孔。
例如，在本公开至少一实施例提供额显示基板中，所述多条子折线中的每条子折线呈W形。
例如，在本公开至少一实施例提供额显示基板中，所述W形的子折线包括所述第一线段和所述第二线段、第三线段和第四线段，所述第一线段和所述第二线段位于所述第三线段和第四线段之间，所述第三线段与所述第一线段连接，所述第四线段与所述第二线段连接；所述第一线段与所述第四线段基本平行，所述第二线段与所述第三线段基本平行。
例如，在本公开至少一实施例提供额显示基板中，所述纵向垂于所述横向，所述第一线段与所述横向的夹角为45°，所述第二线段与所述横向的夹角为45°。
例如，在本公开至少一实施例提供额显示基板中，在所述纵向上，所述辅助线段位于相邻的两条所述子折线的第三线段之间。
例如，在本公开至少一实施例提供额显示基板中，所述连接线段、所述辅助线段和所述第三线段彼此基本平行。
例如，在本公开至少一实施例提供额显示基板中，所述第二纵向电压线将所述第一区域分割成所述第一子区域和所述第二子区域，第一子区域的结构和第二子区域的结构相对于所述第二纵向电压线基本呈轴对称；所述下显示区包括第四区域，所述第四区域的结构与所述第二区域的结构相对于所述第二纵向电压线基本呈轴对称；穿过所述第一区域和所述第四区域的所述数据线包括在所述第二子区域中沿所述纵向延伸的第三连接线和在所述第四区域中沿所述横向延伸的第四连接线；所述第三连接线与所述纵向电压线同层设置，所述第四连接线与所述横向电压线同层设置，同一条所述数据线的所 述第三连接线与所述第四连接线通过第二连接孔电连接；位于所述第一区域中的所述中间横向电压线的与其左端相对的右端与所述第四区域中的所述第四连接线通过第四断口断开。
例如，在本公开至少一实施例提供额显示基板中，所述显示基板包括多条所述第一连接线、多条所述第二连接线、多条所述第三连接线和多条所述第四连接线；所述多条第一连接线与所述多条第二连接线分别通过多个所述第一连接孔电连接，所述多条第三连接线与所述多条第四连接线分别通过多个所述第二连接孔电连接；所述多个第一连接孔构成的平面图案是第五线段，所述第五线段是所述第一区域与所述第二区域的边界；所述多个第二连接孔构成的平面图案是第六线段，所述第六线段是所述第一区域与所述第四区域的边界；所述下显示区还包括第五区域，所述第五区域的结构与所述第三区域的结构相对于所述第二纵向电压线基本呈轴对称，所述第五区域中的与所述多个第一过孔对称的多个第五过孔的平面图案为第七线段；所述连接线段、所述第五线段、所述第六线段和所述第七线段依次连接所构成的平面图案与所述多条子折线中的每条子折线的平面图案相同。
例如，在本公开至少一实施例提供额显示基板中，所述第一区域的平面形状为第一三角形，所述第二区域的平面形状为第二三角形，所述第一三角形的在所述横向上靠近所述左边缘的第一边与所述第二三角形的在所述横向上远离所述显示区的左边缘的第一边至少部分重合；所述第一三角形的两个下顶点位于所述显示区的下边缘上，所述第一三角形的两个下顶点的靠近所述左边缘的左顶点为所述第一子区域的所述左端点；第一三角形为等腰三角形，所述第二纵向电压线基本上是所述等腰三角形的底边的中垂线。
例如，在本公开至少一实施例提供额显示基板中，所述边框区包括沿所述左边缘延伸的左边框区，所述左边框区中设置有沿所述横向延伸的多条辅助连接线，所述多条辅助连接线与所述边缘纵向电压线同层设置；所述显示区包括像素阵列，所述像素阵列包括沿所述横向延伸的多个像素行和沿所述纵向延伸的多个像素列；所述多个像素列包括最靠近所述左边缘的边缘像素列，所述多条边缘纵向电压线包括穿过所述边缘像素列的外边缘纵向电压线；所述多条辅助连接线中的每条在所述横向上的左端与所述左引线电连接，所 述多条辅助连接线中的每条在所述横向上与其左端相对的右端与所述外边缘纵向电压线电连接，且与对应的一条所述第一横向电压线的左端通过第二边缘过孔电连接。
例如，在本公开至少一实施例提供额显示基板中，所述右显示区包括沿所述右边缘延伸的第二边缘显示区和位于所述第二边缘显示区的靠近所述左显示区的一侧的第二中间显示区；所述第二边缘显示区与所述第一边缘显示区相对于沿所述纵向延伸的对称轴对称，所述第二中间显示区与所述第一中间显示区相对于所述第二纵向电压线呈轴对称。
例如，在本公开至少一实施例提供额显示基板中，所述显示基板还包括：第二电源电压线，配置为给所述子像素提供不同于所述第一电源电压的第二电源电压；所述纵向电压线与所述上显示区中的数据线同层设置，所述横向电压线所述第二电源电压线同层设置。
本公开至少一实施例还提供一种显示装置，包括本公开实施例提供的任意一种显示基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为根据本公开实施例提供的一种显示基板的整体平面示意图。
图2为包括图1中的下显示区和部分上显示区的局部放大示意图。
图3A为图2中的区域R1的局部放大示意图。
图3B-3D为图2中的区域R3的部分膜层的示意图。
图4为包括图1中的区域R2和区域R3的局部放大示意图。
图5A为图4中的区域R2的局部放大示意图。
图5B-5D为图4中的区域R2的部分膜层的示意图。
图6A为图4中的区域R3的局部放大示意图。
图6B-6D为图3中的区域R3的部分膜层的示意图。
图7A为图3中的区域R4的局部放大示意图。
图7B-7D为图3中的区域R4的部分膜层的示意图。
图8A为图3中的区域R5的局部放大示意图。
图8B-8C为图3中的区域R5的部分膜层的示意图。
图9为图3中的区域R6的局部放大示意图。
图10为根据本公开实施例的像素电路的等效电路图。
图11A-11H包括像素电路中不同膜层的示意图。
图11I为图11A-11F所示膜层层叠示意图。
图12为根据本公开实施例提供的一种显示基板的示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开中的附图并不是严格按实际比例绘制，显示基板中横向电压线、纵向电压线、各个过孔的数量也不是限定为图中所示的数量，各个结构的具体地尺寸和数量可根据实际需要进行确定。本公开中所描述的附图仅是结构示意图。
本公开中使用的“平行”、“垂直”以及“相同”等特征均包括严格意义的“平行”、“垂直”、“相同”等特征，以及“基本平行”、“基本垂直”、“基 本相同”等包含一定误差的情况，考虑到测量和与特定量的测量相关的误差(例如，测量系统的限制)，表示在本领域的普通技术人员所确定的对于特定值的可接受的偏差范围内。例如，“基本”能够表示在一个或多个标准偏差内，或者在所述值的10％或者5％内。
在本公开实施例的下文中没有特别指出一个成分的数量时，意味着该成分可以是一个也可以是多个，或可理解为至少一个。“至少一个”指一个或多个，“多个”指至少两个。
本公开实施例中的“同层”指同一材料在经过同一步骤(例如一步图案化工艺)后形成的多个膜层之间的关系。这里的“同层”并不总是指多个膜层的厚度相同或者多个膜层在截面图中的高度相同。
本公开中使用的“纵向”、“横向”、“上”、“下”、“左”、“右”等表示方向的词，仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变，部局限于说明书附图中所示的方向。例如，“上边缘”、“下边缘”、“左边缘”和“右边缘”不仅限于是附图中所示的上下左右，只要满足对其限定的相对位置关系即可。“左显示区”和“右显示区”也不限于本申请说明书附图中的左和右，只要满足对其限定的相对位置关系即可。“上显示区”和“下显示区”也不限于本申请说明书附图中的左和右，只要满足对其限定的相对位置关系即可。
本公开至少一实施例提供一种显示基板，该显示基板包括：显示区、非显示区、第一电源电压引线和第一电源电压线。显示区设置有子像素，且具有沿横向延伸的下边缘和沿纵向延伸的左边缘，所述横向与所述纵向相交，沿所述纵向延伸的分隔线将所述显示区划分为左显示区和右显示区，所述左显示区包括沿所述左边缘延伸的第一边缘显示区和位于所述第一边缘显示区的靠近所述右显示区的第一中间显示区；非显示区包括围绕至少部分所述显示区的边框区；第一电源电压引线配置为提供第一电源电压，且位于所述边框区内；所述第一电源电压引线包括沿所述下边缘的对应于第一边缘显示区的部分延伸的下引线，而不沿所述下边缘对应于所述第一中间显示区的部分延伸；第一电源电压线包括位于所述第一边缘显示区沿的边缘电压线和位于所述第一中间显示区的中间电压线；所述边缘电压线与所述下引线直接连接 以给所述位于所述第一边缘显示区的子像素提供所述第一电源电压，并且，所述中间电压线与所述下引线间隔开。
本公开至少一实施例还提供一种显示装置，包括本公开实施例提供的任意一种显示基板。
示例性地，图1为根据本公开实施例提供的一种显示基板的整体平面示意图，图2为包括图1中的下显示区和部分上显示区的局部放大示意图。例如，如图1所示，本公开至少一实施例提供的显示基板10包括：显示区1、边框区2、第一电源电压引线4和第一电源电压线vss。显示区1设置有子像素，且具有沿横向X延伸的下边缘1a和沿纵向Y延伸的左边缘1b，横向与纵向相交，例如横向与纵向垂直；当然，在另一些实施例中，横向与纵向也可以不垂直。显示区1包括在横向X上排列的左显示区11和右显示区12。例如沿纵向Y延伸的分隔线ML将显示区1划分为左显示区11和右显示区12，例如分隔线ML为下边缘1a的中垂线，以使左显示区11和右显示区12对称，整个显示基板10的显示效果均匀，但不限于分隔线ML为下边缘1a的中垂线的情况。左显示区11包括沿左边缘1b延伸的第一边缘显示区11P和位于第一边缘显示区11P的靠近右显示区12的第一中间显示区11M；边框区2为非显示区，围绕至少部分显示区1。例如，显示基板10还可以包括焊盘3，焊盘3位于下边缘1a的远离显示区1的一侧；第一电源电压引线4与焊盘3连接以配置为提供第一电源电压VSS，且位于边框区2内；第一电源电压引线4包括沿下边缘1a的对应于第一边缘显示区11P的部分延伸的下引线41，而不沿下边缘1a对应于第一中间显示区11M的部分延伸；第一电源电压线vss包括位于第一边缘显示区11P的边缘电压线LP和位于第一中间显示区11M的中间电压线LM，边缘电压线LP与下引线41接触而电连接以给位于第一边缘显示区11P的子像素提供第一电源电压VSS，并且，中间电压线LM与下引线41间隔开，即中间电压线LM不与来自焊盘3的下引线4直接连接。如此，在本公开实施例提供的显示基板10中，边缘电压线与下引线41接触而电连接以给第一边缘显示区11P的子像素提供VSS信号，中间电压线LM与下引线41间隔开即不接触，而是通过与左引线42或上引线43、或其他第一电源电压线vss连接而给第一中间显示区11M提供VSS信号， 即，不通过将从设置于下边缘1a的远离显示区一侧的焊盘3引出的第一电源电压引线4直接连入第一中间显示区11M，也即，中间电压线LM不经过边框区2与焊盘3连接，不与第一电源电压线vss直接连接，不经焊盘3获取第一电源电压VSS，而是经由边缘电压线获取第一电源电压VSS，从而减少设置在扇出(Fanout)区域的走线，进一步减小扇出区域，以减小下边框的宽度，进一步实现更窄的边框。
例如，边缘电压线LP与下引线41直接连接，即边缘电压线LP与下引线41彼此接触，且边缘电压线LP与下引线41之间不存在任何其他的结构作为两者连接的媒介；例如，边缘电压线LP与下引线41同层设置，且构成连续的一体成型结构，这种情况下，边缘电压线LP与下引线41的材料是相同的，可以通过同一构图工艺形成，如此，可简化显示基板的结构和制作工艺。
当然，在其他实施例中，边缘电压线LP与下引线41可以异层设置，两者通过过孔彼此接触。需要说明的是，在本公开中，术语“直接连接”是指彼此连接的两个结构(例如边缘电压线LP与下引线41直接连接等)彼此接触，彼此连接的两个结构之间不存在任何其他的结构作为两者连接的媒介。例如，彼此直接连接的两个结构可以是连续的一体成型结构，此时彼此直接连接的两个结构的材料是相同的，可以通过同一构图工艺形成该两个结构以简化显示基板的制作工艺；或者，彼此直接连接的两个结构的材料也可以是不同的，例如彼此直接连接的两个结构都是导电的信号线，两者可以分别采用与两者的功能相匹配的材料，满足对不同性能例如不同导电率的需求。
例如，例如，如图1所示，第一电源电压线vss包括沿纵向Y延伸的纵向电压线YL和沿横向X延伸的横向电压线XL，纵向电压线YL与横向电压线XL异层设置；纵向电压线YL包括位于第一边缘显示区11P的边缘纵向电压线YLP，横向电压线XL包括位于第一边缘显示区11P且与边缘纵向电压线YLP相交的边缘横向电压线XLP，边缘纵向电压线YLP与边缘横向电压线XLP构成边缘电压线LP；第一电源电压引线4还包括沿显示区1的左边缘1b延伸的左引线42，边缘纵向电压线YLP与下引线41直接连接，边缘横向电压线XLP与左引线42直接连接。例如，边缘纵向电压线YLP在第 一边缘显示区11P在纵向上内贯穿整个显示区，以给整个第一边缘显示区11P的子像素提供第一电源电压VSS。如此，边缘纵向电压线YLP与与之靠近的下引线41直接连接，能够节省空间，有利于减小下边缘1a外侧的边框区。
例如，焊盘3上设置有1号第一电源电压引脚4a，下引线41与第一电源电压引脚4a电连接，并且，第一电源电压引脚4a位于焊盘3在横向X上靠近第一边缘显示区11P的第一端，因此，就近使第一电源电压引脚4a、下引线41和第一边缘显示区11P的缘纵向电压线YLP依次直接连接，可以有效减少下边框的走线，减小下边缘1a外侧的边框区。
例如，如图1所示，在一些实施例中，焊盘3上还可以设置有2号第一电源电压引脚4b，2号第一电源电压引脚4b靠近右边缘1d，即位于焊盘3在横向X上靠近下文的第二边缘显示区12P的第二端，第二边缘显示区12P与第一边缘显示区11P的与第一电源电压线vss相关的结构相对于沿纵向Y延伸的对称轴呈轴对称，与1号第一电源电压引脚4a和第一边缘显示区11P中的第一电源电压线vss类似，2号第一电源电压引脚4b与第二边缘显示区12P中的边缘纵向电压线直接连接，以给第二边缘显示区12P的子像素提供第一电源电压VSS。
图6A为图4中的区域R3的局部放大示意图，图6B-6D为图3中的区域R3的部分膜层的示意图。例如，如图1和图6A所示，边缘纵向电压线YLP的靠近下引线41的下端与下引线41直接连接。例如，边缘纵向电压线YLP的与其下端相对的上端与上引线43直接连接，以更加可靠地通过边缘纵向电压线YLP提供第一电源电压VSS。
例如，如图1所示，结合图8所示的像素电路的等效电路图，显示基板10还包括数据线data，子像素包括：驱动晶体管T3、发光元件和数据晶体管T4，驱动晶体管T3配置为控制流经发光元件的驱动电流的大小，发光元件配置为接收驱动电流且被驱动电流驱动以发光，数据晶体管T4配置为响应于第一控制信号将数据信号DATA写入驱动晶体管T3的栅极，数据线data配置为给子像素传输数据信号DATA；显示区1域包括下显示区14和上显示区13，下显示区14靠近下边缘1a，上显示区13在纵向上位于下显示区14的远离下边缘1a的一侧；下显示区14包括第一区域①和第二区域②，第 一区域①包括在横向X上靠近左边缘1b的第一子区域A和远离左边缘1b的第二子区域B，穿过第一子区域A和第二区域②的数据线data包括在第一子区域A内沿纵向Y延伸的第一连接线DL1、在第二区域②内沿横向X延伸的第二连接线DL2、以及位于上显示区13内沿纵向Y延伸的第五连接线DL5，第五连接线DL5与第一连接线DL1同层设置；第一连接线DL1与纵向电压线YL同层设置，第二连接线DL2与横向电压线XL同层设置，同一条数据线data的第一连接线DL1与第二连接线DL2通过第一连接孔VC1电连接，同一条数据线data的第五连接线DL5与第二连接线DL2第三连接孔VC3电连接。从而，对于一条数据线data，形成一条如图1中的三个箭头所示意的数据信号DATA的传输通道。例如，多条数据线data分别通过多条数据信号引线CL与焊盘3连接，例如与焊盘3中的集成电路IC电连接，以给数据线data提供数据信号DATA。
例如，第一子区域A位于第一中间显示区11M内，第二区域②至少部分位于第一中间显示区11M内；第一子区域A具有在横向X上最靠近显示区1的左边缘1b的左端点PO，沿纵向Y延伸且经过左端点PO的直线为第一边缘显示区11P与第一中间显示区11M的分界线IL。即，该直线与左边缘1b之间的区域为第一边缘显示区11P。第一子区域A位于第一中间显示区11M。
例如，如图1-2所示，分界线IL穿过第二区域②且将第二区域②分割成靠近显示区1的左边缘1b的第一子区域A和远离显示区1的左边缘1b的第二子区域B，第一子区域A位于第一边缘显示区11P内，第二子区域B位于第一中间显示区11M内。
图3A为图2中的区域R1的局部放大示意图，图3B-3D为图2中的区域R3的部分膜层的示意图。结合图1-2和图3A-3D，或者结合图1和图6A-6D，下显示区14还包括第三区域③，第三区域③位于第一边缘显示区11P内，且在横向X上位于第二区域②的远离第一区域①的一侧；边缘横向电压线XLP包括位于第三区域③的下部边缘横向电压线XLP1，边缘纵向电压线YLP穿过第三区域③，且与下部边缘横向电压线XLP1相交于第一交点P1，下部边缘横向电压线XLP1的左端与左引线42电连接，下部边缘横向电 压线XLP1的与其左端相对的右端与在第二区域②中的第二连接线DL2通过第一断口OP1断开。第一断口OP1可参考图1-2，图3A-3B是局部示意图，只示出了有限的几个像素，因此，没有示意出第一断口OP1。纵向电压线YL包括多条边缘纵向电压线YLP和多条边缘横向电压线XLP，多条边缘纵向电压线YLP和多条边缘横向电压线XLP彼此交织成网格，网格包括多个第一交点P1；在多个第一交点P1中的一部分第一交点P1的每个的位置，一条边缘纵向电压线YLP通过第一过孔V1与一条下部边缘横向电压线XLP1电连接，从而在多个第一交点P1处存在多个第一过孔V1。如此，多条边缘纵向电压线YLP与多条下部边缘横向电压线XLP1在第三区域③电连接呈网状结构，能够降低第一电源电压线vss在第三区域③中传递第一电源电压VSS的电阻，由第三区域③中的边缘纵向电压线YLP与下部边缘横向电压线XLP1构成的网状的第一电源电压线vss上的压降较低。
例如，图4B所示的膜层与图4C所示的膜层之间存在第一绝缘层，第一过孔V1贯穿第一绝缘层，通过穿过第一过孔V1的第一连接结构C1将边缘纵向电压线YLP与下部边缘横向电压线XLP1电连接。
例如，位于显示区1中的所有沿纵向Y延伸的第一电源电压线vss(纵向电压线YL)均与上显示区13中的数据线data同层设置，位于显示区1中的横向电压线XL第二电源电压线同层设置；所有沿X方向延伸的第一电源电压线vss(横向电压线XL)均位于纵向电压线YL的靠近衬底基板的一侧。例如，纵向电压线YL位于下文的第六导电层580，横向电压线XL位于下文的第五导电层570。当然，在其他实施例中，不限于如此，只要向电压线YL与横向电压线XL设置在不同的金属层即可，两个金属层之间设置有第一绝缘层。
图3A-3B示出了三个第一过孔V1作为示例，但是对于第一过孔V1的数量不限。
例如，参考图1-2，多条边缘纵向电压线YLP通过多个第一过孔V1与多条边缘横向电压线XLP电连接，多个第一过孔V1的位置构成的平面图案为位于第三区域③内的连接线段SC(图1中的第三区域③内的虚线代表连接线段SC)，连接线段SC的延伸方向与横向X和纵向Y均相交。这里的“多 个第一过孔V1的位置构成的平面图案”是指多个第一过孔V1的位置排列而成的整体图形。
例如，在图1-2所示的实施例中，连接线段SC为直线段，以与下文中的W形折线的形状保持一致。当然，在其他实施例中，如果需要，连接线段SC也可以为曲线段。
例如，如图1所示，第三区域③是由第二区域②的在横向X上靠近左边缘1b的第一边SL1、左边缘1b以及下边缘1a所限定出的拐角区。第三区域③为该拐角区可以将该拐角区内原本由于实现数据线data经第二区域②和第一区域①的设计(Fanout in pixel，FIP技术)而设置第一断口OP1而浮置的接入第一电源电压信号，从而防止浮置导线带来的信号干扰，例如浮置导线容易囤积静电而造成静电干扰。
用于分别连接多条数据线data的第五连接线DL5与第二连接线DL2的多个第三连接孔VC3的平面图案为线段例如直线段，该线段作为第二区域②的第一边SL1，也作为第三区域③是与第二区域②的分界线。
例如，参考图1-2，边框区2包括围绕拐角区③的边框角区域20，边框角区域20中设置有呈网格状的辅助第一电源电压线vss，如此，可大大降低第一边缘显示区11P内的第一电源低压线的压降。
图4为包括图1中的区域R2和区域R3的局部放大示意图，区域R2包括边框角区域20；图5A为图4中的区域R2的局部放大示意图，图5B-5D为图4中的区域R2的部分膜层的示意图。结合图4和图5A-5D，网格状的辅助第一电源电压线vss包括：多条纵向辅助电压线YAL和多条横向辅助电压线XAL。多条纵向辅助电压线YAL沿纵向Y延伸，与纵向电压线YL同层设置，其中，多条纵向辅助电压线YAL中的每条在纵向Y上的第一端与第一电源电压引线4(例如下引线41或连接下引线41和左引线42的拐角引线)直接连接，多条纵向辅助电压线YAL的每条在纵向Y上的与其第一端相对的第二端与穿过拐角区③的一条边缘纵向电压线YLP电连接，例如直接连接；多条横向辅助电压线XAL沿横向X延伸，与多条纵向辅助电压线YAL同层设置，其中，多条横向辅助电压线XAL中的每条在横向X上的一端与第一电源电压引线4(例如左引线42或连接下引线41和左引线42的拐角引 线)直接连接，多条横向辅助电压线XAL中的每条在横向X上的与其第一端相对的第二端与一条边缘纵向电压线YLP电连接。如图5D所示多条纵向辅助电压线YAL和多条横向辅助电压线同层设置，例如与纵向电压线YL同层设置，可通过同一道构图工艺同时形成纵向辅助电压线YAL、横向辅助电压线以及纵向电压线YL，以简化显示基板的结构和制作工艺。
例如，参考图5A-5D，显示区1包括像素阵列，像素阵列包括沿横向X延伸的多个像素行和沿纵向Y延伸的多个像素列；多个像素行包括靠近下边缘1a的多个边缘像素行PXR；多条横向辅助电压线XAL与多个边缘像素行PXR一一对应，多个边缘像素行PXR中的每个边缘像素行PXR包括最靠近左边缘1b的边缘子像素P，多条边缘纵向电压线YLP包括穿过每个边缘像素行PXR的边缘子像素P的最边缘纵向电压线YLP0；多条横向辅助电压线XAL中的每条的第二端与穿过对应的边缘像素行PXR的最边缘纵向电压线YLP0电连接，例如直接连接；并且，多条横向辅助电压线XAL中的每条的第二端通过第一边缘过孔VP1与穿过对应的边缘像素行PXR的边缘横向电压线XLP电连接。如图5C所示，通过穿过第一绝缘层的第一边缘连接结构CP1将横向辅助电压线XAL的第二端与对应的边缘像素行PXR的边缘横向电压线XLP电连接。图5A-5D示出一条横向辅助电压线XAL由于其对应的最靠近下边缘1a的一个边缘像素行PXR的连接关系，其他边缘像素行PXR的连接情况与此相同，只是在该实施例中，为了适应于拐角区的形状，对应于各个边缘像素行PXR的横向辅助电压线XAL的长度不同。在其他实施例中，如果需要，各个边缘像素行PXR的横向辅助电压线XAL的长度也可以，适应于显示基板的像素排布进行设计即可。
例如，如图1和图5A-5B所示，第二电源电压引线4b-1位于围绕下边缘1a的下边框区，与第二电源电压引脚4b电连接，穿过多个像素列的第二电源电压线与第二电源电压引线4b-1电连接，从而给多个像素列的像素提供第二电源电压VDD。
例如，如图1所示，横向电压线XL还包括多条第一横向电压线XLU，多条第一横向电压线XLU在纵向Y上排列，位于上显示区13；第一横向电压线XLU的左端与左引线42电连接，边缘横向电压线XLP还包括位于上显 示区13的上部边缘横向电压线XLP2，上部边缘横向电压线XLP2作为一条第一横向电压线XLU的一部分。纵向电压线YL还包括多条中间纵向电压线YLM，多条第一横向电压线XLU在横向X上排列，沿纵向Y穿过部分第一中间显示区11M且穿过上显示区13；多条中间纵向电压线YLM、多条边缘纵向电压线YLP与多条第一横向电压线XLU交织成网格，以减小第一电源电压线vss的电阻，降低第一电源电压线vss上的压降。
多条边缘纵向电压线YLP与多条第一横向电压线XLU在第一边缘显示区11P内相交于多个辅助交点AP，在多个辅助交点AP中的一部分辅助交点AP的每个的位置，一条边缘纵向电压线YLP通过辅助过孔AV与一条第一横向电压线XLU在第一边缘显示区11P内电连接，多条边缘纵向电压线YLP通过多个辅助过孔AV与多条第一横向电压线XLU电连接；多个辅助过孔AV的位置构成的平面图案为位于第一边缘显示区11P内的辅助线段SA，辅助线段SA的远离左边缘1b的一端悬置，即没有其的过孔图案与辅助线段SA的远离左边缘1b的一端连接，辅助线段SA不同于下文中的W形折线的第三线段S3。如此，能够进一步有效减小第一边缘显示区11P内第一电源电压线vss的电阻，降低第一边缘显示区11P内第一电源电压线vss的压降。
在辅助线段SA的位置，一条边缘纵向电压线YLP通过辅助过孔AV与一条第一横向电压线XLU在第一边缘显示区11P内电连接的结构与图3A-3D所示的区域R1的结构相同，可参考图3A-3D，在此不再重复。
例如，继续参考图1，辅助线段SA的延伸方向与连接线段SC的延伸方向相同，例如辅助线段SA与连接线段SC的长度也相同，以保持通过过孔连接的连接点的排布走势的均一性，防止显示基板产生mura不良。例如，显示基板10包括多个辅助线段SA，连接线段SC、多个辅助线段SA沿纵向Y彼此间隔排列。
例如，如图1所示，显示区1还包括与下边缘1a相对的上边缘1c，第一电源电压引线4还包括沿上边缘1c延伸的上引线43，上引线43与左引线42电连接；边缘纵向电压线YLP的上端与上引线43连接，边缘纵向电压线YLP的与其上端相对的下端与下引线41直接连接。
图7A为图3中的区域R4的局部放大示意图，图7B-7D为图3中的区 域R4的部分膜层的示意图。例如，如图1所示，纵向电压线YL包括位于第一中间显示区11M的中间纵向电压线YLM，中间纵向电压线YLM包括：第一纵向电压线YLM1和第二纵向电压线YML2。第一纵向电压线YLM1沿纵向Y依次穿过上显示区13和至少部分第二区域②。结合图1和图7A-7D，第一纵向电压线YLM1的上端与上引线43电连接，第一纵向电压线YLM1的与其上端相对的下端与在第一子区域A内的第一连接线DL1通过第二断口OP2断开，图7A和图7D所示的局部示意出了位于区域②内的第二两个第二断口OP2。第二纵向电压线YML2沿纵向Y依次穿过上显示区13和第一区域①；横向电压线XL包括位于第一区域①的中间横向电压线XLM，中间横向电压线XLM与第二区域②内的第二连接线DL2通过第三断口OP3断开，如图1-2所示，位于第一区域①中的中间横向电压线XLM的与其左端相对的右端与第四区域④中的第四连接线DL4通过第四断口OP4断开。因此，多条中间横向电压线XLM的每条在横向X上的两端分别与对应的第二连接线D2和对应的第四连接线DL4断开。
如图第二纵向电压线YML2与中间横向电压线XLM相交于第二交点P2，第二纵向电压线YML2在第二交点P2处通过第二过孔V2与中间横向电压线XLM电连接。
例如，第二纵向电压线YML2通过在纵向Y上排列的多个第二过孔V2分别与在纵向上排列的多条中间横向电压线XLM电连接。图7A-7D所示的局部具有三个第二过孔V2，但是不代表显示基板只具有三个第二过孔V2；例如多条中间横向电压线XLM的每一条均通过第二过孔V2与第二纵向电压线YML2，以将第一电源电压VSS传输到第一区域①内的每个像素子。例如，如图7B所示，通过穿过第二过孔V2的第二连接结构C2将第二纵向电压线YML2与中间横向电压线XLM。
例如，如图1所示，位于上显示区13的多条第一横向电压线XLU与第二纵向电压线YML2相交于多个第三交点P3，并且，在多个第三交点P3中的至少一部分第三交点P3的每个的位置，一条第一横向电压线XLU通过第三过孔V3与第二纵向电压线YML2电连接。从而，通过使得中间横向电压线XLM与第二纵向电压线YLM2通过第二过孔V2电连接，而第二纵向电 压线YLM2通过第三过孔V3与第一横向电压线XLU电连接，第一横向电压线XLU与第一电源电压引线4(左引线42)电连接，从而，通过第一横向电压线XLU给第二纵向电压线YML2提供第一电源电压VSS，通过第二纵向电压线YML2给中间横向电压线XLM提供第一电源电压VSS，从而实现给第一区域①内的像素提供第一电源电压VSS，而不是通过将位于第一区域①的第一电源电压线与围绕下边缘1b的边框区内的来自于焊盘3的第一电源电压引线直接连接的方式来给第一区域①的子像素提供第一电源电压VSS。结合图1和图6A、图6D可知，下引线41只与位于第一边缘显示区11P内的边缘纵向电压线YLP直接连接，而不与位于第一中间显示区11M和第二中间显示区12M内的中间纵向电压线YLM连接。
例如，第二过孔V2和第三过孔V3均贯穿第一绝缘层。
例如，第一电源电压引线4与纵向电压线YLP同层设置；例如第一电源电压引线4与纵向电压线YLP的材料相同、且是连续的一体成型结构。可以通过同一道构图工艺形成，简化了显示基板的结构和制作工艺。
例如，如图1所示，显示区1还包括与左边缘1b相对的右边缘1d，第一电源引线还包括沿右边缘1d延伸的右引线44，右引线44与上引线43电连接；多条第一横向电压线XLU的每条线沿横向X贯穿上显示区13，且多条第一横向电压线XLU的每条的与其左端相对的右端与右引线44电连接，以同时从第一横向电压线XLU的左端和右端向显示区1传递第一电源电压VSS，提高信号传递的速度，有利于提高显示基板的显示质量。
例如，多条中间纵向电压线YLM与上显示区13内的多条第一横向电压线XLU在上显示区13内彼此相交于多个第四交点P4，以连接成网格状，有利于减小上。在多个第四交点P4中一部分第四交点P4的每个的位置，一条中间纵向电压线YLM通过第四过孔V4与一条第一横向电压线XLU电连接，从而使得上显示区13中沿横向X延伸的多条第一横向电压线XLU与沿纵向Y延伸的中间纵向电压线YLM连接成网格状，以减小这部分位于上显示区13内的第一电源电压线vss的电阻，减小第一电源电压线vss上的压降。
多个第四过孔V4的位置构成的平面图案为折线(虚线)，以与由第二区域②与第三区域③的边界SL1(虚线)、第二区域②与第一区域①的第四 区域④的边界即第五线段S5(虚线)、第一区域①与第四区域④的边界即第六线段S6(虚线)、以及第四区域④与第五区域⑤的边界SL3(虚线)构成的W型折线的形状相一致(至少均为折线)，有利于保持在下显示区14中通过过孔连接的连接点和上显示区13中通过过孔连接的连接点的排布走势的均一性，以防止显示基板产生mura显示不良。
对于一条中间纵向电压线YLM通过第四过孔V4与一条第一横向电压线XLU电连接的结构与图3A-3D所示的区域R1的结构相同，可参考图3A-3D，在此不再重复。
例如，如图1所示，折线包括从左边缘1b延伸到右边缘1d的多条子折线，多条子折线中的每条子折线包括首尾相连的多个折线段；多个折线段包括沿第一方向延伸的第一线段S1(虚线)和沿第二方向延伸的第二线段S2(虚线)，第一方向与第二方向相交，且第一方向和第二方向均与横向X和纵向Y相交，第一线段S1的第一端与第二线段S2的第一端重合，例如第一线段S1的第一端与第二线段S2的第一端相交于上顶点TP；多条子折线的多个顶点位于第二纵向电压线YML2上，在顶点位置的第四过孔V4均为第二过孔V2。
例如，如图1所示，多条子折线中的每条子折线呈W形。图1中的一条呈W形的虚线走线为一条子折线。
例如，W形的子折线包括第一线段S1(虚线)和第二线段S2(虚线)、第三线段S3(虚线)和第四线段S4(虚线)，第一线段S1和第二线段S2位于第三线段S3和第四线段S4之间，第三线段S3与第一线段S1连接，第四线段S4与第二线段S2连接；第一线段S1与第四线段S4基本平行，第二线段S2与第三线段S3基本平行。
例如，纵向垂于横向，第一线段S1与横向的夹角为45°，第二线段S2与横向的夹角为45°，以尽可能保证在保持W形走线的情况下，使中间纵向电压线YLM通过第四过孔V4与第一横向电压线XLU在更多的交点处进行连接。
例如，在纵向Y上，辅助线段SA位于相邻的两条子折线的第三线段S3之间。
例如，连接线段SC、辅助线段SA和第三线段S3彼此基本平行，以保持在第一边缘显示区11P中的各个位置处通过过孔连接的连接点的排布走势的均一性，以防止显示基板产生mura显示不良。
例如，如图2所示，第二纵向电压线YML2将第一区域①分割成第一子区域A和第二子区域B，第一子区域A的结构和第二子区域B的结构相对于第二纵向电压线YML2基本呈轴对称；下显示区14包括第四区域④，第四区域④的结构与第二区域②的结构相对于第二纵向电压线YML2基本呈轴对称；穿过第一区域①和第四区域④的数据线data包括在第二子区域B中沿纵向Y延伸的第三连接线DL3、在第四区域④中沿横向X延伸的第四连接线DL4、以及位于上显示区13内沿纵向Y延伸的第六连接线DL6，第六连接线DL6与第一连接线DL1同层设置；第三连接线DL3与纵向电压线YL同层设置，第四连接线DL4与横向电压线XL同层设置，同一条数据线data的第三连接线DL3与第四连接线DL4通过第二连接孔VC2电连接；第六连接线DL6与第四连接线DL4通过第四连接孔VC4电连接，以形成数据线data上的数据信号的传导通道。
例如，显示基板10包括多条第一连接线DL1、多条第二连接线DL2、多条第三连接线DL3和多条第四连接线DL4；多条第一连接线DL1与多条第二连接线DL2分别通过多个第一连接孔VC1电连接，多条第三连接线DL3与多条第四连接线DL4分别通过多个第二连接孔VC2电连接；多个第一连接孔VC1构成的平面图案是第五线段S5，第五线段S5是第一区域①与第二区域②的边界；多个第二连接孔VC2构成的平面图案是第六线段S6，第六线段S6是第一区域①与第四区域④的边界；下显示区14还包括第五区域⑤，第五区域⑤的结构与第三区域③的结构相对于第二纵向电压线YML2基本呈轴对称，第五区域⑤中的与多个第一过孔V1对称的多个第五过孔V5的平面图案为第七线段S7。如图1所示，连接线段SC(虚线)、第五线段S5(虚线)、第六线段S6(虚线)和第七线段S7(虚线)依次连接所构成的平面图案与多条子折线中的每条子折线(例如呈W形的子折线)的平面图案相同，以保持在下显示区14中通过过孔连接的连接点和上显示区13中通过过孔连接的连接点的排布走势的均一性，以防止显示基板产生mura显示不良。
例如，如图1所示，第二区域②与第三区域③的分界线也是第二区域②的第一边SL1，第一线段S1与横向X的夹角小于第一边SL1与横向X的夹角。
例如，如图1和图2所示，第一区域①的平面形状为第一三角形，第二区域②的平面形状为第二三角形，第一三角形的在横向X上靠近左边缘1b的第二边(即第二连接线SL2)与第二三角形的在横向X上远离显示区1的左边缘1b的第一边(即第二连接线SL2)至少部分重合；第一三角形的两个下顶点DP1和DP2位于显示区1的下边缘1a上，第一三角形的两个下顶点的靠近左边缘1b的左顶点为第一子区域A的左端点PO；第一三角形为等腰三角形，第二纵向电压线YML2基本上是等腰三角形的底边的中垂线。如此排布能够使整个显示区1的数据线和第一电源电压线的排布均匀一致，防止显示基板产生mura不良。
图8A为图3中的区域R5的局部放大示意图，图8B-8C为图3中的区域R5的部分膜层的示意图。例如，参考图1和图8A-8C，边框区2包括沿左边缘1b延伸的左边框区2a，左边框区2中设置有沿横向X延伸的多条辅助连接线ACL，多条辅助连接线ACL与边缘纵向电压线YLP同层设置。。显示区1包括像素阵列，像素阵列包括沿横向X延伸的多个像素行和沿纵向Y延伸的多个像素列。例如，多条辅助连接线ACL与多条第一横向电压线XLU一一对应，与上显示区13的多个像素行一一对应。多个像素列包括最靠近左边缘1b的边缘像素列PXC0，多条边缘纵向电压线YLP包括穿过边缘像素列PXC0的外边缘纵向电压线YLP-1；多条辅助连接线ACL中的每条在横向X上的左端与左引线42电连接，例如直接连接，多条辅助连接线ACL中的每条在横向X上与其左端相对的右端与外边缘纵向电压线YLP电连接，且与对应的一条第一横向电压线XLU的左端通过第二边缘过孔VP2电连接。
例如，辅助连接线ACL与左引线42同层设置，例如两者的材料相同，是连续的一体成型结构。当然，两者的材料也可以不相同。
这里以左边框区2a中的情况为例，对于与左边框区在横向X上相对的右边框区中，也设置有多条辅助连接线ACL，右边框区中辅助连接线ACL与第一横向电压线XLU的右端的连接方式与左边框区2a中辅助连接线ACL 与第一横向电压线XLU的左端的连接方式相同，在此不再重复。
例如，参考图1，右显示区12包括沿右边缘1d延伸的第二边缘显示区12P和位于第二边缘显示区12P的靠近左显示区11的一侧的第二中间显示区12M；第二边缘显示区12P与第一边缘显示区11P相对于沿纵向Y延伸的对称轴对称，第二中间显示区12M与第一中间显示区11M相对于第二纵向电压线YML2呈轴对称。第一中间显示区11M和第二中间显示区12M构成中间显示区，第二子区域B位于第二中间显示区12M，第一区域①位于中间显示区。
例如，第一电源电压引线4还包括沿下边缘1a的对应于第二边缘显示区12P的部分延伸的另一下引线45，例如给第二边缘显示区12P提供第一电源电压VSS的边缘电压线与另一下引线45接触以电连接，例如，两者直接连接，即第二边缘显示区12P提供第一电源电压VSS的边缘电压线与另一下引线451彼此接触，且第二边缘显示区12P提供第一电源电压VSS的边缘电压线与另一下引线45之间不存在任何其他的结构作为两者连接的媒介；例如，第二边缘显示区12P提供第一电源电压VSS的边缘电压线与另一下引线45同层设置，且构成连续的一体成型结构。
当然，在其他实施例中，第二边缘显示区12P提供第一电源电压VSS的边缘电压线与另一下引线45可以异层设置，两者通过过孔彼此接触。
例如，显示基板10还包括第二电源电压线vdd(图1未示出)，第二电源电压线vdd配置为给子像素提供不同于第一电源电压VSS的第二电源电压；例如，第一电源电压VSS与第二电源电压VDD极性相反。例如第一电源电压VSS为低电平，第二电源电压VDD为高电平。当然，也可以是第一电源电压VSS为高电平，第二电源电压VDD为低电平。
例如，纵向电压线YL与上显示区13中的数据线data同层设置，横向电压线XL第二电源电压线同层设置。
图10为根据本公开实施例的像素电路的等效电路图，图11A至图11H包括像素电路中不同膜层的示意图，图11I为图11A至图11F所示膜层层叠示意图。图11A中的虚线框代表一个子像素的区域。
在一些示例中，如图10所示，显示基板还包括多个子像素，至少部分子 像素包括发光元件120以及与发光元件120电连接的像素电路110。
例如，如图10至图11I所示，像素电路包括多个晶体管以及至少一个电容。例如，像素电路包括第二复位晶体管T1、阈值补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6，第一复位控制晶体管T7、第三复位晶体管T8以及存储电容C。
例如，如图10至图11I所示，显示基板还包括复位电源信号线561、551、和554，扫描信号线552、531和523，第二电源电压线vdd，复位控制信号线522、532和553，发光控制信号线521以及数据线582。
例如，如图10至图11I所示，阈值补偿晶体管T2的第一极与驱动晶体管T3的第一极电连接，阈值补偿晶体管T2的第二极与驱动晶体管T3的栅极电连接，阈值补偿晶体管T2的栅极与扫描信号线531和552电连接以接收补偿控制信号；第一复位控制晶体管T7的第一极与复位电源信号线561电连接以接收复位信号Vinit2，第一复位控制晶体管T7的第二极与发光元件的第一电极电连接(即N4节点)，第一复位控制晶体管T7的栅极与复位控制信号线522电连接以接收复位控制信号Reset(N+1)；第三复位晶体管T8的第一极与复位电源信号线551电连接以接收复位信号Vref，第三复位晶体管T8的第二极与驱动晶体管T3的第二极电连接，第三复位晶体管T8的栅极与复位控制信号线522电连接；数据写入晶体管T4的第一极与驱动晶体管T3的第二极电连接，数据写入晶体管T4的第二极与数据线200(数据线data)电连接以接收数据信号Data，数据写入晶体管T4的栅极与扫描信号线523电连接以接收扫描信号Gate；存储电容C的第一极与第二电源电压线vdd电连接，存储电容C的第二极与驱动晶体管T3的栅极电连接；第二复位晶体管T1的第一极与复位电源信号线554电连接以接收复位信号Vinit1，第二复位晶体管T1的第二极与驱动晶体管T3的栅极电连接，第二复位晶体管T1的栅极与复位控制信号线553和532电连接以接收复位控制信号Reset(N)；第一发光控制晶体管T6的栅极与发光控制信号线521电连接以接收发光控制信号EM，第一发光控制晶体管T6的第一极与驱动晶体管T3的第一极电连接，第一发光控制晶体管T6的第二极与发光元件120的第一电极电连接；第二发光控制晶体管T5的第一极与第二电源电压线vdd电连接以接收第一 电源信号VDD，第二发光控制晶体管T5的第二极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T5的栅极与发光控制信号线521电连接以接收发光控制信号EM，发光元件120的第二电极与电压端VSS(后续第三信号线600)电连接。上述电源信号线指输出电压信号VDD的信号线，可以与电压源连接以输出恒定的电压信号，例如正电压信号。
需要说明的是，在本公开实施例中，各像素电路除了可以为图10所示的8T1C(即八个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管的结构，如7T1C结构、7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。
图11A示出了有源半导体图案510。例如，如图11A所示，有源半导体图案510可用于制作上述的驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6、第一复位控制晶体管T7以及第三复位控制晶体管T8的有源层以用于形成上述晶体管的沟道区。有源半导体图案510包括各子像素的上述晶体管的有源层图案(沟道区)和掺杂区图案(源漏区)，且同一像素电路中的上述晶体管的有源层图案和掺杂区图案一体设置。
例如，有源半导体图案510可以包括一体形成的低温多晶硅层，源极区域和漏极区域可以通过掺杂等进行导体化实现各结构的电连接。例如，上述的源极区域和漏极区域可为掺杂有p型杂质的区域。
图11B示出了位于有源半导体图案510远离衬底基板一侧的第一导电层图案520。例如，如图11B所示，第一导电层图案520包括复位控制信号线522、扫描信号线523、电容的一极524以及发光控制信号线521。例如，第一导电层图案520可以包括驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6、第一复位控制晶体管T7以及第三复位控制晶体管T8的栅极。
需要说明的是，图11A中的各虚线矩形框示出了有源半导体图案510与第一导电层图案520交叠的各个部分，即沟道区。作为各个晶体管的沟道区，在每个沟道区两侧的有源半导体层通过离子掺杂等工艺导体化作为各个晶体管的第一极和第二极。晶体管的源极、漏极在结构上可以是对称的，所以其 源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
例如，如图11B和图11I所示，数据写入晶体管T4的栅极可以为扫描信号线523与有源半导体图案510交叠的部分；第一发光控制晶体管T6的栅极可以为发光控制信号线521与有源半导体图案510交叠的第一部分，第二发光控制晶体管T5的栅极可以为发光控制信号线521与有源半导体图案510交叠的第二部分。第三复位晶体管T8的栅极为复位控制信号线522与有源半导体图案510交叠的第一部分，第一复位控制晶体管T7的栅极为复位控制信号线522与有源半导体图案510交叠的第二部分。
图11C示出了第一导电层图案520远离衬底基板一侧的第二导电层图案530。例如，如图11C所示，第二导电层图案530包括扫描信号线531、电容C的第二极533以及复位控制信号线532。
图11D示出了第二导电层图案530远离衬底基板一侧的有源层图案540。例如，如图11D所示，有源层图案540包括第二复位晶体管T1和阈值补偿晶体管T2的沟道区。例如，第二复位晶体管T1和阈值补偿晶体管T2中的有源层采用氧化物半导体的情况下，因用氧化物半导体的晶体管具备磁滞特性好，漏电流低的特点，同时迁移率(Mobility)较低，故可以采用氧化物半导体的晶体管代替晶体管中的低温多晶硅材料，形成低温多晶硅-氧化物的(LTPO)像素电路，实现低漏电，利于提高晶体管的栅极电压的稳定性。
例如，如图11C、3D和图11I所示，第二复位晶体管T1的栅极可以为复位控制信号线532与有源层图案540交叠的部分，阈值补偿晶体管T2的栅极可以为扫描信号线531与有源层图案540交叠的部分。
图11E示出了有源层图案540远离衬底基板一侧的第三导电层550。例如，如图11E所示，第三导电层550包括复位电源信号线554、复位控制信号线553、扫描信号线552以及复位电源信号线551。
例如，如图11C至图11F以及图11I所示，复位控制信号线553与第二复位晶体管T1的沟道区交叠，第二复位晶体管T1包括位于有源层两侧的双 栅极，第二复位晶体管T1为双栅晶体管；扫描信号线552与阈值补偿晶体管T2的沟道区交叠，阈值补偿晶体管T2包括位于有源层两侧的双栅极，阈值补偿晶体管T2为双栅晶体管。
例如，第二复位晶体管T1和阈值补偿晶体管T2可以为N型晶体管。数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6、第一复位控制晶体管T7以及第三复位控制晶体管T8可以为P型晶体管。
图11F示出了位于第三导电层550远离衬底基板一侧的第四导电层560。例如，如图11F所示，第四导电层560包括复位电源信号线561、连接部568、连接部569、连接部563、连接部567、连接部562、连接部564、连接部565以及连接部566。
例如，如图10至图11I所示，连接部568的两端连接复位电源信号线551，中间连接第三复位晶体管T8的第一极；连接部569连接数据线data与数据写入晶体管T4的第二极；连接部563用于电连接数据写入晶体管T4的第一极与第三复位晶体管T8的第二极，以将复位信号Vref引到N2节点；连接部567用于电连接驱动晶体管T3的第一极与阈值补偿晶体管T2的第一极；连接部562的中间连接第二电源电压线vdd(如图11H，即第二电源电压线vdd)，连接部562的两端连接电容的一极533；连接部564的一端与存储电容C的第二极533连接，连接部564的另一端与第二发光控制晶体管T5的第一极连接；连接部565用于电连接发光元件的第一电极与第一发光控制晶体管T6的第二极；连接部566用于电连接复位电源信号线554与第二复位晶体管T1的第一极。
图11G示出了位于第四导电层560远离衬底基板一侧的第五导电层570。例如，如图11G所示，第五导电层570包括连接部573、连接部575、第二电源电压线572(传输第二电源电压VDD)、连接部574、横向电压线XL(例如为中间横向电压线XLM等)。例如，第五导电层570还包括第四连接线。
例如，如图10至图11G所示，连接部573用于与数据线data电连接，例如数据线data通过连接部573与显示区1中的一些沿横向X延伸的与数据线data异层设置的连接线电连接以向该连接线传输数据信号DATA；连接部 575为预留垫，第一连接线可以通过该预留垫与第二连接线电连接，或者，纵向电压线可以通过该预留垫与横向电压线电连接。例如，连接部574与连接部565电连接以实现第一发光控制晶体管T6的第二极与发光元件的第一电极的电连接。例如，第二电源电压线572与第二电源电压线vdd电连接。
图11H示出了位于第五导电层570远离衬底基板一侧的第六导电层580。例如，如图11H所示，第六导电层580包括数据线data、第二电源电压线vdd、第五连接线450、连接部584和连接部585。
例如，连接部584和连接部585与不同发光元件的第一电极电连接。
例如，如图11G和图11H所示，数据线data包括转接垫290，数据线data通过转接垫290与连接部573连接，以与显示区1中的一些沿横向X延伸的与数据线data异层设置的连接线电连接，以向该连接线传输数据信号DATA。例如，纵向电压线YL均包括转接垫459，纵向电压线YL可通过转接垫459纵向电压线YL可通过转接垫459与通过相应的转接垫459与连接部575电连接，连接部575与对应的需要与该纵向电压线YL电连接的横向电压线XL电连接，从而实现纵向电压线YL与横向电压线XL电连接。
如图12所示，本公开至少一实施例还提供一种显示装置100，包括公开至少实施例提供的任意一种显示基板10。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。

Claims (27)

  1. 一种显示基板，包括：
    显示区，设置有子像素，且具有沿横向延伸的下边缘和沿纵向延伸的左边缘，其中，所述横向与所述纵向相交，所述显示区包括在所述横向上排列的左显示区和右显示区，所述左显示区包括沿所述左边缘延伸的第一边缘显示区和位于所述第一边缘显示区的靠近所述右显示区的第一中间显示区；
    非显示区，包括围绕至少部分所述显示区的边框区；
    第一电源电压引线，配置为提供第一电源电压，且位于所述边框区内，其中，所述第一电源电压引线包括沿所述下边缘的对应于第一边缘显示区的部分延伸的下引线，所述第一电源电压引线不沿所述下边缘对应于所述第一中间显示区的部分延伸；
    第一电源电压线，包括位于所述第一边缘显示区沿的边缘电压线和位于所述第一中间显示区的中间电压线，其中，所述边缘电压线与所述下引线接触而电连接以给所述位于所述第一边缘显示区的子像素提供所述第一电源电压，并且，所述中间电压线与所述下引线间隔开。
  2. 根据权利要求1所述的显示基板，其中，
    所述第一电源电压线包括沿所述纵向延伸的纵向电压线和沿所述横向延伸的横向电压线，所述纵向电压线与所述横向电压线异层设置；
    所述纵向电压线包括位于所述第一边缘显示区的边缘纵向电压线，所述横向电压线包括位于所述第一边缘显示区且与所述边缘纵向电压线相交的边缘横向电压线，所述边缘纵向电压线与所述边缘横向电压线构成所述边缘电压线；
    所述第一电源电压引线还包括沿所述显示区的左边缘延伸的左引线，所述边缘纵向电压线与所述下引线直接连接，所述边缘横向电压线与所述左引线直接连接。
  3. 根据权利要求2所述的显示基板，还包括数据线，其中，所述子像素包括：驱动晶体管、发光器件和数据晶体管，所述驱动晶体管配置为控制流经所述发光器件的驱动电流的大小，所述发光器件配置为接收所述驱动电流 且被所述驱动电流驱动以发光，所述数据晶体管配置为响应于第一控制信号将数据信号写入所述驱动晶体管的栅极，所述数据线配置为给所述子像素传输所述数据信号；
    所述显示区域包括下显示区和上显示区，所述下显示区靠近所述下边缘，所述上显示区在纵向上位于所述下显示区的远离所述下边缘的一侧；
    所述下显示区包括第一区域和第二区域，所述第一区域包括在所述横向上靠近所述左边缘的第一子区域和远离所述左边缘的第二子区域，穿过所述第一子区域和所述第二区域的所述数据线包括在所述第一子区域内沿所述纵向延伸的第一连接线和在所述第二区域内沿所述横向延伸的第二连接线；所述第一连接线与所述纵向电压线同层设置，所述第二连接线与所述横向电压线同层设置，同一条所述数据线的所述第一连接线与所述第二连接线通过第一连接孔电连接；所述第一子区域位于所述第一中间显示区内，所述第二区域至少部分位于所述中间所述显示区内；
    所述第一子区域具有在所述横向上最靠近所述显示区的左边缘的左端点，沿所述纵向延伸且经过所述左端点的直线为所述第一边缘显示区与所述第一中间显示区的分界线。
  4. 根据权利要求3所述的显示基板，其中，所述分界线穿过所述第二区域且将所述第二区域分割成靠近所述显示区的左边缘的第一子区域和远离所述显示区的左边缘的第二子区域，所述第一子区域位于所述第一边缘显示区内，所述第二子区域位于所述第一中间显示区内；
    所述下显示区还包括：
    第三区域，位于所述第一边缘显示区内，且在所述横向上位于所述第二区域的远离所述第一区域的一侧，其中，
    所述边缘横向电压线包括位于所述第三区域的下部边缘横向电压线，所述边缘纵向电压线穿过所述第三区域，且与所述下部边缘横向电压线相交于第一交点，所述下部边缘横向电压线的左端与所述左引线电连接，所述下部边缘横向电压线的与其左端相对的右端与在所述第二区域中的所述第二连接线通过第一断口断开；
    所述纵向电压线包括多条所述边缘纵向电压线和多条所述边缘横向电压 线，所述多条所述边缘纵向电压线和多条所述边缘横向电压线彼此交织成网格，所述网格包括多个所述第一交点；
    在所述多个第一交点中的一部分第一交点的每个的位置，一条所述边缘纵向电压线通过第一过孔与一条所述下部边缘横向电压线电连接。
  5. 根据权利要求4所述的显示基板，其中，所述多条边缘纵向电压线通过多个所述第一过孔与所述多条边缘横向电压线电连接，所述多个第一过孔的位置构成的平面图案为位于所述第三区域内的连接线段，所述连接线段的延伸方向与所述第一方向和所述第二方向均相交。
  6. 根据权利要求4或5所述的显示基板，其中，所述第三区域是由所述第二区域的在所述横向上靠近所述左边缘的第二边、所述左边缘以及所述下边缘所限定出的拐角区。
  7. 根据权利要求6所述的显示基板，其中，所述边框区包括围绕所述拐角区的边框角区域，所述边框角区域中设置有呈网格状的辅助第一电源电压线，所述网格状的辅助第一电源电压线包括：
    多条纵向辅助电压线，沿所述纵向延伸，与所述纵向电压线同层设置，其中，所述多条纵向辅助电压线中的每条在所述纵向上的第一端与所述第一电源电压引线直接连接，所述多条纵向辅助电压线的每条在所述纵向上的与其第一端相对的第二端与穿过所述拐角区的一条所述边缘纵向电压线电连接；以及
    多条横向辅助电压线，沿所述横向延伸，与所述多条纵向辅助电压线同层设置，其中，所述多条横向辅助电压线中的每条在所述横向上的一端与所述第一电源电压引线直接连接，所述多条横向辅助电压线中的每条在所述横向上的与其第一端相对的第二端与一条所述边缘纵向电压线电连接。
  8. 根据权利要求7所述的显示基板，其中，
    所述显示区包括像素阵列，所述像素阵列包括沿所述横向延伸的多个像素行和沿所述纵向延伸的多个像素列；所述多个像素行包括靠近所述下边缘的多个边缘像素行；所述多条横向辅助电压线与所述多个边缘像素行一一对应，所述多个边缘像素行中的每个边缘像素行包括最靠近所述左边缘的边缘子像素，所述多条边缘纵向电压线包括穿过每个所述边缘像素行的边缘子像 素的最边缘纵向电压线；
    所述多条横向辅助电压线中的每条的第二端与穿过对应的所述边缘像素行的最边缘纵向电压线电连接，且通过第一边缘过孔与穿过对应的所述边缘像素行的所述边缘横向电压线电连接。
  9. 根据权利要求5所述的显示基板，其中，所述横向电压线还包括：
    多条第一横向电压线，在所述纵向上排列，位于所述上显示区，其中，所述第一横向电压线的左端与所述左引线电连接，所述边缘横向电压线还包括位于所述上显示区的上部边缘横向电压线，所述上部边缘横向电压线作为一条所述第一横向电压线的一部分；
    所述纵向电压线还包括：
    多条中间纵向电压线，在所述横向上排列，沿所述纵向穿过部分所述第一中间显示区且穿过所述上显示区，其中，所述多条中间纵向电压线、所述多条边缘纵向电压线与所述多条第一横向电压线交织成网格；
    所述多条边缘纵向电压线与所述多条第一横向电压线在所述第一边缘显示区内相交于多个辅助交点，在所述多个辅助交点中的一部分辅助交点的每个的位置，一条所述边缘纵向电压线通过辅助过孔与一条所述第一横向电压线电连接，所述多条边缘纵向电压线通过多个所述辅助过孔与所述多条第一横向电压线电连接；
    多个所述辅助过孔的位置构成的平面图案为位于所述第一边缘显示区内的辅助线段，所述辅助线段的远离所述左边缘的一端悬置。
  10. 根据权利要求9所述的显示基板，其中，所述辅助线段的延伸方向与所述连接线段的延伸方向相同；
    所述显示基板包括多个所述辅助线段，所述连接线段、所述多个辅助线段沿所述纵向彼此间隔排列。
  11. 根据权利要求9或10所述的显示基板，其中，所述显示区还包括与所述下边缘相对的上边缘，所述第一电源电压引线还包括沿所述上边缘延伸的上引线，所述上引线与所述左引线电连接；
    所述边缘纵向电压线的上端与所述上引线连接，所述边缘纵向电压线的与其上端相对的下端与所述下引线直接连接；
    所述纵向电压线包括位于所述第一中间显示区的中间纵向电压线，所述中间纵向电压线包括：
    第一纵向电压线，沿所述纵向依次穿过所述上显示区和至少部分所述第二区域，其中，所述第一纵向电压线的上端与所述上引线电连接，所述第一纵向电压线的与其上端相对的下端与所述在第一子区域内的所述第一连接线通过第二断口断开；以及
    第二纵向电压线，沿所述纵向依次穿过所述上显示区和所述第一区域，其中，所述横向电压线包括位于所述第一区域的中间横向电压线，所述中间横向电压线与所述第二区域内的第二连接线通过第三断口断开，所述第二纵向电压线与所述中间横向电压线相交于第二交点，所述第二纵向电压线在所述第二交点处通过第二过孔与所述中间横向电压线电连接。
  12. 根据权利要求11所述的显示基板，其中，所述多条第一横向电压线与所述多条第二纵向电压线相交于多个第三交点，并且，在所述多个第三交点中的至少一部分第三交点的每个的位置，一条所述第一横向电压线通过第三过孔与一条所述第二纵向电压线电连接。
  13. 根据权利要求11或12所述的显示基板，其中，所述显示区还包括与所述左边缘相对的右边缘，所述第一电源引线还包括沿所述右边缘延伸的右引线，所述右引线与所述上引线电连接；
    所述多条第一横向电压线的每条线沿所述横向贯穿所述上显示区，且所述多条第一横向电压线的每条的与其左端相对的右端与所述右引线电连接。
  14. 根据权利要求13所述的显示基板，其中，所述多条中间纵向电压线与所述多条第一横向电压线在所述上显示区内彼此相交于多个第四交点，在所述多个第四交点中一部分第四交点的每个的位置，一条所述中间纵向电压线通过第四过孔与一条所述第一横向电压线电连接；
    多个所述第四过孔的位置构成的平面图案为折线。
  15. 根据权利要求14所述的显示基板，其中，所述折线包括从所述左边缘延伸到所述右边缘的多条子折线，所述多条子折线中的每条子折线包括首尾相连的多个折线段；
    所述多个折线段包括沿第一方向延伸的第一线段和沿第二方向延伸的第 二线段，所述第一方向与所述第二方向相交，且所述第一方向和所述第二方向均与所述横向和所述纵向相交，所述第一线段的第一端与所述第二线段的第一端相交于上顶点；
    所述多条子折线的多个所述顶点位于第二纵向电压线上，在所述顶点位置的所述第四过孔均为所述第二过孔。
  16. 根据权利要求15所述的显示基板，其中，所述多条子折线中的每条子折线呈W形。
  17. 根据权利要求16所述的显示基板，其中，所述W形的子折线包括所述第一线段和所述第二线段、第三线段和第四线段，所述第一线段和所述第二线段位于所述第三线段和第四线段之间，所述第三线段与所述第一线段连接，所述第四线段与所述第二线段连接；
    所述第一线段与所述第四线段基本平行，
    所述第二线段与所述第三线段基本平行。
  18. 根据权利要求17所述的显示基板，其中，所述纵向垂于所述横向，所述第一线段与所述横向的夹角为45°，所述第二线段与所述横向的夹角为45°。
  19. 根据权利要求17或18所述的显示基板，其中，在所述纵向上，所述辅助线段位于相邻的两条所述子折线的第三线段之间。
  20. 根据权利要求19所述的显示基板，其中，所述连接线段、所述辅助线段和所述第三线段彼此基本平行。
  21. 根据权利要求15-20中任一所述的显示基板，其中，所述第二纵向电压线将所述第一区域分割成所述第一子区域和所述第二子区域，第一子区域的结构和第二子区域的结构相对于所述第二纵向电压线基本呈轴对称；
    所述下显示区包括第四区域，所述第四区域的结构与所述第二区域的结构相对于所述第二纵向电压线基本呈轴对称；穿过所述第一区域和所述第四区域的所述数据线包括在所述第二子区域中沿所述纵向延伸的第三连接线和在所述第四区域中沿所述横向延伸的第四连接线；所述第三连接线与所述纵向电压线同层设置，所述第四连接线与所述横向电压线同层设置，同一条所述数据线的所述第三连接线与所述第四连接线通过第二连接孔电连接；
    位于所述第一区域中的所述中间横向电压线的与其左端相对的右端与所述第四区域中的所述第四连接线通过第四断口断开。
  22. 根据权利要求21所述的显示基板，其中，所述显示基板包括多条所述第一连接线、多条所述第二连接线、多条所述第三连接线和多条所述第四连接线；所述多条第一连接线与所述多条第二连接线分别通过多个所述第一连接孔电连接，所述多条第三连接线与所述多条第四连接线分别通过多个所述第二连接孔电连接；
    所述多个第一连接孔构成的平面图案是第五线段，所述第五线段是所述第一区域与所述第二区域的边界；
    所述多个第二连接孔构成的平面图案是第六线段，所述第六线段是所述第一区域与所述第四区域的边界；
    所述下显示区还包括第五区域，所述第五区域的结构与所述第三区域的结构相对于所述第二纵向电压线基本呈轴对称，所述第五区域中的与所述多个第一过孔对称的多个第五过孔的平面图案为第七线段；
    所述连接线段、所述第五线段、所述第六线段和所述第七线段依次连接所构成的平面图案与所述多条子折线中的每条子折线的平面图案相同。
  23. 根据权利要求21或22所述的显示基板，其中，
    所述第一区域的平面形状为第一三角形，所述第二区域的平面形状为第二三角形，所述第一三角形的在所述横向上靠近所述左边缘的第一边与所述第二三角形的在所述横向上远离所述显示区的左边缘的第一边至少部分重合；所述第一三角形的两个下顶点位于所述显示区的下边缘上，所述第一三角形的两个下顶点的靠近所述左边缘的左顶点为所述第一子区域的所述左端点；
    第一三角形为等腰三角形，所述第二纵向电压线基本上是所述等腰三角形的底边的中垂线。
  24. 根据权利要求9-23中任一所述的显示基板，其中，所述边框区包括沿所述左边缘延伸的左边框区，所述左边框区中设置有沿所述横向延伸的多条辅助连接线，所述多条辅助连接线与所述边缘纵向电压线同层设置；
    所述显示区包括像素阵列，所述像素阵列包括沿所述横向延伸的多个像 素行和沿所述纵向延伸的多个像素列；所述多个像素列包括最靠近所述左边缘的边缘像素列，所述多条边缘纵向电压线包括穿过所述边缘像素列的外边缘纵向电压线；
    所述多条辅助连接线中的每条在所述横向上的左端与所述左引线电连接，所述多条辅助连接线中的每条在所述横向上与其左端相对的右端与所述外边缘纵向电压线电连接，且与对应的一条所述第一横向电压线的左端通过第二边缘过孔电连接。
  25. 根据权利要求13-23中任一所述的显示基板，其中，所述右显示区包括沿所述右边缘延伸的第二边缘显示区和位于所述第二边缘显示区的靠近所述左显示区的一侧的第二中间显示区；
    所述第二边缘显示区与所述第一边缘显示区相对于沿所述纵向延伸的对称轴对称，所述第二中间显示区与所述第一中间显示区相对于所述第二纵向电压线呈轴对称。
  26. 根据权利要求2-23中任一所述的显示基板，其中，所述显示基板还包括：
    第二电源电压线，配置为给所述子像素提供不同于所述第一电源电压的第二电源电压；
    所述纵向电压线与所述上显示区中的数据线同层设置，所述横向电压线所述第二电源电压线同层设置。
  27. 一种显示装置，包括权利要求1-26中任一项所述的显示基板。
PCT/CN2023/107944 2022-07-28 2023-07-18 显示基板以及显示装置 WO2024022172A1 (zh)

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