WO2024022254A1 - 显示基板以及显示装置 - Google Patents

显示基板以及显示装置 Download PDF

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Publication number
WO2024022254A1
WO2024022254A1 PCT/CN2023/108663 CN2023108663W WO2024022254A1 WO 2024022254 A1 WO2024022254 A1 WO 2024022254A1 CN 2023108663 W CN2023108663 W CN 2023108663W WO 2024022254 A1 WO2024022254 A1 WO 2024022254A1
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WIPO (PCT)
Prior art keywords
line
connection
lines
area
signal
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PCT/CN2023/108663
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English (en)
French (fr)
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WO2024022254A9 (zh
Inventor
王梦奇
于子阳
蒋志亮
胡明
陈飞
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2024022254A1 publication Critical patent/WO2024022254A1/zh
Publication of WO2024022254A9 publication Critical patent/WO2024022254A9/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • Embodiments of the present disclosure relate to a display substrate and a display device.
  • thin film transistor can include amorphous silicon (a-Si) TFT, low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) TFT, oxide (such as indium gallium zinc oxide TFT) wait.
  • a-Si amorphous silicon
  • LTPS Low Temperature Poly-Silicon
  • oxide such as indium gallium zinc oxide TFT
  • LTPO Low Temperature Polycrystalline Oxide
  • LTPO is a low-power display technology.
  • LTPO technology combines low-temperature polysilicon technology and oxide technology to prepare LTPS TFT and oxide TFT in the display panel, thus combining LTPS TFT
  • the advantages of TFT and the advantages of oxide TFTs are used to maximize the advantages of ultra-high mobility of low-temperature polysilicon and the advantages of small leakage current of oxide to achieve better display performance.
  • OLED organic light-emitting diode
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • the display substrate includes a base substrate and a plurality of first signal lines and a plurality of second signal lines located on the base substrate.
  • the base substrate includes a first region and a second region, the first region is located around the second region; the plurality of first signal lines do not pass through the second region; the plurality of first signal lines do not pass through the second region; The two signal lines are located on different layers from the plurality of first signal lines and do not pass through the second area.
  • the plurality of first signal lines include extension lines A portion of the first signal lines passing through the second area, each first signal line in the portion of the first signal lines including a first sub-signal line and a second sub-signal line located on both sides of the second area, The first sub-signal line and the second sub-signal line are connected through a first connection extending along the first direction.
  • the line is electrically connected to a second connection line extending along the second direction, and the part of the first signal line is electrically connected to a plurality of first connection lines and a plurality of second connection lines; the plurality of second signal lines A portion of the second signal line including an extension line passing through the second area, each second signal line in the portion of the second signal line includes a third sub-signal line and a fourth sub-signal line located on both sides of the second area.
  • the third sub-signal line and the fourth sub-signal line are electrically connected through a third connection line extending along the first direction and a fourth connection line extending along the second direction, and the Some of the second signal lines are electrically connected to a plurality of third connection lines and a plurality of fourth connection lines; in a direction perpendicular to the substrate, at least one second connection line overlaps with at least one third connection line, And on the same side of the second area, at least one first connection line is located on a side of at least one third connection line away from the second area.
  • the plurality of first signal lines include data lines
  • the plurality of second signal lines at least include light emitting control signal lines.
  • a minimum distance between a fourth connection line closest to the second area and an edge of the second area is smaller than a minimum distance between a first connection line closest to the second area and The minimum distance between the edges of the second area.
  • a first group of connection lines among the plurality of second connection lines is located on a side of at least one fourth connection line close to the second area.
  • a second group of connection lines among the plurality of second connection lines is located on a side of the at least one fourth connection line away from the second area.
  • the first set of connection lines overlaps the third connection line in a direction perpendicular to the base substrate, and the second set of connection lines overlaps the third connection line.
  • the connecting lines do not overlap.
  • a second connection line among the first group of connection lines closest to the second group of connection lines and a second connection line among the second group of connection lines closest to the first group of connection lines The distance between a second connecting line is the first distance, the distance between two adjacent second connecting lines in the second group of connecting lines is the second distance, and the first distance is the same as the second connecting line.
  • the distance ratio is greater than 2.
  • the first connection line connected to the one of the second connection lines in the first group of connection lines that is closest to the second group of connection lines includes two or more first connection lines respectively located on the one of the first group of connection lines.
  • the two connecting lines are two parts on both sides in the first direction.
  • the first connection line connected to the one second connection line of the first set of connection lines closest to the second set of connection lines extends to the second set of connection lines.
  • the position of the second connecting line closest to the first group of connecting lines among the connecting lines is not limited
  • each of the N first connection lines that are respectively connected to the N second connection lines in the first set of connection lines that are closest to the second set of connection lines Each line includes two parts respectively located on both sides of the second connection line connected thereto in the first direction, and among the N first connection lines arranged in the direction close to the second area, the The length of the part of the first connection line that is located on the side of the second connection line connected to it and close to the second group of connection lines gradually decreases, N is a positive integer greater than or equal to 1, and is located in the second area The number of the second connecting lines in the first group of connecting lines on the center side is greater than or equal to N.
  • a second signal line closest to the second area is located closest to Between a fourth connection line in the second area and an adjacent fourth connection line.
  • At least one first signal line among the plurality of first signal lines whose extension line does not pass through the second area is located on the first connection The line is close to the side of the second area.
  • a distance between a first connection line and a third connection line that are closest to each other among the plurality of first connection lines and the plurality of third connection lines is the same as that between two adjacent ones.
  • the ratio of the distances between the third connecting lines is 0.8 to 1.2.
  • At least one first connection line and at least one third connection line are located on the same layer, and at least one second connection line and at least one fourth connection line are located on the same layer.
  • At least one first connection line and at least one third connection line are located on the same layer as the plurality of first signal lines.
  • the plurality of second signal lines are located between the plurality of first signal lines and the substrate, and the fourth connection line is located between the plurality of first signal lines. and the plurality of second signal lines.
  • the first area is a display area
  • the first area surrounds the second area
  • the base substrate further includes a peripheral area surrounding the display area
  • the second group of connection lines includes the second connection lines located in the first area and the second connection lines located in the peripheral area.
  • the second connection lines located in the first area and the second connection lines are located in the peripheral area.
  • a connection line is arranged in different layers, and the second connection line and the first connection line located in the peripheral area are arranged in the same layer.
  • the second connection line located in the peripheral area and the first signal line are arranged on the same layer.
  • At least one second connection line and at least one fourth connection line in the first group of connection lines are arranged in the same layer and spaced apart, and are located on the same straight line.
  • At least one first signal line connected to the second group of connection lines is connected to each third signal line in a direction perpendicular to the base substrate. All four connecting lines overlap.
  • the orthographic projection of each first connecting line on a straight line extending along the first direction overlaps with the orthographic projection of each third connecting line on the straight line; at least one second connecting line
  • the orthographic projection on the straight line extending along the second direction does not overlap with the orthographic projection of the at least one fourth connecting line on the straight line.
  • the display substrate further includes: a light-emitting element and a pixel circuit located on the base substrate, and the pixel circuit is electrically connected to the light-emitting element.
  • the pixel circuit includes a driving transistor, a light-emitting control transistor and a reset transistor.
  • the gate of the light-emitting control transistor is electrically connected to the light-emitting control signal line.
  • the first electrode of the light-emitting control transistor is connected to the first electrode of the driving transistor.
  • the second electrode of the light-emitting control transistor is electrically connected to the light-emitting element; the gate electrode of the reset transistor is electrically connected to the reset control signal line, and one electrode of the reset transistor is electrically connected to the third electrode of the driving transistor.
  • Two poles are electrically connected, or one pole of the reset transistor is electrically connected to the second pole of the light emitting control transistor; the second signal line includes the reset control signal line.
  • the display substrate further includes: a light-emitting element and a pixel circuit located on the substrate substrate, the pixel circuit is electrically connected to the light-emitting element; wherein the pixel circuit includes at least one N type thin film transistor and at least one P-type thin film transistor; the second signal line includes a signal line connected to the gate electrode of at least one of the P-type thin film transistor.
  • the display substrate further includes: a light-emitting element and a pixel circuit located on the base substrate, the pixel circuit is electrically connected to the light-emitting element; wherein the pixel circuit includes at least one oxide
  • the second signal line includes a signal line connected to the gate of at least one low-temperature polysilicon thin film transistor.
  • the first area is a display area, the first area surrounds the second area, and the substrate substrate further includes a peripheral area surrounding the display area; the display substrate It also includes: a plurality of fifth connection lines extending along the first direction and a plurality of sixth connection lines extending along the second direction, and the first connection lines are located on the same layer and on the same straight line.
  • the fifth connection line is spaced apart from the first connection line, and the fifth connection line and the third connection line are located at the same layer and in the same straight line and are spaced apart from the second connection line.
  • the connecting lines are on the same layer and on the same
  • the sixth connecting line in a straight line is spaced apart from the second connecting line, and the sixth connecting line and the fourth connecting line located on the same layer and in the same straight line as the fourth connecting line are spaced apart, And at least one of the fifth connection line and the sixth connection line is electrically connected to a third signal line, and the third signal line is located in the peripheral area.
  • At least one of the distance between the fifth connection line and the first connection line and the distance between the fifth connection line and the third connection line is different from that of the third connection line.
  • the film layer where the four connection lines are located overlaps, and at least one of the distance between the sixth connection line and the second connection line and the distance between the sixth connection line and the fourth connection line is different from that of the third connection line.
  • the film layers where a connecting line is located overlap.
  • At least one first connection line is provided with two first signal lines immediately adjacent to the first connection line on both sides, and the connection between the two first signal lines and the first connection line is The ratio of the minimum distance between the two first signal lines is 0.9 to 1.1; at least one third connection line is provided with two first signal lines immediately adjacent to the third connection line on both sides, and the two first signal lines are connected to the third connection line. The ratio of the minimum distances between lines is 0.9 to 1.1.
  • Another embodiment of the present disclosure provides a display device, including any of the above display substrates.
  • FIG. 1 is a partial plan view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 2 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure.
  • 3A to 3H include schematic diagrams of different film layers in the pixel circuit.
  • FIG. 3I is a schematic diagram of the film layer stacking shown in FIGS. 3A to 3F.
  • FIG. 4 is a partial planar structural schematic diagram provided according to another example of an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of part of the film layer in area E1 shown in FIG. 4 .
  • Figures 6 and 7 are schematic diagrams of two conductive layers at the position shown in Figure 5.
  • FIG. 8 is a schematic diagram of part of the film layer in area E2 shown in FIG. 4 .
  • Figures 9 to 10 are schematic diagrams of two conductive layers at the position shown in Figure 8.
  • FIG. 11 is a schematic diagram of part of the film layer in area E3 shown in FIG. 4 .
  • FIG. 12 is a schematic diagram of part of the film layer in area E4 shown in FIG. 4 .
  • FIG. 13 is a schematic diagram of a partial film layer including the area E1 shown in FIG. 4 .
  • Figures 14 and 15 are schematic diagrams of two conductive layers at the position shown in Figure 13.
  • FIG. 16 is a schematic diagram of part of the film layer in area E5 shown in FIG. 1 .
  • FIG. 17 is a schematic diagram of part of the film layer in area E6 shown in FIG. 16 .
  • FIG. 18 is a schematic diagram of part of the film layer in area E7 shown in FIG. 16 .
  • FIG. 19 is a schematic diagram of a partial structure of area E8 shown in FIG. 4 .
  • FIG. 20 is a schematic diagram of a partial structure of area E9 shown in FIG. 19 .
  • Figures 21 to 25 are schematic diagrams of different film layers in the positions shown in Figure 20.
  • Characteristics such as “parallel”, “perpendicular” and “identical” used in the embodiments of the present disclosure include “parallel”, “perpendicular”, “identical” and other characteristics in the strict sense, as well as “approximately parallel”, “approximately perpendicular”, “Substantially the same” and the like, including certain errors, mean what is acceptable for a particular value as determined by one of ordinary skill in the art, taking into account the errors in the measurement and associated with the measurement of the particular quantity (e.g., limitations of the measurement system). within the deviation range. For example, “approximately” can mean within one or more standard deviations, or within 10% or 5% of the stated value.
  • the component can be one or more, or it can be understood as at least one.
  • At least one means one or more, and “plurality” means at least two.
  • “Same layer” in the embodiment of the present disclosure refers to the relationship between multiple film layers formed of the same material after going through the same step (such as a one-step patterning process). The "same layer” here does not always mean that the thickness of multiple film layers is the same or that the thickness of multiple film layers is the same in the cross-sectional view. are the same height.
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • the display substrate includes a base substrate, and a plurality of first signal lines and a plurality of second signal lines located on the base substrate.
  • the base substrate includes a first area and a second area, the first area is located around the second area; a plurality of first signal lines are located on the base substrate and do not pass through the second area; a plurality of second signal lines and a plurality of The first signal line is located on a different layer and does not pass through the second area.
  • At least part of the first signal lines extends along the first direction, and at least part of the second signal lines extends along the second direction, and the first direction intersects with the second direction; the plurality of first signal lines include extension lines passing through part of the first signal lines in the second area. signal lines.
  • Each first signal line in some of the first signal lines includes a first sub-signal line and a second sub-signal line located on both sides of the second area. The first sub-signal line and the second sub-signal line pass along the second area.
  • the first connection lines extending in one direction are electrically connected to the second connection lines extending in the second direction, and part of the first signal lines are electrically connected to the plurality of first connection lines and the plurality of second connection lines; the plurality of second signals
  • the line includes a partial second signal line extending through the second area, and each second signal line in the partial second signal line includes a third sub-signal line and a fourth sub-signal line located on both sides of the second area.
  • the sub-signal line and the fourth sub-signal line are electrically connected through a third connection line extending along the first direction and a fourth connection line extending along the second direction, and part of the second signal line is connected to a plurality of third connection lines and a plurality of The fourth connection line is electrically connected; in a direction perpendicular to the base substrate, at least one second connection line overlaps with at least one third connection line, and on the same side of the second area, at least one first connection line is located at least A third connecting line is on the side away from the second area.
  • the display substrate provided by the embodiment of the present disclosure uses first connection lines, second connection lines, third connection lines and fourth connection lines to connect signal lines located on both sides of the second area, and the first connection line is located at the third connection line. While away from the side of the second area, the second connection line overlaps with the third connection line. While reducing the wiring space around the second area to increase the area of the display area, the first signal line and the second signal line can be reduced. Line load changes.
  • FIG. 1 is a partial plan view of a display substrate according to an embodiment of the present disclosure.
  • the display substrate includes a base substrate 100 and a plurality of first signal lines 200 and a plurality of second signal lines 300 located on the base substrate 100 .
  • the base substrate 100 includes a first area 101 and a second area 102.
  • the first area 101 is located around the second area 102.
  • FIG. 1 schematically shows that the first area 101 surrounds the second area 102, but is not limited thereto.
  • the first area 101 may be located only at part of the peripheral position of the second area 102, for example, the first area 101 only surrounds the second area. part of 102.
  • the first area 101 is a display area
  • the second area 102 can be a display area located at the The hole area in one area 101, such as the second area 102, can be a display area or a non-display area.
  • the second area 102 is an area where no signal lines pass through.
  • the edge of the second area 102 may be the edge of the hole area.
  • at least part of the edge of the second region 102 is not parallel to both the first direction and the second direction.
  • the shape of the second area 102 may be circular or oval. But it is not limited thereto.
  • the shape of the second area 102 may be a polygon, such as a quadrilateral, a hexagon, or an octagon.
  • the shape of the first region 101 may be a quadrilateral, such as a rectangle, but is not limited thereto.
  • the shape of the first region 101 may also be a circle or other polygons other than a quadrilateral, such as a hexagon, an octagon, etc.
  • the plurality of first signal lines 200 do not pass through the second region 102 ; the plurality of second signal lines 300 and the plurality of first signal lines 200 are located on different layers and do not pass through the second region 102 .
  • each first signal line 200 does not pass through the second area 102, and each second signal line 300 does not pass through the second area 102.
  • the plurality of first signal lines 200 that do not pass through the second area 102 include the first signal lines 200 whose extension lines do not pass through the second area 102 and the first signal lines 200 whose extension lines pass through the second area 102;
  • the plurality of second signal lines 300 in the area 102 include second signal lines 300 whose extension lines do not pass through the second area 102 and second signal lines 300 whose extension lines pass through the second area 102 .
  • FIG. 1 schematically shows that the first direction is the X direction and the second direction is the Y direction, but it is not limited thereto.
  • the first direction and the second direction can be interchanged.
  • the first direction and the second direction may be perpendicular, but are not limited thereto.
  • the angle between the first direction and the second direction may be 60 to 110 degrees.
  • one of the first direction and the second direction may be a row direction and the other may be a column direction.
  • each first signal line 200 extends along a first direction
  • each second signal line 200 extends along a second direction
  • the extension of the first signal line along the first direction may mean that the overall extension direction of the first signal line is the first direction
  • the first signal line may be a straight line extending along the first direction, or may be a straight line extending along the first direction.
  • a polyline extending in one direction; the extension of the second signal line in the second direction may mean that the overall extension direction of the second signal line is the second direction, and the second signal line may be a straight line extending in the second direction, or it may be a straight line extending in the second direction.
  • the plurality of first signal lines 200 include a portion of the first signal line 200 whose extension line passes through the second area 102 .
  • Each of the portions of the first signal lines 200 includes an extension line located in the second area 102 .
  • the first sub-signal line 210 and the second sub-signal line 220 on both sides pass through the first connecting line 410 extending along the first direction and the second connecting line 410 extending along the second direction.
  • the two connection lines 420 are electrically connected, and part of the first signal line 200 is electrically connected to the plurality of first connection lines 410 and the plurality of second connection lines 420 .
  • the first connection line 410 is electrically connected to the second connection line 420, extending
  • the first signal line 200 passing through the second area 102 will be disconnected at the second area 102 to form two parts, namely the first sub-signal line 210 and the second sub-signal line 220.
  • the two parts transmit the same signal.
  • the two parts are electrically connected through the first connection line 410 and the second connection line 420 .
  • embodiments of the present disclosure are not limited to all first connection lines being located on the same layer and all second connection lines being located on the same layer.
  • some of the second connection lines may be on the same layer as the first connection lines, and some of the second connection lines may be on the same layer as the first connection lines.
  • Connecting lines are located on different layers.
  • the plurality of second signal lines 300 includes a portion of the second signal line 300 whose extension line passes through the second area 102 .
  • Each of the partial second signal lines 300 includes an extension line located in the second area 102 .
  • the third sub-signal line 310 and the fourth sub-signal line 320 on both sides pass through the third connecting line 430 extending along the first direction and the third connecting line 430 extending along the second direction.
  • the four connection lines 440 are electrically connected, and part of the second signal line 300 is electrically connected to the plurality of third connection lines 430 and the plurality of fourth connection lines 440 .
  • connection line 430 and the fourth connection line 440 are electrically connected, and the second signal line 300 whose extension line passes through the second area 102 will be disconnected at the second area 102 to form two parts, that is, a third sub-signal.
  • the line 310 and the fourth sub-signal line 320 transmit the same signal, and the two parts are electrically connected through the fourth connection line 440 and the third connection line 430 .
  • extension line passing through the part of the first signal line 200 in the second area 102 may refer to the portion of the first signal line 200 extending toward the second area 102 near the end point of the second area 102 .
  • extension line passing through the part of the second signal line 300 in the second area 102 may refer to the portion of the second signal line 300 extending toward the second area 102 near the end point of the second area 102 .
  • embodiments of the present disclosure are not limited to all third connection lines being located on the same layer and all fourth connection lines being located on the same layer.
  • some fourth connection lines may be on the same layer as the third connection lines, and some fourth connection lines may be on the same layer as the third connection lines.
  • Connecting lines are located on different layers.
  • the first signal line 200 whose extension line does not pass through the second area 102 can be a continuous signal line
  • the second signal line 300 whose extension line does not pass through the second area 102 can be a continuous signal. Wire.
  • At least one second connection line 420 overlaps with at least one third connection line 430 , and on the same side of the second area 102 , at least one first connection line 420 overlaps with the third connection line 430 .
  • the line 410 is located on a side of the at least one third connection line 430 away from the second area 101 .
  • the display substrate provided by the embodiment of the present disclosure not only uses the first connection line and the second connection line to connect the first signal lines located on both sides of the second area, but also uses the third connection line and the fourth connection line to connect the first signal lines located on both sides of the second area.
  • side of the second signal line, and at least one first connection line is located at least one third connection line While away from the side of the second area, the second connection line overlaps with the third connection line.
  • the first signal line and the second signal line can be reduced.
  • the line's loading (loading) changes suddenly to prevent uneven display, such as mura.
  • the first signal line is Both the fan-out line and the second signal line are connected through connecting lines extending along the first direction and the second direction.
  • FIP Flexible-out In Pixel, the fan-out line is located in the pixel area
  • Part of the electrical connection can save the border size around the second area. For example, reducing the border around the second area can help increase the area of the display area, thereby improving the display effect.
  • the length of the first signal line 200 whose extension line does not pass through the second area 102 is greater than the length of the second signal line 300 whose extension line does not pass through the second area 102 .
  • the ratio of the size of the first signal line 200 in the first direction where the extension line does not pass through the second area 102 to the maximum size of the second area 102 in the first direction is r1, and the extension line does not pass through the second area 102 .
  • the ratio of the maximum size of the second signal line 400 passing through the second area 102 in the second direction to the maximum size of the second area 102 in the second direction is r2, and r1 is greater than r2.
  • the minimum distance between the fourth connection line 440 closest to the second area 102 and the edge of the second area 102 is smaller than the minimum distance between the first connection line 410 closest to the second area and the second area 102 .
  • the minimum distance between the edges of area 102 is smaller than the minimum distance between the edges of area 102.
  • the proportion of the size of the second region to the length of the first signal line is smaller than the proportion of the size of the second region to the length of the second signal line. Therefore, the length of the third connection line has a greater impact on the load of the second signal line than The length of the second connection line affects the load of the first signal line.
  • the fourth connection line is arranged closer to the edge of the second area than the first connection line, so that the third connection line can be connected to the second signal line whose extension line passes through the second area. The length is shorter, thereby reducing the load difference between the load on the second signal line where the extension line passes through the second area and the load on the second signal line where the extension line does not pass through the second area.
  • a fourth connection line 440 closest to the second area 102 and a second second connection line 440 closest to the second area 102 and whose extension line does not pass through the second area 102 The distance between the signal lines 300 is D1, the distance between a first connection line 410 closest to the second area 102 and a first signal line 200 closest to the second area 102 and whose extension line does not pass through the second area 102 is D2, D1 is smaller than D2.
  • the first signal line 200 includes a data line
  • the second signal line 300 at least includes a lighting control signal line.
  • FIG. 2 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIGS. 3A to 3H include schematic diagrams of different film layers in the pixel circuit.
  • FIG. 3I is a schematic diagram of the film layer stacking shown in FIGS. 3A to 3F.
  • the display substrate further includes a plurality of sub-pixels, and at least some of the sub-pixels include a light-emitting element 120 and a pixel circuit 110 electrically connected to the light-emitting element 120 .
  • the pixel circuit includes a plurality of transistors and at least one capacitor.
  • the pixel circuit includes a second reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a second light emitting control transistor T5, a first light emitting control transistor T6, a first reset transistor T7, and a third reset transistor. T8 and storage capacitor C.
  • the display substrate also includes reset power signal lines 561, 551 and 554, scan signal lines 552, 531 and 523, power signal lines 581, reset control signal lines 522, 532 and 553, light emitting Control signal line 521 and data line 200.
  • the first electrode of the threshold compensation transistor T2 is electrically connected to the first electrode of the driving transistor T3, and the second electrode of the threshold compensation transistor T2 is electrically connected to the gate electrode of the driving transistor T3.
  • the gate electrode of the transistor T2 is electrically connected to the scan signal lines 531 and 552 to receive the compensation control signal; the first electrode of the first reset transistor T7 is electrically connected to the reset power signal line 561 to receive the reset signal Vinit2.
  • the diode is electrically connected to the first electrode of the light-emitting element (i.e., the N4 node), the gate of the first reset transistor T7 is electrically connected to the reset control signal line 522 to receive the reset control signal Reset(N+1); the third reset transistor T8 The first electrode of the third reset transistor T8 is electrically connected to the reset power signal line 551 to receive the reset signal Vref. The second electrode of the third reset transistor T8 is electrically connected to the second electrode of the driving transistor T3. The gate electrode of the third reset transistor T8 is connected to the reset control signal.
  • the line 522 is electrically connected; the first pole of the data writing transistor T4 is electrically connected to the second pole of the driving transistor T3, and the second pole of the data writing transistor T4 is electrically connected to the data line 200 (first signal line 200) to receive data.
  • Signal Data the gate of the data writing transistor T4 is electrically connected to the scanning signal line 523 to receive the scanning signal Gate; the first pole of the storage capacitor C is electrically connected to the power signal line 581, and the second pole of the storage capacitor C is electrically connected to the driving transistor T3
  • the gate of the second reset transistor T1 is electrically connected to the reset power signal line 554 to receive the reset signal Vinit1.
  • the second electrode of the second reset transistor T1 is electrically connected to the gate of the driving transistor T3.
  • the gate of the reset transistor T1 is electrically connected to the reset control signal lines 553 and 532 to receive the reset control signal Reset(N); the gate of the first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line 521 to receive the light-emitting control signal EM, The first pole of the first light emitting control transistor T6 and the driving
  • the first electrode of the transistor T3 is electrically connected, the second electrode of the first light-emitting control transistor T6 is electrically connected with the first electrode of the light-emitting element 120;
  • the first electrode of the second light-emitting control transistor T5 is electrically connected with the power signal line 581 to receive the third a power supply signal VDD, the second electrode of the second light-emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T3, and the gate electrode of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line 521 to receive the light-emitting control signal EM
  • each pixel circuit in addition to the 8T1C (ie, eight transistors and one capacitor) structure shown in FIG. 2 , each pixel circuit can also be a structure including other numbers of transistors, such as 7T1C. structure, 7T2C structure, 6T1C structure, 6T2C structure or 9T2C structure, the embodiments of the present disclosure are not limited to this.
  • FIG. 3A shows a first active layer pattern 510.
  • the first active layer pattern 510 can be used to fabricate the above-mentioned driving transistor T3, data writing transistor T4, second light emitting control transistor T5, first light emitting control transistor T6, first reset transistor T7 and The active layer of the third reset transistor T8 is used to form the channel region of the above-mentioned transistor.
  • the first active layer pattern 510 includes the active area pattern (channel area) and the doping area pattern (source and drain area) of the above-mentioned transistor of each sub-pixel, and the active area pattern and doping area pattern of the above-mentioned transistor in the same pixel circuit
  • the mixed area pattern is set in one piece.
  • the first active layer pattern 510 may include an integrally formed low-temperature polysilicon layer, and the source region and the drain region may be conductive through doping or the like to achieve electrical connections between the structures.
  • the above-mentioned source region and drain region may be regions doped with p-type impurities.
  • FIG. 3B shows the first conductive layer pattern 520 located on the side of the first active layer pattern 510 away from the base substrate.
  • the first conductive layer pattern 520 includes a reset control signal line 522 , a scanning signal line 523 , a first pole of the capacitor 524 and a light emission control signal line 521 .
  • the first conductive layer pattern 520 may include gate electrodes of the driving transistor T3, the data writing transistor T4, the second light emission control transistor T5, the first light emission control transistor T6, the first reset transistor T7, and the third reset transistor T8.
  • each dotted rectangular frame in FIG. 3A shows each portion where the first active layer pattern 510 and the first conductive layer pattern 520 overlap, that is, the channel region.
  • the active semiconductor layers on both sides of each channel region are conductive through processes such as ion doping to serve as the first pole and the second pole of each transistor.
  • the source and drain of a transistor can be symmetrical in structure, so there can be no difference in physical structure between the source and drain.
  • the gate electrode as the control electrode one of the electrodes is directly described as the first electrode and the other is the second electrode. Therefore, the first electrode and the second electrode of all or part of the transistors in the embodiments of the present disclosure can be interchanged as needed. of.
  • the gate electrode of the data writing transistor T4 may be a portion where the scanning signal line 523 overlaps the first active layer pattern 510; the gate electrode of the first light emitting control transistor T6 may be a light emitting transistor.
  • the first portion where the control signal line 521 overlaps with the first active layer pattern 510 and the gate electrode of the second light emitting control transistor T5 may be the second portion where the light emitting control signal line 521 overlaps with the first active layer pattern 510 .
  • the gate of the third reset transistor T8 is the first portion where the reset control signal line 522 overlaps the first active layer pattern 510.
  • the gate of the first reset transistor T7 is where the reset control signal line 522 overlaps the first active layer pattern 510.
  • FIG. 3C shows the second conductive layer pattern 530 on the side of the first conductive layer pattern 520 away from the base substrate.
  • the second conductive layer pattern 530 includes a scanning signal line 531 , a second pole 533 of the capacitor C, and a reset control signal line 532 .
  • FIG. 3D shows the second active layer pattern 540 on the side of the second conductive layer pattern 530 away from the base substrate.
  • the second active layer pattern 540 includes channel regions of the second reset transistor T1 and the threshold compensation transistor T2.
  • the transistor using the oxide semiconductor has the characteristics of good hysteresis characteristics and low leakage current, so the oxide semiconductor can be used
  • the transistor replaces the low-temperature polysilicon material in the transistor to form a low-temperature polysilicon-oxide (LTPO) pixel circuit, which achieves low leakage and helps improve the stability of the gate voltage of the transistor.
  • LTPO low-temperature polysilicon-oxide
  • the gate electrode of the second reset transistor T1 may be a portion where the reset control signal line 532 overlaps the second active layer pattern 540
  • the gate electrode of the threshold compensation transistor T2 may be The portion where the signal line 531 overlaps the second active layer pattern 540 is scanned.
  • FIG. 3E shows the third conductive layer 550 on the side of the second active layer pattern 540 away from the base substrate.
  • the third conductive layer 550 includes a reset power signal line 554 , a reset control signal line 553 , a scan signal line 552 and a reset power signal line 551 .
  • the reset control signal line 553 overlaps the channel region of the second reset transistor T1.
  • the second reset transistor T1 includes a top gate and a bottom gate located on both sides of the active layer.
  • the scanning signal line 552 overlaps the channel region of the threshold compensation transistor T2, which includes a top gate and a bottom gate located on both sides of the active layer.
  • the second reset transistor T1 and the threshold compensation transistor T2 may be N-type transistors.
  • drive The moving transistor T3, the data writing transistor T4, the second light emitting control transistor T5, the first light emitting control transistor T6, the first reset transistor T7 and the third reset transistor T8 may be P-type transistors.
  • FIG. 3F shows the fourth conductive layer 560 located on the side of the third conductive layer 550 away from the base substrate.
  • the fourth conductive layer 560 includes a reset power signal line 561, a connecting portion 568, a connecting portion 569, a connecting portion 563, a connecting portion 567, a connecting portion 562, a connecting portion 564, a connecting portion 565 and a connecting portion. 566.
  • connection portion 568 both ends of the connection portion 568 are connected to the reset power supply signal line 551 , and the middle is connected to the first pole of the third reset transistor T8 ; the connection portion 569 is connected to the first signal line 200 and the data writing transistor.
  • connection part 563 is used to electrically connect the first pole of the data writing transistor T4 and the second pole of the third reset transistor T8 to lead the reset signal Vref to the N2 node;
  • connection part 567 is used to electrically connect The first pole of the driving transistor T3 and the first pole of the threshold compensation transistor T2;
  • middle of the connection portion 562 is connected to the power signal line 581, and both ends of the connection portion 562 are connected to the second pole 533 of the capacitor.
  • the second pole 533 is electrically connected, and on the other hand, the power supply voltage is applied to the second pole 533 of the capacitor C; one end of the connecting portion 564 is connected to the second pole 533 of the capacitor C, and the other end of the connecting portion 564 is connected to the second luminous
  • the first pole of the control transistor T5 is connected; the connection part 565 is used to electrically connect the first electrode of the light-emitting element and the second pole of the first light-emitting control transistor T6; the connection part 566 is used to electrically connect the reset power signal line 554 and the second reset The first pole of transistor T1.
  • FIG. 3G shows the fifth conductive layer 570 located on the side of the fourth conductive layer 560 away from the base substrate.
  • the fifth conductive layer 570 includes a connecting portion 573 , a connecting portion 575 , a power signal line 572 , a connecting portion 574 , a second connecting line 420 and a sixth connecting line 460 .
  • the fifth conductive layer 570 further includes fourth connection lines.
  • the connecting portion 573 is electrically connected to the first signal line 200 .
  • the first signal line 200 is electrically connected to the second connecting line 420 through the connecting portion 573 to transmit the first signal to the second connecting line 420 .
  • a connecting block can be added between the connecting portion 573 and the second connecting line 420 to realize the electrical connection between the first signal line 200 and the second connecting line 420; the connecting portion 575 is a reserved pad, and the reserved pad
  • the electrical connection can be maintained with the first connection line through the via hole, and a connection block is added between the second connection line 420 and the connection portion 575 at the position where the first connection line and the second connection line need to be electrically connected, so that The first connection line can be electrically connected to the second connection line 420 through the reserved pad; similarly, the third connection line can be electrically connected to the fourth connection line through the reserved pad.
  • connection portion 574 is electrically connected to the connection portion 565 to realize the electrical connection between the second electrode of the first light-emitting control transistor T6 and the first electrode of the light-emitting element.
  • the power signal line 572 is electrically connected to the power signal line 581 .
  • FIG. 3H shows the sixth conductive layer 580 located on the side of the fifth conductive layer 570 away from the base substrate.
  • the sixth conductive layer 580 includes a first signal line 200 , a power signal line 581 , a fifth connection line 450 , a connection portion 584 and a connection portion 585 .
  • the sixth conductive layer 580 further includes first connection lines and third connection lines.
  • the connecting portion 584 and the connecting portion 585 are electrically connected to first electrodes of different light-emitting elements.
  • the first signal line 200 includes an adapter pad 290 , and the first signal line 200 is connected to the connection portion 573 through the adapter pad 290 to be electrically connected to the second connection line.
  • the fifth connection line, the first connection line and the third connection line all include transfer pads 459, and each connection line is electrically connected to the connection portion 575 through the corresponding transfer pad 459.
  • the second signal line 300 may be located in the first conductive layer pattern 520 .
  • the second signal line 300 may include at least one of the light emission control signal line 521 and the reset control signal line 522 .
  • the plurality of second signal lines 300 are located between the plurality of first signal lines 200 and the base substrate 100
  • the fourth connection lines 440 are located between the plurality of first signal lines 200 and the plurality of base substrates 100 . between the second signal lines 300.
  • all the first connection lines 410 are located on the side of the third connection line 430 away from the second area 102 .
  • first connection lines and some of the third connection lines can be arranged alternately, which is beneficial to reducing the first signal line of the extension line passing through the second area and the first signal line of the extension line not passing through the second area. Load differences on signal lines.
  • some of the second connection lines 420 and each of the fourth connection lines 440 are located on the same layer.
  • the second connection lines 420 and the fourth connection lines 440 arranged on the same layer at least one of the second connection lines 420 and The fourth connecting lines 440 are located on the same straight line and are arranged at intervals.
  • the second connection line 420 and the third connection line 430 that are located in the same straight line as the fourth connection line 440 overlap.
  • At least one extension line of the first signal line 200 passing through the second area 102 is located between at least one third connection line 430 and the second area 102 .
  • at least one extension line does not pass through the first portion of the second area 102.
  • the signal line 200 is located between at least one third connection line 430 and the second area 102 .
  • at least one third connection line 430 is located between at least one first signal line 200 whose extension line does not pass through the second area 102 and at least one first signal line 200 whose extension line passes through the second area 102 .
  • At least one first signal line 200 whose extension line does not pass through the second area 102 among the plurality of first signal lines 200 is located on the first connection line 410 The side close to the second area 102.
  • the first connection lines 410 provided on the same side of the second area 102 are arranged at equal intervals.
  • at least part of the fourth connection lines 440 provided on the same side of the second area 102 are arranged at equal intervals.
  • the distance between the first connection line 410 and the third connection line 430 that are closest to each other among the plurality of first connection lines 410 and the plurality of third connection lines 430 is the same as the distance between the first connection line 410 and the third connection line 430 .
  • the ratio of the distances between two adjacent third connection lines 430 is 0.8 ⁇ 1.2.
  • the ratio of the distance between the closest first connection line 410 and the third connection line 430 to the distance between the two adjacent third connection lines 430 is 0.9 ⁇ 1.1.
  • the distance between a first connection line 410 and a third connection line 430 that are closest to each other is equal to the distance between two adjacent third connection lines 430 .
  • the length of the second connection line connected to the first connection line can be made shorter, thereby reducing the distance between the first connection line and the third connection line.
  • the load difference between the first signal line connected by a connecting line and the load of the first signal line closest to the second area and the extension line does not pass through the second area is helpful to avoid the mura phenomenon on the display substrate during display.
  • At least part of the first connection lines 410 and at least part of the third connection lines 430 are located on the same layer, and at least part of the second connection lines 420 are connected to at least part of the fourth connection lines.
  • Line 440 is on the same floor.
  • each first connecting line 410 on a straight line extending along the first direction overlaps with the orthographic projection of each third connecting line 430 on a straight line extending along the first direction
  • at least one second connecting line 420 is The orthographic projection on the straight line extending along the second direction does not overlap with the orthographic projection of the at least one fourth connecting line 440 on the straight line.
  • the first connection line and the third connection line are arranged along the second direction to prevent the first connection line and the third connection line from interfering; because some of the second connection line and the fourth connection line are in the second direction, By setting the spacing, a part of the second connection line can be inserted into the third connection line, so that this part of the second connection line is electrically connected to the first signal line located on the side of the third connection line close to the second area, which can reduce the risk of the second connection line as much as possible.
  • the length of the second connection line is the first signal line that is closest to the extension line and does not pass through the second area (can be called a normal signal line). The load difference between the first signal line and the normal signal line is reduced, thereby reducing the load difference between the first signal line electrically connected to the second connection line and the normal signal line.
  • the second signal line 300 closest to the second area 102 is located in the portion of the second signal lines 300 whose extension lines do not pass through the second area 102 .
  • a fourth connection line 440 close to the second area 102 and the fourth connection line 440 adjacent thereto By arranging the fourth connection line closest to the second area to be closer to the second signal line closest to the second area and with the extension line not passing through the second area, the fourth connection line closest to the second area can be reduced.
  • the length of the third connection line connected by the line can thereby reduce the difference in load on the second signal line electrically connected to the fourth connection line and the second signal line load on the extension line that does not pass through the second area, which is conducive to reducing display mura. .
  • the first group of connection lines 4201 among the plurality of second connection lines 420 is located on a side of the at least one fourth connection line 440 close to the second area 102 .
  • the second group of connection lines 4202 among the plurality of second connection lines 420 is located on the side of the at least one fourth connection line 440 away from the second area 102 .
  • the number of second connection lines 420 included in the first group of connection lines 4201 may be smaller than the number of second connection lines 420 included in the second group of connection lines 4202 .
  • a plurality of fourth connection lines 440 are provided between the first group of connection lines 4201 and the second group of connection lines 4202.
  • the second connection line by arranging the second connection line to include two sets of connection lines located on both sides of the fourth connection line, it is possible to prevent the fourth connection line and the second connection line from causing interference due to being arranged on the same layer. , and can prevent the first signal line and the second signal line from causing sudden load changes and causing display mura.
  • the first set of connection lines 4201 and the third connection lines 430 overlap, and the second set of connection lines 4202 and the third connection lines 430 do not overlap. overlap.
  • connection line 430 does not overlap with the second connection line 420 .
  • each connection line 420 in the first set of connection lines 4201 overlaps with at least one third connection line 430.
  • At least one first signal line 200 connected to the line 4202 overlaps with each fourth connection line 440 in a direction perpendicular to the base substrate 100 .
  • each first signal line 200 connected to the second group of connection lines 4202 overlaps with all the fourth connection lines 440 in a direction perpendicular to the base substrate 100.
  • the second set of connection lines is arranged on a side of the fourth connection line away from the second area.
  • the second connection lines 420 in the first group of connection lines 4201 are arranged at equal intervals.
  • the second connection lines 420 in the second group of connection lines 4202 are arranged at equal intervals.
  • the distance between two adjacent second connection lines 420 in the first group of connection lines 4201 may be equal to the distance between two adjacent second connection lines 420 in the second group of connection lines 4202 .
  • the distance between the second connection line 420 closest to the fourth connection line 440 in the second group of connection lines 4202 and the fourth connection line 440 may be the same as the distance between two adjacent second connection lines in the second group of connection lines 4202 .
  • the distance between lines 420 is equal.
  • a second connection line 420 of the first set of connection lines 4201 that is closest to the second set of connection lines 4202 and a second set of connection lines 4202 that is closest to the first set of connection lines 4201 The distance between one second connection line 420 is the first distance S1, and the distance between two adjacent second connection lines 420 in the second group of connection lines 4202 is the second distance S2.
  • the first distance S1 and the second distance The ratio of S2 is greater than 2.
  • the ratio of the first distance S1 to the second distance S2 is greater than 3.
  • the ratio of the first distance S1 to the second distance S2 is greater than 4.
  • the ratio of the first distance S1 to the second distance S2 is greater than 5.
  • the ratio of the first distance S1 to the second distance S2 is greater than 6.
  • the ratio of the first distance S1 to the second distance S2 is greater than 7.
  • the ratio of the first distance S1 to the second distance S2 is greater than 8.
  • the ratio of the first distance S1 to the second distance S2 is greater than 9.
  • the ratio of the first distance S1 to the second distance S2 is greater than 10.
  • FIG. 4 is a partial planar structural schematic diagram provided according to another example of an embodiment of the present disclosure.
  • Figure 5 is a schematic diagram of part of the film layer in area E1 shown in Figure 4.
  • Figures 6 and 7 are schematic diagrams of the two conductive layers at the position shown in Figure 5.
  • Figure 8 is a schematic diagram of part of the film layer in area E2 shown in Figure 4.
  • Figure 9 to 10 are schematic diagrams of the two conductive layers at the position shown in Figure 8 .
  • the film layer structure of the area shown in FIGS. 5 to 10 may have the same characteristics as the film layer structure of the corresponding area of the display substrate shown in FIG. 1 .
  • the first signal line 200 includes first signal lines 201 - 1 and 201 - 2 whose extension lines pass through the second area 102 , and first signal lines whose extension lines do not pass through the second area 102 Lines 202-1 and 202-2, the first signal line 201-1 is the first signal line closest to the extension line that does not pass through the second area 102 and the extension line passes through the second area 102.
  • the first signal line 202-1 is The extension line closest to the extension line passing through the second area 102 does not pass through a first signal line in the second area 102 .
  • the second connection line 420 includes a second connection line 420 - 2 electrically connected to the first signal line 201 - 2 and a second connection electrically connected to the first signal line 201 - 1 Line 420-1.
  • the second connection line 420-1 is electrically connected to the first signal line 201-1 through the connection part 0421
  • the second connection line 420-2 is electrically connected to the first signal line 201-2 through the connection part 0422.
  • the first connection line 410 includes a first connection line 410 - 1 connected to the second connection line 420 - 1 and a first connection line electrically connected to the second connection line 420 - 2 410-2.
  • the second connection line 420-1 is electrically connected to the first connection line 410-1 through the connection part 0423
  • the second connection line 420-2 is electrically connected to the first connection line 410-2 through the connection part 0425.
  • the first signal line 210 (ie, the first signal line 201 - 1 ) located on one side of the second area 102 connects the first signal to the first connection line 420 - 1 through the second connection line 420 - 1 .
  • the line 410-1 is transmitted to the first signal line 220 located on the other side of the second area 102; the first signal line 201-2 located on one side of the second area 102 transmits the first signal through the second connection line 420-2 and the first signal line 220.
  • a connection line 410-2 is transmitted to the first signal line 220 located on the other side of the second area 102.
  • the black dotted arrows in Figures 5 and 8 schematically illustrate the transmission path of the first signal.
  • the display substrate further includes a plurality of fifth connection lines 450 extending along the first direction and a plurality of sixth connection lines 460 extending along the second direction.
  • the plurality of fifth connection lines 450 include at least part of the fifth connection lines 450 located on the same layer as the first connection line 410 , and at least part of the fifth connection lines 450 are The fifth connection line 450 and the first connection line 410 in which the first connection line 410 is located on the same straight line are spaced apart. For example, a gap 0426 is provided between the first connection line 410-1 and the fifth connection line 450.
  • two connecting lines located on the same straight line and spaced apart can be broken into two different connecting lines for the same connecting line.
  • the plurality of sixth connection lines 460 include at least part of the sixth connection lines 460 located on the same layer as the second connection line 420 .
  • the sixth connection line 460 and the second connection line 420 in which the second connection line 420 is located on the same straight line are spaced apart.
  • a gap 0424 is provided between the second connection line 420-1 and the sixth connection line 460.
  • the plurality of fifth connection lines 450 include at least part of the fifth connection lines 450 located on the same layer as the third connection line 430 , and at least part of the fifth connection lines 450 are connected to the third connection line 450 .
  • the fifth connection line 450 and the third connection line 430 whose line 430 is located on the same straight line are spaced apart.
  • the plurality of sixth connection lines 460 include at least part of the sixth connection lines 460 located on the same layer as the fourth connection line 440 , and at least part of the sixth connection lines 460 are connected to the fourth connection line 460 .
  • the sixth connection line 460 and the fourth connection line 440 whose lines 440 are located on the same straight line are spaced apart.
  • the display substrate further includes a peripheral area 103 surrounding the display area, such as the first area 101 .
  • the peripheral area 103 is an area not used for display, and the display area is an area used for display.
  • the first area 101 is an area used for display.
  • the display substrate further includes a third signal line 600 located in the peripheral area 103 , at least one of the fifth connection line 450 and the sixth connection line 460 and the third signal line 600 .
  • Signal line 600 is electrically connected.
  • the third signal line 600 may be a ring-shaped signal line surrounding the display area.
  • the third signal line 600 is configured to transmit a VSS signal.
  • the third signal line 600 is configured to be electrically connected to the second electrode of the light-emitting element, such as the cathode.
  • both the fifth connection line 450 and the sixth connection line 460 are electrically connected to the third signal line 600 .
  • the embodiment of the present disclosure is beneficial to improving the uniformity of the connection line positions and reducing display mura; in addition, by connecting the fifth connection line and the sixth connection line with the third The electrical connection of the signal lines is beneficial to reducing the load of the third signal line.
  • At least one first connection line 410 and at least one third connection line 430 are located on the same layer as the plurality of first signal lines 200 .
  • each first connection line 410 is arranged on the same layer as the first signal line 200 .
  • each third connection line 430 is arranged on the same layer as the first signal line 200 .
  • At least one of the distance between the fifth connection line 450 and the first connection line 410 and the distance between the fifth connection line 450 and the third connection line 430 is the same as that of the fourth connection line 450 .
  • the film layer where the connecting line 440 is located overlaps, such as overlapping with the structure in the fifth conductive layer 570 .
  • at least one of the distance between the sixth connection line 460 and the second connection line 420 and the distance between the sixth connection line 460 and the fourth connection line 440 overlaps with the film layer where the first connection line 410 is located, such as with the first connection line 410.
  • the structures in six conductive layers 580 overlap.
  • the gap 0424 between the second connection line 420 and the sixth connection line 460 overlaps the first signal line 200 .
  • the gap 0426 between the first connection line 410 and the fifth connection line 450 overlaps the second connection line 420 .
  • At least one first connection line 410 is provided with two first signal lines 200 immediately adjacent to the first connection line 410 on both sides, and the two first signal lines 200 are connected to the first connection line 410 .
  • the ratio of the minimum distance between a connecting line 410 is 0.9 ⁇ 1.1.
  • the minimum distance between the two first signal lines 200 and the first connection line 410 is the same.
  • multiple first signal lines 200 can be divided into multiple first signal line pairs 200 , and each first signal line pair 200 is located between two adjacent sub-pixels, such as two light-emitting elements. And a first connection line 410 is provided between at least one first signal line pair 200 .
  • At least one third connection line 430 is provided with two first signal lines 200 immediately adjacent to the third connection line 430 on both sides, and the two first signal lines 200 are connected to the third connection line 430 .
  • the ratio of the minimum distances between the three connecting lines 430 is 0.9 to 1.1.
  • the minimum distance between the two first signal lines 200 and the third connection line 430 is the same.
  • a third connection line 430 is disposed between at least one first signal line pair 200 .
  • At least one fifth connection line 450 is provided with two first signal lines 200 immediately adjacent to the fifth connection line 450 on both sides, and the two first signal lines 200 and the fifth connection line
  • the ratio of the minimum distance between 450 is 0.9 ⁇ 1.1.
  • the minimum distance between the two first signal lines 200 and the fifth connection line 450 is the same.
  • the first connection line and the first signal line are arranged in a 2in1 manner
  • the third connection line and the first signal line are arranged in a 2in1 manner
  • the fifth connection line and the first signal line are arranged in a 2in1 manner. 2in1 mode setting.
  • Two first connection lines may also be provided between at least one first signal line pair, such as using a 1in1 arrangement.
  • FIG. 11 is a schematic diagram of part of the film layers in area E3 shown in FIG. 4
  • FIG. 12 is a schematic diagram of part of the film layers in area E4 shown in FIG. 4
  • Figure 13 is a schematic diagram of a partial film layer including the area E1 shown in Figure 4.
  • Figures 14 and 15 are schematic diagrams of the two conductive layers at the position shown in Figure 13.
  • the first connection line 410 connected to a second connection line 420 of the first set of connection lines 4201 that is closest to the second set of connection lines 4202 includes a second connection line 410 located respectively at a second connection line 420 of the first set of connection lines 4201 .
  • a part 411 of the first connection line 410 is used to transmit to the first signal line 200 located on the other side of the second area 102
  • the first signal, the other part 412 of the first connection line 410 is used to balance the parasitic capacitance on the first connection line 410 and the second connection line 420 of the second set of connection lines 4202 that is closest to the first set of connection lines 4201
  • the difference in parasitic capacitance, such as another part 412 can serve as the load compensation part.
  • a part 411 of the first connection line 410 may be regarded as a forward extending part, and the other part 412 may be regarded as a reverse extending part.
  • the distance between the two second connecting lines that are respectively located in the first group of connecting lines and the second group of connecting lines and are closest to each other is greater than the distance between the two adjacent second connecting lines in the first group of connecting lines (or the second group of connecting lines).
  • the distance between two connecting lines is determined by extending the length of the first connecting line connected to the second connecting line in the first group of connecting lines that is closest to the second group of connecting lines, if the first connecting line includes Transmitting a part of the forward extension of the first signal line and another part extending in the reverse direction relative to the forward extension part can reduce the load mutation of the second connection line in the two sets of connection lines, thereby reducing display mura and improving the display effect.
  • the first connection line 410 connected to a second connection line 420 - 11 of the first set of connection lines 4201 that is closest to the second set of connection lines 4202 extends to the position of the second connection line 420-12 of the second set of connection lines 4202 that is closest to the first set of connection lines 4201.
  • the reversely extending portion 412 of the first connection line 410 connected to the second connection line 420-11 extends to the position of the second connection line 420-12.
  • Embodiments of the present disclosure extend the reversely extending portion of the first connection line connected to a second connection line of the first set of connection lines closest to the second set of connection lines to the second set of connection lines closest to the first set of connection lines.
  • the position of a second connecting line of the connecting line is conducive to minimizing the load difference on the two second connecting lines that are located respectively in the first group of connecting lines and the second group of connecting lines and are closest to each other, thus preventing The gap between the two sets of connecting lines is set larger to produce a larger load jump.
  • the spacing between the reversely extending portion 412 of the first connection line 410 and the fifth connection line 450 connected to the second connection line 420 - 11 is different from that of the second connection line 420 - 11 .
  • the N first connection lines are respectively connected to the N second connection lines 420 of the first set of connection lines 4201 that are closest to the second set of connection lines 4202 .
  • Each first connection line 410 in 410 includes two parts 411 and 412 respectively located on both sides of the second connection line 420 connected to it in the first direction, and along the direction close to the second area 102, the Nth The lengths of the two parts 411 and 412 of a connecting line 410 on both sides of the second connecting line 420 connected to it in the first direction gradually decrease, N is a positive integer greater than or equal to 1, and are located in the second area 102 The number of second connection lines 420 in the first group of connection lines 4101 on the center side is greater than or equal to N.
  • the second connection line 420 of the first set of connection lines 4201 that is closest to the second set of connection lines 4202 includes a second connection line 420-1, a second connection line 420- 2 and the second connection line 420-3.
  • the first connection line 410 includes a first connection line 410-1 connected to the second connection line 420-1, and a first connection line 410- connected to the second connection line 420-2. 2 and the first connection line 410-3 connected to the second connection line 420-3.
  • the portion 412-3 of the first connection line 410-3, the portion 412-2 of the first connection line 410-2, and the portion 412 of the first connection line 410-1 The length of -1 gradually decreases, for example, the length of the portion 412-3 of the first connection line 410-3 is greater than the length of the portion 412-2 of the first connection line 410-2.
  • adjusting the length of the reverse extension of the first connection line is beneficial to While reducing the sudden change in load between the second connection line in the second group of connection lines and the second connection line in the first group of connection lines, the load difference between adjacent second connection lines in the first group of connection lines is reduced as much as possible.
  • any two adjacent first connection lines 410 among the plurality of first connection lines 410 connected to at least part of the second connection lines 420 in the first group of connection lines 4201 are opposite to each other.
  • the length difference to the extended portion is within a certain range.
  • the length difference can be the size of 1 to 5 sub-pixels in the first direction.
  • the length difference can be the size of 2 to 4 sub-pixels in the first direction.
  • the first connection line 410 connected to the second connection line 420 in the first group of connection lines 4201 may include two reverse extension portions 412 and a second connection line 410 between the two reverse extension portions 412 .
  • Forward extension 411 For example, each first connection line 410 includes two reversely extending portions 412 with equal lengths.
  • FIG. 16 is a schematic diagram of part of the film layers in area E5 shown in FIG. 1
  • FIG. 17 is a schematic diagram of part of the film layers in area E6 shown in FIG. 16
  • FIG. 18 is a schematic diagram of part of the film layers in area E7 shown in FIG. 16 .
  • the plurality of second connection lines 4202 include the second connection lines 420 located in the first area 101 and the second connection lines 420 located in the peripheral area 103 .
  • the second connection line 420 located in the first area 102 and the first connection line 410 are arranged in different layers, and the second connection line 420 located in the peripheral area 103 is arranged in the same layer as the first connection line 410 .
  • a first connection line 410 and two second connection lines The two second connection lines 420 are electrically connected.
  • one second connection line 420 located in the first area 101 and the first connection line 410 are arranged in different layers.
  • One second connection line 420 located in the peripheral area 103 and The first connection lines 410 are arranged on the same layer and integrated.
  • the second connection line 420 located in the peripheral area 103 is arranged on the same layer as the first signal line 200 .
  • the second sub-signal line 220 located in the second area 102 and close to the peripheral area 103 and the second connection line 420 connected thereto are on the same layer and are integrated.
  • FIG. 17 and FIG. 18 schematically show that the fifth connection line 450 is electrically connected to the third signal line 600 located in the peripheral area 103 .
  • the fifth connection line 450 in the E6 area is directly electrically connected to the third signal line 600
  • the fifth connection line 450 in the E7 area is connected to the third signal line 600 through the adapter line 0450 provided in the same layer as the second connection line provided in the first area 101.
  • the third signal line 600 is electrically connected.
  • the third connection line 430 and the fourth connection line 440 are both located in the first area 101 .
  • each second connection line 420 included in the first group of connection lines 4201 and the first connection lines 410 connected to each second connection line 420 in the first group of connection lines 4201 are located in the first area 101 .
  • the display substrate further includes: a plurality of first light-emitting elements, a plurality of first pixel circuits and a plurality of second pixel circuits located in the first area 101, and a plurality of second light-emitting elements located in the second area 102, a plurality of The first pixel circuit is electrically connected to a plurality of first light-emitting elements in a one-to-one correspondence, and the plurality of second pixel circuits is electrically connected to a plurality of second light-emitting elements in a one-to-one correspondence.
  • the second area 102 can be an area for setting up a camera.
  • the second pixel circuit that drives the second light-emitting element in the second area 102 to emit light is located in the first area 101, which can increase the light transmittance of the second area 102. That is, the light transmittance of the second region 102 is increased by separately disposing the light-emitting element and the pixel circuit.
  • FIG. 19 is a schematic diagram of a partial structure of area E8 shown in FIG. 4 .
  • FIG. 20 is a schematic diagram of a partial structure of area E9 shown in FIG. 19 .
  • FIGS. 21 to 25 are schematic diagrams of different film layers in the positions shown in FIG. 20 .
  • the E9 area is a small area within the E8 area.
  • the second signal line 300 includes a light emission control signal line 521 .
  • the light emission control signal line 521 adopts unilateral driving.
  • the light emission control signal line 521 is electrically connected to the fourth connection line 440 - 11 in the fifth conductive layer 570 through the adapter line 5611 .
  • the fourth connection line 440 - 11 is electrically connected to the third connection line 430-1 in the sixth conductive layer 580 through the connection portion 575, and the third connection line 430-1 is electrically connected to the fourth connection line 440-1 through the connection portion 575, thereby connecting the second
  • the third sub-signal line 310 (luminous The control signal line 521) is electrically connected to the fourth sub-signal line 320 (light-emitting control signal line 521) located on the right side of the second area 102.
  • the extension line does not pass through the second area 102 and the one closest to the second area 102 emits light.
  • the control signal line 521 is located between a fourth connection line 440-1 closest to the second area 102 and an adjacent fourth connection line 440-2.
  • the second signal line 300 includes a reset control signal line 522 .
  • the reset control signal line 522 adopts single-sided driving.
  • the reset control signal line 522 is electrically connected to the fourth connection line 440-12 in the fifth conductive layer 570 through the adapter line in the fourth conductive layer 560
  • the fourth connection line 440-12 is electrically connected to the third connection line 430-2 in the sixth conductive layer 580 through the connection part 575
  • the third connection line 430-2 is electrically connected to the fourth connection line 440-2 through the connection part 575.
  • the process of writing signals to the light-emitting control transistor is less affected by the parasitic capacitance, and the signals of the reset transistor T7 and the reset transistor T8 are also less affected by the parasitic capacitance.
  • At least one of the reset control signal line electrically connected to T8 and the light-emitting control signal line is configured to use a connection line extending along the first direction and a connection line extending along the second direction to achieve electrical connection between the two parts located on both sides of the second area. , which is conducive to reducing the wiring space around the second area to increase the area of the display area without affecting the working performance of the pixel circuit as much as possible.
  • the scanning signal lines 523 adopt bilateral driving, so the scanning signal lines 523 located on both sides of the second area can be disconnected.
  • the scanning signal line 531 electrically connected to the threshold compensation transistor T2 adopts unilateral driving.
  • the scanning signal line 531 located on one side of the second area 102 is connected to the scanning signal line 531 located on the other side of the second area 102 through the connecting line 525 in the first conductive layer 520 and/or the connecting line in the fourth conductive layer 560 . Electrical connection.
  • the scanning signal line electrically connected to the threshold compensation transistor T2 does not use a connection line extending along the first direction and a connection line extending along the second direction to realize two parts located on both sides of the second area. Instead of realizing the electrical connection between the two parts located on both sides of the second area through the winding around the edge of the second area, the parasitic capacitance generated on the scanning signal line electrically connected to the threshold compensation transistor T2 can be lowered.
  • the reset control signal line 532 electrically connected to the second reset transistor T1 adopts unilateral driving.
  • the reset control signal line 532 located on one side of the second area 102 is electrically connected to the reset control signal line 532 located on the other side of the second area 102 through the connection line in the fourth conductive layer 560 , or the reset control signal line 532 located on one side of the second area 102
  • the reset control signal line 532 is directly wound at the edge of the second area 102 to the other side of the second area 102 .
  • the reset control signal line electrically connected to the second reset transistor T1 does not use a connection line extending along the first direction and a connection line extending along the second direction to realize the connection on both sides of the second area.
  • the electrical connection between the two parts, but the electrical connection between the two parts located on both sides of the second area through the winding around the edge of the second area, can eliminate the parasitic generated on the reset control signal line electrically connected to the second reset transistor T1. Capacitance is low.
  • the first light-emitting control transistor and the second light-emitting control transistor electrically connected to the light-emitting control signal line, and the first reset transistor and the third reset transistor electrically connected to the reset control signal line are all
  • the P-type transistor, the threshold compensation transistor and the second reset transistor are all N-type transistors. Since P-type transistors have less impact on gate signal voltage jumps than N-type transistors, it is preferred that all or part of the corresponding gate control lines of P-type transistors adopt connection lines extending along the first direction and along the second direction.
  • the direction-extending connection line (ie, FIP connection method) realizes the electrical connection between the two parts located on both sides of the second area, thereby reducing the non-display area around the second area to achieve a narrow frame; at the same time, with the selection of N-type
  • the control signal line electrically connected to the gate of the threshold compensation transistor and the second reset transistor adopts the above-mentioned winding method.
  • the embodiments of the present disclosure are not limited to this.
  • the gate control circuit is electrically connected to the gates of all P-type transistors.
  • Part or all of the signal lines can be electrically connected to the two parts located on both sides of the second area by using the above-mentioned connection lines extending in the first direction and the connection lines extending in the second direction (ie, FIP connection method), thereby reducing the size of the signal line.
  • the non-display area around the second area to achieve narrow borders.
  • the display substrate further includes: a light-emitting element and a pixel circuit located on the base substrate, the pixel circuit being electrically connected to the light-emitting element; wherein the pixel circuit includes at least An N-type thin film transistor and at least one P-type thin film transistor; the second signal line includes a signal line connected to the gate of at least one of the P-type thin film transistor.
  • the display substrate further includes: a light-emitting element and a pixel circuit located on the base substrate, the pixel circuit being electrically connected to the light-emitting element; wherein, the pixel The circuit includes at least one oxide thin film transistor and at least one low temperature polysilicon thin film transistor; the second signal line includes a signal line connected to a gate of at least one of the low temperature polysilicon thin film transistor.
  • Another embodiment of the present disclosure provides a display device, which includes any of the above display substrates.
  • the display device may be a QHD (Quad High Definition) display device, where QHD refers to four times the resolution of a full high-definition screen.
  • the display device may be an FHD (Full High Definition) display device, where FHD refers to full high definition.
  • the display device provided by the embodiment of the present disclosure may be an organic light-emitting diode display device, such as an active-matrix organic light-emitting diode (AMOLED) display device.
  • AMOLED active-matrix organic light-emitting diode
  • the display device may further include a cover located on the display side of the display substrate.
  • the display device may further include a functional component located on a side of the base substrate away from the light-emitting element, and the functional component is directly opposite to the second area.
  • functional components include camera modules (for example, front camera modules), 3D structured light modules (for example, 3D structured light sensors), time-of-flight 3D imaging modules (for example, time-of-flight sensors), infrared sensors At least one of the detection modules (for example, infrared sensing sensor).
  • the display device electrically connects the signal lines located on both sides of the second area by using a first connection line, a second connection line, a third connection line and a fourth connection line, and the first connection line is located on the third connection line. While the lines are away from one side of the second area, the second connection line overlaps with the third connection line. While reducing the wiring space around the second area to increase the area of the display area, the first signal line and the second connection line can be reduced. The load on the signal line suddenly changes.
  • the display device may include any product or component with a display function such as a mobile phone, a tablet computer, a notebook computer, a navigator, etc. This is not limited in the embodiments of the present disclosure.

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Abstract

显示基板以及显示装置。显示基板包括第一信号线(200)和第二信号线(300)。显示基板包括第一区域(101)和第二区域(102)；第一信号线(200)和第二信号线(300)均不经过第二区域(102)。第一信号线(200)沿第一方向延伸，第二信号线(300)沿第二方向延伸；延长线经过第二区域(102)的第一信号线(200)的位于第二区域(102)两侧的部分通过沿第一方向延伸的第一连接线(410)和沿第二方向延伸的第二连接线(420)电连接；延长线经过第二区域(102)的第二信号线(300)的位于第二区域(102)两侧的部分通过沿第一方向延伸的第三连接线(430)和沿第二方向延伸的第四连接线(440)电连接；第二连接线(420)与第三连接线(430)交叠，且第二区域(102)的同一侧中第一连接线(410)位于第三连接线(430)远离第二区域(102)的一侧。显示基板在降低第二区域周边布线空间的同时，减小第一信号线和第二信号线的负载突变。

Description

显示基板以及显示装置
本申请要求于2022年7月28日递交的中国专利申请第202210898751.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种显示基板以及显示装置。
背景技术
在显示技术领域，薄膜晶体管(thin film transistor,TFT)可以包括非晶硅(a-Si)TFT、低温多晶硅(Low Temperature Poly-Silicon,LTPS)TFT、氧化物(如铟镓锌氧化物TFT)等。低温多晶氧化物(Low Temperature Polycrystalline Oxide,LTPO)是一种低功耗显示技术，LTPO技术将低温多晶硅工艺和氧化物工艺融合，在显示面板中制备LTPS TFT和氧化物TFT，从而结合LTPS TFT的优点和氧化物TFT的优点，最大程度地利用低温多晶硅超高迁移率的优势以及氧化物的漏电流较小的优势以实现更为出色的显示性能。
随着人们对显示产品视觉效果的不断追求，窄边框以及显示全面屏逐渐成为当前有机发光二极管(OLED)显示产品发展的大趋势。
发明内容
本公开实施例提供一种显示基板以及显示装置。
本公开的实施例中，显示基板包括衬底基板以及位于所述衬底基板上的多条第一信号线以及多条第二信号线。所述衬底基板包括第一区域和第二区域，所述第一区域位于所述第二区域的周边；所述多条第一信号线，不经过所述第二区域；所述多条第二信号线，与所述多条第一信号线位于不同层，且不经过所述第二区域。其中，至少部分第一信号线沿第一方向延伸，至少部分第二信号线沿第二方向延伸，所述第一方向与所述第二方向相交；所述多条第一信号线包括延长线经过所述第二区域的部分第一信号线，所述部分第一信号线中的每条第一信号线包括位于所述第二区域两侧的第一子信号线和第二子信号线，所述第一子信号线和所述第二子信号线通过沿所述第一方向延伸的第一连接 线和沿所述第二方向延伸的第二连接线电连接，且所述部分第一信号线与多条第一连接线和多条第二连接线电连接；所述多条第二信号线包括延长线经过所述第二区域的部分第二信号线，所述部分第二信号线中的每条第二信号线包括位于所述第二区域两侧的第三子信号线和第四子信号线，所述第三子信号线和所述第四子信号线通过沿所述第一方向延伸的第三连接线和沿所述第二方向延伸的第四连接线电连接，且所述部分第二信号线与多条第三连接线和多条第四连接线电连接；在垂直于所述衬底基板的方向上，至少一条第二连接线与至少一条第三连接线交叠，且所述第二区域的同一侧中，至少一条第一连接线位于至少一条第三连接线远离所述第二区域的一侧。
例如，根据本公开的实施例，所述多条第一信号线包括数据线，所述多条第二信号线至少包括发光控制信号线。
例如，根据本公开的实施例，最靠近所述第二区域的一条第四连接线与所述第二区域的边缘之间的最小距离小于最靠近所述第二区域的一条第一连接线与所述第二区域的边缘之间的最小距离。
例如，根据本公开的实施例，所述第二区域的同一侧中，所述多条第二连接线中的第一组连接线位于至少一条第四连接线靠近所述第二区域的一侧，所述多条第二连接线中的第二组连接线位于所述至少一条第四连接线远离所述第二区域的一侧。
例如，根据本公开的实施例，沿垂直于所述衬底基板的方向，所述第一组连接线与所述第三连接线交叠，且所述第二组连接线与所述第三连接线没有交叠。
例如，根据本公开的实施例，所述第一组连接线中最靠近所述第二组连接线的一条第二连接线与所述第二组连接线中最靠近所述第一组连接线的一条第二连接线之间的距离为第一距离，所述第二组连接线中相邻两条第二连接线之间的距离为第二距离，所述第一距离与所述第二距离之比大于2。
例如，根据本公开的实施例，与所述第一组连接线中最靠近所述第二组连接线的所述一条第二连接线连接的所述第一连接线包括分别位于所述一条第二连接线在所述第一方向上的两侧的两部分。
例如，根据本公开的实施例，与所述第一组连接线中最靠近所述第二组连接线的所述一条第二连接线连接的所述第一连接线延伸至所述第二组连接线中最靠近所述第一组连接线的一条第二连接线的位置处。
例如，根据本公开的实施例，与所述第一组连接线中最靠近所述第二组连接线的N条第二连接线分别连接的N条第一连接线中的每条第一连接线均包括分别位于与其连接的第二连接线在所述第一方向上的两侧的两部分，且沿靠近所述第二区域的方向排列的所述N条第一连接线中，所述第一连接线的位于与其连接的所述第二连接线的靠近所述第二组连接线一侧的部分的长度逐渐减小，N为大于等于1的正整数，且位于所述第二区域中心一侧的所述第一组连接线中的所述第二连接线的数量大于等于N。
例如，根据本公开的实施例，所述多条第二信号线中延长线不经过所述第二区域的部分第二信号线中最靠近所述第二区域的一条第二信号线位于最靠近所述第二区域的一条第四连接线和与其相邻的第四连接线之间。
例如，根据本公开的实施例，所述第二区域的同一侧中，所述多条第一信号线中延长线不经过所述第二区域的至少一条第一信号线位于所述第一连接线靠近所述第二区域的一侧。
例如，根据本公开的实施例，所述多条第一连接线和所述多条第三连接线中彼此最靠近的一条第一连接线和一条第三连接线之间的距离与相邻两条第三连接线之间的距离之比为0.8～1.2。
例如，根据本公开的实施例，在所述第一区域内，至少一条第一连接线与至少一条第三连接线位于同层，至少一条第二连接线与至少一条第四连接线位于同层。
例如，根据本公开的实施例，至少一条第一连接线和至少一条第三连接线均与所述多条第一信号线位于同层。
例如，根据本公开的实施例，所述多条第二信号线位于所述多条第一信号线与所述衬底基板之间，所述第四连接线位于所述多条第一信号线与所述多条第二信号线之间。
例如，根据本公开的实施例，所述第一区域为显示区，所述第一区域围绕所述第二区域，所述衬底基板还包括围绕所述显示区的周边区，所述多条第二组连接线包括位于所述第一区域的所述第二连接线以及位于所述周边区的所述第二连接线，位于所述第一区域的所述第二连接线与所述第一连接线不同层设置，位于所述周边区的所述第二连接线与所述第一连接线同层设置。
例如，根据本公开的实施例，位于所述周边区的所述第二连接线与所述第一信号线同层设置。
例如，根据本公开的实施例，所述第一组连接线中的至少一条第二连接线与至少一条第四连接线同层且间隔设置，且位于同一直线上。
例如，根据本公开的实施例，在所述第二区域的同一侧中，与所述第二组连接线连接的至少一条第一信号线在垂直于所述衬底基板的方向上与各第四连接线均交叠。
例如，根据本公开的实施例，各第一连接线在沿所述第一方向延伸的直线上的正投影与各第三连接线在该直线上的正投影交叠；至少一条第二连接线在沿所述第二方向延伸的直线上的正投影与至少一条第四连接线在该直线上的正投影没有交叠。
例如，根据本公开的实施例，显示基板还包括：位于所述衬底基板上的发光元件和像素电路，所述像素电路与所述发光元件电连接。所述像素电路包括驱动晶体管、发光控制晶体管以及复位晶体管，所述发光控制晶体管的栅极与所述发光控制信号线电连接，所述发光控制晶体管的第一极与所述驱动晶体管的第一极电连接，所述发光控制晶体管的第二极与所述发光元件电连接；所述复位晶体管的栅极与复位控制信号线电连接，所述复位晶体管的一极与所述驱动晶体管的第二极电连接，或者所述复位晶体管的一极与所述发光控制晶体管的第二极电连接；所述第二信号线包括所述复位控制信号线。
例如，根据本公开的实施例，显示基板还包括：位于所述衬底基板上的发光元件和像素电路，所述像素电路与所述发光元件电连接；其中，所述像素电路包括至少一个N型薄膜晶体管和至少一个P型薄膜晶体管；所述第二信号线包括与至少一个所述P型薄膜晶体管的栅极相连接的信号线。
例如，根据本公开的实施例，显示基板还包括：位于所述衬底基板上的发光元件和像素电路，所述像素电路与所述发光元件电连接；其中，所述像素电路包括至少一个氧化物薄膜晶体管和至少一个低温多晶硅薄膜晶体管；所述第二信号线包括与至少一个所述低温多晶硅薄膜晶体管的栅极相连接的信号线。
例如，根据本公开的实施例，所述第一区域为显示区，所述第一区域围绕所述第二区域，所述衬底基板还包括围绕所述显示区的周边区；所述显示基板还包括：沿所述第一方向延伸的多条第五连接线和沿所述第二方向延伸的多条第六连接线，与所述第一连接线位于同层且位于同一直线的所述第五连接线与所述第一连接线间隔设置，与所述第三连接线位于同层且位于同一直线的所述第五连接线与所述第三连接线间隔设置，与所述第二连接线位于同层且位于同 一直线的所述第六连接线与所述第二连接线间隔设置，与所述第四连接线位于同层且位于同一直线的所述第六连接线与所述第四连接线间隔设置，且所述第五连接线和所述第六连接线的至少之一与第三信号线电连接，所述第三信号线位于所述周边区。
例如，根据本公开的实施例，所述第五连接线与所述第一连接线间隔位置处以及所述第五连接线与所述第三连接线间隔位置处的至少之一与所述第四连接线所在膜层交叠，所述第六连接线与所述第二连接线间隔位置处以及所述第六连接线与所述第四连接线间隔位置处的至少之一与所述第一连接线所在膜层交叠。
例如，根据本公开的实施例，至少一条第一连接线两侧设置有与该第一连接线紧邻的两条第一信号线，且所述两条第一信号线与该第一连接线之间的最小距离之比为0.9～1.1；至少一条第三连接线两侧设置有与该第三连接线紧邻的两条第一信号线，且所述两条第一信号线与该第三连接线之间的最小距离之比为0.9～1.1。
本公开另一实施例提供一种显示装置，包括上述任一显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为根据本公开实施例提供的显示基板的局部平面示意图。
图2为根据本公开实施例的像素电路的等效电路图。
图3A至图3H包括像素电路中不同膜层的示意图。
图3I为图3A至图3F所示膜层层叠示意图。
图4为根据本公开实施例的另一示例提供的局部平面结构示意图。
图5为图4所示区域E1的部分膜层示意图。
图6和图7为图5所示位置处的两层导电层示意图。
图8为图4所示区域E2的部分膜层示意图。
图9至图10为图8所示位置处的两层导电层示意图。
图11为图4所示区域E3的部分膜层示意图。
图12为图4所示区域E4的部分膜层示意图。
图13为包括图4所示区域E1的局部膜层示意图。
图14和图15为图13所示位置处的两层导电层示意图。
图16为图1所示区域E5的部分膜层的示意图。
图17为图16所示区域E6的部分膜层示意图。
图18为图16所示区域E7的部分膜层示意图。
图19为图4所示区域E8的部分结构的示意图。
图20为图19所示区域E9的部分结构的示意图。
图21至图25为图20所示位置中不同膜层的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
本公开实施例中使用的“平行”、“垂直”以及“相同”等特征均包括严格意义的“平行”、“垂直”、“相同”等特征，以及“大致平行”、“大致垂直”、“大致相同”等包含一定误差的情况，考虑到测量和与特定量的测量相关的误差(例如，测量系统的限制)，表示在本领域的普通技术人员所确定的对于特定值的可接受的偏差范围内。例如，“大致”能够表示在一个或多个标准偏差内，或者在所述值的10％或者5％内。在本公开实施例的下文中没有特别指出一个成分的数量时，意味着该成分可以是一个也可以是多个，或可理解为至少一个。“至少一个”指一个或多个，“多个”指至少两个。本公开实施例中的“同层”指同一材料在经过同一步骤(例如一步图案化工艺)后形成的多个膜层之间的关系。这里的“同层”并不总是指多个膜层的厚度相同或者多个膜层在截面图 中的高度相同。
本公开实施例提供一种显示基板以及显示装置。显示基板包括衬底基板、以及位于衬底基板上的多条第一信号线和多条第二信号线。衬底基板包括第一区域和第二区域，第一区域位于第二区域的周边；多条第一信号线位于衬底基板上，且不经过第二区域；多条第二信号线与多条第一信号线位于不同层，且不经过第二区域。至少部分第一信号线沿第一方向延伸，至少部分第二信号线沿第二方向延伸，第一方向与第二方向相交；多条第一信号线包括延长线经过第二区域的部分第一信号线，部分第一信号线中的每条第一信号线包括位于第二区域两侧的第一子信号线和第二子信号线，第一子信号线和第二子信号线通过沿第一方向延伸的第一连接线和沿第二方向延伸的第二连接线电连接，且部分第一信号线与多条第一连接线和多条第二连接线电连接；多条第二信号线包括延长线经过第二区域的部分第二信号线，部分第二信号线中的每条第二信号线包括位于第二区域两侧的第三子信号线和第四子信号线，第三子信号线和第四子信号线通过沿第一方向延伸的第三连接线和沿第二方向延伸的第四连接线电连接，且部分第二信号线与多条第三连接线和多条第四连接线电连接；在垂直于衬底基板的方向上，至少一条第二连接线与至少一条第三连接线交叠，且第二区域的同一侧中，至少一条第一连接线位于至少一条第三连接线远离第二区域的一侧。
本公开实施例提供的显示基板通过采用第一连接线、第二连接线、第三连接线和第四连接线连接位于第二区域两侧的信号线，且第一连接线位于第三连接线远离第二区域的一侧的同时，第二连接线与第三连接线交叠，在降低第二区域周边布线空间以增加显示区的面积的同时，可以减小第一信号线和第二信号线的负载突变。
下面结合附图对本公开实施例提供的显示基板以及显示装置进行描述。
图1为根据本公开实施例提供的显示基板的局部平面示意图。如图1所示，显示基板包括衬底基板100、以及位于衬底基板100上的多条第一信号线200和多条第二信号线300。衬底基板100包括第一区域101和第二区域102，第一区域101位于第二区域102的周边。例如，图1示意性的示出第一区域101围绕第二区域102，但不限于此，第一区域101可以仅位于第二区域102的部分周边位置，如第一区域101仅围绕第二区域102的一部分。
例如，如图1所示，第一区域101为显示区，第二区域102可以为位于第 一区域101内的孔区，如第二区域102可以为显示区，也可以为非显示区。例如第二区域102为没有任何信号线经过的区域。例如，第二区域102的边缘可以为孔区的边缘。例如，第二区域102的至少部分边缘与第一方向和第二方向均不平行。例如，第二区域102的形状可以为圆形或者椭圆形。但不限于此，第二区域102的形状可以为多边形，如四边形、六边形或者八边形等。例如，第一区域101的形状可以为四边形，如矩形，但不限于此，第一区域的101的形状也可以为圆形、除四边形外的其他多边形，如六边形、八边形等。
如图1所示，多条第一信号线200不经过第二区域102；多条第二信号线300与多条第一信号线200位于不同层，且不经过第二区域102。例如，每条第一信号线200不经过第二区域102，每条第二信号线300不经过第二区域102。例如，不经过第二区域102的多条第一信号线200包括延长线不经过第二区域102的第一信号线200以及延长线经过第二区域102的第一信号线200；不经过第二区域102的多条第二信号线300包括延长线不经过第二区域102的第二信号线300以及延长线经过第二区域102的第二信号线300。
如图1所示，至少部分第一信号线200沿第一方向延伸，至少部分第二信号线300沿第二方向延伸，第一方向与第二方向相交。图1示意性的示出第一方向为X方向，第二方向为Y方向，但不限于此，第一方向与第二方向可以互换。例如，第一方向与第二方向可以垂直，但不限于此，第一方向与第二方向之间的夹角可以为60～110度。例如，第一方向和第二方向之一可以为行方向，另一个为列方向。例如，每条第一信号线200沿第一方向延伸，每条第二信号线200沿第二方向延伸。本公开实施例中第一信号线沿第一方向延伸可以指第一信号线的整体的延伸方向为第一方向，而第一信号线可以是沿第一方向延伸的直线，也可以为沿第一方向延伸的折线；第二信号线沿第二方向延伸可以指第二信号线的整体的延伸方向为第二方向，而第二信号线可以是沿第二方向延伸的直线，也可以为沿第二方向延伸的折线。
如图1所示，多条第一信号线200包括延长线经过第二区域102的部分第一信号线200，部分第一信号线200中的每条第一信号线200包括位于第二区域102两侧的第一子信号线210和第二子信号线220，第一子信号线210和第二子信号线220通过沿第一方向延伸的第一连接线410和沿第二方向延伸的第二连接线420电连接，且部分第一信号线200与多条第一连接线410和多条第二连接线420电连接。例如，第一连接线410与第二连接线420电连接，延长 线经过第二区域102的第一信号线200会在第二区域102位置处断开而形成为两部分，即第一子信号线210和第二子信号线220，这两部分传输相同的信号，且这两部分通过第一连接线410以及第二连接线420电连接。
例如，本公开实施例不限于所有第一连接线位于同一层，所有第二连接线位于同一层，如部分第二连接线可以与第一连接线同层，部分第二连接线可以与第一连接线位于不同层。
如图1所示，多条第二信号线300包括延长线经过第二区域102的部分第二信号线300，部分第二信号线300中的每条第二信号线300包括位于第二区域102两侧的第三子信号线310和第四子信号线320，第三子信号线310和第四子信号线320通过沿第一方向延伸的第三连接线430和沿第二方向延伸的第四连接线440电连接，且部分第二信号线300与多条第三连接线430和多条第四连接线440电连接。例如，第三连接线430和第四连接线440电连接，延长线经过第二区域102的第二信号线300会在第二区域102位置处断开而形成为两部分，即第三子信号线310和第四子信号线320，这两部分传输相同的信号，且这两部分通过第四连接线440以及第三连接线430电连接。
例如，上述“延长线经过第二区域102的部分第一信号线200”的延长线可以指第一信号线200靠近第二区域102的端点向第二区域102延伸的部分。例如，上述“延长线经过第二区域102的部分第二信号线300”的延长线可以指第二信号线300靠近第二区域102的端点向第二区域102延伸的部分。
例如，本公开实施例不限于所有第三连接线位于同一层，所有第四连接线位于同一层，如部分第四连接线可以与第三连接线同层，部分第四连接线可以与第三连接线位于不同层。
例如，如图1所示，延长线不经过第二区域102的第一信号线200可以为一条连续的信号线，延长线不经过第二区域102的第二信号线300可以为一条连续的信号线。
如图1所示，在垂直于衬底基板100的方向上，至少一条第二连接线420与至少一条第三连接线430交叠，且第二区域102的同一侧中，至少一条第一连接线410位于至少一条第三连接线430远离第二区域101的一侧。
本公开实施例提供的显示基板通过采用第一连接线和第二连接线连接位于第二区域两侧的第一信号线的同时，采用第三连接线和第四连接线连接位于第二区域两侧的第二信号线，且至少一条第一连接线位于至少一条第三连接线 远离第二区域的一侧的同时，第二连接线与第三连接线交叠，在降低第二区域周边布线空间以增加显示区的空间的同时，可以减小第一信号线和第二信号线的负载(loading)突变，防止出现显示不均，如显示mura。
相比于一般显示基板中，第一信号线和第二信号线至少之一在第二区域周边围绕第二区域边界绕线的设计，本公开实施例提供的显示基板中，通过将第一信号线和第二信号线均通过沿第一方向和第二方向延伸的连接线，如采用FIP(Fun-out In Pixel，fan-out线位于像素区)连接线实现位于第二区域两侧的两部分的电连接，可以节省第二区域周边的边界尺寸，如减小第二区域周围边框，有利于提高显示区域的面积，进而提升显示效果。
例如，如图1所示，显示基板的第一区域101中，延长线不经过第二区域102的第一信号线200的长度大于延长线不经过第二区域102的第二信号线300的长度。
例如，如图1所示，延长线不经过第二区域102的第一信号线200在第一方向上的尺寸与第二区域102在第一方向上的最大尺寸之比为r1，延长线不经过第二区域102的第二信号线400在第二方向上的最大尺寸与第二区域102在第二方向上的最大尺寸之比为r2，r1大于r2。
在一些示例中，如图1所示，最靠近第二区域102的第四连接线440与第二区域102的边缘之间的最小距离小于最靠近第二区域的第一连接线410与第二区域102的边缘之间的最小距离。
第二区域的尺寸在第一信号线长度上的占比小于第二区域的尺寸在第二信号线长度上的占比，由此，第三连接线的长度对于第二信号线的负载影响大于第二连接线的长度对于第一信号线的负载影响。本公开实施例提供的显示基板中，将第四连接线设置为比第一连接线更靠近第二区域的边缘，可以使得与延长线经过第二区域的第二信号线连接的第三连接线的长度较短，从而降低延长线经过第二区域的第二信号线上的负载与延长线没有经过第二区域的第二信号线上的负载差异。
例如，如图1所示，第二区域102的同一侧中，最靠近第二区域102的一条第四连接线440与最靠近第二区域102且延长线不经过第二区域102的一条第二信号线300之间的距离为D1，最靠近第二区域102的一条第一连接线410与最靠近第二区域102且延长线不经过第二区域102的一条第一信号线200之间的距离为D2，D1小于D2。
在一些示例中，如图1所示，第一信号线200包括数据线，第二信号线300至少包括发光控制信号线。
图2为根据本公开实施例的像素电路的等效电路图，图3A至图3H包括像素电路中不同膜层的示意图，图3I为图3A至图3F所示膜层层叠示意图。
在一些示例中，如图2所示，显示基板还包括多个子像素，至少部分子像素包括发光元件120以及与发光元件120电连接的像素电路110。
例如，如图2至图3I所示，像素电路包括多个晶体管以及至少一个电容。例如，像素电路包括第二复位晶体管T1、阈值补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6，第一复位晶体管T7、第三复位晶体管T8以及存储电容C。
例如，如图2至图3I所示，显示基板还包括复位电源信号线561、551和554，扫描信号线552、531和523，电源信号线581，复位控制信号线522、532和553，发光控制信号线521以及数据线200。
例如，如图2至图3I所示，阈值补偿晶体管T2的第一极与驱动晶体管T3的第一极电连接，阈值补偿晶体管T2的第二极与驱动晶体管T3的栅极电连接，阈值补偿晶体管T2的栅极与扫描信号线531和552电连接以接收补偿控制信号；第一复位晶体管T7的第一极与复位电源信号线561电连接以接收复位信号Vinit2，第一复位晶体管T7的第二极与发光元件的第一电极电连接(即N4节点)，第一复位晶体管T7的栅极与复位控制信号线522电连接以接收复位控制信号Reset(N+1)；第三复位晶体管T8的第一极与复位电源信号线551电连接以接收复位信号Vref，第三复位晶体管T8的第二极与驱动晶体管T3的第二极电连接，第三复位晶体管T8的栅极与复位控制信号线522电连接；数据写入晶体管T4的第一极与驱动晶体管T3的第二极电连接，数据写入晶体管T4的第二极与数据线200(第一信号线200)电连接以接收数据信号Data，数据写入晶体管T4的栅极与扫描信号线523电连接以接收扫描信号Gate；存储电容C的第一极与电源信号线581电连接，存储电容C的第二极与驱动晶体管T3的栅极电连接；第二复位晶体管T1的第一极与复位电源信号线554电连接以接收复位信号Vinit1，第二复位晶体管T1的第二极与驱动晶体管T3的栅极电连接，第二复位晶体管T1的栅极与复位控制信号线553和532电连接以接收复位控制信号Reset(N)；第一发光控制晶体管T6的栅极与发光控制信号线521电连接以接收发光控制信号EM，第一发光控制晶体管T6的第一极与驱动 晶体管T3的第一极电连接，第一发光控制晶体管T6的第二极与发光元件120的第一电极电连接；第二发光控制晶体管T5的第一极与电源信号线581电连接以接收第一电源信号VDD，第二发光控制晶体管T5的第二极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T5的栅极与发光控制信号线521电连接以接收发光控制信号EM，发光元件120的第二电极与电压端VSS(后续第三信号线600)电连接。上述电源信号线指输出电压信号VDD的信号线，可以与电压源连接以输出恒定的电压信号，例如正电压信号。
需要说明的是，在本公开实施例中，各像素电路除了可以为图2所示的8T1C(即八个晶体管和一个电容)结构之外，还可以为包括其他数量的晶体管的结构，如7T1C结构、7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。
图3A示出了第一有源层图案510。例如，如图3A所示，第一有源层图案510可用于制作上述的驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6、第一复位晶体管T7以及第三复位晶体管T8的有源层以用于形成上述晶体管的沟道区。第一有源层图案510包括各子像素的上述晶体管的有源区图案(沟道区)和掺杂区图案(源漏区)，且同一像素电路中的上述晶体管的有源区图案和掺杂区图案一体设置。
例如，第一有源层图案510可以包括一体形成的低温多晶硅层，源极区域和漏极区域可以通过掺杂等进行导体化实现各结构的电连接。例如，上述的源极区域和漏极区域可为掺杂有p型杂质的区域。
图3B示出了位于第一有源层图案510远离衬底基板一侧的第一导电层图案520。例如，如图3B所示，第一导电层图案520包括复位控制信号线522、扫描信号线523、电容的第一极524以及发光控制信号线521。例如，第一导电层图案520可以包括驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6、第一复位晶体管T7以及第三复位晶体管T8的栅极。
需要说明的是，图3A中的各虚线矩形框示出了第一有源层图案510与第一导电层图案520交叠的各个部分，即沟道区。作为各个晶体管的沟道区，在每个沟道区两侧的有源半导体层通过离子掺杂等工艺导体化作为各个晶体管的第一极和第二极。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管， 除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
例如，如图3B和图3I所示，数据写入晶体管T4的栅极可以为扫描信号线523与第一有源层图案510交叠的部分；第一发光控制晶体管T6的栅极可以为发光控制信号线521与第一有源层图案510交叠的第一部分，第二发光控制晶体管T5的栅极可以为发光控制信号线521与第一有源层图案510交叠的第二部分。第三复位晶体管T8的栅极为复位控制信号线522与第一有源层图案510交叠的第一部分，第一复位晶体管T7的栅极为复位控制信号线522与第一有源层图案510交叠的第二部分。
图3C示出了第一导电层图案520远离衬底基板一侧的第二导电层图案530。例如，如图3C所示，第二导电层图案530包括扫描信号线531、电容C的第二极533以及复位控制信号线532。
图3D示出了第二导电层图案530远离衬底基板一侧的第二有源层图案540。例如，如图3D所示，第二有源层图案540包括第二复位晶体管T1和阈值补偿晶体管T2的沟道区。例如，第二复位晶体管T1和阈值补偿晶体管T2中的有源层采用氧化物半导体的情况下，因用氧化物半导体的晶体管具备磁滞特性好、漏电流低的特点，故可以采用氧化物半导体的晶体管代替晶体管中的低温多晶硅材料，形成低温多晶硅-氧化物的(LTPO)像素电路，实现低漏电，利于提高晶体管的栅极电压的稳定性。
例如，如图3C、3D和图3I所示，第二复位晶体管T1的栅极可以为复位控制信号线532与第二有源层图案540交叠的部分，阈值补偿晶体管T2的栅极可以为扫描信号线531与第二有源层图案540交叠的部分。
图3E示出了第二有源层图案540远离衬底基板一侧的第三导电层550。例如，如图3E所示，第三导电层550包括复位电源信号线554、复位控制信号线553、扫描信号线552以及复位电源信号线551。
例如，如图3C至图3F以及图3I所示，复位控制信号线553与第二复位晶体管T1的沟道区交叠，第二复位晶体管T1包括位于有源层两侧的顶栅和底栅；扫描信号线552与阈值补偿晶体管T2的沟道区交叠，阈值补偿晶体管T2包括位于有源层两侧的顶栅和底栅。
例如，第二复位晶体管T1和阈值补偿晶体管T2可以为N型晶体管。驱 动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6、第一复位晶体管T7以及第三复位晶体管T8可以为P型晶体管。
图3F示出了位于第三导电层550远离衬底基板一侧的第四导电层560。例如，如图3F所示，第四导电层560包括复位电源信号线561、连接部568、连接部569、连接部563、连接部567、连接部562、连接部564、连接部565以及连接部566。
例如，如图2至图3I所示，连接部568的两端连接复位电源信号线551，中间连接第三复位晶体管T8的第一极；连接部569连接第一信号线200与数据写入晶体管T4的第二极；连接部563用于电连接数据写入晶体管T4的第一极与第三复位晶体管T8的第二极，以将复位信号Vref引到N2节点；连接部567用于电连接驱动晶体管T3的第一极与阈值补偿晶体管T2的第一极；连接部562的中间连接电源信号线581，连接部562的两端连接电容的第二极533，一方面将相邻的电容C第二极533进行电性连接，另一方面将电源电压加载到电容C第二极533上；连接部564的一端与电容C的第二极533连接，连接部564的另一端与第二发光控制晶体管T5的第一极连接；连接部565用于电连接发光元件的第一电极与第一发光控制晶体管T6的第二极；连接部566用于电连接复位电源信号线554与第二复位晶体管T1的第一极。
图3G示出了位于第四导电层560远离衬底基板一侧的第五导电层570。例如，如图3G所示，第五导电层570包括连接部573、连接部575、电源信号线572、连接部574、第二连接线420以及第六连接线460。例如，第五导电层570还包括第四连接线。
例如，如图2至图3G所示，连接部573与第一信号线200电连接，如第一信号线200通过连接部573与第二连接线420电连接以向第二连接线420传输第一信号，例如可以在连接部573和第二连接线420之间增设连接块来实现第一信号线200和第二连接线420的电性连接；连接部575为预留垫，该预留垫可以与第一连接线通过过孔保持电性连接，在需要将第一连接线和第二连接线进行电性连接的位置，在第二连接线420和连接部575之间增设连接块，使得第一连接线可以通过预留垫与第二连接线420电连接；同样地，第三连接线可以通过预留垫与第四连接线电连接。例如，连接部574与连接部565电连接以实现第一发光控制晶体管T6的第二极与发光元件的第一电极的电连接。例如，电源信号线572与电源信号线581电连接。
图3H示出了位于第五导电层570远离衬底基板一侧的第六导电层580。例如，如图3H所示，第六导电层580包括第一信号线200、电源信号线581、第五连接线450、连接部584和连接部585。例如，第六导电层580还包括第一连接线和第三连接线。
例如，连接部584和连接部585与不同发光元件的第一电极电连接。
例如，如图3G和图3H所示，第一信号线200包括转接垫290，第一信号线200通过转接垫290与连接部573连接，以与第二连接线电连接。例如，第五连接线、第一连接线以及第三连接线均包括转接垫459，各连接线通过相应的转接垫459与连接部575电连接。
例如，如图1至图3H所示，第二信号线300可以位于第一导电层图案520中。例如，第二信号线300可以包括发光控制信号线521和复位控制信号线522的至少之一。
例如，如图1至图3H所示，多条第二信号线300位于多条第一信号线200与衬底基板100之间，第四连接线440位于多条第一信号线200与多条第二信号线300之间。
例如，如图1所示，第二区域102的同一侧中，所有第一连接线410均位于第三连接线430远离第二区域102的一侧。通过将所有第一连接线设置为均位于第三连接线远离第二区域的一侧，有利于尽量减少与所有延长线经过第二区域的第二信号线连接的第三连接线的长度，进而降低延长线经过第二区域的第二信号线与延长线没有经过第二区域的第二信号线的负载差异。
当然，本公开实施例不限于此，部分第一连接线和部分第三连接线可以交替设置，有利于降低延长线经过第二区域的第一信号线与延长线不经过第二区域的第一信号线的负载差异。
例如，如图1所示，部分第二连接线420与各第四连接线440位于同层，同层设置的第二连接线420与第四连接线440中，至少一条第二连接线420与第四连接线440位于同一直线且间隔设置。例如，在垂直于衬底基板100的方向上，与第四连接线440位于同一直线的第二连接线420与第三连接线430交叠。
例如，如图1所示，在第二区域102的同一侧，至少一条延长线经过第二区域102的第一信号线200位于至少一条第三连接线430与第二区域102之间。例如，在第二区域102的同一侧，至少一条延长线不经过第二区域102的第一 信号线200位于至少一条第三连接线430与第二区域102之间。例如，至少一条第三连接线430位于至少一条延长线不经过第二区域102的第一信号线200与至少一条延长线经过第二区域102的第一信号线200之间。
在一些示例中，如图1所示，第二区域102的同一侧中，多条第一信号线200中延长线不经过第二区域102的至少一条第一信号线200位于第一连接线410靠近第二区域102的一侧。
例如，如图1所示，在第二区域102的同一侧设置的至少部分第一连接线410等间距设置。例如，在第二区域102的同一侧设置的至少部分第四连接线440等间距设置。通过将第一连接线等间距设置，有利于降低与第一连接线连接的第一信号线出现较大的负载突变；通过将第四连接线等间距设置，有利于降低与第四连接线连接的第二信号线出现较大的负载突变。
在一些示例中，如图1所示，多条第一连接线410和多条第三连接线430中彼此最靠近的一条第一连接线410和一条第三连接线430之间的距离与相邻两条第三连接线430之间的距离之比为0.8～1.2。例如，彼此最靠近的一条第一连接线410和一条第三连接线430之间的距离与相邻两条第三连接线430之间的距离之比为0.9～1.1。例如，彼此最靠近的一条第一连接线410和一条第三连接线430之间的距离与相邻两条第三连接线430之间的距离相等。
通过将最靠近第二区域的一条第一连接线设置为与第三连接线之间的距离较近，可以使得与该第一连接线连接第二连接线的长度较小，进而降低与该第一连接线连接的第一信号线上的负载与最靠近第二区域且延长线不经过第二区域的第一信号线的负载差异，有利于避免显示基板在显示时出现mura现象。
在一些示例中，如图1所示，在第一区域101中，至少部分第一连接线410与至少部分第三连接线430位于同层，至少部分第二连接线420与至少部分第四连接线440位于同层。
例如，各第一连接线410在沿第一方向延伸的直线上的正投影与各第三连接线430在沿第一方向延伸的直线上的正投影交叠，至少一条第二连接线420在沿第二方向延伸的直线上的正投影与至少一条第四连接线440在该直线上的正投影没有交叠。
本公开实施例将第一连接线与第三连接线沿第二方向排列以防止第一连接线与第三连接线发生干涉；由于部分第二连接线与第四连接线在第二方向上 间隔设置，可以将部分第二连接线穿插在第三连接线中，以使得这部分第二连接线与位于第三连接线靠近第二区域一侧的第一信号线电连接，可以尽量降低第二连接线的长度，如第二连接线上的寄生电容为最靠近延长线不经过第二区域的第一信号线(可以称为正常信号线)的一条延长线经过第二区域的第一信号线与该正常信号线上的负载差异，进而降低与第二连接线电连接的第一信号线上的负载和正常信号线上的负载差异。
在一些示例中，如图1所示，多条第二信号线300中延长线不经过第二区域102的部分第二信号线300中最靠近第二区域102的一条第二信号线300位于最靠近第二区域102的一条第四连接线440和与其相邻的第四连接线440之间。通过将最靠近第二区域的第四连接线设置为与最靠近第二区域且延长线不经过第二区域的第二信号线距离较近，可以减小与最靠近第二区域的第四连接线连接的第三连接线的长度，进而降低与该第四连接线电连接的第二信号线上负载与延长线不经过第二区域的第二信号线上负载的差异，有利于降低显示mura。
在一些示例中，如图1所示，第二区域102的同一侧中，多条第二连接线420中的第一组连接线4201位于至少一条第四连接线440靠近第二区域102的一侧，多条第二连接线420中的第二组连接线4202位于该至少一条第四连接线440远离第二区域102的一侧。例如，第一组连接线4201包括的第二连接线420的数量可以小于第二组连接线4202包括的第二连接线420的数量。例如，第一组连接线4201与第二组连接线4202之间设置有多条第四连接线440。
本公开实施例提供的显示装置，通过将第二连接线设置为包括位于第四连接线两侧的两组连接线，既可以防止第四连接线与第二连接线因同层设置而产生干扰，又可以防止第一信号线和第二信号线产生负载突变而造成显示mura。
在一些示例中，如图1所示，沿垂直于衬底基板100的方向，第一组连接线4201与第三连接线430交叠，且第二组连接线4202与第三连接线430没有交叠。
例如，如图1所示，在垂直于衬底基板100的方向，至少一条第三连接线430与第二连接线420没有交叠。例如，第一组连接线4201中的每条连接线420与至少一条第三连接线430交叠。
在一些示例中，如图1所示，在第二区域102的同一侧中，与第二组连接 线4202连接的至少一条第一信号线200在垂直于衬底基板100的方向上与各第四连接线440均交叠。例如，在第二区域102的同一侧中，与第二组连接线4202连接的每条第一信号线200在垂直于衬底基板100的方向上与所有第四连接线440均交叠。
由于与第二组连接线连接的第一信号线与第四连接线交叠，为了避免第二组连接线中的第二连接线与第四连接线的位置发生干涉，本公开实施例提供的显示基板中，将第二组连接线设置在第四连接线远离第二区域的一侧。
例如，如图1所示，在第二区域102的沿第二方向延伸的中心线的同一侧中，第一组连接线4201中的第二连接线420等间距设置。例如，在第二区域102的沿第二方向延伸的中心线的同一侧中，第二组连接线4202中的第二连接线420等间距设置。例如，第一组连接线4201中相邻两条第二连接线420之间的距离可以与第二组连接线4202中相邻两条第二连接线420之间的距离相等。
例如，第二组连接线4202中最靠近第四连接线440的一条第二连接线420与该第四连接线440之间的距离可以与第二组连接线4202中相邻两条第二连接线420之间的距离相等。
在一些示例中，如图1所示，第一组连接线4201中最靠近第二组连接线4202的一条第二连接线420与第二组连接线4202中最靠近第一组连接线4201的一条第二连接线420之间的距离为第一距离S1，第二组连接线4202中相邻两条第二连接线420之间的距离为第二距离S2，第一距离S1与第二距离S2之比大于2。例如，第一距离S1与第二距离S2之比大于3。例如，第一距离S1与第二距离S2之比大于4。例如，第一距离S1与第二距离S2之比大于5。例如，第一距离S1与第二距离S2之比大于6。例如，第一距离S1与第二距离S2之比大于7。例如，第一距离S1与第二距离S2之比大于8。例如，第一距离S1与第二距离S2之比大于9。例如，第一距离S1与第二距离S2之比大于10。
图4为根据本公开实施例的另一示例提供的局部平面结构示意图。
图5为图4所示区域E1的部分膜层示意图，图6和图7为图5所示位置处的两层导电层示意图，图8为图4所示区域E2的部分膜层示意图，图9至图10为图8所示位置处的两层导电层示意图。图5至图10所示区域的膜层结构可以与图1所示显示基板中相应区域的膜层结构具有相同的特征。
例如，如图4至图10所示，第一信号线200包括延长线经过第二区域102的第一信号线201-1和201-2，以及延长线不经过第二区域102的第一信号线202-1和202-2，第一信号线201-1为最靠近延长线不经过第二区域102的延长线经过第二区域102的一条第一信号线，第一信号线202-1为最靠近延长线经过第二区域102的延长线不经过第二区域102的一条第一信号线。
例如，如图4至图10所示，第二连接线420包括与第一信号线201-2电连接的第二连接线420-2以及与第一信号线201-1电连接的第二连接线420-1。例如，第二连接线420-1通过连接部0421与第一信号线201-1电连接，第二连接线420-2通过连接部0422与第一信号线201-2电连接。
例如，如图4至图10所示，第一连接线410包括与第二连接线420-1连接的第一连接线410-1以及与第二连接线420-2电连接的第一连接线410-2。例如，第二连接线420-1通过连接部0423与第一连接线410-1电连接，第二连接线420-2通过连接部0425与第一连接线410-2电连接。
例如，如图4至图10所示，位于第二区域102一侧的第一信号线210(即第一信号线201-1)将第一信号通过第二连接线420-1和第一连接线410-1传输至位于第二区域102另一侧的第一信号线220；位于第二区域102一侧的第一信号线201-2将第一信号通过第二连接线420-2和第一连接线410-2传输至位于第二区域102另一侧的第一信号线220。图5和图8中的黑色虚线箭头示意性的示出了第一信号的传输路径。
在一些示例中，如图9和图10所示，显示基板还包括沿第一方向延伸的多条第五连接线450和沿第二方向延伸的多条第六连接线460。
在一些示例中，如图9和图10所示，多条第五连接线450包括与第一连接线410位于同层的至少部分第五连接线450，上述至少部分第五连接线450中与第一连接线410位于同一直线的第五连接线450与第一连接线410间隔设置，如第一连接线410-1与第五连接线450之间设置有间隔0426。
例如，位于同一直线且间隔设置的两条连接线可以为同一条连接线断开为两段不同的连接线。
在一些示例中，如图9和图10所示，多条第六连接线460包括与第二连接线420位于同层的至少部分第六连接线460，上述至少部分第六连接线460中与第二连接线420位于同一直线的第六连接线460与第二连接线420间隔设置，如第二连接线420-1与第六连接线460之间设置有间隔0424。
在一些示例中，如图1所示，多条第五连接线450包括与第三连接线430位于同层的至少部分第五连接线450，上述至少部分第五连接线450中与第三连接线430位于同一直线的第五连接线450与第三连接线430间隔设置。
在一些示例中，如图1所示，多条第六连接线460包括与第四连接线440位于同层的至少部分第六连接线460，上述至少部分第六连接线460中与第四连接线440位于同一直线的第六连接线460与第四连接线440间隔设置。
在一些示例中，如图1所示，显示基板还包括周边区103，周边区103围绕显示区，如第一区域101。例如，周边区103为不用于显示的区域，显示区为用于显示的区域，如第一区域101为用于显示的区域。
在一些示例中，如图1、图17以及图18所示，显示基板还包括位于周边区103的第三信号线600，第五连接线450和第六连接线460的至少之一与第三信号线600电连接。例如，第三信号线600可以为围绕显示区的一圈环状信号线。例如，第三信号线600被配置为传输VSS信号。例如，第三信号线600被配置为与发光元件的第二电极，如阴极电连接。
例如，第五连接线450和第六连接线460均与第三信号线600电连接。
本公开实施例通过设置多条第五连接线和多条第六连接线，有利于提高连接线位置的均匀性，降低显示mura；此外，通过将第五连接线和第六连接线与第三信号线电连接，有利于降低第三信号线的负载。
在一些示例中，如图5至图10所示，至少一条第一连接线410和至少一条第三连接线430均与多条第一信号线200位于同层。例如，各第一连接线410均与第一信号线200同层设置。例如，各第三连接线430均与第一信号线200同层设置。
在一些示例中，如图5至图10所示，第五连接线450与第一连接线410间隔位置处以及第五连接线450与第三连接线430间隔位置处的至少之一与第四连接线440所在膜层交叠，如与第五导电层570中的结构交叠。例如，第六连接线460与第二连接线420间隔位置处以及第六连接线460与第四连接线440间隔位置处的至少之一与第一连接线410所在膜层交叠，如与第六导电层580中的结构交叠。
例如，如图5至图10所示，第二连接线420与第六连接线460之间的间隔0424与第一信号线200交叠。例如，第一连接线410与第五连接线450之间的间隔0426与第二连接线420交叠。
本公开实施例提供的显示基板中，通过将位于同一直线上的两条连接线的之间的间隔被另一层连接线或者另一层信号线遮挡，有利于进一步降低显示mura，如息屏mura。
在一些示例中，如图8所示，至少一条第一连接线410两侧设置有与该第一连接线410紧邻的两条第一信号线200，且两条第一信号线200与该第一连接线410之间的最小距离之比为0.9～1.1。例如，两条第一信号线200与该第一连接线410之间的最小距离相同。
例如，如图8所示，多条第一信号线200可以划分为多个第一信号线对200，每个第一信号线对200位于相邻两个子像素，如两个发光元件之间，且至少一个第一信号线对200之间设置有一条第一连接线410。
在一些示例中，如图1所示，至少一条第三连接线430两侧设置有与该第三连接线430紧邻的两条第一信号线200，且两条第一信号线200与该第三连接线430之间的最小距离之比为0.9～1.1。例如，两条第一信号线200与该第三连接线430之间的最小距离相同。
例如，至少一个第一信号线对200之间设置有一条第三连接线430。
例如，如图10所示，至少一条第五连接线450两侧设置有与该第五连接线450紧邻的两条第一信号线200，且两条第一信号线200与该第五连接线450之间的最小距离之比为0.9～1.1。例如，两条第一信号线200与该第五连接线450之间的最小距离相同。
本公开实施例提供的显示基板中，第一连接线与第一信号线采用2in1的方式设置，第三连接线与第一信号线采用2in1的方式设置，第五连接线与第一信号线采用2in1的方式设置。
当然，本公开实施例不限于此，至少一个第一信号线对之间还可以设置两条第一连接线，如采用1in1设置方式。
图11为图4所示区域E3的部分膜层示意图，图12为图4所示区域E4的部分膜层示意图。图13为包括图4所示区域E1的局部膜层示意图，图14和图15为图13所示位置处的两层导电层示意图。
在一些示例中，如图4和图11所示，与第一组连接线4201中最靠近第二组连接线4202的一条第二连接线420连接的第一连接线410包括分别位于一条第二连接线420在第一方向上的两侧的两部分411和412。例如，该第一连接线410的一部分411用于向位于第二区域102另一侧的第一信号线200传输 第一信号，该第一连接线410的另一部分412用于平衡该第一连接线410上的寄生电容与第二组连接线4202中最靠近第一组连接线4201的一条第二连接线420上的寄生电容的差异，如另一部分412可以作为负载补偿部分。例如，该第一连接线410的一部分411可以视为正向延伸的部分，另一部分412可以视为反向延伸的部分。
在分别位于第一组连接线与第二组连接线中且彼此最靠近的两条第二连接线之间的距离大于第一组连接线(或第二组连接线)中相邻两条第二连接线之间的距离时，通过将与第一组连接线中最靠近第二组连接线的一条第二连接线连接的第一连接线的长度延长，如该第一连接线包括用于传输第一信号线的正向延伸的一部分以及相对于该正向延伸的部分反向延伸的另一部分，可以降低两组连接线中第二连接线的负载突变，进而降低显示mura，提升显示效果。
在一些示例中，如图4、图11和图12所示，与第一组连接线4201中最靠近第二组连接线4202的一条第二连接线420-11连接的第一连接线410延伸至第二组连接线4202中最靠近第一组连接线4201的一条第二连接线420-12的位置处。例如，与第二连接线420-11连接的第一连接线410的反向延伸的部分412延伸至第二连接线420-12的位置处。
本公开实施例通过将与第一组连接线中最靠近第二组连接线的一条第二连接线连接的第一连接线反向延伸的部分延伸至第二组连接线中最靠近第一组连接线的一条第二连接线的位置处，有利于将分别位于第一组连接线和第二组连接线且彼此最靠近的两条第二连接线上的负载差异降到最低，进而防止因两组连接线之间的间隔设置的较大而产生较大的负载跳变。
例如，如图4、图11和图12所示，与第二连接线420-11连接的第一连接线410的反向延伸部分412和第五连接线450之间的间隔与第二连接线420-12交叠。
在一些示例中，如图4、图11至图15所示，与第一组连接线4201中最靠近第二组连接线4202的N条第二连接线420分别连接的N条第一连接线410中的每条第一连接线410均包括分别位于与其连接的第二连接线420在第一方向上的两侧的两部分411和412，且沿靠近第二区域102的方向，N条第一连接线410中位于与其连接的第二连接线420在第一方向上的两侧的两部分411和412的长度均逐渐减小，N为大于等于1的正整数，且位于第二区域102中心一侧的第一组连接线4101中的第二连接线420的数量大于等于N。
例如，如图4、图13至图15所示，第一组连接线4201中最靠近第二组连接线4202的第二连接线420包括第二连接线420-1、第二连接线420-2以及第二连接线420-3，第一连接线410包括与第二连接线420-1连接的第一连接线410-1，与第二连接线420-2连接的第一连接线410-2以及与第二连接线420-3连接的第一连接线410-3。
例如，如图4、图13至图15所示，沿第二组连接线4202指向第一组连接线4201的方向，第二连接线420-3、第二连接线420-2以及第二连接线420-1依次排列，如第二连接线420-3比第二连接线420-2更靠近第二组连接线4202。
例如，如图4、图13至图15所示，第一连接线410-3的部分412-3、第一连接线410-2的部分412-2以及第一连接线410-1的部分412-1的长度逐渐减小，如第一连接线410-3的部分412-3的长度大于第一连接线410-2的部分412-2的长度。
本公开实施例提供的显示基板中，根据第一组连接线中各第二连接线与第二组连接线之间的距离关系，调节对第一连接线反向延长的部分的长度，有利于降低第二组连接线中的第二连接线与第一组连接线中的第二连接线的负载突变的同时，尽量降低第一组连接线中相邻第二连接线上负载差异。
例如，如图4、图13至图15所示，与第一组连接线4201中至少部分第二连接线420连接的多条第一连接线410中任意相邻两个第一连接线410反向延长部分的长度差均在一定范围内，如长度差可以为1～5个子像素在第一方向上的尺寸，如长度差可以为2～4个子像素在第一方向上的尺寸。
例如，如图4所示，与第一组连接线4201中的第二连接线420连接的第一连接线410可以包括两个反向延伸部分412以及位于两个反向延伸部分412之间的正向延伸部分411。例如，每条第一连接线410包括的两个反向延伸部分412的长度相等。
图16为图1所示区域E5的部分膜层的示意图，图17为图16所示区域E6的部分膜层示意图，图18为图16所示区域E7的部分膜层示意图。
在一些示例中，如图1、图11、图12、图16至图18所示，多条第二组连接线4202包括位于第一区域101的第二连接线420以及位于周边区103的第二连接线420，位于第一区域102的第二连接线420与第一连接线410不同层设置，位于周边区103的第二连接线420与第一连接线410同层设置。
例如，如图1、图16至图18所示，一条第一连接线410与两条第二连接 线420电连接，这两条第二连接线420中位于第一区域101中的一条第二连接线420与第一连接线410不同层设置，位于周边区103中的一条第二连接线420与第一连接线410同层且一体化设置。
在一些示例中，如图1、图16至图18所示，位于周边区103的第二连接线420与第一信号线200同层设置。例如，位于第二区域102靠近周边区103的第二子信号线220和与其连接的第二连接线420同层且一体化设置。
例如，图17和图18示意性的示出第五连接线450与位于周边区103的第三信号线600电连接。例如，E6区域中的第五连接线450直接与第三信号线600电连接，E7区域中的第五连接线450通过与第一区域101设置的第二连接线同层设置的转接线0450与第三信号线600电连接。
例如，如图1所示，第三连接线430和第四连接线440均位于第一区域101。
例如，如图1所示，第一组连接线4201包括的各第二连接线420以及与第一组连接线4201中各第二连接线420连接的第一连接线410均位于第一区域101。
例如，显示基板还包括：位于第一区域101的多个第一发光元件、多个第一像素电路以及多个第二像素电路，以及位于第二区域102的多个第二发光元件，多个第一像素电路与多个第一发光元件一一对应电连接，多个第二像素电路与多个第二发光元件一一对应电连接。例如，第二区域102可以为用于设置摄像头的区域，驱动第二区域102中的第二发光元件发光的第二像素电路位于第一区域101，可以提高第二区域102的光透过率，即通过发光元件和像素电路分离设置的方式来提高第二区域102的光透过率。
图19为图4所示区域E8的部分结构的示意图，图20为图19所示区域E9的部分结构的示意图，图21至图25为图20所示位置中不同膜层的示意图。E9区域为E8区域中的小区域。
例如，如图2至图4以及图19至图25所示，第二信号线300包括发光控制信号线521。例如，发光控制信号线521采用单边驱动。
例如，如图2至图4以及图19至图25所示，发光控制信号线521通过转接线5611与第五导电层570中的第四连接线440-11电连接，第四连接线440-11通过连接部575与第六导电层580中的第三连接线430-1电连接，第三连接线430-1通过连接部575与第四连接线440-1电连接，从而将位于第二区域102左侧(以图中所示Y方向箭头相反的方向为向左)的第三子信号线310(发光 控制信号线521)与位于第二区域102右侧的第四子信号线320(发光控制信号线521)电连接。
例如，如图2至图4以及图19至图25所示，多条发光控制信号线521中延长线不经过第二区域102的部分发光控制信号线521中最靠近第二区域102的一条发光控制信号线521位于最靠近第二区域102的一条第四连接线440-1和与其相邻的第四连接线440-2之间。
例如，如图2至图4以及图19至图25所示，第二信号线300包括复位控制信号线522。例如，复位控制信号线522采用单边驱动。
例如，如图2至图4以及图19至图25所示，复位控制信号线522通过第四导电层560中的转接线与第五导电层570中的第四连接线440-12电连接，第四连接线440-12通过连接部575与第六导电层580中的第三连接线430-2电连接，第三连接线430-2通过连接部575与第四连接线440-2电连接，从而将位于第二区域102左侧的第三子信号线310(复位控制信号线522)与位于第二区域102右侧的第四子信号线320(复位控制信号线522)电连接。
本公开实施例提供的显示基板中，发光控制晶体管写入信号的过程受到寄生电容影响较小，复位晶体管T7以及复位晶体管T8的信号受寄生电容影响也较小，通过将复位晶体管T7和复位晶体管T8电连接的复位控制信号线，以及发光控制信号线至少之一设置为采用沿第一方向延伸的连接线和沿第二方向延伸的连接线实现位于第二区域两侧的两部分的电连接，有利于在尽量不影响像素电路工作性能的基础上降低第二区域周边布线空间以增加显示区的面积。
例如，扫描信号线523采用双边驱动，因此位于第二区域两侧的扫描信号线523可以断开设置。
例如，如图2至图4以及图19至图25所示，与阈值补偿晶体管T2电连接的扫描信号线531采用单边驱动。例如，位于第二区域102一侧的扫描信号线531通过第一导电层520中的连接线525和/或第四导电层560中连接线与位于第二区域102另一侧的扫描信号线531电连接。
本公开实施例提供的显示基板中，与阈值补偿晶体管T2电连接的扫描信号线没有采用沿第一方向延伸的连接线和沿第二方向延伸的连接线实现位于第二区域两侧的两部分的电连接，而是通过围绕第二区域边缘的绕线实现位于第二区域两侧的两部分的电连接，可以使得与阈值补偿晶体管T2电连接的扫描信号线上产生的寄生电容较低。
例如，如图2至图4以及图19至图25所示，与第二复位晶体管T1电连接的复位控制信号线532采用单边驱动。例如，位于第二区域102一侧的复位控制信号线532通过第四导电层560中连接线与位于第二区域102另一侧的复位控制信号线532电连接，或者位于第二区域102一侧的复位控制信号线532直接在第二区域102边缘绕线至第二区域102另一侧。
本公开实施例提供的显示基板中，与第二复位晶体管T1电连接的复位控制信号线没有采用沿第一方向延伸的连接线和沿第二方向延伸的连接线实现位于第二区域两侧的两部分的电连接，而是通过围绕第二区域边缘的绕线实现位于第二区域两侧的两部分的电连接，可以使得与第二复位晶体管T1电连接的复位控制信号线上产生的寄生电容较低。
本公开实施例提供的像素电路中，与发光控制信号线电连接的第一发光控制晶体管、第二发光控制晶体管，以及与复位控制信号线电连接的第一复位晶体管和第三复位晶体管均为P型晶体管，阈值补偿晶体管和第二复位晶体管均为N型晶体管。由于P型晶体管相对于N型晶体管，栅极信号的电压跳变影响较小，因此优选P型管的对应的栅控制线中的全部或者部分采用沿第一方向延伸的连接线和沿第二方向延伸的连接线(即FIP连线方式)方式实现位于第二区域两侧的两部分的电连接，从而缩小第二区域周边的非显示区面积，以实现窄边框；同时，与选用N型晶体管的阈值补偿晶体管和第二复位晶体管的栅极电连接的控制信号线采用上述绕线方式。
当然，本公开实施例不限于此，当像素电路中的所有晶体管均为低温多晶硅晶体管(LTPS)，如所有晶体管均为P型晶体管时，与所有P型晶体管的栅极电连接的栅极控制信号线的部分或者全部可以采用上述沿第一方向延伸的连接线和沿第二方向延伸的连接线(即FIP连线方式)方式实现位于第二区域两侧的两部分的电连接，进而缩小第二区域周边的非显示区面积，以实现窄边框。
可选地，根据本公开的实施例，显示基板还包括：位于所述衬底基板上的发光元件和像素电路，所述像素电路与所述发光元件电连接；其中，所述像素电路包括至少一个N型薄膜晶体管和至少一个P型薄膜晶体管；所述第二信号线包括与至少一个所述P型薄膜晶体管的栅极相连接的信号线。
可选地，根据本公开的实施例，显示基板还包括：位于所述衬底基板上的发光元件和像素电路，所述像素电路与所述发光元件电连接；其中，所述像素 电路包括至少一个氧化物薄膜晶体管和至少一个低温多晶硅薄膜晶体管；所述第二信号线包括与至少一个所述低温多晶硅薄膜晶体管的栅极相连接的信号线。
本公开另一实施例提供一种显示装置，该显示装置包括上述任一显示基板。
例如，显示装置可以为QHD(Quad High Definition)显示装置，QHD指全高清屏分辨率的4倍。例如，显示装置可以为FHD(Full High Definition)显示装置，FHD指全高清。
例如，本公开实施例提供的显示装置可以为有机发光二极管显示装置，如有源矩阵有机发光二极管(Active-matrix organic light-emitting diode，AMOLED)显示装置。
例如，显示装置还可以包括位于显示基板显示侧的盖板。例如，显示装置还可以包括位于衬底基板远离发光元件一侧的功能部件，功能部件与第二区域正对。例如，功能部件包括相机模组(例如，前置摄像模组)、3D结构光模组(例如，3D结构光传感器)、飞行时间法3D成像模组(例如，飞行时间法传感器)、红外感测模组(例如，红外感测传感器)等至少之一。
本公开实施例提供的显示装置通过采用第一连接线、第二连接线、第三连接线和第四连接线电连接位于第二区域两侧的信号线，且第一连接线位于第三连接线远离第二区域的一侧的同时，第二连接线与第三连接线交叠，在降低第二区域周边布线空间以增加显示区的面积的同时，可以减小第一信号线和第二信号线的负载突变。
例如，该显示装置可以包括手机、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件，本公开实施例对此不作限制。
有以下几点需要说明：
(1)本公开的实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (27)

  1. 一种显示基板，包括：
    衬底基板，包括第一区域和第二区域，所述第一区域位于所述第二区域的周边；
    多条第一信号线，位于所述衬底基板上，且不经过所述第二区域；
    多条第二信号线，与所述多条第一信号线位于不同层，且不经过所述第二区域，
    其中，至少部分第一信号线沿第一方向延伸，至少部分第二信号线沿第二方向延伸，所述第一方向与所述第二方向相交；
    所述多条第一信号线包括延长线经过所述第二区域的部分第一信号线，所述部分第一信号线中的每条第一信号线包括位于所述第二区域两侧的第一子信号线和第二子信号线，所述第一子信号线和所述第二子信号线通过沿所述第一方向延伸的第一连接线和沿所述第二方向延伸的第二连接线电连接，且所述部分第一信号线与多条第一连接线和多条第二连接线电连接；
    所述多条第二信号线包括延长线经过所述第二区域的部分第二信号线，所述部分第二信号线中的每条第二信号线包括位于所述第二区域两侧的第三子信号线和第四子信号线，所述第三子信号线和所述第四子信号线通过沿所述第一方向延伸的第三连接线和沿所述第二方向延伸的第四连接线电连接，且所述部分第二信号线与多条第三连接线和多条第四连接线电连接；
    在垂直于所述衬底基板的方向上，至少一条第二连接线与至少一条第三连接线交叠，且所述第二区域的同一侧中，至少一条第一连接线位于至少一条第三连接线远离所述第二区域的一侧。
  2. 根据权利要求1所述的显示基板，其中，所述多条第一信号线包括数据线，所述多条第二信号线至少包括发光控制信号线。
  3. 根据权利要求1或2所述的显示基板，其中，最靠近所述第二区域的一条第四连接线与所述第二区域的边缘之间的最小距离小于最靠近所述第二区域的一条第一连接线与所述第二区域的边缘之间的最小距离。
  4. 根据权利要求1-3任一项所述的显示基板，其中，所述第二区域的同一侧中，所述多条第二连接线中的第一组连接线位于至少一条第四连接线靠近所述第二区域的一侧，所述多条第二连接线中的第二组连接线位于所述至少一 条第四连接线远离所述第二区域的一侧。
  5. 根据权利要求4所述的显示基板，其中，沿垂直于所述衬底基板的方向，所述第一组连接线与所述第三连接线交叠，且所述第二组连接线与所述第三连接线没有交叠。
  6. 根据权利要求4或5所述的显示基板，其中，所述第一组连接线中最靠近所述第二组连接线的一条第二连接线与所述第二组连接线中最靠近所述第一组连接线的一条第二连接线之间的距离为第一距离，所述第二组连接线中相邻两条第二连接线之间的距离为第二距离，所述第一距离与所述第二距离之比大于2。
  7. 根据权利要求4所述的显示基板，其中，与所述第一组连接线中最靠近所述第二组连接线的一条第二连接线连接的所述第一连接线包括分别位于所述一条第二连接线在所述第一方向上的两侧的两部分。
  8. 根据权利要求7所述的显示基板，其中，与所述第一组连接线中最靠近所述第二组连接线的所述一条第二连接线连接的所述第一连接线延伸至所述第二组连接线中最靠近所述第一组连接线的一条第二连接线的位置处。
  9. 根据权利要求7或8所述的显示基板，其中，与所述第一组连接线中最靠近所述第二组连接线的N条第二连接线分别连接的N条第一连接线中的每条第一连接线均包括分别位于与其连接的第二连接线在所述第一方向上的两侧的两部分，且沿靠近所述第二区域的方向排列的所述N条第一连接线中，所述第一连接线的位于与其连接的所述第二连接线的靠近所述第二组连接线一侧的部分的长度逐渐减小，N为大于等于1的正整数，且位于所述第二区域中心一侧的所述第一组连接线中的所述第二连接线的数量大于等于N。
  10. 根据权利要求4-9任一项所述的显示基板，其中，所述多条第二信号线中延长线不经过所述第二区域的部分第二信号线中最靠近所述第二区域的一条第二信号线位于最靠近所述第二区域的一条第四连接线和与其相邻的第四连接线之间。
  11. 根据权利要求1-10任一项所述的显示基板，其中，所述第二区域的同一侧中，所述多条第一信号线中延长线不经过所述第二区域的至少一条第一信号线位于所述第一连接线靠近所述第二区域的一侧。
  12. 根据权利要求1-11任一项所述的显示基板，其中，所述多条第一连接线和所述多条第三连接线中彼此最靠近的一条第一连接线和一条第三连接线 之间的距离与相邻两条第三连接线之间的距离之比为0.8～1.2。
  13. 根据权利要求1-12任一项所述的显示基板，其中，在所述第一区域内，至少一条第一连接线与至少一条第三连接线位于同层，至少一条第二连接线与至少一条第四连接线位于同层。
  14. 根据权利要求13所述的显示基板，其中，至少一条第一连接线和至少一条第三连接线均与所述多条第一信号线位于同层。
  15. 根据权利要求13所述的显示基板，其中，所述多条第二信号线位于所述多条第一信号线与所述衬底基板之间，所述第四连接线位于所述多条第一信号线与所述多条第二信号线之间。
  16. 根据权利要求4-10任一项所述的显示基板，其中，所述第一区域为显示区，所述第一区域围绕所述第二区域，所述衬底基板还包括围绕所述显示区的周边区，所述多条第二组连接线包括位于所述第一区域的所述第二连接线以及位于所述周边区的所述第二连接线，位于所述第一区域的所述第二连接线与所述第一连接线不同层设置，位于所述周边区的所述第二连接线与所述第一连接线同层设置。
  17. 根据权利要求16所述的显示基板，其中，位于所述周边区的所述第二连接线与所述第一信号线同层设置。
  18. 根据权利要求4所述的显示基板，其中，所述第一组连接线中的至少一条第二连接线与至少一条第四连接线同层且间隔设置，且位于同一直线上。
  19. 根据权利要求4所述的显示基板，其中，在所述第二区域的同一侧中，与所述第二组连接线连接的至少一条第一信号线在垂直于所述衬底基板的方向上与各第四连接线均交叠。
  20. 根据权利要求1-19任一项所述的显示基板，其中，各第一连接线在沿所述第一方向延伸的直线上的正投影与各第三连接线在该直线上的正投影交叠；至少一条第二连接线在沿所述第二方向延伸的直线上的正投影与至少一条第四连接线在该直线上的正投影没有交叠。
  21. 根据权利要求2所述的显示基板，还包括：
    位于所述衬底基板上的发光元件和像素电路，所述像素电路与所述发光元件电连接；
    其中，所述像素电路包括驱动晶体管、发光控制晶体管以及复位晶体管，所述发光控制晶体管的栅极与所述发光控制信号线电连接，所述发光控制晶体 管的第一极与所述驱动晶体管的第一极电连接，所述发光控制晶体管的第二极与所述发光元件电连接；
    所述复位晶体管的栅极与复位控制信号线电连接，所述复位晶体管的一极与所述驱动晶体管的第二极电连接，或者所述复位晶体管的一极与所述发光控制晶体管的第二极电连接；
    所述第二信号线包括所述复位控制信号线。
  22. 根据权利要求1所述的显示基板，还包括：
    位于所述衬底基板上的发光元件和像素电路，所述像素电路与所述发光元件电连接；
    其中，所述像素电路包括至少一个N型薄膜晶体管和至少一个P型薄膜晶体管；
    所述第二信号线包括与至少一个所述P型薄膜晶体管的栅极相连接的信号线。
  23. 根据权利要求1所述的显示基板，还包括：
    位于所述衬底基板上的发光元件和像素电路，所述像素电路与所述发光元件电连接；
    其中，所述像素电路包括至少一个氧化物薄膜晶体管和至少一个低温多晶硅薄膜晶体管；
    所述第二信号线包括与至少一个所述低温多晶硅薄膜晶体管的栅极相连接的信号线。
  24. 根据权利要求1-23任一项所述的显示基板，其中，所述第一区域为显示区，所述第一区域围绕所述第二区域，所述衬底基板还包括围绕所述显示区的周边区；
    所述显示基板还包括：沿所述第一方向延伸的多条第五连接线和沿所述第二方向延伸的多条第六连接线，与所述第一连接线位于同层且位于同一直线的所述第五连接线与所述第一连接线间隔设置，与所述第三连接线位于同层且位于同一直线的所述第五连接线与所述第三连接线间隔设置，与所述第二连接线位于同层且位于同一直线的所述第六连接线与所述第二连接线间隔设置，与所述第四连接线位于同层且位于同一直线的所述第六连接线与所述第四连接线间隔设置，且所述第五连接线和所述第六连接线的至少之一与第三信号线电连接，所述第三信号线位于所述周边区。
  25. 根据权利要求24所述的显示基板，其中，所述第五连接线与所述第一连接线间隔位置处以及所述第五连接线与所述第三连接线间隔位置处的至少之一与所述第四连接线所在膜层交叠，所述第六连接线与所述第二连接线间隔位置处以及所述第六连接线与所述第四连接线间隔位置处的至少之一与所述第一连接线所在膜层交叠。
  26. 根据权利要求1-25任一项所述的显示基板，其中，至少一条第一连接线两侧设置有与该第一连接线紧邻的两条第一信号线，且所述两条第一信号线与该第一连接线之间的最小距离之比为0.9～1.1；至少一条第三连接线两侧设置有与该第三连接线紧邻的两条第一信号线，且所述两条第一信号线与该第三连接线之间的最小距离之比为0.9～1.1。
  27. 一种显示装置，包括权利要求1-26任一项所述的显示基板。
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