WO2024020767A1 - 阵列基板及其制备方法、液晶盒、显示装置 - Google Patents

阵列基板及其制备方法、液晶盒、显示装置 Download PDF

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Publication number
WO2024020767A1
WO2024020767A1 PCT/CN2022/107816 CN2022107816W WO2024020767A1 WO 2024020767 A1 WO2024020767 A1 WO 2024020767A1 CN 2022107816 W CN2022107816 W CN 2022107816W WO 2024020767 A1 WO2024020767 A1 WO 2024020767A1
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Prior art keywords
substrate
base substrate
orthographic projection
pixel electrode
sub
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PCT/CN2022/107816
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English (en)
French (fr)
Inventor
邸云萍
张晨阳
王利忠
张宜驰
郑皓亮
张震
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京东方科技集团股份有限公司
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Priority to CN202280002356.1A priority Critical patent/CN117795408A/zh
Priority to PCT/CN2022/107816 priority patent/WO2024020767A1/zh
Publication of WO2024020767A1 publication Critical patent/WO2024020767A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate and a preparation method thereof, a liquid crystal cell, and a display device.
  • the working principle of the liquid crystal spatial light modulator is based on optical phased array technology: the refractive index of the liquid crystal layer is controlled by an external electric field, so that the liquid crystal layer at different positions has different refractive index, so a certain phase will be formed between different positions of the liquid crystal layer.
  • the phase distribution at the entire position of the liquid crystal layer can be made to have a periodic morphology similar to a grating structure through appropriate electric field adjustment. That is equivalent to using liquid crystal to form a phase depth topography similar to a grating structure.
  • the liquid crystal layer can achieve different phase depth topography. The light beam Different angles of deflection can be achieved.
  • An embodiment of the present disclosure provides an array substrate.
  • the array substrate includes:
  • a first planarization layer located on the side of the thin film transistor facing away from the first base substrate;
  • the common electrode is located on the side of the first planarization layer facing away from the thin film transistor;
  • a first dielectric layer located on the side of the common electrode facing away from the first planarization layer
  • a plurality of first pixel electrodes are located on a side of the first dielectric layer away from the common electrode; the first pixel electrodes are electrically connected to the thin film transistors in a one-to-one correspondence through first via holes penetrating the first dielectric layer and the first planarization layer; A surface of a pixel electrode on a side facing away from the first base substrate has at least a first groove corresponding to the first via hole;
  • a plurality of flat portions located on the side of the first groove away from the first base substrate; the distance from the surface of the flat portions away from the first base substrate to the first base substrate is equal to the distance between the first pixel electrode and the first substrate The distance from one side surface of the substrate to the first base substrate is approximately the same.
  • the array substrate further includes:
  • the plurality of second pixel electrodes are located on the side of the first pixel electrode away from the first base substrate and are in contact with the first pixel electrode.
  • the orthographic projection of the second pixel electrode on the first base substrate covers the orthographic projection of the first pixel electrode on the first base substrate.
  • the second pixel electrode includes a first opening, and an orthographic projection of the first opening on the first base substrate covers an orthographic projection of the flat portion on the first base substrate.
  • an orthographic projection of the first opening on the first base substrate substantially overlaps an orthographic projection of the flat portion on the first base substrate.
  • the orthographic projection of the second pixel electrode on the first base substrate surrounds the orthographic projection of the flat portion on the first base substrate, and the orthographic projection of the second pixel electrode on the first base substrate is in contact with the flat portion.
  • the orthographic projections of the first substrate are spliced to form a closed pattern.
  • the common electrode includes a transparent material
  • the first pixel electrode includes a transparent material, and the second pixel electrode includes a reflective material; or both the first pixel electrode and the second pixel electrode include a reflective material.
  • the array substrate further includes:
  • the first protective layer is located on the side of the second pixel electrode facing away from the first base substrate;
  • a plurality of floating reflective patterns are located on the side of the first protective layer facing away from the second pixel electrode; the orthographic projection of the floating reflective patterns on the first base substrate covers the orthographic projection of the adjacent second pixel electrode on the first base substrate. the gap between.
  • the common electrode, the first pixel electrode, and the second pixel electrode all include transparent materials.
  • the common electrode includes a reflective material and the first pixel electrode includes a transparent material.
  • the first via hole includes: a first sub-via hole penetrating the first planarization layer and a second sub-via hole penetrating the first dielectric layer;
  • the first dielectric layer covers part of the first sub-via, the orthographic projection of the second sub-via on the first substrate is located within the orthographic projection of the first sub-via on the first substrate, and the second sub-via The hole is located within the first sub-via.
  • the first via hole includes: a first sub-via hole penetrating the first planarization layer and a second sub-via hole penetrating the first dielectric layer;
  • the orthographic projection of the first sub-via hole on the first substrate substrate is located within the orthographic projection of the second sub-via hole on the first substrate substrate.
  • the cross-sectional area of the first sub-via hole parallel to the plane direction of the first base substrate gradually decreases, and the second sub-via hole is parallel to the first base substrate.
  • the cross-sectional area in the plane direction of the first substrate substrate gradually decreases, and the maximum area of the cross-section of the first sub-via hole parallel to the plane direction of the first substrate substrate is equal to the second sub-via hole parallel to the first substrate.
  • the cross-sectional area of the first sub-via hole parallel to the plane direction of the first base substrate gradually decreases, and the second sub-via hole is parallel to the first base substrate.
  • the cross-sectional area in the plane direction of the first base substrate gradually decreases, and the maximum area of the cross-section of the second sub-via hole parallel to the plane direction of the first base substrate is larger than that of the first sub-via hole parallel to the first substrate.
  • the array substrate further includes:
  • a plurality of first connection electrodes are arranged in the same layer as the common electrode and cover the first sub-via; the first connection electrodes are in contact with the first pixel electrode and the thin film transistor.
  • a thin film transistor includes: an active layer, a gate electrode, a source electrode and a drain electrode; the drain electrode is electrically connected to the first pixel electrode; and the source electrode is located between the drain electrode and the first substrate substrate.
  • the array substrate includes multiple scan lines and multiple data lines that intersect horizontally and vertically; the multiple scan lines and the multiple data lines divide multiple sub-pixel units; the sub-pixel units include thin film transistors and are electrically connected to the thin film transistors. a first pixel electrode; a plurality of scan lines extending along the first direction and arranged along the second direction; a plurality of data lines extending along the second direction and arranged along the first direction; the first direction intersects with the second direction; a plurality of sub-pixels The unit is divided into: a plurality of sub-pixel unit rows extending along the first direction and arranged along the second direction, and a plurality of sub-pixel unit columns extending along the second direction and arranged along the first direction.
  • Each sub-pixel unit row includes a The thin film transistors included in the sub-pixel unit rows are scan lines electrically connected to each other, and each sub-pixel unit column includes a data line electrically connected to the thin film transistors included in the sub-pixel unit column;
  • the scan line is located between the drain electrode and the active layer, and the area with overlapping scan lines and the active layer in the orthographic projection of the first base substrate is the gate electrode;
  • the data line is located on the side of the scan line away from the active layer, and the area of the data line that is electrically connected to the active layer is the source.
  • the orthographic projection of the first pixel electrode on the first base substrate overlaps with the orthographic projection of the scan line located in an adjacent sub-pixel unit row with the first pixel electrode on the first base substrate.
  • the orthographic projection of the first pixel electrode on the first base substrate overlaps with the orthographic projection of the data line located in the same sub-pixel unit column as the first pixel electrode on the first base substrate.
  • the pattern of the orthographic projection of the active layer on the first base substrate includes: a first part, a second part and a third part connected in sequence;
  • the first part is electrically connected to the source
  • the third part is electrically connected to the drain
  • the orthographic projection of the scan line on the first substrate overlaps with the orthographic projection of the second part on the first substrate.
  • the first portion and the third portion each include a portion extending along the second direction, and the second portion extends along the first direction;
  • the second part is respectively connected to the first part and the third part at both ends in the first direction, and in the second direction, the first part and the third part are respectively located on both sides of the second part;
  • the extension direction of the second part is parallel to the extension direction of the scan line; the orthographic projection of the second part on the first substrate falls within the orthographic projection of the scan line on the first substrate.
  • the width of the second portion is less than the width of the scan line in the second direction.
  • the second portion extends in the second direction
  • the second part is respectively connected to the first part and the third part at both ends in the second direction, and in the first direction, the first part and the third part are respectively located on both sides of the second part;
  • the extension direction of the second part is perpendicular to the extension direction of the scan line; the orthographic projection of the second part on the first substrate overlaps the orthographic projection of the scan line on the first substrate, and the first part and the third part are on The orthographic projection of the first base substrate and the orthographic projection of the scan line on the first base substrate do not overlap with each other.
  • the pattern of the orthographic projection of the active layer on the first base substrate includes: a first part, a second part and a third part connected in sequence; the first part and the third part extend along the second direction, and the second part The portion extends along the first direction;
  • the second part is respectively connected to the first part and the third part at both ends in the first direction, and in the second direction, the first part and the third part are respectively located on the same side of the second part;
  • the first part is electrically connected to the source, and the third part is electrically connected to the drain;
  • the orthographic projection of the scan line on the first base substrate overlaps with the orthographic projection of the first part and the third part on the first base substrate, and the orthographic projection of the scan line on the first base substrate overlaps with the orthographic projection of the second part on the first base substrate.
  • the orthographic projections of a substrate do not overlap with each other;
  • the gate electrode includes a first gate electrode and a second gate electrode; an area with overlapping scan lines with the first portion on the orthographic projection of the first substrate substrate is the first gate electrode, and the area with the third portion on the first substrate substrate is the first gate electrode.
  • the area with overlapping scan lines in the orthographic projection is the second gate.
  • the orthographic projection pattern of the active layer on the first base substrate includes: a first part and a second part connected to each other; the first part extends along the first direction, and the second part extends along the second direction;
  • the first part is electrically connected to the drain electrode, and the second part is electrically connected to the source electrode;
  • the orthographic projection of the scan line on the first substrate overlaps at least the orthographic projection of one of the first part and the second part on the first substrate.
  • the shape of the orthographic projection of the scan line on the first base substrate is a strip extending along the first direction, and the orthographic projection of the scan line on the first base substrate is only related to the first part on the first base substrate.
  • the orthographic projection of has overlap.
  • the orthographic projection of the scan line on the first substrate has an overlap with the orthographic projections of the first part and the second part on the first substrate;
  • the gate electrode includes a first gate electrode and a second gate electrode; an area with overlapping scan lines and the second portion on the orthographic projection of the first substrate substrate is the first gate electrode, and the area with the first portion on the first substrate substrate is The area with overlapping scan lines in the orthographic projection is the second gate.
  • the orthographic projection pattern of the scan line on the first base substrate includes a strip-shaped first pattern extending along the first direction, and the first pattern is aligned with the first pattern on one side of the first pattern in the second direction.
  • the orthographic projection of the first pattern on the first base substrate overlaps with the orthographic projection of the second part on the first base substrate, and the orthographic projection of the second pattern on the first base substrate overlaps with the orthographic projection of the first part on the first substrate.
  • the orthographic projection of the base substrate has overlap.
  • the orthogonal projection shape of the first pixel electrode on the first base substrate is a rectangle
  • the minimum distance between the edge of the first via hole in the orthographic projection of the first base substrate close to the first pixel electrode and the edge of the first pixel electrode in the orthographic projection of the first base substrate is less than or equal to 1.5 microns.
  • the orthographic projection of the first via hole on the first substrate is close to one of the right angles of the rectangle.
  • the array substrate has a pixel density greater than 1,000.
  • An embodiment of the present disclosure provides a method for preparing an array substrate.
  • the method includes:
  • a plurality of thin film transistors, a first planarization layer, a pattern of a common electrode, and a first dielectric layer are sequentially formed on the first base substrate, and a first via hole is formed through the first planarization layer and the first dielectric layer;
  • a first pixel electrode is formed on a side of the first dielectric layer away from the common electrode layer; wherein the first pixel electrode is electrically connected to the thin film transistor in a one-to-one correspondence through a first via hole penetrating the first dielectric layer and the first planarization layer,
  • the surface of the first pixel electrode on the side facing away from the first base substrate has at least a first groove corresponding to the first via hole;
  • a flat portion is formed on a side of the first groove facing away from the first base substrate; the distance from the flat portion to the first base substrate is the same as the first pixel electrode being far away from the first base substrate. The distance from the side surface to the first base substrate is approximately the same.
  • the opposing substrate is arranged opposite to the array substrate;
  • the liquid crystal layer is located between the array substrate and the counter substrate.
  • a display device provided by an embodiment of the present disclosure includes a liquid crystal cell provided by an embodiment of the present disclosure.
  • Figure 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • Figure 3 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • Figure 5 is a top view of a second pixel electrode and a flat portion provided by an embodiment of the present disclosure
  • Figure 6 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • Figure 7 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • Figure 8 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • Figure 9 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • Figure 10 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • Figure 11 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • Figure 12 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • Figure 13 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • Figure 14 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • Figure 15 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • Figure 16 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • Figure 17 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • Figure 18 is a schematic structural diagram of an active layer provided by an embodiment of the present disclosure.
  • Figure 19 is a schematic structural diagram of a scan line provided by an embodiment of the present disclosure.
  • Figure 20 is a schematic structural diagram of a data line and a drain provided by an embodiment of the present disclosure.
  • Figure 21 is a schematic structural diagram of a first via hole provided by an embodiment of the present disclosure.
  • Figure 22 is a schematic structural diagram of a first pixel electrode provided by an embodiment of the present disclosure.
  • Figure 23 is a schematic structural diagram of a data line provided by an embodiment of the present disclosure.
  • Figure 24 is a schematic structural diagram of a drain provided by an embodiment of the present disclosure.
  • Figure 25 is a schematic structural diagram of a flat portion provided by an embodiment of the present disclosure.
  • Figure 26 is a schematic structural diagram of a second pixel electrode provided by an embodiment of the present disclosure.
  • Figure 27 is a schematic structural diagram of another second pixel electrode provided by an embodiment of the present disclosure.
  • Figure 28 is a schematic diagram of the positional relationship between a first pixel electrode and a first via hole according to an embodiment of the present disclosure
  • Figure 29 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • Figure 30 is a schematic structural diagram of another active layer provided by an embodiment of the present disclosure.
  • Figure 31 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • Figure 32 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • Figure 33 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present disclosure.
  • Figure 34 is a schematic flow chart of a method for preparing an array substrate according to an embodiment of the present disclosure
  • Figure 35 is a schematic structural diagram of a liquid crystal cell provided by an embodiment of the present disclosure.
  • Figure 36 is a schematic structural diagram of another liquid crystal cell provided by an embodiment of the present disclosure.
  • Figure 37 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • FIG. 38 is a schematic structural diagram of another display device provided by an embodiment of the present disclosure.
  • a liquid crystal cell includes an array substrate.
  • the array substrate includes a pixel electrode and a common electrode that need to be insulated from each other, and the common electrode is located between the pixel electrode and the first substrate, the pixel electrode needs to pass through at least two layers of insulating films.
  • the via hole of the layer is electrically connected to the thin film transistor. Due to the existence of the via hole, the surface of the first pixel electrode on the side facing away from the first substrate is uneven, and the uniformity of the cell thickness is poor.
  • the liquid crystal cell is used for light field control. low quality.
  • the array substrate includes:
  • a plurality of thin film transistors 2 are located on one side of the first base substrate 1;
  • the first planarization layer 3 is located on the side of the thin film transistor 2 facing away from the first base substrate 1;
  • the common electrode 4 is located on the side of the first planarization layer 3 facing away from the thin film transistor 2;
  • the first dielectric layer 5 is located on the side of the common electrode 4 away from the first planarization layer 3;
  • a plurality of first pixel electrodes 6 are located on the side of the first dielectric layer 5 away from the common electrode 4; the first pixel electrodes 6 communicate with the thin film transistor through the first via hole 7 penetrating the first dielectric layer 5 and the first planarization layer 4. 2 are electrically connected in one-to-one correspondence; the surface of the first pixel electrode 6 on the side facing away from the first base substrate 1 has at least a first groove 8 corresponding to the first via hole 7;
  • a plurality of flat portions 9 are located on the side of the first groove 8 away from the first base substrate 1; the distance h1 between the surface of the flat portion 9 away from the first base substrate 1 and the first base substrate 1 is equal to the distance h1 between the first groove 8 and the first base substrate 1.
  • the distance h2 from the surface of the pixel electrode 6 away from the first base substrate 1 to the first base substrate 1 is approximately the same.
  • the distance h1 from the surface of the flat part away from the first base substrate to the first base substrate is approximately the same as the distance h2 from the surface of the first pixel electrode away from the first base substrate to the first base substrate.
  • the distance h2 from one side surface to the first base substrate is the same, which can be regarded as the flat portion filling the first groove.
  • the error is, for example, 0.3 microns, that is,
  • the distance h2 from the side surface of the pixel electrode away from the first base substrate to the first base substrate is the same.
  • the distance from the surface of the flat portion away from the first base substrate to the first base substrate is the same as the distance from the first pixel electrode’s side surface far away from the first base substrate to the first base substrate.
  • the distance is approximately the same, that is, the flat portion is used to fill the first groove of the first pixel electrode in the first via hole area, which can improve the thickness uniformity of the array substrate.
  • the array substrate is used in a liquid crystal cell, it can further improve the thickness uniformity of the liquid crystal cell, improve the control quality of the liquid crystal cell during light field control, and avoid uneven image quality and insufficient modulation linearity.
  • the array substrate further includes:
  • the plurality of second pixel electrodes 10 are located on the side of the first pixel electrode 6 away from the first base substrate 1 and are in contact with the first pixel electrode 6 .
  • the second pixel electrode is provided on one side of the substantially flat surface formed by the first pixel electrode and the flat portion.
  • the second pixel electrode and the first pixel electrode can be regarded as stacked pixel electrodes.
  • the array substrate provided by the embodiments of the present disclosure can be applied to reflective liquid crystal display or transmissive liquid crystal display.
  • the second pixel electrode when the array substrate provided by the embodiment of the present disclosure is applied to a reflective liquid crystal display, the second pixel electrode includes a reflective material. That is, the second pixel electrode not only serves as an electric field formed between the pixel electrode and the common electrode to control the deflection of the liquid crystal, but also serves as a reflective electrode.
  • the common electrode and the first pixel electrode include transparent materials. That is, the common electrode and the first pixel electrode are transparent electrodes.
  • the common electrode includes a transparent material and the first pixel electrode includes a reflective material. That is, both the first pixel electrode and the second pixel electrode are reflective electrodes. In some embodiments, the first pixel electrode and the second pixel electrode may include the same material.
  • the transparent material is, for example, indium tin oxide (ITO), and the reflective material can be a single layer of aluminum (Al), a single layer of Al alloy, titanium (Ti)/Al/Ti stack, Ti/Al/nitride Titanium (TiN) laminate, etc.
  • ITO indium tin oxide
  • the reflective material can be a single layer of aluminum (Al), a single layer of Al alloy, titanium (Ti)/Al/Ti stack, Ti/Al/nitride Titanium (TiN) laminate, etc.
  • the common electrode, the first pixel electrode, and the second pixel electrode all include transparent materials.
  • the common electrode, the first pixel electrode and the second pixel electrode may be made of the same material, for example, ITO.
  • the second pixel electrode corresponds to the first pixel electrode one-to-one.
  • the orthographic projection of the second pixel electrode 10 on the first base substrate 1 covers the orthographic projection of the first pixel electrode 6 on the first base substrate 1 .
  • the array substrate includes a plurality of pixel units, each pixel unit includes a plurality of sub-pixel units, and each sub-pixel unit includes a thin film transistor and a first pixel electrode.
  • each pixel unit includes a plurality of sub-pixel units
  • each sub-pixel unit includes a thin film transistor and a first pixel electrode.
  • the electric field generated between the first pixel electrode and the common electrode controls the deflection of the liquid crystal to control the light transmission of the sub-pixel.
  • the first pixel electrode needs to be electrically connected to the thin film transistor through the first via hole, the depth of the first via hole is generally greater than 1 micron.
  • the first pixel electrode at the first via hole is not flat.
  • the first pixel electrode and the common The morphology in which the electric field generated between the electrodes controls the deflection of the liquid crystal molecules is different from the morphology in which the electric field generated between the flat first pixel electrode and the common electrode controls the deflection of the liquid crystal molecules in the remaining areas. Therefore, the first pixel at the first via hole The pixel electrode cannot control the deflection of the liquid crystal to achieve light transmission, and the first pixel electrode area corresponding to the first via hole cannot be utilized. That is, the area corresponding to the first via hole is a non-transmissive area. The existence of uneven areas of the first pixel electrode seriously affects the sub-pixel aperture ratio.
  • a second pixel electrode is further provided on the side of the first pixel electrode facing away from the first base substrate, and the orthographic projection of the second pixel electrode on the first base substrate covers the first pixel electrode on the first base substrate.
  • An orthographic projection of the first base substrate, that is, the second pixel electrode covers the first pixel electrode and the flat portion. Since the flat portion roughly fills the first groove, the surface of the second pixel electrode on the side facing away from the first substrate is substantially flat.
  • the second pixel electrode in the area corresponding to the first groove can be used to control the deflection of liquid crystal molecules to achieve light transmission, which can improve the sub-pixel aperture ratio.
  • the orthographic projection of the first pixel electrode 6 on the first base substrate 1 falls within the orthographic projection of the second pixel electrode 10 on the first base substrate 1 .
  • the second pixel electrode 10 covers the edge of the first pixel electrode 6 .
  • the first pixel electrode material may be deposited first to form the first pixel electrode layer, and the first pixel electrode layer may be patterned to form the pattern of the first pixel electrode, and then the pattern of the flat part may be formed, and then the second pixel electrode layer may be deposited.
  • the pixel electrode material forms a second pixel electrode layer and a patterning process is performed on the second pixel electrode layer to form a pattern of the second pixel electrode.
  • the orthographic projection of the second pixel electrode 10 on the first base substrate 1 substantially overlaps the orthographic projection of the first pixel electrode 6 on the first base substrate 1 .
  • the orthographic projection of the second pixel electrode on the first base substrate substantially overlaps with the orthographic projection of the first pixel electrode on the first base substrate means: the orthographic projection of the second pixel electrode on the first base substrate
  • the difference between the edge and the edge of the orthographic projection of the first pixel electrode on the first base substrate is within the error allowable range. That is, when the difference between the edge of the orthographic projection of the second pixel electrode on the first base substrate and the edge of the orthogonal projection of the first pixel electrode on the first base substrate is within the allowable error range, it can be regarded as the second pixel electrode.
  • the orthographic projection on the first base substrate overlaps with the orthographic projection of the first pixel electrode on the first base substrate.
  • the first pixel electrode material can be deposited first to form the first pixel electrode layer, and then the pattern of the flat portion can be formed, and then the second pixel electrode material can be deposited to form the second pixel electrode layer, and then the first pixel electrode layer and
  • the second pixel electrode layer is subjected to a patterning process to form the patterns of the second pixel electrode and the first pixel electrode. That is, no patterning process is required after forming the first pixel electrode layer, and one patterning process is performed after forming the second pixel electrode layer.
  • the process of forming a pattern of the second pixel electrode and the first pixel electrode that substantially overlaps on the first base substrate can save one patterning process and save costs.
  • the first pixel electrode 6 and the second pixel electrode 10 include the same material.
  • the first pixel electrode and the second pixel electrode include the same reflective material; when the array substrate is used in a transmissive liquid crystal display, the first pixel electrode and the second pixel electrode include the same transparent material. Material. Therefore, there is no need to perform a patterning process after forming the first pixel electrode layer, and after forming the second pixel electrode layer, the second pixel electrode and the first pixel electrode overlapped on the first base substrate are formed through a patterning process. The craftsmanship of the pattern is simple and easy to implement.
  • the second pixel electrode when the array substrate is used in a reflective liquid crystal display, the second pixel electrode may also be arranged in a manner different from that shown in FIGS. 1 to 3 .
  • the second pixel electrode includes a first opening 24 , and the first opening 24 covers the flat portion 9 in the orthographic projection of the first base substrate 1 on the first base substrate 1 . Orthographic projection.
  • the second pixel electrode exposes the flat portion. Therefore, it is possible to avoid straying of reflected light due to minute unevenness of the reflective electrode caused by minute depressions or tiny protrusions on the surface of the flat portion away from the first base substrate, thereby improving the reflective liquid crystal display effect.
  • the orthographic projection of the first opening 24 on the first base substrate 1 substantially overlaps the orthographic projection of the flat portion 9 on the first base substrate.
  • the orthographic projection of the first opening on the first base substrate and the orthographic projection of the flat portion on the first base substrate substantially overlap means that the orthogonal projection edge of the first opening on the first base substrate overlaps with the orthographic projection of the flat portion on the first base substrate.
  • the difference between the orthographic projection edges of the first base substrate and the first substrate is within the error range. That is, when the difference between the front projection edge of the first opening on the first base substrate and the front projection edge of the flat portion on the first base substrate is within the error range, it can be considered that the front projection of the first opening on the first base substrate It overlaps with the orthographic projection of the flat portion on the first base substrate.
  • the orthographic projection of the second pixel electrode 10 on the first base substrate 1 surrounds the orthographic projection of the flat portion 9 on the first base substrate 1
  • the second pixel electrode 10 is on the first base substrate 1 .
  • the orthographic projection of a base substrate 1 and the orthographic projection of the flat portion 9 on the first base substrate 1 are spliced to form a closed pattern. That is, there is no hollow area in the area corresponding to the orthographic projection of the second pixel electrode 10 on the first base substrate and the orthographic projection of the flat portion 9 on the first base substrate.
  • the orthographic projection of the second pixel electrode 10 on the first base substrate and the orthographic projection of the flat portion 9 on the first base substrate are spliced to form a closed rectangle.
  • the orthographic projection of the second pixel electrode 10 and the flat portion 9 on the first base substrate 1 covers the orthographic projection of the first pixel electrode 6 on the first base substrate 1 .
  • the orthographic projection of the first pixel electrode 6 on the first base substrate 1 falls within the orthographic projection of the second pixel electrode 10 and the flat portion 9 on the first base substrate 1 .
  • the orthographic projection of the second pixel electrode 10 and the flat portion 9 on the first base substrate 1 is approximately the same as the orthographic projection of the first pixel electrode 6 on the first base substrate 1 . overlapping.
  • the orthographic projection of the second pixel electrode and the flat portion on the first base substrate substantially overlaps with the orthographic projection of the first pixel electrode on the first base substrate means: the second pixel electrode and the flat portion are on the first base substrate.
  • the difference between the orthographic projection edge of the base substrate and the orthographic projection edge of the first pixel electrode on the first base substrate is within an error range.
  • the first pixel electrode material can be deposited first to form the first pixel electrode layer, and then the pattern of the flat portion can be formed, and then the second pixel electrode material can be deposited to form the second pixel electrode layer, and then the first pixel electrode layer and
  • the second pixel electrode layer is subjected to a patterning process to form the patterns of the second pixel electrode and the first pixel electrode. That is, no patterning process is required after forming the first pixel electrode layer, and one patterning process is performed after forming the second pixel electrode layer.
  • the process of forming a pattern of the second pixel electrode and the first pixel electrode that substantially overlaps on the first base substrate can save one patterning process and save costs.
  • the thickness of the first planarization layer 3 is greater than the thickness of the first dielectric layer 5 .
  • the first via hole 7 includes: a first sub-via hole 11 that penetrates the first planarization layer 3 and a second sub-via hole that penetrates the first dielectric layer 5 . Via 12.
  • the first dielectric layer 5 covers part of the first sub-via 11
  • the second sub-via 12 is in the orthographic projection of the first substrate 1
  • the first sub-via hole 11 is located within the orthographic projection of the first substrate substrate 1
  • the second sub-via hole 12 is located within the first sub-via hole 11 .
  • first a first planarization layer is formed and a patterning process is performed to form a first sub-via hole, then a pattern of a common electrode is formed, and then a first dielectric layer is formed and a patterning process is performed to form a second sub-via hole.
  • the first sub-via hole and the second sub-via hole are set holes, the area of the second sub-via hole is smaller than the area of the first sub-via hole, and the second sub-via hole is located in the first sub-via hole. inside the via hole.
  • the material of the first planarization layer is an organic material
  • the material of the first dielectric layer is an inorganic material.
  • the organic material may be, for example, a photosensitive resin.
  • the inorganic material can be silicon nitride (SiN), silicon oxide (SiO2), or SiN/SiO2 stack.
  • the shape of the cross-section of the first via hole 7 in the direction perpendicular to the first base substrate 1 is a polygon with more than four sides.
  • the orthographic projection of the first sub-via hole 11 on the first substrate substrate 1 is located at the orthographic projection of the second sub-via hole 12 on the first substrate substrate 1 Inside.
  • the first sub-via 11 is parallel to the plane direction of the first base substrate.
  • the cross-sectional area gradually decreases, the cross-sectional area of the second sub-via hole 12 parallel to the plane direction of the first substrate substrate gradually decreases, and the cross-sectional area of the first sub-via hole 11 parallel to the plane direction of the first substrate substrate.
  • the maximum area is equal to the minimum cross-sectional area of the second sub-via 12 parallel to the plane direction of the first substrate.
  • the first planarization layer is formed first, and then the pattern of the common electrode is formed, and then the first dielectric layer is formed, and the first dielectric layer and the first planarization layer are patterned to form the second sub-via. , the first sub-via. That is, the second sub-via hole and the first sub-via hole are formed through one patterning process, which can save the array substrate preparation process.
  • the material of the first planarization layer is an inorganic material
  • the material of the first dielectric layer is an inorganic material.
  • the inorganic material included in the first planarization layer may be, for example, SiO 2 ; the inorganic material included in the first dielectric layer may be SiN, SiO 2 , or SiN/SiO 2 stack.
  • the second sub-via hole and the first sub-via hole are formed through a patterning process, and the second pixel electrode and the first sub-via are formed through a patterning process.
  • the pattern of the pixel electrode can save two patterning processes.
  • the cross-section shape of the first via hole 7 in the direction perpendicular to the first substrate 1 is a trapezoid as an example.
  • the first groove 8 is vertically
  • the shape of the cross section in the direction of the first base substrate 1 is a trapezoid
  • the shape of the cross section of the flat portion 9 in the direction perpendicular to the first base substrate 1 is a trapezoid.
  • the angle between the first sub-via and the plane of the first substrate may be different from that of the second sub-via.
  • the included angle between the hole and the plane of the first substrate is different, that is, the cross-section shape of the first via hole in a direction perpendicular to the first substrate is a hexagon.
  • the first via hole including the second sub-via hole and the first sub-via hole formed through one patterning process is The shape of the first via hole of the sub-via hole is more regular, and accordingly, the shape of the first groove is also more regular, which can reduce the maximum area of the first groove in a direction parallel to the plane of the first substrate substrate.
  • the maximum size of the first via hole in a direction parallel to the plane of the first base substrate is, for example, 3 microns.
  • the first sub-via 11 is parallel to the plane direction of the first substrate 1 .
  • the cross-sectional area gradually decreases, the cross-sectional area of the second sub-via hole 12 parallel to the plane direction of the first substrate substrate gradually decreases, and the cross-sectional area of the first sub-via hole 11 parallel to the plane direction of the first substrate substrate.
  • the maximum area of the cross-section is greater than the minimum area of the cross-section of the second sub-via 12 parallel to the plane direction of the first base substrate;
  • the array substrate also includes:
  • a plurality of first connection electrodes 23 are arranged in the same layer as the common electrode 4 and cover the first sub-via 11; the first connection electrodes 23 are in contact with the first pixel electrode 6 and the thin film transistor 2.
  • the first pixel electrode is electrically connected to the thin film transistor through the first connection electrode provided in the same layer as the common electrode.
  • the second pixel electrode covers the flat part, and in FIG. 10 the second pixel electrode exposes the flat part.
  • the pattern of the first connection electrode is also formed in the first via hole, so that the process of electrically connecting the first pixel electrode and the thin film transistor is simple and easy to implement, and can also avoid Since the first via hole is deep and directly contacts the thin film transistor through the first pixel electrode, the yield of the array substrate can be improved, thereby improving the array substrate yield.
  • the area of the orthographic projection of the first sub-via hole 11 on the first base substrate 1 is smaller than the area of the orthogonal projection of the first connection electrode 23 on the first base substrate 1 .
  • area, and the orthographic projection of the first sub-via hole 11 on the first base substrate 1 falls within the orthographic projection of the first connection electrode 23 on the first base substrate 11 . That is, the first connection electrode not only covers the area of the first sub-via hole, but also covers part of the first planarization layer.
  • the width of the orthographic projection of the first sub-via on the first substrate is greater than or equal to 3 microns and less than or equal to 4 microns. That is, the size of the first sub-via is smaller.
  • the second pixel electrode exposes the flat portion, the area that cannot be used to control the deflection of the liquid crystal to achieve light transmission can be reduced, so that the aperture ratio can be increased.
  • the material of the first planarization layer is an organic material
  • the material of the first dielectric layer is an inorganic material.
  • the organic material may be, for example, a photosensitive resin.
  • the inorganic material can be silicon nitride (SiN), silicon oxide (SiO 2 ), or a SiN/SiO 2 stack.
  • the array substrate when used in a reflective liquid crystal display, as shown in Figures 11 to 14, the array substrate also includes:
  • the first protective layer 13 is located on the side of the second pixel electrode 10 facing away from the first base substrate 1;
  • a plurality of floating reflective patterns 22 are located on the side of the first protective layer 13 away from the second pixel electrode 10; the orthographic projection of the floating reflective patterns 22 on the first base substrate 1 covers the adjacent second pixel electrode 10 on the first substrate 1. The gap between the orthographic projections of the base substrate 1.
  • the array substrate provided by the embodiment of the present disclosure is provided with a floating reflective pattern covering the gap between adjacent second pixel electrodes, which can increase the coverage area of the reflective film layer, thereby increasing the reflectivity.
  • the orthographic projection of the floating reflective pattern 22 on the first base substrate 1 overlaps with the orthographic projection of the second pixel electrode 10 on the first base substrate 1 .
  • the orthographic projection of the floating reflection pattern on the first base substrate overlaps the orthographic projection of the second pixel electrode on the first base substrate.
  • the width is about 1 micron.
  • the distance between two adjacent second pixel electrodes is greater than 0 and less than or equal to 2.5 microns. That is, the distance between two adjacent second pixel electrodes is small, so that the reflectivity can be increased.
  • the array substrate includes a common electrode 4 and a first pixel electrode 6. No second pixel electrode is provided on the side of the first pixel electrode 6 away from the first base substrate 1.
  • the material of the common electrode includes a reflective material, and the material of the first pixel electrode includes a transparent material. That is, the common electrode also serves as a reflective electrode. This can reduce the thickness of the array substrate and reduce the array substrate preparation process.
  • the thin film transistor 2 includes: an active layer 17, a gate G, a source S, and a drain D; the drain D and The first pixel electrode 6 is electrically connected.
  • the drain electrode includes a transparent material.
  • the drain electrode since the drain electrode is electrically connected to the first pixel electrode, the drain electrode is usually close to the gap between adjacent first pixel electrodes. When the drain electrode is made of conventional metal materials, it is easy to cause gaps between adjacent first pixel electrodes. Reflection near the gap. In the array substrate provided by embodiments of the present disclosure, the drain electrode includes a transparent material, thereby preventing light reflection from the drain electrode near the gap between adjacent first pixel electrodes.
  • the source S and the drain D are arranged in the same layer.
  • the source S is located between the drain D and the first substrate 1 .
  • the source electrode and the drain electrode are disposed on different conductive layers.
  • the edge of the orthographic projection of the source electrode on the first base substrate and the edge of the orthogonal projection of the drain electrode on the first base substrate are reduced, The distance between them will not cause a short circuit between the source and the drain, which can simplify the design difficulty of the array substrate layout.
  • reducing the distance between the edge of the source electrode on the orthographic projection of the first base substrate and the edge of the drain electrode on the orthogonal projection of the first base substrate can also reduce the size of the sub-pixel unit, which is beneficial to achieving high pixel density. , which can improve the resolution and help achieve high-resolution display.
  • the array substrate provided by embodiments of the present disclosure has a pixel density greater than or equal to 1,000. That is, the array substrate provided by the embodiment of the present disclosure can be applied to high-resolution display products. It should be noted that when the pixel density is 1000, the resolution of the array substrate applied to the display product is, for example, 2000 ⁇ 2000. In order to achieve higher resolution, the pixel density of the array substrate can be further increased. For example, the pixel density can be greater than or equal to 2500, or even greater than or equal to 4000.
  • the active layer 17 is located between the drain D and the first substrate 1;
  • the array substrate also includes a multi-layer insulating layer located between the drain electrode D and the active layer 17 .
  • the thin film transistor 2 has a top gate structure, and the gate G is located between the active layer 17 and the source S;
  • Figure 1 As shown in Figure 4, Figure 6 to Figure 15, when the source S and the drain D are arranged on the same layer, the multi-layer insulating layer located between the drain D and the active layer 17 includes: the gate electrode of the active layer 17 G and the gate insulating layer 15, the first interlayer insulating layer 16 between the gate G and the source S and drain D; as shown in Figure 16, when the source S and the drain D are located on different layers , the multi-layer insulating layer located between the drain D and the active layer 17 includes: the first interlayer located between the gate G of the active layer 17 and the gate insulating layer 15 located between the gate G and the source S.
  • the active layer 17 includes: a first conductive region 19, a second conductive region 18, and a semiconductor region 20; a gate electrode
  • the orthographic projection of G on the first base substrate 1 falls within the orthographic projection of the semiconductor region 20 on the first base substrate 1; the drain D is electrically connected to the first conductive region 19 through a second via hole penetrating the multi-layer insulating layer.
  • the second via hole penetrates the first interlayer insulating layer 16 and the gate insulating layer 15; when the source S and the drain D are on different layers, the second via hole Penetrating the second interlayer insulating layer 25, the first interlayer insulating layer 16, and the gate insulating layer 15; the source S passes through the third via hole and the second conductive region penetrating the first interlayer insulating layer 16, the gate insulating layer 15 18 electrical connections.
  • the array substrate further includes a buffer layer 14 located between the active layer 17 and the first base substrate 1 .
  • the orthographic projection of the first via hole 7 on the first substrate substrate and the orthographic projection of the second via hole 26 on the first substrate substrate do not overlap with each other. This can avoid overlapping of different via holes, causing the flatness of the area of the via hole to be too different from the flatness of other areas, affecting the thickness uniformity of the liquid crystal cell.
  • the array substrate specifically includes a plurality of scanning lines 29 and a plurality of data lines 30 that intersect horizontally and vertically; the plurality of scanning lines 29 and the plurality of data lines 30 divide a plurality of sub-pixel units; and more
  • the scan lines 29 extend along the first direction X and are arranged along the second direction Y; the plurality of data lines extend along the second direction Y and are arranged along the first direction X; the first direction
  • the unit is divided into: a plurality of sub-pixel unit rows extending along the first direction X and arranged along the second direction Y, and a plurality of sub-pixel unit columns extending along the second direction Y and arranged along the first direction X.
  • Each sub-pixel unit row It includes a scan line 20 that is electrically connected to the thin film transistors included in the sub-pixel unit row, and each sub-pixel unit column includes a data line 30 that is electrically connected to the thin film transistors included in the sub-pixel unit column.
  • the scan line 29 is located between the drain electrode S and the active layer 17 in a direction perpendicular to the first substrate;
  • the orthographic projection of the area with overlapping scan lines 29 is the gate G;
  • the orthographic projection of the first pixel electrode 6 on the first base substrate overlaps with the orthographic projection of the scanning line 29 located in an adjacent sub-pixel unit row to the first pixel electrode 6 on the first base substrate.
  • the orthographic projection of the first pixel electrode on the first substrate overlaps with the orthographic projection of the adjacent row of scan lines on the first substrate, which can increase the density of the first pixel electrode. voltage holding capability without affecting the light emission of this row of sub-pixel units.
  • the scan line is located between the gate insulating layer and the first interlayer insulating layer.
  • the orthographic projection of the first pixel electrode 6 on the first base substrate and the data line 30 located in the same sub-pixel unit column as the first pixel electrode 6 are on the first base substrate.
  • the orthographic projection of has overlap.
  • the orthographic projection of the first pixel electrode on the first substrate has an intersection with the orthographic projection of the data line included in the sub-pixel unit column where the first pixel electrode is located on the first substrate.
  • Stacking can block the light noise caused by the data lines without affecting the potential on the data lines of other columns.
  • the orthographic projection of the first pixel electrode 6 on the first base substrate and the orthographic projection of the data line 30 on the first base substrate in the first direction The width smaller than the data line 30 is taken as an example for illustration.
  • the width of the area where the orthographic projection of the first pixel electrode on the first base substrate and the orthographic projection of the data line on the first base substrate overlap in the first direction is equal to the width of the data line, further increasing the The area of the first pixel electrode is increased to increase the aperture ratio.
  • the region of the data line 30 electrically connected to the active layer 17 is the source S.
  • the data line is between the first interlayer insulation layer and the first planarization layer.
  • FIG. 18 is a pattern of the active layer 17, the second via hole 26 and the third via hole 31 corresponding to the area shown in FIG. 17; in FIG. 17, the active layer 17 overlaps with the scan line 29.
  • the area of the active layer 17 is the semiconductor area of the active layer, and the area of the active layer 17 that does not overlap with the scanning line 29 is the conductive area of the active layer.
  • the areas corresponding to the second via hole 26 and the third via hole 31 may be the first conductive area and the second conductive area respectively.
  • the center line connecting the second via hole 26 and the third via hole 31 located in adjacent sub-pixel unit rows is not a horizontal line extending along the first direction X is used as an example. In specific implementation, it is also It may be arranged that the center connection line of the second via hole 26 and the third via hole 31 located in adjacent sub-pixel unit rows is on a horizontal line extending along the first direction X.
  • FIG. 19 is an orthographic projection pattern of the scanning line 29 corresponding to the area shown in FIG. 17 on the first base substrate.
  • FIG. 20 is an orthographic projection pattern of the data line 30 and the drain D corresponding to the area shown in FIG. 17 on the first base substrate; FIG. 17 and FIG. 20 show that the data line 30 and the drain D are on the same layer. Take an example for illustration.
  • the pattern of the film layer where the data line 30 is located and the pattern of the film layer where the drain D is located are as shown in Figures 23 and 24 respectively.
  • both the data line and the drain electrode may include metal electrode materials, or the data line may include metal electrode materials and the drain electrode may include transparent electrode materials.
  • FIG. 21 is the orthographic projection pattern of the first via hole 7 corresponding to the area shown in FIG. 17 on the first base substrate; FIG. 17 and FIG. 21 show that the area of the first sub-via hole 11 is smaller than that of the second sub-via hole 7.
  • the area of the sub-via hole 12 and the orthographic projection of the first sub-via hole 11 on the first base substrate fall within the orthographic projection of the second sub-via hole 12 on the first base substrate are taken as an example for illustration.
  • FIG. 22 is an orthographic projection pattern of the first pixel electrode 6 corresponding to the area shown in FIG. 17 on the first base substrate.
  • FIG. 17 does not show the pattern of the flat portion.
  • the pattern of the orthographic projection of the flat portion on the first base substrate may be as shown in FIG. 25 , for example.
  • the shape of the outline of the orthographic projection of the second pixel electrode on the first base substrate is different from the shape of the outline of the orthogonal projection of the first pixel electrode on the first base substrate.
  • the shapes are the same.
  • the patterns of the second pixel electrodes are as shown in Figures 26 and 27.
  • the orthographic projection of the second pixel electrode 10 on the first base substrate shown in FIG. 26 covers the orthographic projection of the first pixel electrode on the first base substrate; the second pixel electrode 10 shown in FIG. 27 includes the first opening 24 .
  • the orthogonal projection shape of the first pixel electrode 6 on the first base substrate is a rectangle.
  • the shape of the outline of the orthographic projection of the second pixel electrode on the first base substrate is a rectangle.
  • At least one edge of the first via hole in the orthographic projection of the first substrate substrate has an overlapping area with an edge of the first pixel electrode in the orthographic projection of the first substrate substrate. Therefore, the orthographic projection of the first via hole on the first base substrate is close to the edge of the orthographic projection of the first pixel electrode on the first base substrate, which can ensure the flatness of most areas of the first pixel electrode.
  • the edge of the orthographic projection of the first via hole on the first base substrate is in line with the first pixel electrode. It is not easy to realize that the edge of the orthographic projection of the first base substrate has an overlapping area. Therefore, in some embodiments, it can be designed such that as shown in FIGS. 17 and 28 , the orthographic projection of the first via hole 7 on the first base substrate is close to the edge of the first pixel electrode 6 and the first pixel electrode 6 is at the same position.
  • a substrate has a certain distance between edges of orthographic projections of the substrate.
  • the first The orthographic projection of the via hole on the first substrate is still close to the edge of the orthographic projection of the first pixel electrode on the first substrate, which can still ensure the flatness of most areas of the first pixel electrode.
  • FIG. 28 takes as an example that the orthographic projection of the first sub-via hole 11 on the first substrate falls within the orthographic projection of the second sub-via 12 on the first substrate.
  • the edge of the hole 7 in the orthographic projection of the first base substrate close to the first pixel electrode 6 is the edge of the first sub-via hole 11 in the orthographic projection of the first base substrate close to the first pixel electrode 6 .
  • h3 and h4 are the distance between the edge of the first sub-via 11 in the orthographic projection of the first base substrate close to the first pixel electrode 6 and the edge of the first pixel electrode in the orthographic projection of the first base substrate. distance.
  • the minimum distance between the edge of the first via hole in the orthographic projection of the first base substrate close to the first pixel electrode and the edge of the first pixel electrode in the orthographic projection of the first base substrate is less than or equal to 1.5 Micron. That is, the distance between the edge of the first via hole in the orthographic projection of the first base substrate and the edge of the first pixel electrode in the orthogonal projection of the first base substrate is relatively close, which can still ensure that most areas of the first pixel electrode Flatness. Especially for solutions where the second pixel electrode is not provided or the second pixel electrode has a first opening, ensuring the flatness of most areas of the first pixel electrode can ensure the aperture ratio.
  • the first via hole 7 in the orthographic projection of the first base substrate is close to one of the right angles of the rectangular shape of the first pixel electrode 6 in the orthographic projection of the first base substrate. That is, each edge of one of the right angles of the rectangle of the orthographic projection of the first via hole on the first base substrate is close to the first pixel electrode on the first base substrate and the first pixel electrode is on the first base substrate.
  • the distance between the edges of the orthographic projection is less than or equal to 1.5 microns.
  • the pattern of a pixel electrode 6 has a first symmetry axis 32 extending along the first direction X and a second symmetry axis 33 extending along the second direction Y.
  • the first symmetry axis 32 and the second symmetry axis 33 connect the first pixel electrode 6 Divided into four sub-regions, the four sub-regions are sub-region a, sub-region b, sub-region c, and sub-region d; the orthographic projection of the first via hole 7 on the first substrate only falls into one of the four sub-regions.
  • the orthographic projection of the sub-region on the first substrate It should be noted that FIG. 28 takes as an example that the orthographic projection of the first via hole 7 on the first substrate only falls into the orthographic projection of the sub-region d on the first substrate.
  • the distance between each edge of the first pixel electrode in the area d close to the orthographic projection of the first via hole on the first substrate substrate and the edge of the first pixel electrode on the orthographic projection of the first substrate substrate are less than or equal to 1.5 microns. That is, in Figure 28, h3 and h4 are both less than or equal to 1.5 microns.
  • the orthographic projection pattern of the active layer 17 on the first substrate includes: a first part 34 , a second part 35 and a third part 36 connected in sequence;
  • the first part 34 is electrically connected to the source S
  • the third part is electrically connected to the drain D
  • the scan line 29 is in the orthographic projection of the first substrate
  • the second part 35 is in the orthographic projection of the first substrate. Orthographic projection has overlap.
  • both the first part 34 and the third part 36 include parts extending along the second direction Y, and the second part 35 extends along the first direction X;
  • the second part 35 is connected to the first part 34 and the third part 36 respectively at both ends in the first direction X, and in the second direction Y, the first part 34 and the third part 36 are respectively located on both sides of the second part 35;
  • the extension direction of the second part 35 is parallel to the extension direction of the scan line 29; the orthographic projection of the second part 35 on the first substrate falls within the orthographic projection of the scan line 29 on the first substrate.
  • the orthographic projection pattern of the active layer on the first base substrate includes: a first part, a second part and a third part connected in sequence, and the first part and the third part are respectively located on the first substrate.
  • the pattern on both sides of the two parts, that is, the active layer is a polygonal pattern that is bent at least three times. Therefore, the active layer is evenly distributed in the sub-pixel unit, which prevents the active layer from being too concentrated and causing its area in the sub-pixel unit to be larger, which is conducive to achieving high pixel density.
  • the length of the active layer channel region can also be increased to reduce the leakage current of the thin film transistor.
  • the width of the second portion 35 is smaller than the width of the scan line 29 .
  • the width-to-length ratio of the active layer channel region can be adjusted by adjusting the width between the second part and the scanning line, so that the width-to-length ratio of the active layer channel region meets the required driving current requirements of the thin film transistor.
  • the pattern of the active layer's orthographic projection on the first base substrate includes: a first part, a second part and a third part connected in sequence
  • the pattern of the active layer may also be arranged in other ways.
  • the second portion 35 extends along the second direction Y;
  • the second part 35 is connected to the first part 34 and the third part 36 respectively at both ends in the second direction Y, and in the first direction X, the first part 34 and the third part 36 are respectively located on both sides of the second part 35;
  • the extension direction of the second part 35 is perpendicular to the extension direction of the scan line 29; the orthographic projection of the second part 35 on the first substrate overlaps the orthographic projection of the scan line 29 on the first substrate, and the first part 34
  • the orthographic projection of the third portion 36 on the first substrate does not overlap with the orthographic projection of the scan line 29 on the first substrate.
  • the orthographic projection pattern of the active layer on the first base substrate includes: a first part, a second part and a third part connected in sequence, and the first part and the third part are respectively located on the first substrate.
  • the pattern on both sides of the two parts, that is, the active layer is a polygonal pattern that is bent at least three times. Therefore, the active layer is evenly distributed in the sub-pixel unit, which prevents the active layer from being too concentrated and causing its area in the sub-pixel unit to be larger, which is conducive to achieving high pixel density.
  • the second part extends along the second direction, which can achieve uniform distribution of the active layer while reducing its size in the first direction, which can further increase the pixel density.
  • the second part is a regular strip pattern, so that the overlapping portions of the active layer and the scanning lines are in a regular quadrilateral pattern, compared to the case where the active layer and the scanning lines are in an irregular pattern. This can reduce the impact of active layer pattern manufacturing process deviation on the width and length of the thin film transistor channel region.
  • the patterns of active layers included in two adjacent sub-pixel unit rows in the array substrate shown in Figure 29 are not exactly the same.
  • the first part 34 is located at Below the second part 35
  • the second part 36 is located above the second part 35; but one row of second via holes 26 is located on the left side of the second part 35
  • the third via hole 31 is located on the right side of the second part 35
  • the other row of second via holes 26 is located on the left side of the second part 35.
  • the via hole 26 is located on the right side of the second part 35
  • the third via hole 31 is located on the left side of the second part 35 .
  • the region of the second portion 35 that overlaps the scan line 29 is a semiconductor region, and the region of the second portion 35 that does not overlap with the scan line 29 and the first portion 24.
  • the area of the third part 36 is a conductive area.
  • the pattern of the active layer's orthographic projection on the first base substrate includes: a first part, a second part and a third part connected in sequence
  • the pattern of the active layer may also be arranged in other ways.
  • the orthographic projection pattern of the active layer 17 on the first substrate includes: a first part 34 , a second part 35 and a third part 36 connected in sequence; the first part 34 and The third part 36 extends along the second direction Y, and the second part 35 extends along the first direction X;
  • the second part 35 is connected to the first part 34 and the third part 36 respectively at both ends in the first direction X, and in the second direction Y, the first part 34 and the third part 36 are respectively located on the same side of the second part 35;
  • the first part 34 is electrically connected to the source S, and the third part 36 is electrically connected to the drain D;
  • the gate includes a first gate G1 and a second gate G2;
  • the orthographic projection of the scan line 29 on the first base substrate overlaps with the orthographic projection of the first portion 34 and the third portion 36 on the first base substrate, and the orthographic projection of the scan line 29 on the first base substrate overlaps with the orthographic projection of the first base substrate.
  • the orthographic projections of the two parts 35 on the first substrate do not overlap with each other;
  • the area with the first portion 34 having an overlapping scan line 29 in the orthographic projection of the first substrate is the first gate G1, and the third portion 36 having an overlapping scan line 29 in the orthographic projection of the first substrate.
  • the area is the second gate G2.
  • the shape of the pattern of the active layer 17 on the first base substrate shown in FIG. 31 is U-shaped. It should be noted that, in order to clearly illustrate the orthographic relationship between the active layer and each film layer of the transistor, the orthographic projection of the first pixel electrode on the first base substrate is not shown in FIG. 31 .
  • the shape of the pattern of the active layer on the first base substrate is U-shaped, so that the scanning lines extending along the first direction can overlap with the two areas of the active layer.
  • the electrode includes a first gate G1 and a second gate G2, that is, the thin film transistor is a double-gate thin film transistor, which can reduce the leakage current of the thin film transistor.
  • the region having the first part 24 and the third part 36 that overlap with the scan line 29 is a semiconductor region, and the first part 24 and the third part 36 that do not overlap with the scan line 29 are The area and the second part 35 are conductive areas.
  • the patterns of the active layer can also be arranged in other ways.
  • the orthographic projection pattern of the active layer 17 on the first substrate includes: a first part 34 and a second part 35 connected to each other; the first part 34 is along the first Extending in the direction X, the second portion 35 extends in the second direction Y;
  • the first part 34 is electrically connected to the drain D, and the second part 35 is electrically connected to the source S;
  • the orthographic projection of the scan line 29 on the first substrate overlaps at least the orthographic projection of one of the first part 34 and the second part 35 on the first substrate.
  • the orthographic projection pattern of the active layer on the first base substrate is L-shaped.
  • the shape of the orthographic projection of the scan line 29 on the first substrate is a strip extending along the first direction X, and the orthographic projection of the scan line 29 on the first substrate is only There is an overlap with the second portion 35 in the orthographic projection of the first substrate.
  • the region of the second portion 35 that overlaps the scan line 29 is a semiconductor region, and the region of the second portion 35 that does not overlap with the scan line 29 and the first portion 34 are conductors. ization area.
  • the pattern of the first part is a stripe shape, and the scanning line overlaps with the second part of the stripe shape, which can increase the width-to-length ratio of the channel region of the active layer and increase the driving current of the thin film transistor.
  • the orthographic projection of the scan line 29 on the first substrate has overlap with the orthographic projections of the first part 34 and the second part 35 on the first substrate;
  • the area with the second portion 35 having overlapping scan lines 29 in the orthographic projection of the first base substrate is the first gate G1, and the area with the first portion 34 in the orthographic projection of the first base substrate having overlapping scan lines 29 The area is the second gate G2.
  • the scanning line overlaps with the two areas of the active layer, and the gate electrode includes a first gate electrode G1 and a second gate electrode G2. That is, the thin film transistor is a dual-gate thin film transistor, which can be reduced in size. Leakage current of thin film transistors.
  • the pattern of the orthographic projection of the scan line 29 on the first substrate includes a strip-shaped first pattern 37 extending along the first direction X, and in the second direction Y a second pattern 38 connected to the first pattern 37 on one side of the first pattern 37;
  • the orthographic projection of the first pattern 37 on the first base substrate overlaps with the orthographic projection of the second portion 35 on the first base substrate.
  • the orthographic projection of the second pattern 38 on the first base substrate overlaps with the orthographic projection of the first portion 34 on the first base substrate.
  • the region having the first portion 34 and the second portion 35 that overlap with the scan line 29 is a semiconductor region, and the first portion 34 and the second portion 35 that do not overlap with the scan line 29 are semiconductor regions.
  • the area is the conductive area.
  • the common electrode 4 is a planar electrode having a plurality of second openings 21 , and the common electrode 4 avoids the pixel electrode through the second openings 21 .
  • the common electrode layer can be deposited on the entire surface, and then a patterning process is performed on the entire common electrode layer to form a plurality of second openings.
  • a strip shape that overlaps with the orthographic projection of the first pixel electrode on the first base substrate can also be formed in the area outside the second opening.
  • the third opening, the strip-shaped third opening extends along the second direction, and the number of the third opening can be set according to actual needs.
  • embodiments of the present disclosure also provide a method for preparing an array substrate, as shown in Figure 34, including:
  • S101 Form a plurality of thin film transistors, a first planarization layer, a pattern of a common electrode, and a first dielectric layer in sequence on the first base substrate, and form a first via hole penetrating the first planarization layer and the first dielectric layer. ;
  • S102 Form a first pixel electrode on a side of the first dielectric layer away from the common electrode layer; wherein the first pixel electrode corresponds to the thin film transistor one-to-one through a first via hole penetrating the first dielectric layer and the first planarization layer.
  • the surface of the first pixel electrode on the side facing away from the first base substrate has at least a first groove corresponding to the first via hole;
  • a flat portion that fills the first groove of the first pixel electrode is also formed, which can improve the thickness uniformity of the array substrate.
  • the thickness uniformity of the liquid crystal cell can be improved, the control quality of the liquid crystal cell during light field control can be improved, and uneven image quality and insufficient modulation linearity can be avoided.
  • the method further includes:
  • a second pixel electrode is formed on a side of the flat portion facing away from the first base substrate.
  • forming the first pixel electrode on a side of the first dielectric layer facing away from the common electrode layer specifically includes:
  • Forming a second pixel electrode on the side of the flat portion facing away from the first base substrate specifically includes:
  • the second pixel electrode layer is patterned to form a plurality of second pixel electrode patterns.
  • the patterning process for the first pixel electrode layer and the patterning process for the second pixel electrode layer include, for example: glue coating, exposure, development, etching and other steps.
  • the etching may use a dry etching process, for example.
  • forming the first pixel electrode on a side of the first dielectric layer facing away from the common electrode layer specifically includes:
  • Forming a second pixel electrode on the side of the flat portion facing away from the first base substrate specifically includes:
  • the second pixel electrode layer and the first pixel electrode layer are patterned to form a plurality of second pixel electrode patterns and a plurality of first pixel electrode patterns.
  • the preparation method of the array substrate provided by the embodiment of the present disclosure, there is no need to perform patterning processing after forming the first pixel electrode layer, but after forming the second pixel electrode layer, it is formed on the first base substrate through a patterning process and roughly overlaps with the first base substrate.
  • the patterns of the second pixel electrode and the first pixel electrode can save one patterning process and save costs.
  • the patterning process for the second pixel electrode layer and the first pixel electrode layer includes, for example, steps such as glue coating, exposure, development, and etching.
  • the etching may use a dry etching process, for example.
  • the method further includes:
  • a pattern of floating reflective patterns is formed on a side of the first protective layer facing away from the second pixel electrode.
  • forming a flat portion on a side of the first groove away from the first base substrate specifically includes:
  • the pattern of the flat part is formed using an exposure and development process
  • An ashing process is performed on the surface of the flat part.
  • performing an ashing process on the surface of the flat portion can improve the planarization effect of the surface of the flat portion facing away from the base substrate.
  • the first via hole includes a first sub-via hole and a second sub-via hole, and a first planarization layer, a common electrode, and a first dielectric layer are sequentially formed on the first base substrate, and a through-threaded sub-via hole is formed.
  • a planarization layer and the first via hole of the first dielectric layer specifically including:
  • a patterning process is performed on the first dielectric layer to form a plurality of second sub-vias penetrating the first dielectric layer, thereby obtaining a pattern of the first dielectric layer.
  • the material of the first planarization layer is an organic material
  • the material of the first dielectric layer is an inorganic material.
  • the organic material may be, for example, a photosensitive resin.
  • the inorganic material can be silicon nitride (SiN), silicon oxide (SiO2), or SiN/SiO2 stack.
  • Perform a patterning process on the first planarization layer For example, you can perform a pre-baking, exposure, and development process on the first planarization layer including a photosensitive resin to form the first sub-via hole, and then pattern the first sub-via hole including the first sub-via hole.
  • the first planarization layer undergoes a thermal curing process.
  • the patterning process for the first dielectric layer includes, for example, glue coating, exposure, development, etching and other steps. For example, dry etching may be used for etching.
  • forming the pattern of the common electrode on the side of the first planarization layer away from the first base substrate also includes:
  • a pattern of the first connection electrode covering the first sub-via hole is formed.
  • the common electrode material can be deposited on the side of the first planarization layer away from the first base substrate to form a common electrode layer, and then the common electrode layer is patterned to form the pattern of the common electrode and the pattern of the first connection electrode. pattern.
  • the pattern of the first connection electrode is also formed in the first via hole, so that the subsequently formed first pixel electrode communicates with the thin film transistor through the first connection electrode.
  • Electrical connection so that the process of electrically connecting the first pixel electrode and the thin film transistor is simple and easy to implement. It can also avoid overlapping and disconnection due to the deep first via hole and direct contact with the thin film transistor through the first pixel electrode, which can improve the array. Substrate yield.
  • the first via hole includes a first sub-via hole and a second sub-via hole, and a first planarization layer, a common electrode, and a first dielectric layer are sequentially formed on the first base substrate, and a through-threaded sub-via hole is formed.
  • a planarization layer and the first via hole of the first dielectric layer specifically including:
  • a patterning process is performed on the first dielectric layer and the planarization layer to form a second sub-via hole penetrating the first dielectric layer and a first sub-via hole penetrating the first planarization layer, thereby obtaining a pattern of the first dielectric layer.
  • the array substrate preparation method provided by the embodiment of the present disclosure forms the second sub-via and the first sub-via through a single patterning process, which can save the array substrate preparation process.
  • the material of the first planarization layer is an inorganic material
  • the material of the first dielectric layer is an inorganic material.
  • the inorganic material included in the first planarization layer may be, for example, SiO 2 ; the inorganic material included in the first dielectric layer may be SiN, SiO 2 , or SiN/SiO 2 stack.
  • organosiloxane is spin-coated on the side of the thin film transistor facing away from the first base substrate, and a thermal curing process is used to form a SiO 2 layer as the first planarization layer.
  • the patterning process for the first dielectric layer and the SiO 2 layer includes, for example, glue coating, exposure, development, etching and other steps.
  • the etching may use a dry etching process, for example.
  • the thickness of the first dielectric layer is less than the thickness of the SiO 2 layer, and the thickness of the first dielectric layer is less than 100 nanometers.
  • the first planarization layer before forming the first planarization layer, it specifically includes:
  • a pattern of scan lines is formed on the side of the gate insulating layer facing away from the active layer; the area with overlapping scan lines and the orthographic projection of the active layer on the first substrate is the gate electrode of the thin film transistor;
  • the conductive area includes a first conductive area and a second conductive area
  • a first interlayer insulating layer is formed on the side of the scan line away from the gate insulating layer, a second via hole is formed through the first interlayer insulating layer and the gate insulating layer, and a third via hole is formed through the first interlayer insulating layer and the gate insulating layer.
  • the pattern of the data line and the pattern of the drain electrode are formed on the side of the first interlayer insulation layer away from the scan line; the drain electrode is in contact with the second via hole and the first conductive area of the active layer, and the data line is connected to the first conductive area through the third via hole.
  • the second conductive area of the active layer is in contact with the second conductive area of the active layer, and the area of the scan line that is in contact with the second conductive area of the active layer is the source of the thin film transistor.
  • the first planarization layer before forming the first planarization layer, it specifically includes:
  • a pattern of scan lines is formed on the side of the gate insulating layer facing away from the active layer; the area with overlapping scan lines and the orthographic projection of the active layer on the first substrate is the gate electrode of the thin film transistor;
  • the conductive area includes a first conductive area and a second conductive area
  • first interlayer insulating layer on the side of the scan line facing away from the gate insulating layer, and form a third via hole penetrating the first interlayer insulating layer and the gate insulating layer;
  • a pattern of data lines is formed on the side of the first interlayer insulating layer away from the scan line; the data line contacts the second conductive area of the active layer through the third via hole, and the data line contacts the second conductive area of the active layer.
  • the area of the line is the source of the thin film transistor;
  • a drain electrode pattern is formed on a side of the second interlayer insulating layer facing away from the data line; the drain electrode is in contact with the second via hole and the first conductive area of the active layer.
  • the source electrode and the drain electrode are arranged on different conductive layers.
  • the distance between the edges of the orthographic projection of the base substrate will not cause a short circuit between the source and the drain, which can simplify the design difficulty of the array substrate layout.
  • reducing the distance between the edge of the source electrode on the orthographic projection of the first base substrate and the edge of the drain electrode on the orthogonal projection of the first base substrate can also reduce the size of the sub-pixel unit, which is beneficial to achieving high pixel density. , which can improve the resolution and help achieve high-resolution display.
  • a liquid crystal cell provided by an embodiment of the present disclosure, as shown in Figures 35 and 36, includes:
  • the array substrate 39 provided by the embodiment of the present disclosure.
  • the opposing substrate 40 is arranged opposite to the array substrate 39;
  • the liquid crystal layer 41 is located between the array substrate 39 and the counter substrate 40 .
  • the liquid crystal cell provided by the embodiments of the present disclosure can be used as a display panel for a liquid crystal display.
  • the opposite substrate 40 includes a second base substrate 48 , a color filter 49 and a black matrix 50 located on the second base substrate 48 close to the liquid crystal layer 41 .
  • the black matrix 50 includes an opening area 51 corresponding to a one-to-one sub-pixel unit, and the color filter 49 is located in the opening area 51 .
  • the plurality of sub-pixel units include a plurality of red sub-pixel units, a plurality of blue sub-pixel units and a plurality of green sub-pixel units; correspondingly, the color filter includes a red color film corresponding to the red sub-pixel unit, A blue color film corresponding to the blue sub-pixel unit, and a green color film corresponding to the green sub-pixel unit.
  • the liquid crystal cell serves as a light control panel, that is, through appropriate electric field adjustment, the phase distribution at the entire position of the liquid crystal layer assumes a periodic topography similar to a grating structure.
  • the opposite substrate 40 includes a second base substrate 48, and the second base substrate 48 is located close to the black matrix 50 of the liquid crystal layer 41.
  • the black matrix 50 includes opening areas 51 corresponding to one-to-one sub-pixel units.
  • a display device provided by an embodiment of the present disclosure includes the above-mentioned liquid crystal cell 42 provided by an embodiment of the present disclosure.
  • the above-mentioned liquid crystal cell 42 provided by the embodiment of the present disclosure is a first liquid crystal cell 46
  • the display device further includes: a second liquid crystal cell 47 located on the light emitting side of the first liquid crystal cell 46 .
  • the display device provided by the embodiment of the present disclosure includes a two-layer liquid crystal cell, that is, the display device includes a double-layer liquid crystal panel.
  • the first liquid crystal cell serves as a light control panel.
  • Each sub-pixel unit of the light control panel can independently control light and dark, which can make the picture displayed by the display device more delicate and improve the display effect.
  • the first facing substrate of the first liquid crystal cell does not need to be provided with a color filter.
  • the second liquid crystal cell serves as a display panel.
  • the second liquid crystal cell also includes an array substrate, a liquid crystal layer and a counter substrate.
  • the second counter substrate of the second liquid crystal cell needs to be provided with a color filter.
  • the second liquid crystal cell is a transmissive liquid crystal cell.
  • the array substrate included in the second liquid crystal cell can also adopt the above-mentioned transmissive display array substrate provided by the embodiment of the present disclosure, that is, the common electrode and the first pixel electrode both include transparent materials, and the flat portion fills the groove of the first pixel electrode.
  • the array substrate included in the second liquid crystal cell may also include a second pixel electrode, and the second pixel electrode includes a transparent material.
  • the display device when the display device is a transmissive liquid crystal display, the display device further includes a backlight module located on a side of the first liquid crystal cell away from the second liquid crystal cell.
  • the display device can be applied to 3D display; as shown in Figure 38, the display device further includes:
  • the cylindrical lens structure 43 is located on the light exit side of the liquid crystal cell 42;
  • the light-transmitting spacer layer 44 is located between the liquid crystal cell 42 and the cylindrical lens structure 43;
  • the flat layer 45 is located on the side of the cylindrical lens structure 45 away from the light-transmitting spacer layer 44 .
  • the display device when the display device is a transmissive liquid crystal display, the display device further includes a backlight module located on the light entrance side of the liquid crystal cell.
  • the display device provided by the embodiment of the present disclosure is: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.
  • Other essential components of the display device are understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used to limit the present disclosure.
  • the array substrate and its preparation method, liquid crystal cell, and display device use the flat portion to fill the first groove of the first pixel electrode in the first via hole area, which can improve the performance of the array substrate. thickness uniformity.
  • the thickness uniformity of the liquid crystal cell can be improved, the control quality of the liquid crystal cell during light field control can be improved, and uneven image quality and insufficient modulation linearity can be avoided.

Abstract

阵列基板（39）及其制备方法、液晶盒（42）、显示装置。阵列基板（39）包括：第一衬底基板（1）；多个薄膜晶体管（2）；第一平坦化层（3）；公共电极（4），位于第一平坦化层（3）背离薄膜晶体管（2）的一侧；第一介质层（5），位于公共电极（4）背离第一平坦化层（3）的一侧；多个第一像素电极（6），位于第一介质层（5）背离公共电极（4）的一侧；第一像素电极（6）通过贯穿第一介质层（5）以及第一平坦化层（3）的第一过孔（7）与薄膜晶体管（2）一一对应电连接；第一像素电极（6）背离第一衬底基板（1）一侧的表面具有至少与第一过孔（7）对应的第一凹槽（8）；多个平坦部（9），位于第一凹槽（8）背离第一衬底基板（1）的一侧；平坦部（9）远离第一衬底基板（1）一侧的表面到第一衬底基板（1）的距离与第一像素电极（6）远离第一衬底基板（1）一侧表面到第一衬底基板（1）的距离大致相同。

Description

阵列基板及其制备方法、液晶盒、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、液晶盒、显示装置。
背景技术
液晶空间光调制器的工作原理是基于光学相控阵技术：通过外加电场控制液晶层的折射率，使不同位置的液晶层具有不同的折射率，因而液晶层不同位置之间会形成一定的相位差，可以通过适当的电场调节使得液晶层整体位置上的相位分布呈周期性的类似于光栅结构的形貌。即相当于使用液晶形成类似光栅结构的相位深度形貌，当光束入射至液晶层光栅相位面上时，光束会发生偏转，通过不同电场的调制，液晶层可以实现不同的相位深度形貌，光束便可以实现不同角度的偏转。
对于小尺寸液晶空间光调制器，液晶封装时往往不添加间隔物，仅通过周边封框胶和盒内的液晶分子实现盒厚支撑作用，但盒厚均一性较差，导致液晶空间光调制器光场调控时调控质量变差，容易出现画质不均、调制线性度不足等不良。
发明内容
本公开实施例提供的一种阵列基板，阵列基板包括：
第一衬底基板；
多个薄膜晶体管，位于第一衬底基板的一侧；
第一平坦化层，位于薄膜晶体管背离第一衬底基板的一侧；
公共电极，位于第一平坦化层背离薄膜晶体管的一侧；
第一介质层，位于公共电极背离第一平坦化层的一侧；
多个第一像素电极，位于第一介质层背离公共电极的一侧；第一像素电 极通过贯穿第一介质层以及第一平坦化层的第一过孔与薄膜晶体管一一对应电连接；第一像素电极背离第一衬底基板一侧的表面具有至少与第一过孔对应的第一凹槽；
多个平坦部，位于第一凹槽背离第一衬底基板的一侧；平坦部远离第一衬底基板一侧的表面到第一衬底基板的距离与第一像素电极远离第一衬底基板一侧表面到第一衬底基板的距离大致相同。
在一些实施例中，阵列基板还包括：
多个第二像素电极，位于第一像素电极背离第一衬底基板一侧，与第一像素电极接触。
在一些实施例中，第二像素电极在第一衬底基板的正投影覆盖第一像素电极在第一衬底基板的正投影。
在一些实施例中，第二像素电极包括第一开口，第一开口在第一衬底基板的正投影覆盖平坦部在第一衬底基板的正投影。
在一些实施例中，第一开口在第一衬底基板的正投影与平坦部在第一衬底基板的正投影大致交叠。
在一些实施例中，第二像素电极在第一衬底基板的正投影包围平坦部在第一衬底基板的正投影，且第二像素电极在第一衬底基板的正投影与平坦部在第一衬底基板的正投影拼接组成封闭图形。
在一些实施例中，公共电极包括透明材料；
第一像素电极包括透明材料，第二像素电极包括反射材料；或者，第一像素电极和第二像素电极均包括反射材料。
在一些实施例中，阵列基板还包括：
第一保护层，位于第二像素电极背离第一衬底基板的一侧；
多个浮置反射图案，位于第一保护层背离第二像素电极的一侧；浮置反射图案在第一衬底基板的正投影覆盖相邻第二像素电极在第一衬底基板的正投影之间的间隙。
在一些实施例中，公共电极、第一像素电极以及第二像素电极均包括透 明材料。
在一些实施例中，公共电极包括反射材料，第一像素电极包括透明材料。
在一些实施例中，第一过孔包括：贯穿第一平坦化层的第一子过孔以及贯穿第一介质层的第二子过孔；
第一介质层覆盖第一子过孔的部分区域，第二子过孔在第一衬底基板的正投影位于第一子过孔在第一衬底基板的正投影内，且第二子过孔位于第一子过孔内。
在一些实施例中，第一过孔包括：贯穿第一平坦化层的第一子过孔以及贯穿第一介质层的第二子过孔；
第一子过孔在第一衬底基板的正投影位于第二子过孔在第一衬底基板的正投影内。
在一些实施例中，在第一像素电极指向第一衬底基板的方向上，第一子过孔平行于第一衬底基板所在平面方向上的截面面积逐渐减小，第二子过孔平行于第一衬底基板所在平面方向上的截面面积逐渐减小，且第一子过孔平行于第一衬底基板所在平面方向上的截面的最大面积等于第二子过孔平行于第一衬底基板所在平面方向上的截面最小面积。
在一些实施例中，在第一像素电极指向第一衬底基板的方向上，第一子过孔平行于第一衬底基板所在平面方向上的截面面积逐渐减小，第二子过孔平行于第一衬底基板所在平面方向上的截面面积逐渐减小，且第二子过孔平行于第一衬底基板所在平面方向上的截面的最大面积大于第一子过孔平行于第一衬底基板所在平面方向上的截面最小面积。
在一些实施例中，阵列基板还包括：
多个第一连接电极，与公共电极同层设置且覆盖第一子过孔；第一连接电极与第一像素电极以及薄膜晶体管接触。
在一些实施例中，薄膜晶体管包括：有源层，栅极，源极和漏极；漏极与第一像素电极电连接；源极位于漏极与第一衬底基板之间。
在一些实施例中，阵列基板包括横纵交叉的多条扫描线和多条数据线； 多条扫描线和多条数据线划分多个子像素单元；子像素单元包括薄膜晶体管和与薄膜晶体管电连接的第一像素电极；多条扫描线沿第一方向延伸、沿第二方向排列，多条数据线沿第二方向延伸、沿第一方向排列；第一方向与第二方向交叉；多个子像素单元划分为：沿第一方向延伸、沿第二方向排列的多个子像素单元行，沿第二方向延伸、沿第一方向排列的多个子像素单元列，每一子像素单元行包括一个与该子像素单元行包括的薄膜晶体管电连接的扫描线，每一子像素单元列包括一个与该子像素单元列包括的薄膜晶体管电连接的数据线；
在垂直于第一衬底基板的方向上，扫描线位于漏极和有源层之间，与有源层在第一衬底基板的正投影具有交叠的扫描线的区域为栅极；
数据线位于扫描线背离有源层的一侧，与有源层电连接的数据线的区域为源极。
在一些实施例中，第一像素电极在第一衬底基板的正投影与和该第一像素电极位于相邻子像素单元行的扫描线在第一衬底基板的正投影具有交叠。
在一些实施例中，第一像素电极在第一衬底基板的正投影与和该第一像素电极位于相同子像素单元列的数据线在第一衬底基板的正投影具有交叠。
在一些实施例中，有源层在第一衬底基板的正投影的图案包括：依次连接的第一部分、第二部分和第三部分；
第一部分与源极电连接，第三部分与漏极电连接，扫描线在第一衬底基板的正投影与第二部分在第一衬底基板的正投影具有交叠。
在一些实施例中，第一部分和第三部分均包括沿第二方向延伸的部分，第二部分沿第一方向延伸；
第二部分在第一方向的两端分别与第一部分和第三部分连接，且在第二方向上，第一部分和第三部分分别位于第二部分的两侧；
第二部分的延伸方向与扫描线的延伸方向平行；第二部分在第一衬底基板的正投影落入扫描线在第一衬底基板的正投影内。
在一些实施例中，在第二方向上，第二部分的宽度小于扫描线的宽度。
在一些实施例中，第二部分沿第二方向延伸；
第二部分在第二方向的两端分别与第一部分和第三部分连接，且在第一方向上，第一部分和第三部分分别位于第二部分的两侧；
第二部分的延伸方向与扫描线的延伸方向垂直；第二部分在第一衬底基板的正投影与扫描线在第一衬底基板的正投影具有交叠，且第一部分和第三部分在第一衬底基板的正投影与扫描线在第一衬底基板的正投影互不交叠。
在一些实施例中，有源层在第一衬底基板的正投影的图案包括：依次连接的第一部分、第二部分和第三部分；第一部分和第三部分沿第二方向延伸，第二部分沿第一方向延伸；
第二部分在第一方向的两端分别与第一部分和第三部分连接，且在第二方向上，第一部分和第三部分分别位于第二部分的同一侧；
第一部分与源极电连接，第三部分与漏极电连接；
扫描线在第一衬底基板的正投影与第一部分和第三部分在第一衬底基板的正投影均具有交叠，且扫描线在第一衬底基板的正投影与第二部分在第一衬底基板的正投影互不交叠；
栅极包括第一栅极和第二栅极；与第一部分在第一衬底基板的正投影具有交叠的扫描线的区域为第一栅极，与第三部分在第一衬底基板的正投影具有交叠的扫描线的区域为第二栅极。
在一些实施例中，有源层在第一衬底基板的正投影的图案包括：相互连接的第一部分和第二部分；第一部分沿第一方向延伸，第二部分沿第二方向延伸；
第一部分与漏极电连接，第二部分与源极电连接；
扫描线在第一衬底基板的正投影至少与第一部分、第二部分之一在第一衬底基板的正投影具有交叠。
在一些实施例中，扫描线在第一衬底基板的正投影的形状为沿第一方向延伸的条形，扫描线在第一衬底基板的正投影仅与第一部分在第一衬底基板的正投影具有交叠。
在一些实施例中，扫描线在第一衬底基板的正投影与第一部分和第二部分在第一衬底基板的正投影均具有交叠；
栅极包括第一栅极和第二栅极；与第二部分在第一衬底基板的正投影具有交叠的扫描线的区域为第一栅极，与第一部分在第一衬底基板的正投影具有交叠的扫描线的区域为第二栅极。
在一些实施例中，扫描线在第一衬底基板的正投影的图案包括沿第一方向延伸的、条形的第一图案，以及在第二方向上在第一图案一侧与第一图案连接的第二图案；
第一图案在第一衬底基板的正投影与第二部分在第一衬底基板的正投影具有交叠，第二图案在第一衬底基板的正投影与第部一分在第一衬底基板的正投影具有交叠。
在一些实施例中，第一像素电极在第一衬底基板的正投影的形状为矩形；
第一过孔在第一衬底基板的正投影靠近第一像素电极的边缘与第一像素电极在第一衬底基板的正投影的边缘之间的最小距离小于等于1.5微米。
在一些实施例中，第一过孔在第一衬底基板的正投影靠近矩形的其中一个直角。
在一些实施例中，阵列基板的像素密度大于1000。
本公开实施例提供的一种阵列基板的制备方法，方法包括：
在第一衬底基板上依次形成多个薄膜晶体管、第一平坦化层、公共电极的图案、第一介质层，并形成贯穿第一平坦化层和第一介质层的第一过孔；
在第一介质层背离公共电极层的一侧形成第一像素电极；其中，第一像素电极通过贯穿第一介质层以及第一平坦化层的第一过孔与薄膜晶体管一一对应电连接，第一像素电极背离第一衬底基板一侧的表面具有至少与第一过孔对应的第一凹槽；
在第一凹槽背离第一衬底基板的一侧形成平坦部；平坦部远离第一衬底基板一侧的表面到第一衬底基板的距离与第一像素电极远离第一衬底基板一侧表面到第一衬底基板的距离大致相同。
本公开实施例提供的一种液晶盒，包括：
本公开实施例提供的阵列基板；
对向基板，与阵列基板相对设置；
液晶层，位于阵列基板和对向基板之间。
本公开实施例提供的一种显示装置，包括本公开实施例提供的液晶盒。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种阵列基板的结构示意图；
图2为本公开实施例提供的另一种阵列基板的结构示意图；
图3为本公开实施例提供的又一种阵列基板的结构示意图；
图4为本公开实施例提供的又一种阵列基板的结构示意图；
图5为本公开实施例提供的一种第二像素电极和平坦部的俯视图；
图6为本公开实施例提供的又一种阵列基板的结构示意图；
图7为本公开实施例提供的又一种阵列基板的结构示意图；
图8为本公开实施例提供的又一种阵列基板的结构示意图；
图9为本公开实施例提供的又一种阵列基板的结构示意图；
图10为本公开实施例提供的又一种阵列基板的结构示意图；
图11为本公开实施例提供的又一种阵列基板的结构示意图；
图12为本公开实施例提供的又一种阵列基板的结构示意图；
图13为本公开实施例提供的又一种阵列基板的结构示意图；
图14为本公开实施例提供的又一种阵列基板的结构示意图；
图15为本公开实施例提供的又一种阵列基板的结构示意图；
图16为本公开实施例提供的又一种阵列基板的结构示意图；
图17为本公开实施例提供的又一种阵列基板的结构示意图；
图18为本公开实施例提供的一种有源层的结构示意图；
图19为本公开实施例提供的一种扫描线的结构示意图；
图20为本公开实施例提供的一种数据线和漏极的结构示意图；
图21为本公开实施例提供的一种第一过孔的结构示意图；
图22为本公开实施例提供的一种第一像素电极的结构示意图；
图23为本公开实施例提供的一种数据线的结构示意图；
图24为本公开实施例提供的一种漏极的结构示意图；
图25为本公开实施例提供的一种平坦部的结构示意图；
图26为本公开实施例提供的一种第二像素电极的结构示意图；
图27为本公开实施例提供的另一种第二像素电极的结构示意图；
图28为本公开实施例提供的一种第一像素电极与第一过孔位置关系的示意图；
图29为本公开实施例提供的一种阵列基板的结构示意图；
图30为本公开实施例提供的另一种有源层的结构示意图；
图31为本公开实施例提供的又一种阵列基板的结构示意图；
图32为本公开实施例提供的又一种阵列基板的结构示意图；
图33为本公开实施例提供的又一种阵列基板的结构示意图；
图34为本公开实施例提供的一种阵列基板的制备方法的流程示意图；
图35为本公开实施例提供的一种液晶盒的结构示意图；
图36为本公开实施例提供的另一种液晶盒的结构示意图；
图37为本公开实施例提供的一种显示装置的结构示意图；
图38为本公开实施例提供的另一种显示装置的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然， 所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
相关技术中，液晶盒包括阵列基板，当阵列基板包括需要相互绝缘的像素电极和公共电极，且公共电极位于像素电极和第一衬底基板之间时，像素电极至少需要通过贯穿两层绝缘膜层的过孔与薄膜晶体管电连接，由于过孔的存在，导致第一像素电极背离第一衬底基板一侧的表面不平坦，盒厚均一性较差，利用液晶盒进行光场调控时调控质量差。
基于相关技术存在的上述问题，本公开实施例提供了一种阵列基板，如图1～图9，所示，阵列基板包括：
第一衬底基板1；
多个薄膜晶体管2，位于第一衬底基板1的一侧；
第一平坦化层3，位于薄膜晶体管2背离第一衬底基板1的一侧；
公共电极4，位于第一平坦化层3背离薄膜晶体管2的一侧；
第一介质层5，位于公共电极4背离第一平坦化层3的一侧；
多个第一像素电极6，位于第一介质层5背离公共电极4的一侧；第一像 素电极6通过贯穿第一介质层5以及第一平坦化层4的第一过孔7与薄膜晶体管2一一对应电连接；第一像素电极6背离第一衬底基板1一侧的表面具有至少与第一过孔7对应的第一凹槽8；
多个平坦部9，位于第一凹槽8背离第一衬底基板1的一侧；平坦部9远离第一衬底基板1一侧的表面到第一衬底基板1的距离h1与第一像素电极6远离第一衬底基板1一侧表面到第一衬底基板1的距离h2大致相同。
需要说明的是，平坦部远离第一衬底基板一侧的表面到第一衬底基板的距离h1与第一像素电极远离第一衬底基板一侧表面到第一衬底基板的距离h2大致相同是指：|h1-h2|在误差允许范围内。即当|h1-h2|在误差允许范围内时，都可以看作平坦部远离第一衬底基板一侧的表面到第一衬底基板的距离h1与第一像素电极远离第一衬底基板一侧表面到第一衬底基板的距离h2相同，可以看作平坦部填平第一凹槽。在具体实施时，误差例如为0.3微米，即|h1-h2|小于等于0.3微米，都可以看作平坦部远离第一衬底基板一侧的表面到第一衬底基板的距离h1与第一像素电极远离第一衬底基板一侧表面到第一衬底基板的距离h2相同。
本公开实施例提供的阵列基板，平坦部远离第一衬底基板一侧的表面到第一衬底基板的距离与第一像素电极远离第一衬底基板一侧表面到第一衬底基板的距离大致相同，即利用平坦部填平第一像素电极在第一过孔区域具有的第一凹槽，可以提高阵列基板的厚度均一性。当阵列基板应用于液晶盒时，进而可以提高液晶盒厚均一性，提高液晶盒进行光场调控时的调控质量，避免出现画质不均、调制线性度不足。
在一些实施例中，如图1所示，阵列基板还包括：
多个第二像素电极10，位于第一像素电极6背离第一衬底基板1一侧，与第一像素电极6接触。
即本公开实施例提供的阵列基板中，在第一像素电极与平坦部形成的大致平坦表面的一侧设置第二像素电极。第二像素电极与第一像素电极可以看作叠层像素电极。
在具体实施时，本公开实施例提供的阵列基板可以应用于反射式液晶显示，也可以应用于透射式液晶显示。
在具体实施时，当本公开实施例提供的阵列基板应用于反射式液晶显示时，第二像素电极包括反射材料。即第二像素电极除了作为像素电极与公共电极之间形成的电场控制液晶发生偏转之外，还作为反射电极。
在一些实施例中，公共电极以及第一像素电极包括透明材料。即公共电极以及第一像素电极为透明电极。
或者，在一些实施例中，公共电极包括透明材料，第一像素电极包括反射材料。即第一像素电极与第二像素电极均为反射电极。在一些实施例中，第一像素电极与第二像素电极包括的材料可以相同。
在一些实施例中，透明材料例如为氧化铟锡(ITO)，反射材料可为单层铝(Al)、单层Al合金、钛(Ti)/Al/Ti叠层、Ti/Al/氮化钛(TiN)叠层等。
在具体实施时，当本公开实施例提供的阵列基板应用于透射式液晶显示时，公共电极、第一像素电极以及第二像素电极均包括透明材料。公共电极、第一像素电极以及第二像素电极包括的材料可以相同，例如均为ITO。
在一些实施例中，第二像素电极与第一像素电极一一对应。
在一些实施例中，如图1、图2所示，第二像素电极10在第一衬底基板1的正投影覆盖第一像素电极6在第一衬底基板1的正投影。
需要说明的是，阵列基板包括多个像素单元，每个像素单元包括多个子像素单元，每个子像素单元包括一个薄膜晶体管和一个第一像素电极。相关技术中，当阵列基板应用于液晶盒时，第一像素电极与公共电极之间产生的电场控制液晶偏转以控制子像素透光。但由于第一像素电极需要通过第一过孔与薄膜晶体管电连接，第一过孔的深度一般大于1微米，第一过孔处的第一像素电极不平坦，该区域第一像素电极和公共电极之间产生的电场控制液晶分子偏转的形貌，与其余区域平坦的第一像素电极和公共电极之间产生的电场控制液晶分子偏转的形貌不同，因此，第一过孔处的第一像素电极无法控制液晶偏转实现透光，第一过孔对应的第一像素电极区域无法被利用。即 第一过孔对应的区域为非透光区。第一像素电极不平坦的区域的存在，严重影响子像素开口率。
本公开实施例提供的阵列基板，在第一像素电极背离第一衬底基板一侧还设置有第二像素电极，且第二像素电极在第一衬底基板的正投影覆盖第一像素电极在第一衬底基板的正投影，即第二像素电极覆盖第一像素电极和平坦部。由于平坦部大致填平第一凹槽，因此第二像素电极背离第一衬底基板一侧的表面大致为平面，当阵列基板应用于液晶显示产品时，无论是反射式液晶显示还是透射式液晶显示，第一凹槽对应的区域第二像素电极可以被利用控制液晶分子偏转以实现透光，可以提高子像素开口率。
在一些实施例中，如图1所示，第一像素电极6在第一衬底基板1的正投影落入第二像素电极10在第一衬底基板1的正投影内。
在具体实施时，如图1所示，第二像素电极10覆盖第一像素电极6的边缘。
在具体实施时，可以先沉积第一像素电极材料形成第一像素电极层并对第一像素电极层进行图形化工艺形成第一像素电极的图案，再形成平坦部的图案，之后再沉积第二像素电极材料形成第二像素电极层并对第二像素电极层进行图形化工艺形成第二像素电极的图案。
或者，在一些实施例中，如图2所示，第二像素电极10在第一衬底基板1的正投影与第一像素电极6在第一衬底基板1的正投影大致重叠。
需要说明的是，第二像素电极在第一衬底基板的正投影与第一像素电极在第一衬底基板的正投影大致重叠是指：第二像素电极在第一衬底基板的正投影的边缘与第一像素电极在第一衬底基板的正投影的边缘之差在误差允许范围内。即当第二像素电极在第一衬底基板的正投影的边缘与第一像素电极在第一衬底基板的正投影的边缘之差在误差允许范围内时，都可以看作第二像素电极在第一衬底基板的正投影与第一像素电极在第一衬底基板的正投影重叠。
在具体实施时，例如可以先沉积第一像素电极材料形成第一像素电极层， 再形成平坦部的图案，之后沉积第二像素电极材料形成第二像素电极层，再对第一像素电极层和第二像素电极层进行图形化工艺形成第二像素电极和第一像素电极的图案，即在形成第一像素电极层之后无需进行图形化处理，而在形成第二像素电极层之后通过一次图形化工艺形成在第一衬底基板上大致重叠的第二像素电极和第一像素电极的图案，可以节省一次图形化工艺，节省成本。
在一些实施例中，如图3所示，第一像素电极6与第二像素电极10包括的材料相同。当阵列基板应用与反射式液晶显示时，第一像素电极以及第二像素电极包括相同的反射材料；当阵列基板应用与透射式液晶显示时，第一像素电极以及第二像素电极包括相同的透明材料。从而，在形成第一像素电极层之后无需进行图形化处理，而在形成第二像素电极层之后通过一次图形化工艺形成在第一衬底基板上重叠的第二像素电极和第一像素电极的图案的工艺简单、易于实现。
在具体实施时，当阵列基板应用与反射式液晶显示时，第二像素电极也可以采用与图1～图3不同的设置方式。
在一些实施例中，如图4、图5所示，第二像素电极包括第一开口24，第一开口24在第一衬底基板1的正投影覆盖平坦部9在第一衬底基板的正投影。
即本公开实施例提供的阵列基板，第二像素电极露出平坦部。从而可以避免由于平坦部背离第一衬底基板一侧的表面具有微小凹陷或者微小凸起带来的反射电极微小不平坦导致反射光的杂散，可以提高反射式液晶显示效果。
在一些实施例中，如图4所示，第一开口24在第一衬底基板1的正投影与平坦部9在第一衬底基板的正投影大致交叠。
需要说明的是，第一开口在第一衬底基板的正投影与平坦部在第一衬底基板的正投影大致交叠是指，第一开口在第一衬底基板的正投影边缘与平坦部在第一衬底基板的正投影边缘之差在误差范围内。即当第一开口在第一衬底基板的正投影边缘与平坦部在第一衬底基板的正投影边缘之差在误差范围 内，均可以认为第一开口在第一衬底基板的正投影与平坦部在第一衬底基板的正投影交叠。
在一些实施例中，如图4所示，第二像素电极10在第一衬底基板1的正投影包围平坦部9在第一衬底基板1的正投影，且第二像素电极10在第一衬底基板1的正投影与平坦部9在第一衬底基板1的正投影拼接组成封闭图形。即第二像素电极10在第一衬底基板的正投影与平坦部9在第一衬底基板的正投影对应的区域不存在镂空区。如图5所示，第二像素电极10在第一衬底基板的正投影与平坦部9在第一衬底基板的正投影拼接组成封闭矩形。
在一些实施例中，如图4所示，第二像素电极10和平坦部9在第一衬底基板1的正投影覆盖第一像素电极6在第一衬底基板1的正投影。
在一些实施例中，如图4所示，第一像素电极6在第一衬底基板1的正投影落入第二像素电极10和平坦部9在第一衬底基板1的正投影内。
或者，如图6所示，在一些实施例中，第二像素电极10和平坦部9在第一衬底基板1的正投影与第一像素电极6在第一衬底基板1的正投影大致重叠。
需要说明的是，第二像素电极和平坦部在第一衬底基板的正投影与第一像素电极在第一衬底基板的正投影大致重叠是指：第二像素电极和平坦部在第一衬底基板的正投影边缘与第一像素电极在第一衬底基板的正投影的边缘之差在误差范围内。即当第二像素电极和平坦部在第一衬底基板的正投影边缘与第一像素电极在第一衬底基板的正投影的边缘之差在误差范围内，均可以认为第二像素电极和平坦部在第一衬底基板的正投影与第一像素电极在第一衬底基板的正投影重叠。
在具体实施时，例如可以先沉积第一像素电极材料形成第一像素电极层，再形成平坦部的图案，之后沉积第二像素电极材料形成第二像素电极层，再对第一像素电极层和第二像素电极层进行图形化工艺形成第二像素电极和第一像素电极的图案，即在形成第一像素电极层之后无需进行图形化处理，而在形成第二像素电极层之后通过一次图形化工艺形成在第一衬底基板上大致 重叠的第二像素电极和第一像素电极的图案，可以节省一次图形化工艺，节省成本。
在一些实施例中，如图1～图4、图6～图10所示，在垂直于第一衬底基板1的方向上，第一平坦化层3的厚度大于第一介质层5的厚度。
在一些实施例中，如图1～图4、图6所示，第一过孔7包括：贯穿第一平坦化层3的第一子过孔11以及贯穿第一介质层5的第二子过孔12。
在一些实施例中，如图1～图4、图6所示，第一介质层5覆盖第一子过孔11的部分区域，第二子过孔12在第一衬底基板1的正投影位于第一子过孔11在第一衬底基板1的正投影内，第二子过孔12位于第一子过孔11内。
在具体实施时，例如先形成第一平坦化层并进行图形化工艺形成第一子过孔，之后形成公共电极的图案，再之后形成第一介质层并进行图形化工艺形成第二子过孔。即本公开实施例提供的阵列基板，第一子过孔与第二子过孔为套孔，第二子过孔的面积小于第一子过孔的面积且第二子过孔位于第一子过孔内。在一些实施例中，第一平坦化层的材料为有机材料，第一介质层的材料为无机材料。有机材料例如可以是光敏树脂。无机材料可以为氮化硅(SiN)、氧化硅(SiO2)、或SiN/SiO2叠层。
在一些实施例中，如图1～图4、图6所示，第一过孔7在垂直于第一衬底基板1方向的截面的形状为边数大于四的多边形。
或者，在一些实施例中，如图7～图10所示，第一子过孔11在第一衬底基板1的正投影位于第二子过孔12在第一衬底基板1的正投影内。
在一些实施例中，如图7、图8所示，在第一像素电极6指向第一衬底基板1的方向上，第一子过孔11平行于第一衬底基板所在平面方向上的截面面积逐渐减小，第二子过孔12平行于第一衬底基板所在平面方向上的截面面积逐渐减小，且第一子过孔11平行于第一衬底基板所在平面方向上的截面的最大面积等于第二子过孔12平行于第一衬底基板所在平面方向上的截面最小面积。
在具体实施时，例如先形成第一平坦化层，之后形成公共电极的图案， 再之后形成第一介质层并对第一介质层和第一平坦化层进行图形化工艺形成第二子过孔、第一子过孔。即通过一次图形化工艺形成第二子过孔、第一子过孔，可以节省阵列基板制备工艺流程。在一些实施例中，第一平坦化层的材料为无机材料，第一介质层的材料为无机材料。第一平坦化层包括的无机材料例如可以为SiO 2；第一介质层包括的无机材料可以为SiN、SiO 2、或SiN/SiO 2叠层。
在具体实施时，对于如图7、图8所示的阵列基板，通过一次图形化工艺形成第二子过孔、第一子过孔，且通过一次图形化工艺形成第二像素电极和第一像素电极的图案，可以节省两次图形化工艺流程。
需要说明的是，图7、图8中，以第一过孔7在垂直于第一衬底基板1方向的截面的形状为梯形为例进行举例说明，相应的，第一凹槽8在垂直于第一衬底基板1方向的截面的形状为梯形，平坦部9在垂直于第一衬底基板1方向的截面的形状为梯形。当然，在具体实施时，当第一平坦化层的材料与第一介质层的材料不同时，第一子过孔与第一衬底基板所在平面之间的夹角角度可能与第二子过孔与第一衬底基板所在平面之间的夹角角度不同，即第一过孔在垂直于第一衬底基板方向的截面的形状为六边形。
需要说明的是，图7中第二像素电极覆盖平坦部，图8中第二像素电极露出平坦部。
需要说明的是，相比于通过两次图形化工艺形成的包括第二子过孔、第一子过孔的第一过孔，通过一次图形化工艺形成的包括第二子过孔、第一子过孔的第一过孔形状的形状更规则，相应的，第一凹槽的形状也更规则，可以减小第一凹槽在平行于第一衬底基板所在平面方向上的最大面积，对于第二像素电极露出平坦部的方案，可以减小无法用于控制液晶偏转以实现透光的区域，从而可以增大开口率。在具体实施时，第一过孔在平行于第一衬底基板所在平面方向上的最大例如为3微米。
在一些实施例中，如图9、图10所示，在第一像素电极6指向第一衬底基板1的方向上，第一子过孔11平行于第一衬底基板所在平面方向上的截面 面积逐渐减小，第二子过孔12平行于第一衬底基板所在平面方向上的截面面积逐渐减小，且第一子过孔11的平行于第一衬底基板所在平面方向上的截面的最大面积大于第二子过孔12的平行于第一衬底基板所在平面方向上的截面的最小面积；
阵列基板还包括：
多个第一连接电极23，与公共电极4同层设置且覆盖第一子过孔11；第一连接电极23与第一像素电极6以及薄膜晶体管2接触。
即第一像素电极通过与公共电极同层设置的第一连接电极与薄膜晶体管电连接。
需要说明的是，图9中第二像素电极覆盖平坦部，图10中第二像素电极露出平坦部。
本公开实施例提供的阵列基板，在形成公共电极的图案的同时还在第一过孔形成第一连接电极的图案，从而第一像素电极与薄膜晶体管电连接的工艺简单易于实现，还可以避免由于第一过孔较深、直接通过第一像素电极与薄膜晶体管接触导致的搭接断线，可以提高阵列基板良率。
在一些实施例中，如图9、图10所示，第一子过孔11在第一衬底基板1的正投影的面积小于第一连接电极23在第一衬底基板1的正投影的面积，且第一子过孔11在第一衬底基板1的正投影落入第一连接电极23在第一衬底基板11的正投影内。即第一连接电极除了覆盖第一子过孔的区域，还覆盖部分第一平坦化层。
在一些实施例中，第一子过孔在第一衬底基板的正投影的宽度大于等于3微米且小于等于4微米。即第一子过孔的尺寸较小。对于第二像素电极露出平坦部的情况，可以减小无法用于控制液晶偏转以实现透光的区域，从而可以增大开口率。
在具体实施时，第一平坦化层的材料为有机材料，第一介质层的材料为无机材料。有机材料例如可以是光敏树脂。无机材料可以为氮化硅(SiN)、氧化硅(SiO 2)、或SiN/SiO 2叠层。
在一些实施例中，当阵列基板应用与反射式液晶显示时，如图11～图14所示，阵列基板还包括：
第一保护层13，位于第二像素电极10背离第一衬底基板1的一侧；
多个浮置反射图案22，位于第一保护层13背离第二像素电极10的一侧；浮置反射图案22在第一衬底基板1的正投影覆盖相邻第二像素电极10在第一衬底基板1的正投影之间的间隙。
本公开实施例提供的阵列基板，设置覆盖相邻第二像素电极之间的间隙的浮置反射图案，可以增加反射膜层的覆盖面积，从而可以增加反射率。
在一些实施例中，如图11～图14所示，浮置反射图案22在第一衬底基板1的正投影与第二像素电极10在第一衬底基板1的正投影具有交叠。
在具体实施时，在相邻两个第二像素电极的排列方向上，浮置反射图案在第一衬底基板的正投影与第二像素电极在第一衬底基板的正投影交叠区域的宽度约为1微米。
在一些实施例中，当阵列基板包括第二像素电极时，相邻两个第二像素电极之间的距离大于0且小于或等于2.5微米。即相邻两个第二像素电极之间的距离较小，从而可以增加反射率。
需要说明的是，在具体实施时，不设置第二像素电极，也可以实现反射式液晶显示，在一些实施例中，如图15所示，阵列基板包括公共电极4以及第一像素电极6，第一像素电极6背离第一衬底基板1一侧未设置第二像素电极，公共电极的材料包括反射材料，第一像素电极的材料包括透明材料。即公共电极还作为反射电极。从而可以减小阵列基板的厚度、减少阵列基板制备工艺流程。
在一些实施例中，如图1～图4、图6～图15、图16所示，薄膜晶体管2包括：有源层17，栅极G，源极S和漏极D；漏极D与第一像素电极6电连接。
在一些实施例中，漏极包括透明材料。
需要说明的是，由于漏极与第一像素电极电连接，通常情况漏极靠近相 邻第一像素电极之间的间隙，漏极采用常规的金属材料时，容易造成相邻第一像素电极之间间隙附近反光。本公开实施例提供的阵列基板，漏极包括透明材料，从而可以避免相邻第一像素电极之间间隙附近漏极反光。
在一些实施例中，如图1～图4、图6～图15所示，源极S与漏极D同层设置。
或者，在一些实施例中，如图16所示，源极S位于漏极D与第一衬底基板1之间。
即本公开实施例中，源极与漏极设置于不同导电层，这样，即便减小源极在第一衬底基板的正投影的边缘与漏极在第一衬底基板的正投影的边缘之间的距离，也不会造成源极与漏极之间短路，可以简化阵列基板版图的设计难度。并且减小源极在第一衬底基板的正投影的边缘与漏极在第一衬底基板的正投影的边缘之间的距离还可以减小子像素单元的尺寸，有利于实现高像素密度，从而可以提高分辨率，有利于实现高分辨率显示。
在一些实施例中，本公开实施例提供的阵列基板的像素密度大于或等于1000。即本公开实施例提供的阵列基板可以应用于高分辨率显示产品。需要说明的是，当像素密度为1000时，阵列基板应用于显示产品的分辨率例如为2000×2000。为了实现更高分辨率，还可以进一步提高阵列基板像素密度，例如像素密度可以大于或等于2500、甚至大于或等于4000。
在一些实施例中，如图1～图4、图6～图15、图16所示，有源层17位于漏极D和第一衬底基板1之间；
阵列基板还包括：位于漏极D和有源层17之间的多层绝缘层。
在一些实施例中，如图1～图4、图6～图15、图16所示，薄膜晶体管2为顶栅结构，栅极G位于有源层17和源极S之间；如图1～图4、图6～图15所示，当源极S与漏极D同层设置时，位于漏极D和有源层17之间的多层绝缘层包括：位于有源层17栅极G之间和栅绝缘层15，位于栅极G和源极S、漏极D之间的第一层间绝缘层16；如图16所示，当源极S与漏极D位于不同层时，位于漏极D和有源层17之间的多层绝缘层包括：位于有源层 17栅极G之间和栅绝缘层15，位于栅极G和源极S之间的第一层间绝缘层16、以及位于源极S和漏极D之间的第二层间绝缘层25。
在一些实施例中，如图1～图4、图6～图15、图16所示，有源层17包括：第一导体化区域19、第二导体化区域18以及半导体区域20；栅极G在第一衬底基板1的正投影落入半导体区域20在第一衬底基板1的正投影内；漏极D通过贯穿多层绝缘层的第二过孔与第一导体化区域19电连接；当源极S与漏极D位于同层时，第二过孔贯穿第一层间绝缘层16、栅绝缘层15；当源极S与漏极D位于不同层时，第二过孔贯穿第二层间绝缘层25、第一层间绝缘层16、栅绝缘层15；源极S通过贯穿第一层间绝缘层16、栅绝缘层15的第三过孔与第二导体化区域18电连接。
在一些实施例中，如图1～图4、图6～图15、图16所示，阵列基板还包括位于有源层17和第一衬底基板1之间的缓冲层14。
在一些实施例中，如图17所示，第一过孔7在第一衬底基板的正投影与第二过孔26在第一衬底基板的正投影互不交叠。从而可以避免不同过孔具有重叠导致过孔的区域的平坦度与其余区域平坦度差异过大影响液晶盒厚均一性。
在一些实施例中，如图17所示，阵列基板具体包括横纵交叉的多条扫描线29和多条数据线30；多条扫描线29和多条数据线30划分多个子像素单元；多条扫描线29沿第一方向X延伸、沿第二方向Y排列，多条数据线沿第二方向Y延伸、沿第一方向X排列；第一方向X与第二方向Y交叉；多个子像素单元划分为：沿第一方向X延伸、沿第二方向Y排列的多个子像素单元行，沿第二方向Y延伸、沿第一方向X排列的多个子像素单元列，每一子像素单元行包括一个与该子像素单元行包括的薄膜晶体管电连接扫描线20，每一子像素单元列包括一个与该子像素单元列包括的薄膜晶体管电连接数据线30。
在一些实施例中，如图17所示，在垂直于第一衬底基板的方向上，扫描线29位于漏极S和有源层17之间；与有源层17在第一衬底基板的正投影具有交叠的扫描线29的区域为栅极G；
第一像素电极6在第一衬底基板的正投影与和该第一像素电极6位于相邻子像素单元行的扫描线29在第一衬底基板的正投影具有交叠。
即本公开实施例提供的阵列基板，第一像素电极在第一衬底基板的正投影与相邻行扫描线在第一衬底基板的正投影具有交叠，可以增大第一像素电极的电压保持能力，同时不影响本行子像素单元行发光。
在具体实施时，扫描线位于栅绝缘层与第一层间绝缘层之间。
在一些实施例中，如图17所示，第一像素电极6在第一衬底基板的正投影与和该第一像素电极6位于相同子像素单元列的数据线30在第一衬底基板的正投影具有交叠。
即本公开实施例提供的阵列基板，第一像素电极在第一衬底基板的正投影与该第一像素电极所在的子像素单元列包括的数据线在第一衬底基板的正投影具有交叠，可以遮挡数据线带来的光线噪声，同时不影响其他列数据线上的电位。
需要说明的是，图17中，以在第一方向X上第一像素电极6在第一衬底基板的正投影与数据线30在第一衬底基板的正投影具有交叠的区域的宽度小于数据线30的宽度为例进行举例说明。当然，也可以使得在第一方向上第一像素电极在第一衬底基板的正投影与数据线在第一衬底基板的正投影具有交叠的区域的宽度等于数据线的宽度，进一步增大第一像素电极的面积，提高开口率。
在一些实施例中，如图17所示，与有源层17电连接的数据线30的区域为源极S。
在一些实施例中，数据线位于第一层间绝缘层和第一平坦化层之间。
需要说明的是，图18为图17示出的区域对应的有源层17、第二过孔26以及第三过孔31的图案；图17中与扫描线29具有交叠的有源层17的区域为有源层的半导体区域，与扫描线29互不交叠的有源层17的区域为有源层的导体化区域。第二过孔26以及第三过孔31对应的区域可以分别为第一导体化区域、第二导体化区域。图18中以位于相邻子像素单元行的第二过孔26 和第三过孔31的中心连线不在一条沿第一方向X延伸的水平线上为例进行举例说明，在具体实施时，也可以设置为位于相邻子像素单元行的第二过孔26和第三过孔31的中心连线在一条沿第一方向X延伸的水平线上。
需要说明的是，图19为图17示出的区域对应的扫描线29在第一衬底基板的正投影的图案。
需要说明的是，图20为图17示出的区域对应的数据线30和漏极D在第一衬底基板的正投影的图案；图17以及图20以数据线30和漏极D同层设置为例进行举例说明，当数据线30和漏极D位于不同层时，数据线30所在膜层的图案和漏极D所在膜层的图案分别如图23、图24所示。当数据线和漏极位于不同层时，当数据线和漏极可以均包括金属电极材料，或者，也可以是数据线包括金属电极材料，漏极包括透明电极材料。
需要说明的是，图21为图17示出的区域对应的第一过孔7在第一衬底基板的正投影的图案；图17、图21以第一子过孔11的面积小于第二子过孔12的面积、且第一子过孔11在第一衬底基板的正投影落入第二子过孔12的在第一衬底基板的正投影内为例进行举例说明。
需要说明的是，图22为图17示出的区域对应的第一像素电极6在第一衬底基板的正投影的图案。
需要说明的是，图17未示出平坦部的图案，在具体实施时，平坦部在第一衬底基板的正投影的图案例如可以是如图25所示。
需要说明的是，当阵列基板还包括第二像素电极时，第二像素电极在第一衬底基板的正投影的轮廓的形状与第一像素电极在第一衬底基板的正投影的轮廓的形状相同，在具体实施时，第二像素电极的图案如图26、图27所示。图26所示的第二像素电极10在第一衬底基板的正投影覆盖第一像素电极在第一衬底基板的正投影；图27所示的第二像素电极10包括第一开口24。
在一些实施例中，如图17、图22所示，第一像素电极6在第一衬底基板的正投影的形状为矩形。
相应的，如图26、图27所示，当阵列基板还包括第二像素电极时第二像 素电极在第一衬底基板的正投影的轮廓的形状为矩形。
在一些实施例中，第一过孔在第一衬底基板的正投影的至少一个边缘与第一像素电极在第一衬底基板的正投影的边缘具有重叠区域。从而第一过孔在第一衬底基板的正投影靠近第一像素电极在第一衬底基板的正投影的边缘，可以保证第一像素电极大部分区域的平坦性。
需要说明的是，考虑到对位偏差以及第一过孔、第一像素电极的尺寸偏差，实际制作中第一过孔在第一衬底基板的正投影的至少一个边缘与第一像素电极在第一衬底基板的正投影的边缘具有重叠区域不易实现。因此，在一些实施例中，可以设计为如图17、图28所示，第一过孔7在第一衬底基板的正投影靠近第一像素电极6的边缘与第一像素电极6在第一衬底基板的正投影的边缘之间具有一定距离。当第一过孔在第一衬底基板的正投影靠近第一像素电极的边缘与第一像素电极在第一衬底基板的正投影的边缘之间具有一定距离、且距离较小时，第一过孔在第一衬底基板的正投影仍靠近第一像素电极在第一衬底基板的正投影的边缘，仍可以保证第一像素电极大部分区域的平坦性。
需要说明的是，图28以第一子过孔11在第一衬底基板的正投影落入第二子过孔12在第一衬底基板的正投影内为例进行举例说明，第一过孔7在第一衬底基板的正投影靠近第一像素电极6的边缘即为第一子过孔11在第一衬底基板的正投影靠近第一像素电极6的边缘。图28中h3、h4即为第一子过孔11在第一衬底基板的正投影靠近第一像素电极6的边缘与第一像素电极在第一衬底基板的正投影的边缘之间的距离。
在一些实施例中，第一过孔在第一衬底基板的正投影靠近第一像素电极的边缘与第一像素电极在第一衬底基板的正投影的边缘之间的最小距离小于等于1.5微米。即第一过孔在第一衬底基板的正投影的边缘与第一像素电极在第一衬底基板的正投影的边缘之间的距离较近，仍可以保证第一像素电极大部分区域的平坦性。尤其是对于未设置第二像素电极或第二像素电极具有第一开口的方案，保证第一像素电极大部分区域的平坦性可以保证开口率。
在一些实施例中，如图28所示，第一过孔7在第一衬底基板的正投影靠近第一像素电极6在第一衬底基板的正投影的矩形的其中一个直角。即第一过孔在第一衬底基板的正投影靠近第一像素电极在第一衬底基板的正投影的矩形的其中一个直角的每个边缘与第一像素电极在第一衬底基板的正投影的边缘之间的距离均小于等于1.5微米。
需要说明的是，当第一过孔在第一衬底基板的正投影靠近第一像素电极在第一衬底基板的正投影的矩形的其中一个直角时，如图28所示，矩形的第一像素电极6的图案具有沿第一方向X延伸的第一对称轴32以及沿第二方向Y延伸的第二对称轴33，第一对称轴32和第二对称轴33将第一像素电极6划分为四个子区域，四个子区域分别为子区域a、子区域b、子区域c、子区域d；第一过孔7在第一衬底基板的正投影仅落入四个子区域中的一个子区域在第一衬底基板的正投影。需要说明的是，图28以第一过孔7在第一衬底基板的正投影仅落入子区域d在第一衬底基板的正投影为例进行举例说明。在具体实施时，第一过孔在第一衬底基板的正投影靠近d区域的第一像素电极的每个边缘与第一像素电极在第一衬底基板的正投影的边缘之间的距离均小于等于1.5微米。即图28中，h3、h4均小于等于1.5微米。
在一些实施例中，如图17、图18所示，有源层17在第一衬底基板的正投影的图案包括：依次连接的第一部分34、第二部分35和第三部分36；
如图17所示，第一部分34与源极S电连接，第三部分与漏极D电连接，扫描线29在第一衬底基板的正投影与第二部分35在第一衬底基板的正投影具有交叠。
在一些实施例中，如图17、图18所示，第一部分34和第三部分36均包括沿第二方向Y延伸的部分，第二部分35沿第一方向X延伸；
第二部分35在第一方向X的两端分别与第一部分34和第三部分36连接，且在第二方向Y上，第一部分34和第三部分36分别位于第二部分35的两侧；
第二部分35的延伸方向与扫描线29的延伸方向平行；第二部分35在第一衬底基板的正投影落入扫描线29在第一衬底基板的正投影内。
本公开实施例提供的阵列基板中，有源层在第一衬底基板的正投影的图案包括：依次连接的第一部分、第二部分和第三部分，且第一部分和第三部分分别位于第二部分的两侧，即有源层的图案为至少弯折三次的折线形图案。从而有源层在子像素单元中分布均匀，避免有源层分布过于集中导致其在子像素单元中的面积较大，有利于实现高像素密度。并且还可以增加有源层沟道区的长度，以减小薄膜晶体管的漏电流。
在一些实施例中，如图17所示，在第二方向Y上，第二部分35的宽度小于扫描线29的宽度。
从而可以通过调节第二部分、扫描线之间的宽度来调节有源层沟道区的宽长比，使得有源层沟道区的宽长比满足所需的薄膜晶体管的驱动电流的要求。
当有源层在第一衬底基板的正投影的图案包括：依次连接的第一部分、第二部分和第三部分时，有源层的图案还可以采用其他设置方式。
在一些实施例中，如图29所示，第二部分35沿第二方向Y延伸；
第二部分35在第二方向Y的两端分别与第一部分34和第三部分36连接，且在第一方向X上，第一部分34和第三部分36分别位于第二部分35的两侧；
第二部分35的延伸方向与扫描线29的延伸方向垂直；第二部分35在第一衬底基板的正投影与扫描线29在第一衬底基板的正投影具有交叠，且第一部分34和第三部分36在第一衬底基板的正投影与扫描线29在第一衬底基板的正投影互不交叠。
本公开实施例提供的阵列基板中，有源层在第一衬底基板的正投影的图案包括：依次连接的第一部分、第二部分和第三部分，且第一部分和第三部分分别位于第二部分的两侧，即有源层的图案为至少弯折三次的折线形图案。从而有源层在子像素单元中分布均匀，避免有源层分布过于集中导致其在子像素单元中的面积较大，有利于实现高像素密度。第二部分沿第二方向延伸，可以在实现有源层均匀分布的同时减小其在第一方向上的尺寸，可以进一步提高像素密度。并且，第二部分为规则的条形图案，从而有源层与扫描线具 有交叠的部分为规则的四边形图案，相比于有源层与扫描线具有交叠的部分为不规则图案的情况下，可以减小有源层图案制作工艺偏差对薄膜晶体管沟道区的宽度、长度带来的影响。
需要说明的是，图29所示的阵列基板中相邻两个子像素单元行包括的有源层的图案不完全相同，如图30所示，相邻两个子像素单元行中，第一部分34位于第二部分35下方、第二部分36位于第二部分35上方；但其中一行第二过孔26位于第二部分35左侧、第三过孔31位于第二部分35右侧，另一行第二过孔26位于第二部分35右侧、第三过孔31位于第二部分35左侧。
需要说明的是，如图29～图30所示，与扫描线29具有交叠的第二部分35的区域为半导体区域，与扫描线29互不交叠的第二部分35的区域以及第一部分24、第三部分36的区域为导体化区域。
当有源层在第一衬底基板的正投影的图案包括：依次连接的第一部分、第二部分和第三部分时，有源层的图案还可以采用其他设置方式。
在一些实施例中，如图31所示，有源层17在第一衬底基板的正投影的图案包括：依次连接的第一部分34、第二部分35和第三部分36；第一部分34和第三部分36沿第二方向Y延伸，第二部分35沿第一方向X延伸；
第二部分35在第一方向X的两端分别与第一部分34和第三部分36连接，且在第二方向Y上，第一部分34和第三部分36分别位于第二部分35的同一侧；
第一部分34与源极S电连接，第三部分36与漏极D电连接；
栅极包括第一栅极G1和第二栅极G2；
扫描线29在第一衬底基板的正投影与第一部分34和第三部分36在第一衬底基板的正投影均具有交叠，且扫描线29在第一衬底基板的正投影与第二部分35在第一衬底基板的正投影互不交叠；
与第一部分34在第一衬底基板的正投影具有交叠的扫描线29的区域为第一栅极G1，与第三部分36在第一衬底基板的正投影具有交叠的扫描线29的区域为第二栅极G2。
即图31所示的有源层17在第一衬底基板的图案的形状为U型。需要说明的是，为了清楚的示意出有源层与晶体管各膜层的正投影关系，图31中未示出第一像素电极在第一衬底基板的正投影。
本公开实施例提供的阵列基板，有源层在第一衬底基板的图案的形状为U型，从而可以实现沿第一方向延伸的扫描线与有源层的两个区域具有交叠，栅极包括第一栅极G1和第二栅极G2，即薄膜晶体管为双栅薄膜晶体管，可以减小薄膜晶体管的漏电流。
需要说明的是，如图31所示，与扫描线29具有交叠的第一部分24、第三部分36的区域为半导体区域，与扫描线29互不交叠的第一部分24、第三部分36的区域以及第二部分35为导体化区域。
除了上述图18、图29～图31所示的有源层的图案之外，有源层的图案还可以采用其他设置方式。
在一些实施例中，如图32、图33所示，有源层17在第一衬底基板的正投影的图案包括：相互连接的第一部分34和第二部分35；第一部分34沿第一方向X延伸，第二部分35沿第二方向Y延伸；
第一部分34与漏极D电连接，第二部分35与源极S电连接；
扫描线29在第一衬底基板的正投影至少与第一部分34、第二部分35之一在第一衬底基板的正投影具有交叠。
即本公开实施例提供的阵列基板中，有源层在第一衬底基板的正投影的图案为L型。
在一些实施例中，如图32所示，扫描线29在第一衬底基板的正投影的形状为沿第一方向X延伸的条形，扫描线29在第一衬底基板的正投影仅与第二部分35在第一衬底基板的正投影具有交叠。
需要说明的是，如图32所示，与扫描线29具有交叠的第二部分35的区域为半导体区域，与扫描线29互不交叠的第二部分35的区域以及第一部分34为导体化区域。
在具体实施时，第一部分的图案为条形，扫描线与条形的第二部分具有 交叠，可以增大有源层沟道区的宽长比，提高薄膜晶体管的驱动电流。
或者，在一些实施例中，如图33所示，扫描线29在第一衬底基板的正投影与第一部分34和第二部分35在第一衬底基板的正投影均具有交叠；
与第二部分35在第一衬底基板的正投影具有交叠的扫描线29的区域为第一栅极G1，与第一部分34在第一衬底基板的正投影具有交叠的扫描线29的区域为第二栅极G2。
本公开实施例提供的阵列基板，扫描线与有源层的两个区域具有交叠，栅极包括第一栅极G1和第二栅极G2，即薄膜晶体管为双栅薄膜晶体管，可以减小薄膜晶体管的漏电流。
在一些实施例中，如图33所示，扫描线29在第一衬底基板的正投影的图案包括沿第一方向X延伸的、条形的第一图案37，以及在第二方向Y上在第一图案37一侧与第一图案37连接的第二图案38；
第一图案37在第一衬底基板的正投影与第二部分35在第一衬底基板的正投影具有交叠，第二图案38在第一衬底基板的正投影与第一部分34在第一衬底基板的正投影具有交叠。
需要说明的是，如图33所示，与扫描线29具有交叠的第一部分34、第二部分35的区域为半导体区域，与扫描线29互不交叠的第一部分34、第二部分35的区域为导体化区域。
需要说明的是，图17～图33中并未示出公共电极的图案。在具体实施时，如图1所示，公共电极4为具有多个第二开口21的面状电极，公共电极4通过第二开口21避让像素电极。在具体实施时，可以整面沉积公共电极层，之后再对整面的公共电极层进行图形化工艺形成多个第二开口。当然，在具体实施时，为了调整公共电极与像素电极之间形成的电场，还可以第二开口之外的区域形成与第一像素电极在第一衬底基板的正投影具有交叠的条状第三开口，条状第三开口沿第二方向延伸，第三开口的数量可以根据实际需要进行设置。
基于同一发明构思，本公开实施例还提供了一种阵列基板的制备方法， 如图34所示，包括：
S101、在第一衬底基板上依次形成多个薄膜晶体管、第一平坦化层、公共电极的图案、第一介质层，并形成贯穿第一平坦化层和第一介质层的第一过孔；
S102、在第一介质层背离公共电极层的一侧形成第一像素电极；其中，第一像素电极通过贯穿第一介质层以及第一平坦化层的第一过孔与薄膜晶体管一一对应电连接，第一像素电极背离第一衬底基板一侧的表面具有至少与第一过孔对应的第一凹槽；
S103、在第一凹槽背离第一衬底基板的一侧形成平坦部；平坦部远离第一衬底基板一侧的表面到第一衬底基板的距离与第一像素电极远离第一衬底基板一侧表面到第一衬底基板的距离大致相同。
本公开实施例提供的阵列基板的制备方法，在形成第一像素电极之后，还形成填平第一像素电极的第一凹槽的平坦部，可以提高阵列基板的厚度均一性。当制得的阵列基板应用于液晶盒时，进而可以提高液晶盒厚均一性，提高液晶盒进行光场调控时的调控质量，避免出现画质不均、调制线性度不足。
在一些实施例中，在第一凹槽背离第一衬底基板的一侧形成平坦部之后，还包括：
在平坦部背离第一衬底基板的一侧形成第二像素电极。
在一些实施例中，在第一介质层背离公共电极层的一侧形成第一像素电极，具体包括：
在第一介质层背离公共电极层的一侧沉积第一像素电极材料，形成第一像素电极层；
对第一像素电极层进行图形化处理，形成多个第一像素电极的图案；
在平坦部背离第一衬底基板的一侧形成第二像素电极，具体包括：
在平坦部背离第一衬底基板的一侧沉积第二像素电极材料，形成第二像素电极层；
对第二像素电极层进行图形化处理，形成多个第二像素电极的图案。
在具体实施时，对第一像素电极层进行图形化工艺以及对第二像素电极层进行图形化工艺例如均包括：涂胶、曝光、显影、刻蚀等步骤。刻蚀例如可以采用干刻工艺。
在一些实施例中，在第一介质层背离公共电极层的一侧形成第一像素电极，具体包括：
在第一介质层背离公共电极层的一侧沉积第一像素电极材料，形成第一像素电极层；
在平坦部背离第一衬底基板的一侧形成第二像素电极，具体包括：
在平坦部背离第一衬底基板的一侧沉积第二像素电极材料，形成第二像素电极层；
对第二像素电极层以及第一像素电极层进行图形化处理，形成多个第二像素电极的图案以及多个第一像素电极的图案。
本公开实施例提供的阵列基板的制备方法，在形成第一像素电极层之后无需进行图形化处理，而在形成第二像素电极层之后通过一次图形化工艺形成在第一衬底基板上大致重叠的第二像素电极和第一像素电极的图案，可以节省一次图形化工艺，节省成本。
在具体实施时，对第二像素电极层、第一像素电极层进行图形化工艺例如均包括：涂胶、曝光、显影、刻蚀等步骤。刻蚀例如可以采用干刻工艺。
在一些实施例中，在平坦部背离第一衬底基板的一侧形成第二像素电极之后，还包括：
在第二像素电极背离平坦部一侧形成第一保护层；
在第一保护层背离第二像素电极一侧形成浮置反射图案的图案。
在一些实施例中，在第一凹槽背离第一衬底基板的一侧形成平坦部，具体包括：
在第一凹槽背离第一衬底基板的一侧形成光敏树脂层；
采用曝光显影工艺形成平坦部的图案；
对平坦部的表面进行灰化工艺。
需要说明的是，对平坦部的表面进行灰化工艺，可以提高平坦部背离衬底基板一侧表面的平坦化效果。
在一些实施例中，第一过孔包括第一子过孔以及第二子过孔，在第一衬底基板上依次形成第一平坦化层、公共电极、第一介质层，并形成贯穿第一平坦化层和第一介质层的第一过孔，具体包括：
在薄膜晶体管背离第一衬底基板的一侧沉积第一平坦化层材料，形成第一平坦化层；
对第一平坦化层进行图形化工艺，形成多个第一子过孔，得到第一平坦化层的图案；
在第一平坦化层背离第一衬底基板一侧形成公共电极的图案；
在公共电极背离第一平坦化层的一侧沉积第一介质层材料，形成第一介质层；
对第一介质层进行图形化工艺，形成多个贯穿第一介质层的第二子过孔，得到第一介质层的图案。
在具体实施时，第一平坦化层的材料为有机材料，第一介质层的材料为无机材料。有机材料例如可以是光敏树脂。无机材料可以为氮化硅(SiN)、氧化硅(SiO2)、或SiN/SiO2叠层。对第一平坦化层进行图形化工艺，例如可以对包括光敏树脂的第一平坦化层进行、前烘烤、曝光、显影工艺，形成第一子过孔，之后再对包括第一子过孔的第一平坦化层进行热固化工艺。对第一介质层进行图形化工艺例如均包括：涂胶、曝光、显影、刻蚀等步骤。刻蚀例如可以采用干刻工艺。
在一些实施例中，在第一平坦化层背离第一衬底基板一侧形成公共电极的图案的同时还包括：
形成覆盖第一子过孔的第一连接电极的图案。
具体地，可以在第一平坦化层背离第一衬底基板一侧沉积公共电极材料，形成公共电极层，之后再对共电极层进行图形化处理，形成公共电极的图案 以及第一连接电极的图案。
本公开实施例提供的阵列基板的制备方法，在形成公共电极的图案的同时还在第一过孔形成第一连接电极的图案，这样后续形成的第一像素电极通过第一连接电极与薄膜晶体管电连接，从而第一像素电极与薄膜晶体管电连接的工艺简单易于实现，还可以避免由于第一过孔较深、直接通过第一像素电极与薄膜晶体管接触导致的搭接断线，可以提高阵列基板良率。
在一些实施例中，第一过孔包括第一子过孔以及第二子过孔，在第一衬底基板上依次形成第一平坦化层、公共电极、第一介质层，并形成贯穿第一平坦化层和第一介质层的第一过孔，具体包括：
在薄膜晶体管背离第一衬底基板的一侧旋涂第一平坦化层材料，采用热固化工艺形成第一平坦化层；
在第一平坦化层背离第一衬底基板一侧形成公共电极的图案；
在公共电极背离第一平坦化层的一侧沉积第一介质层材料，形成第一介质层；
对第一介质层以及平坦化层进行图形化工艺，形成贯穿第一介质层的第二子过孔以及贯穿第一平坦化层的第一子过孔，得到第一介质层的图案。
本公开实施例提供的阵列基板的制备方法，通过一次图形化工艺形成第二子过孔、第一子过孔，可以节省阵列基板制备工艺流程。
在具体实施时，第一平坦化层的材料为无机材料，第一介质层的材料为无机材料。第一平坦化层包括的无机材料例如可以为SiO 2；第一介质层包括的无机材料可以为SiN、SiO 2、或SiN/SiO 2叠层。
在具体实施时，在薄膜晶体管背离第一衬底基板的一侧旋涂有机硅氧烷，采用热固化工艺形成SiO 2层作为第一平坦化层。对第一介质层、SiO 2层进行图形化工艺例如均包括：涂胶、曝光、显影、刻蚀等步骤。刻蚀例如可以采用干刻工艺。
在具体实施时，第一介质层的厚度小于SiO 2层的厚度，且第一介质层的厚度小于100纳米。
在一些实施例中，在形成第一平坦化层之前，具体包括：
在第一衬底基板上形成缓冲层；
在缓冲层背离第一衬底基板一侧形成薄膜晶体管的有源层的图案；
在有源层背离缓冲层一侧形成栅绝缘层的图案；
在栅绝缘层背离有源层一侧形成扫描线的图案；与有源层在第一衬底基板的正投影具有交叠的扫描线的区域为薄膜晶体管的栅极；
对有源层未被扫描线覆盖的区域进行导体化处理形成导体化区域；导体化区域包括第一导体化区域和第二导体化区域；
在扫描线背离栅绝缘层一侧形成第一层间绝缘层，并形成贯穿第一层间绝缘层和栅绝缘层的第二过孔、形成贯穿第一层间绝缘层和栅绝缘层的第三过孔；
在第一层间绝缘层背离扫描线一侧形成数据线的图案以及漏极的图案；漏极同第二过孔与有源层的第一导体化区域接触，数据线通过第三过孔与有源层的第二导体化区域接触，与有源层的第二导体化区域接触的扫描线的区域为薄膜晶体管的源极。
或者，在一些实施例中，在形成第一平坦化层之前，具体包括：
在第一衬底基板上形成缓冲层；
在缓冲层背离第一衬底基板一侧形成薄膜晶体管的有源层的图案；
在有源层背离缓冲层一侧形成栅绝缘层的图案；
在栅绝缘层背离有源层一侧形成扫描线的图案；与有源层在第一衬底基板的正投影具有交叠的扫描线的区域为薄膜晶体管的栅极；
对有源层未被扫描线覆盖的区域进行导体化处理形成导体化区域；导体化区域包括第一导体化区域和第二导体化区域；
在扫描线背离栅绝缘层一侧形成第一层间绝缘层，并形成贯穿第一层间绝缘层和栅绝缘层的第三过孔；
在第一层间绝缘层背离扫描线一侧形成数据线的图案；数据线通过第三过孔与有源层的第二导体化区域接触，与有源层的第二导体化区域接触的扫 描线的区域为薄膜晶体管的源极；
在数据线背离第一层间绝缘层的一侧形成第二层间绝缘层，并形成贯穿第二层间绝缘层、第一层间绝缘层和栅绝缘层的第二过孔；
在第二层间绝缘层背离数据线一侧形成漏极的图案；漏极同第二过孔与有源层的第一导体化区域接触。
本公开实施例中提供的阵列基板的制备方法中，源极与漏极设置于不同导电层，这样，即便减小源极在第一衬底基板的正投影的边缘与漏极在第一衬底基板的正投影的边缘之间的距离，也不会造成源极与漏极之间短路，可以简化阵列基板版图的设计难度。并且减小源极在第一衬底基板的正投影的边缘与漏极在第一衬底基板的正投影的边缘之间的距离还可以减小子像素单元的尺寸，有利于实现高像素密度，从而可以提高分辨率，有利于实现高分辨率显示。
本公开实施例提供的一种液晶盒，如图35、图36所示，包括：
本公开实施例提供的阵列基板39；
对向基板40，与阵列基板39相对设置；
液晶层41，位于阵列基板39和对向基板40之间。
在一些实施例中，本公开实施例提供的液晶盒可以作为液晶显示的显示面板。如图35所示，对向基板40包括第二衬底基板48，位于第二衬底基板48靠近液晶层41的彩膜49和黑矩阵50。黑矩阵50包括与子像素单元一一对应的开口区51，彩膜49位于开口区51内。
在一些实施例中，多个子像素单元包括多个红色子像素单元、多个蓝色子像素单元以及多个绿色子像素单元；相应的，彩膜包括与红色子像素单元对应的红色彩膜、与蓝色子像素单元对应的蓝色彩膜、以及与绿色子像素单元对应的绿色彩膜。
或者，在一些实施例中，液晶盒作为光控面板，即通过适当的电场调节使得液晶层整体位置上的相位分布呈周期性的类似于光栅结构的形貌。如图36所示，对向基板40包括第二衬底基板48，位于第二衬底基板48靠近液晶 层41的黑矩阵50。黑矩阵50包括与子像素单元一一对应的开口区51。当液晶盒作为光控面板时开口区内无需设置彩膜。
本公开实施例提供的一种显示装置，如图37、图38，包括本公开实施例提供的上述液晶盒42。
在一些实施例中，如图37所示，本公开实施例提供的上述液晶盒42为第一液晶盒46，显示装置还包括：位于第一液晶盒46出光侧的第二液晶盒47。
即本公开实施例提供的显示装置包括两层液晶盒，即显示装置包括双层液晶面板。其中，第一液晶盒作为光控面板，光控面板的每一子像素单元可以单独控制明暗，可以使得显示装置显示的画面更细腻，以提高显示效果。在具体实施时，第一液晶盒的第一对向基板无需设置彩膜。而第二液晶盒作为显示面板，第二液晶盒也包括阵列基板、液晶层以及对向基板，第二液晶盒的第二对向基板需要设置彩膜。在具体实施时，无论显示装置是透射式显示还是反射式显示，第二液晶盒为透射式液晶盒。第二液晶盒包括的阵列基板也可以采用本公开实施例提供的上述透射式显示的阵列基板，即公共电极、第一像素电极均包括透明材料，平坦部填平第一像素电极的凹槽。当然，第二液晶盒包括的阵列基板也可以包括第二像素电极，第二像素电极包括透明材料。
在一些实施例中，当显示装置为透射式液晶显示时，显示装置还包括位于第一液晶盒背离第二液晶盒一侧的背光模组。
在一些实施例中，显示装置可以应用于3D显示；如图38所示，显示装置还包括：
柱透镜结构43，位于液晶盒42的出光侧；
透光隔垫层44，位于液晶盒42和柱透镜结构43之间；
平坦层45，位于柱透镜结构45背离透光隔垫层44一侧。
在一些实施例中，当显示装置为透射式液晶显示时，显示装置还包括位于液晶盒入光侧的背光模组。
本公开实施例提供的显示装置为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。该显示装置的实施可以参见上述阵列基板、液晶盒的实施例，重复之处不再赘述。
综上所述，本公开实施例提供的阵列基板及其制备方法、液晶盒、显示装置，利用平坦部填平第一像素电极在第一过孔区域具有的第一凹槽，可以提高阵列基板的厚度均一性。进而可以提高液晶盒厚均一性，提高液晶盒进行光场调控时的调控质量，避免出现画质不均、调制线性度不足。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明实施例的精神和范围。这样，倘若本发明实施例的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (31)

  1. 一种阵列基板，其中，所述阵列基板包括：
    第一衬底基板；
    多个薄膜晶体管，位于所述第一衬底基板的一侧；
    第一平坦化层，位于所述薄膜晶体管背离所述第一衬底基板的一侧；
    公共电极，位于所述第一平坦化层背离所述薄膜晶体管的一侧；
    第一介质层，位于所述公共电极背离所述第一平坦化层的一侧；
    多个第一像素电极，位于所述第一介质层背离所述公共电极的一侧；所述第一像素电极通过贯穿所述第一介质层以及所述第一平坦化层的第一过孔与所述薄膜晶体管一一对应电连接；所述第一像素电极背离所述第一衬底基板一侧的表面具有至少与所述第一过孔对应的第一凹槽；
    多个平坦部，位于所述第一凹槽背离所述第一衬底基板的一侧；所述平坦部远离所述第一衬底基板一侧的表面到所述第一衬底基板的距离与所述第一像素电极远离所述第一衬底基板一侧表面到所述第一衬底基板的距离大致相同。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：
    多个第二像素电极，位于所述第一像素电极背离所述第一衬底基板一侧，与所述第一像素电极接触。
  3. 根据权利要求2所述的阵列基板，其中，所述第二像素电极在所述第一衬底基板的正投影覆盖所述第一像素电极在所述第一衬底基板的正投影。
  4. 根据权利要求2所述的阵列基板，其中，所述第二像素电极包括第一开口，所述第一开口在所述第一衬底基板的正投影覆盖所述平坦部在所述第一衬底基板的正投影。
  5. 根据权利要求4所述的阵列基板，其中，所述第二像素电极在所述第一衬底基板的正投影包围所述平坦部在所述第一衬底基板的正投影，且所述第二像素电极在所述第一衬底基板的正投影与所述平坦部在所述第一衬底基 板的正投影拼接组成封闭图形。
  6. 根据权利要求2～5任一项所述的阵列基板，其中，所述公共电极包括透明材料；
    所述第一像素电极包括透明材料，所述第二像素电极包括反射材料；或者，所述第一像素电极和所述第二像素电极均包括反射材料。
  7. 根据权利要求6所述的阵列基板，其中，所述阵列基板还包括：
    第一保护层，位于所述第二像素电极背离所述第一衬底基板的一侧；
    多个浮置反射图案，位于所述第一保护层背离所述第二像素电极的一侧；所述浮置反射图案在所述第一衬底基板的正投影覆盖相邻所述第二像素电极在所述第一衬底基板的正投影之间的间隙。
  8. 根据权利要求1～7任一项所述的阵列基板，其中，所述第一过孔包括：贯穿所述第一平坦化层的第一子过孔以及贯穿所述第一介质层的第二子过孔；
    所述第一介质层覆盖所述第一子过孔的部分区域，所述第二子过孔在所述第一衬底基板的正投影位于所述第一子过孔在所述第一衬底基板的正投影内，且所述第二子过孔位于所述第一子过孔内。
  9. 根据权利要求1～7任一项所述的阵列基板，其中，所述第一过孔包括：贯穿所述第一平坦化层的第一子过孔以及贯穿所述第一介质层的第二子过孔；
    所述第一子过孔在所述第一衬底基板的正投影位于所述第二子过孔在所述第一衬底基板的正投影内。
  10. 根据权利要求9所述的阵列基板，其中，在所述第一像素电极指向所述第一衬底基板的方向上，所述第一子过孔平行于所述第一衬底基板所在平面方向上的截面面积逐渐减小，所述第二子过孔平行于所述第一衬底基板所在平面方向上的截面面积逐渐减小，且所述第一子过孔平行于所述第一衬底基板所在平面方向上的截面的最大面积等于所述第二子过孔平行于所述第一衬底基板所在平面方向上的截面最小面积。
  11. 根据权利要求9所述的阵列基板，其中，在所述第一像素电极指向所述第一衬底基板的方向上，所述第一子过孔平行于所述第一衬底基板所在平面方向上的截面面积逐渐减小，所述第二子过孔平行于所述第一衬底基板所在平面方向上的截面面积逐渐减小，且所述第二子过孔平行于所述第一衬底基板所在平面方向上的截面的最大面积大于所述第一子过孔平行于所述第一衬底基板所在平面方向上的截面最小面积。
  12. 根据权利要求11所述的阵列基板，其中，所述阵列基板还包括：
    多个第一连接电极，与所述公共电极同层设置且覆盖所述第一子过孔；所述第一连接电极与所述第一像素电极以及所述薄膜晶体管接触。
  13. 根据权利要求1～12任一项所述的阵列基板，其中，所述薄膜晶体管包括：有源层，栅极，源极和漏极；所述漏极与所述第一像素电极电连接；所述源极位于所述漏极与所述第一衬底基板之间。
  14. 根据权利要求13所述的阵列基板，其中，所述阵列基板包括横纵交叉的多条扫描线和多条数据线；所述多条扫描线和所述多条数据线划分多个子像素单元；所述子像素单元包括所述薄膜晶体管和与所述薄膜晶体管电连接的所述第一像素电极；所述多条扫描线沿第一方向延伸、沿第二方向排列，所述多条数据线沿所述第二方向延伸、沿所述第一方向排列；所述第一方向与所述第二方向交叉；所述多个子像素单元划分为：沿所述第一方向延伸、沿所述第二方向排列的多个子像素单元行，沿所述第二方向延伸、沿所述第一方向排列的多个子像素单元列，每一所述子像素单元行包括一个与该所述子像素单元行包括的所述薄膜晶体管电连接的所述扫描线，每一所述子像素单元列包括一个与该所述子像素单元列包括的所述薄膜晶体管电连接的所述数据线；
    在垂直于所述第一衬底基板的方向上，所述扫描线位于所述漏极和所述有源层之间，与所述有源层在所述第一衬底基板的正投影具有交叠的所述扫描线的区域为所述栅极；
    所述数据线位于所述扫描线背离所述有源层的一侧，与所述有源层电连 接的所述数据线的区域为所述源极。
  15. 根据权利要求14所述的阵列基板，其中，所述第一像素电极在所述第一衬底基板的正投影与和该所述第一像素电极位于相邻所述子像素单元行的所述扫描线在所述第一衬底基板的正投影具有交叠。
  16. 根据权利要求14或15所述的阵列基板，其中，所述第一像素电极在所述第一衬底基板的正投影与和该所述第一像素电极位于相同所述子像素单元列的所述数据线在第一衬底基板的正投影具有交叠。
  17. 根据权利要求14～16任一项所述的阵列基板，其中，所述有源层在所述第一衬底基板的正投影的图案包括：依次连接的第一部分、第二部分和第三部分；
    所述第一部分与所述源极电连接，所述第三部分与所述漏极电连接，所述扫描线在所述第一衬底基板的正投影与所述第二部分在所述第一衬底基板的正投影具有交叠。
  18. 根据权利要求17所述的阵列基板，其中，所述第一部分和所述第三部分均包括沿所述第二方向延伸的部分，所述第二部分沿所述第一方向延伸；
    所述第二部分在所述第一方向的两端分别与所述第一部分和所述第三部分连接，且在所述第二方向上，所述第一部分和第三部分分别位于所述第二部分的两侧；
    所述第二部分的延伸方向与所述扫描线的延伸方向平行；所述第二部分在所述第一衬底基板的正投影落入所述扫描线在所述第一衬底基板的正投影内。
  19. 根据权利要求18所述的阵列基板，其中，在所述第二方向上，所述第二部分的宽度小于所述扫描线的宽度。
  20. 根据权利要求18所述的阵列基板，其中，所述第二部分沿所述第二方向延伸；
    所述第二部分在所述第二方向的两端分别与所述第一部分和所述第三部分连接，且在所述第一方向上，所述第一部分和第三部分分别位于所述第二 部分的两侧；
    所述第二部分的延伸方向与所述扫描线的延伸方向垂直；所述第二部分在所述第一衬底基板的正投影与所述扫描线在所述第一衬底基板的正投影具有交叠，且所述第一部分和第三部分在所述第一衬底基板的正投影与所述扫描线在所述第一衬底基板的正投影互不交叠。
  21. 根据权利要求14～16任一项所述的阵列基板，其中，所述有源层在所述第一衬底基板的正投影的图案包括：依次连接的第一部分、第二部分和第三部分；所述第一部分和所述第三部分沿所述第二方向延伸，所述第二部分沿所述第一方向延伸；
    所述第二部分在所述第一方向的两端分别与所述第一部分和所述第三部分连接，且在所述第二方向上，所述第一部分和第三部分分别位于所述第二部分的同一侧；
    所述第一部分与所述源极电连接，所述第三部分与所述漏极电连接；
    所述扫描线在所述第一衬底基板的正投影与所述第一部分和所述第三部分所述在第一衬底基板的正投影均具有交叠，且所述扫描线在所述第一衬底基板的正投影与所述第二部分在所述第一衬底基板的正投影互不交叠；
    所述栅极包括所述第一栅极和所述第二栅极；与所述第一部分在所述第一衬底基板的正投影具有交叠的所述扫描线的区域为所述第一栅极，与所述第三部分在所述第一衬底基板的正投影具有交叠的所述扫描线的区域为所述第二栅极。
  22. 根据权利要求14～16任一项所述的阵列基板，其中，所述有源层在所述第一衬底基板的正投影的图案包括：相互连接的第一部分和第二部分；所述第一部分沿所述第一方向延伸，所述第二部分沿所述第二方向延伸；
    所述第一部分与所述漏极电连接，所述第二部分与所述源极电连接；
    所述扫描线在所述第一衬底基板的正投影至少与所述第一部分、所述第二部分之一在所述第一衬底基板的正投影具有交叠。
  23. 根据权利要求22所述的阵列基板，其中，所述扫描线在所述第一衬 底基板的正投影的形状为沿所述第一方向延伸的条形，所述扫描线在所述第一衬底基板的正投影仅与所述第二部分在所述第一衬底基板的正投影具有交叠。
  24. 根据权利要求22所述的阵列基板，其中，所述扫描线在所述第一衬底基板的正投影与所述第一部分和所述第二部分在所述第一衬底基板的正投影均具有交叠；
    所述栅极包括第一栅极和第二栅极；与所述第二部分在所述第一衬底基板的正投影具有交叠的所述扫描线的区域为所述第一栅极，与所述第一部分在所述第一衬底基板的正投影具有交叠的所述扫描线的区域为所述第二栅极。
  25. 根据权利要求24所述的阵列基板，其中，所述扫描线在所述第一衬底基板的正投影的图案包括沿所述第一方向延伸的、条形的第一图案，以及在所述第二方向上在所述第一图案一侧与所述第一图案连接的第二图案；
    所述第一图案在所述第一衬底基板的正投影与所述第二部分在所述第一衬底基板的正投影具有交叠，所述第二图案在所述第一衬底基板的正投影与所述第一部分在所述第一衬底基板的正投影具有交叠。
  26. 根据权利要求1～25任一项所述的阵列基板，其中，所述第一像素电极在第一衬底基板的正投影的形状为矩形；
    所述第一过孔在所述第一衬底基板的正投影靠近所述第一像素电极的边缘与所述第一像素电极在所述第一衬底基板的正投影的边缘之间的最小距离小于等于1.5微米。
  27. 根据权利要求26所述的阵列基板，其中，所述第一过孔在所述第一衬底基板的正投影靠近所述矩形的其中一个直角。
  28. 根据权利要求1～27任一项所述的阵列基板，其中，所述阵列基板的像素密度大于1000。
  29. 一种阵列基板的制备方法，其中，所述方法包括：
    在第一衬底基板上依次形成多个薄膜晶体管、第一平坦化层、公共电极的图案、第一介质层，并形成贯穿所述第一平坦化层和所述第一介质层的第 一过孔；
    在所述第一介质层背离所述公共电极层的一侧形成第一像素电极；其中，所述第一像素电极通过贯穿所述第一介质层以及所述第一平坦化层的第一过孔与所述薄膜晶体管一一对应电连接，所述第一像素电极背离所述第一衬底基板一侧的表面具有至少与所述第一过孔对应的第一凹槽；
    在所述第一凹槽背离所述第一衬底基板的一侧形成平坦部；所述平坦部远离所述第一衬底基板一侧的表面到所述第一衬底基板的距离与所述第一像素电极远离所述第一衬底基板一侧表面到所述第一衬底基板的距离大致相同。
  30. 一种液晶盒，其中，包括：
    根据权利要求1～28任一项所述的阵列基板；
    对向基板，与所述阵列基板相对设置；
    液晶层，位于所述阵列基板和所述对向基板之间。
  31. 一种显示装置，其中，包括根据权利要求30所述的液晶盒。
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Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5877832A (en) * 1996-03-15 1999-03-02 Sharp Kabushiki Kaisha Active matrix substrate, for use in a liquid crystal display and method for producing the same
JP2003149681A (ja) * 2002-07-18 2003-05-21 Seiko Epson Corp 液晶パネル用基板、液晶パネル及び投射型表示装置
US20040046912A1 (en) * 2002-08-09 2004-03-11 Nec Lcd Technologies, Ltd. Substrate for liquid-crystal display device and fabrication method thereof
CN101661176A (zh) * 2008-08-29 2010-03-03 精工爱普生株式会社 液晶装置及投影仪
CN102750024A (zh) * 2011-04-21 2012-10-24 乐金显示有限公司 用于嵌入式触摸传感器液晶显示装置的基板及其制造方法
KR20130053592A (ko) * 2011-11-15 2013-05-24 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 이의 제조 방법
JP2013186360A (ja) * 2012-03-09 2013-09-19 Jvc Kenwood Corp 反射型液晶素子
JP2013195807A (ja) * 2012-03-21 2013-09-30 Japan Display West Co Ltd 液晶表示装置、および、電子機器
KR20150074379A (ko) * 2013-12-24 2015-07-02 엘지디스플레이 주식회사 액정표시장치 및 그의 제조방법
CN104820324A (zh) * 2014-01-31 2015-08-05 Jsr株式会社 液晶显示元件及感放射线性树脂组合物
CN106684101A (zh) * 2017-02-15 2017-05-17 厦门天马微电子有限公司 阵列基板、显示面板及显示装置
US20190056620A1 (en) * 2017-08-18 2019-02-21 Japan Display Inc. Liquid crystal display device
CN109870855A (zh) * 2019-04-09 2019-06-11 京东方科技集团股份有限公司 一种阵列基板、液晶显示面板及液晶显示装置
CN110941123A (zh) * 2019-11-07 2020-03-31 深圳市华星光电半导体显示技术有限公司 Coa型阵列基板及其制造方法
CN111427207A (zh) * 2020-03-31 2020-07-17 厦门天马微电子有限公司 一种显示面板和显示装置
CN112782895A (zh) * 2021-01-27 2021-05-11 武汉华星光电技术有限公司 显示面板及液晶显示装置
CN112782896A (zh) * 2021-01-29 2021-05-11 合肥京东方光电科技有限公司 阵列基板及反射式的显示面板
CN113064304A (zh) * 2021-03-29 2021-07-02 京东方科技集团股份有限公司 液晶显示面板及其制作方法、液晶显示装置
CN114068590A (zh) * 2022-01-14 2022-02-18 京东方科技集团股份有限公司 阵列基板以及显示面板

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5877832A (en) * 1996-03-15 1999-03-02 Sharp Kabushiki Kaisha Active matrix substrate, for use in a liquid crystal display and method for producing the same
JP2003149681A (ja) * 2002-07-18 2003-05-21 Seiko Epson Corp 液晶パネル用基板、液晶パネル及び投射型表示装置
US20040046912A1 (en) * 2002-08-09 2004-03-11 Nec Lcd Technologies, Ltd. Substrate for liquid-crystal display device and fabrication method thereof
CN101661176A (zh) * 2008-08-29 2010-03-03 精工爱普生株式会社 液晶装置及投影仪
CN102750024A (zh) * 2011-04-21 2012-10-24 乐金显示有限公司 用于嵌入式触摸传感器液晶显示装置的基板及其制造方法
KR20130053592A (ko) * 2011-11-15 2013-05-24 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 이의 제조 방법
JP2013186360A (ja) * 2012-03-09 2013-09-19 Jvc Kenwood Corp 反射型液晶素子
JP2013195807A (ja) * 2012-03-21 2013-09-30 Japan Display West Co Ltd 液晶表示装置、および、電子機器
KR20150074379A (ko) * 2013-12-24 2015-07-02 엘지디스플레이 주식회사 액정표시장치 및 그의 제조방법
CN104820324A (zh) * 2014-01-31 2015-08-05 Jsr株式会社 液晶显示元件及感放射线性树脂组合物
CN106684101A (zh) * 2017-02-15 2017-05-17 厦门天马微电子有限公司 阵列基板、显示面板及显示装置
US20190056620A1 (en) * 2017-08-18 2019-02-21 Japan Display Inc. Liquid crystal display device
CN109870855A (zh) * 2019-04-09 2019-06-11 京东方科技集团股份有限公司 一种阵列基板、液晶显示面板及液晶显示装置
CN110941123A (zh) * 2019-11-07 2020-03-31 深圳市华星光电半导体显示技术有限公司 Coa型阵列基板及其制造方法
CN111427207A (zh) * 2020-03-31 2020-07-17 厦门天马微电子有限公司 一种显示面板和显示装置
CN112782895A (zh) * 2021-01-27 2021-05-11 武汉华星光电技术有限公司 显示面板及液晶显示装置
CN112782896A (zh) * 2021-01-29 2021-05-11 合肥京东方光电科技有限公司 阵列基板及反射式的显示面板
CN113064304A (zh) * 2021-03-29 2021-07-02 京东方科技集团股份有限公司 液晶显示面板及其制作方法、液晶显示装置
CN114068590A (zh) * 2022-01-14 2022-02-18 京东方科技集团股份有限公司 阵列基板以及显示面板

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