WO2024012250A1 - 逻辑控制电路、触发器及脉冲产生电路 - Google Patents

逻辑控制电路、触发器及脉冲产生电路 Download PDF

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Publication number
WO2024012250A1
WO2024012250A1 PCT/CN2023/104495 CN2023104495W WO2024012250A1 WO 2024012250 A1 WO2024012250 A1 WO 2024012250A1 CN 2023104495 W CN2023104495 W CN 2023104495W WO 2024012250 A1 WO2024012250 A1 WO 2024012250A1
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Prior art keywords
circuit
mos transistor
mos
output
clock signal
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PCT/CN2023/104495
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English (en)
French (fr)
Inventor
闫浩
赵安
王磊
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北京比特大陆科技有限公司
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Publication of WO2024012250A1 publication Critical patent/WO2024012250A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback

Definitions

  • the present application relates to the field of integrated circuit technology, and in particular to a logic control circuit, a flip-flop and a pulse generating circuit.
  • the output response signal has a long delay.
  • Increasing the size of the transmission gate or inverter in the circuit can effectively reduce the delay, but Increasing the transmission gate or inverter size will result in an increase in circuit power consumption, and in the case of low-voltage circuits, response delays will be more severe.
  • the main purpose of this application is to provide a variety of logic control circuits, flip-flops and pulse generation circuits, aiming to reduce the delay of the pulse signal output by the circuit.
  • this application provides a logic control circuit, which includes:
  • the first MOS tube, the second MOS tube, the third MOS tube and the output circuit the first end of the first MOS tube is connected to the power supply, and the second end of the first MOS tube is connected to the third end of the second MOS tube.
  • One end; the second end of the second MOS tube is connected to the first end of the third MOS tube, and the second end of the third MOS tube is grounded;
  • the second end of the first MOS tube is also used to connect the first end of the output circuit, the second end of the output circuit serves as the output end of the logic control circuit, and the second end of the output circuit It is also used to connect the control end of the first MOS tube to control the on-off of the first MOS tube through the pulse signal at the second end of the output circuit;
  • the control terminal of the second MOS tube is used to receive the first clock signal
  • the control terminal of the third MOS tube is used to receive the second clock signal.
  • the second clock signal has the same waveform as the first clock signal, And be delayed by a preset time period compared with the first clock signal;
  • the voltage signal at the second end of the first MOS transistor is high level; and when the level of the first clock signal is different from the level of the second clock signal , the second MOS tube or the third MOS tube is turned off, so that the second end of the first MOS tube remains at a high level;
  • both the second MOS transistor and the third MOS transistor are turned on. , to set the voltage at the second terminal of the first MOS transistor to a low level.
  • this application also provides another logic control circuit, which includes:
  • the first MOS tube, the second MOS tube, the third MOS tube and the output circuit the first end of the first MOS tube is used to connect to the power supply, and the second end of the first MOS tube is connected to the second MOS tube.
  • the first end of the second MOS tube is connected to the first end of the third MOS tube, and the second end of the third MOS tube is grounded;
  • the second end of the second MOS transistor is also connected to the first end of the output circuit.
  • the second end of the output circuit serves as the output end of the logic control circuit, and the second end of the output circuit is also connected to The control terminal of the third MOS tube controls the on-off of the third MOS tube with the pulse signal passing through the second terminal of the output circuit;
  • the first MOS transistor further includes a control end for receiving a first clock signal
  • the second MOS transistor further includes a control end for receiving a second clock signal
  • the second clock signal is the same as the first clock signal.
  • the signal waveforms are the same and delayed by a preset time length compared with the first clock signal;
  • both the first MOS transistor and the second MOS transistor are turned on. , to set the second end of the first MOS tube to a high level;
  • this application also provides a trigger, which includes:
  • this application also provides a pulse generating circuit, which includes:
  • a first delay inverter circuit One end of the first delay inverter circuit is used to receive the first clock signal, and the other end is connected to the control end of the third MOS transistor to generate the second clock signal.
  • the control terminal of the third MOS transistor is input to cause the second clock signal to be delayed by a first preset time period from the first clock signal.
  • this application also provides a pulse generating circuit, which includes:
  • a first delay inverter circuit one end of the delay inverter circuit is used to receive the first clock signal, and the other end is connected to the control end of the second MOS tube;
  • a second time delay inverting circuit the second time delay inverting circuit is connected between the second end of the second MOS transistor and the control end of the third MOS transistor; the second time delay inverting circuit The circuit is used to perform inversion processing and delay processing on the pulse signal at the second end of the second MOS tube, so that the pulse signal received by the control end of the third MOS tube is larger than the pulse signal at the second end of the second MOS tube.
  • the signal is delayed for a preset time.
  • this application also provides a pulse generating circuit, which includes:
  • a time delay inversion circuit one end of the time delay inversion circuit is used to receive the first clock signal, and the other end is connected to the control end of the second MOS tube;
  • a time delay circuit is connected between the second end of the second MOS transistor and the control end of the third MOS transistor; the time delay circuit is used to control the second time of the second MOS transistor.
  • the voltage signal output from the terminal is delayed for a predetermined period of time, so that the pulse signal received by the control terminal of the third MOS tube is delayed by a preset period of time compared with the pulse signal at the second terminal of the second MOS tube.
  • This application provides a logic control circuit, a trigger and a pulse generation signal.
  • This application uses multiple MOS tubes to work together to reduce the number of electronic components in the circuit to simplify the circuit design, and can reduce the number of electronic components under low-voltage working conditions. The delay of response signal.
  • Figure 1 is a schematic diagram of a logic control circuit provided by an embodiment of the present application.
  • Figure 2 is a schematic diagram of a clock signal of a logic control circuit provided by an embodiment of the present application
  • Figure 3 is a schematic diagram of a logic control circuit provided by another embodiment of the present application.
  • Figure 4 is a schematic diagram of a logic control circuit provided by an embodiment of the present application.
  • Figure 5 is a schematic diagram of a logic control circuit provided by another embodiment of the present application.
  • Figure 6 is a schematic diagram of a logic control circuit provided by another embodiment of the present application.
  • Figure 7 is a schematic diagram of a logic control circuit provided by yet another embodiment of the present application.
  • Figure 8 is a schematic diagram of a logic control circuit provided by another embodiment of the present application.
  • Figure 9 is a schematic diagram of a logic control circuit provided by yet another embodiment of the present application.
  • Figure 10 is a schematic diagram of a logic control circuit provided by yet another embodiment of the present application.
  • Figure 11 is a schematic diagram of a logic control circuit provided by an embodiment of the present application.
  • Figure 12 is a schematic diagram of a pulse generation circuit provided by an embodiment of the present application.
  • Figure 13 is a schematic diagram of a pulse generating circuit provided by another embodiment of the present application.
  • Figure 14 is a timing diagram corresponding to the embodiment of Figure 13;
  • Figure 15 is a pulse generating circuit provided by another embodiment of the present application.
  • M2 NAND gate; Q5, fifth MOS tube; M3, second inverter;
  • M4 inverter; Q6, sixth MOS tube; Q7, seventh MOS tube;
  • Q8 the eighth MOS tube; T1, the first delay inverting circuit; T2, the second delay inverting circuit;
  • T3 delay inversion circuit; T4, delay circuit; CLK, first clock signal;
  • some pulse generating circuits may include a D-type flip-flop, so that a clock signal is input into the D-type flip-flop, and the D-type flip-flop responds to the input clock signal to generate a corresponding pulse signal.
  • a clock signal is input into the D-type flip-flop
  • the D-type flip-flop responds to the input clock signal to generate a corresponding pulse signal.
  • the size or area of the logic gate electronic components in the D-type flip-flop is increased, it can be slowed down. There is a certain delay, but it also increases the power consumption of the circuit and is not convenient for the design of integrated circuits. Moreover, under low-voltage working conditions, the loss and delay in the circuit will be further highlighted.
  • this application proposes a logic control circuit, a flip-flop and a pulse generation circuit.
  • FIG. 1 is a schematic diagram of a logic control circuit provided by an embodiment of the present application.
  • the logic control circuit includes: a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3 and an output circuit 10.
  • the first end of the first MOS transistor Q1 is connected to the power supply
  • the second end of the first MOS transistor Q1 is connected to the first end of the second MOS transistor Q2
  • the second end of the second MOS transistor Q2 is connected to the first end of the third MOS transistor Q3.
  • terminal, the second terminal of the third MOS tube Q3 is grounded.
  • the second end of the first MOS transistor Q1 is also used to connect the first end of the output circuit 10.
  • the second end of the output circuit 10 serves as the output end of the logic control circuit, and the second end of the output circuit 10 is also used to connect the control end of the first MOS transistor Q1. It can be understood that the second end of the output circuit 10 will output a pulse signal, thereby The on and off of the first MOS transistor Q1 can be controlled by the pulse signal output at the second end of the output circuit 10 .
  • the pulse signal received by the first MOS transistor Q1 is called the CDN signal below. It can be understood that the CDN signal can be the same as the pulse signal output by the second terminal of the output circuit 10, or it can be output by the second terminal of the output circuit 10.
  • the pulse signal is preset processed to obtain the CDN signal.
  • the control end of the second MOS transistor Q2 is used to receive the first clock signal CLK
  • the control end of the third MOS transistor Q3 is used to receive the second clock signal CLKND, as shown in Figure 2, which is an embodiment of the present application.
  • a schematic diagram of a clock signal of a logic control circuit is provided. It can be understood that the second clock signal CLKND has the same waveform as the first clock signal CLK and is delayed by a preset time period from the first clock signal CLK.
  • the first clock signal CLK and the second clock signal CLKND exist in an in-phase state and an in-phase state.
  • the in-phase state is used to indicate that the level of the first clock signal CLK is the same as the level of the second clock signal CLKND, that is, the first clock signal CLK and the second clock signal CLKND are both high-level signals or low-level signals; the inverted state is used to indicate the level of the first clock signal CLK and the second clock signal
  • the level of CLKND is opposite. It can be understood that in each cycle, there are two in-phase states, and the duration of each in-phase state is a preset duration.
  • the first clock signal CLK and the second clock signal CLKND may be provided by a clock circuit connected to the logic control circuit.
  • the logic control circuit may be connected to the first clock circuit and the second clock signal CLKND.
  • the clock circuit is connected to receive the first clock signal CLK transmitted by the first clock circuit and the second clock signal CLKND transmitted by the second clock circuit; in other embodiments, the logic control circuit is connected to one clock circuit to receive the same clock signal CLK.
  • the clock signal delivered by the clock circuit is not limited to the clock circuit.
  • the first MOS transistor Q1 is a PMOS transistor
  • the second MOS transistor Q2 and the third MOS transistor Q3 are both NMOS transistors
  • the pulse signal output by the second end of the output circuit 10 is the same as the first MOS transistor Q1.
  • the voltage signal at the second end of the MOS tube Q1 is the same, and for the convenience of description, a data node DYN is introduced.
  • the data node DYN is located at the second end of the first MOS tube Q1 and is used to indicate the level signal at the second end of the first MOS tube Q1. .
  • the time when the data node DYN of the logic control circuit is low level can be used as the initial state. It can be understood that at this time, the pulse signal output by the second end of the output circuit 10 is a low level pulse signal. , and transmits the pulse signal to the control end of the first MOS transistor Q1, so that the first MOS transistor Q1 is turned on, so that the power supply connected to the first end of the first MOS transistor Q1 can be supplied to the first MOS transistor Q1 through the first MOS transistor Q1.
  • the second terminal of MOS transistor Q1 applies a voltage to set the data node DYN to a high level; and when the level of the first clock signal CLK and the level of the second clock signal CLKND are different, the second MOS transistor Q2 or the third The three MOS transistors Q3 are turned off so that the data node DYN can maintain a high level state.
  • the data node DYN of the logic control circuit is in a high-level state.
  • the pulse signal at the second end of the output circuit 10 is also a high-level signal and is transmitted to the control end of the first MOS transistor Q1, the first MOS transistor Q1 is turned off, the data node DYN is still in a high level state, but when the level of the first clock signal CLK and the level of the second clock signal CLKND are the same, the second MOS transistor Q2 and the third MOS transistor Q3 are both turned on, and the data Node DYN is asserted low.
  • the second and third MOS transistors Q3 are NMOS transistors and the first clock signal CLK is a low-level signal
  • the second clock signal CLKND is a high-level signal.
  • the second MOS transistor Q2 is turned off.
  • the third MOS transistor Q3 is turned on, and the data node DYN is still in a high level state.
  • the second MOS transistor Q2 and the third MOS transistor Q3 are both turned on, and the data node DYN can be regarded as grounded through the second MOS transistor Q2 and the third MOS transistor Q3, so that The data node DYN is set to a low level, causing the second terminal of the output circuit 10 to output a low-level pulse signal.
  • the first clock signal CLK and the second clock signal CLKND enter an inverted state, and the logic control The circuit changes to the initial state and repeats the steps of transmitting the low-level pulse signal to the control end of the first MOS transistor Q1, which will not be described here.
  • FIG. 3 is a schematic diagram of a logic control circuit provided by another embodiment of the present application.
  • the first MOS transistor Q1 is an NMOS transistor
  • the second MOS transistor Q2 and the third MOS transistor Q1 are NMOS transistors.
  • Tube Q3 is a PMOS tube.
  • the first MOS transistor Q1 is an NMOS transistor
  • the second terminal of the output circuit 10 outputs a low-level pulse signal and transmits it to the control end of the first MOS transistor Q1
  • the first MOS transistor Q1 will not be turned on, so the data node DYN cannot be set to high level. Therefore, it is necessary to invert the level of the data node DYN or to invert the pulse signal output from the second end of the output circuit 10 to ensure that the CDN signal received by the control end of the first MOS transistor Q1 is consistent with the data node The level signal of DYN is inverted.
  • the signal of the data node DYN is inverted, so that the pulse signal output by the second end of the output circuit 10 is inverted with the level signal of the data node DYN.
  • the pulse signal output by the second end of the output circuit 10 is a high level pulse signal, and the pulse signal is transmitted to the first MOS transistor Q1
  • the control end of the first MOS transistor Q1 is turned on, so that the power supply connected to the first end of the first MOS transistor Q1 can apply a voltage to the second end of the first MOS transistor Q1 through the first MOS transistor Q1, so as to turn on the first MOS transistor Q1.
  • the data node DYN is set to high level; and when the level of the first clock signal CLK and the level of the second clock signal CLKND are different, the second MOS transistor Q2 or the third MOS transistor Q3 is turned off, so that the data node DYN Able to maintain a high level state.
  • the data node DYN of the logic control circuit is in a high-level state, and the pulse signal of the output circuit 10 changes to a low-level signal and is transmitted to the control end of the first MOS transistor Q1.
  • the first MOS transistor Q1 is turned off.
  • the data node DYN is still in a high level state, but when the level of the first clock signal CLK and the level of the second clock signal CLKND are the same, both the second MOS transistor Q2 and the third MOS transistor Q3 are turned on, and the data node DYN is turned on. Set low.
  • the second and third MOS transistors Q3 are PMOS transistors, and the first clock signal CLK is a high-level signal.
  • the second clock signal CLKND is a low-level signal
  • the second MOS transistor Q2 is turned off
  • the third MOS transistor Q2 is turned off.
  • the tube Q3 is turned on, and the data node DYN is still at a high level.
  • the falling edge of the first clock signal CLK arrives and the first clock signal CLK is set to a low level signal, the first clock signal CLK and the second clock signal CLKND enter the same phase state.
  • the second MOS transistor Both Q2 and the third MOS transistor Q3 are turned on, and the data node DYN can be regarded as being grounded through the second MOS transistor Q2 and the third MOS transistor Q3, so that the data node DYN is set to a low level.
  • the logic control circuit changes to the initial state and repeats the steps of transmitting the high-level pulse signal to the control end of the first MOS transistor Q1. No more writing here.
  • Figure 4 is a schematic diagram of a logic control circuit provided by an embodiment of the present application.
  • the output circuit 10 includes a fourth MOS transistor Q4.
  • the control end of the fourth MOS transistor Q4 serves as the control end of the output circuit 10 and is used to receive the enable signal EN.
  • the fourth MOS transistor Q4 The first end of Q4 is connected to the power supply, and the second end of the fourth MOS transistor Q4 is connected to the second end of the first MOS transistor Q1.
  • the fourth MOS transistor Q4 can be connected to the same power supply as the first MOS transistor Q1.
  • the fourth MOS transistor Q4 is used to control the pulse signal output by the second end of the output circuit 10 according to the enable signal. It can be understood that when the enable signal EN is used to indicate signal output, the output circuit 10 can generate the pulse signal through the state of the data node DYN. corresponding pulse signal. When the enable signal is used to indicate no signal output, the fourth MOS transistor Q4 controls the second terminal of the output circuit 10 to output no pulse signal. At this time, the second and third MOS transistors Q3 can still receive the clock signal, but the output circuit 10 There is no pulse signal output at the second end.
  • the enable signal EN when the enable signal EN is a high-level signal, it indicates signal output; when the enable signal EN is a low-level signal, it indicates no signal output.
  • Figure 5 is a schematic diagram of a logic control circuit provided by another embodiment of the present application.
  • the output circuit 10 further includes a first inverter M1
  • the input terminal of the first inverter M1 is connected to the second terminal of the first MOS transistor Q1, and the output terminal of the first inverter M1 serves as the second terminal of the output circuit 10.
  • the first inverter M1 is provided in the output circuit 10, and the level signal of the data node DYN connected to the input end of the first inverter M1 can be inverted, so that the output circuit
  • the pulse signal output by the second terminal of 10 is inverted with the level signal of the data node DYN.
  • the control end of the first MOS tube Q1 needs to receive a low-level signal to turn on the first MOS tube Q1. If When the data node DYN is at a low level and the pulse signal output by the second terminal of the output circuit 10 is at a high level, the first MOS transistor Q1 is not conductive, the data node DYN remains at a low level, and the circuit cannot operate.
  • a stable pulse signal can be obtained after two inversion processes to avoid logic errors in the first MOS transistor Q1 or the data node DYN in the circuit.
  • the inversion processing of the pulse signal output by the second end of the output circuit 10 can be performed in a circuit connected to the logic control circuit, and an inverter or other device capable of inversion processing can be used, so that the third The pulse signal received by the control terminal of a MOS transistor Q1 is inverted with the pulse signal output by the second terminal of the output circuit 10 .
  • FIG. 6 is a schematic diagram of a logic control circuit provided by another embodiment of the present application.
  • the output circuit 10 further includes a first inverter M1 .
  • the input terminal of the inverter M1 is connected to the second terminal of the first MOS transistor Q1, and the output terminal of the first inverter M1 serves as the second terminal of the output circuit 10.
  • the control end of the first MOS tube Q1 needs to receive a high-level signal to enable the first MOS tube Q1 is turned on, if the data node DYN is low level, and the first inverter M1 in the output circuit 10 performs inversion processing, and a high-level pulse signal is output at the second end of the output circuit 10, the first MOS tube Q1 receives the high-level pulse signal and turns on, the data node DYN is set to high level, and the previous steps are repeated, which will not be described here.
  • FIG. 6 can be combined with the embodiment provided in FIG. 4 .
  • Figure 7 is a schematic diagram of a logic control circuit provided by yet another embodiment of the present application.
  • the first MOS transistor Q1 is an NMOS transistor
  • the second, third, and fourth MOS transistors Q4 are PMOS transistors.
  • the output circuit 10 further includes a NAND gate M2 and a first signal input end of the NAND gate M2.
  • the control end of the fourth MOS transistor Q4 is connected, the second signal input end of the NAND gate M2 is connected to the second end of the fourth MOS transistor Q4, and the output end of the NAND gate M2 serves as the second end of the output circuit 10 .
  • the second terminal of the output circuit 10 when the data node DYN or the enable signal EN is low level, the second terminal of the output circuit 10 outputs a high level pulse signal to turn on the first MOS transistor Q1 and set the data node DYN to high level. level.
  • the second terminal of the output circuit 10 outputs a low level pulse signal, so that the first MOS transistor Q1 is turned off and the data node DYN remains in a high level state.
  • the first MOS transistor Q1 is a PMOS transistor
  • the second, third, and fourth MOS transistors Q4 are NMOS transistors.
  • the output circuit 10 further includes a NAND gate M2, and a first signal input of the NAND gate M2. The terminal is connected to the control terminal of the fourth MOS transistor Q4, the second signal input terminal of the NAND gate M2 is connected to the second terminal of the fourth MOS transistor Q4, and the output terminal of the NAND gate M2 serves as the second terminal of the output circuit 10.
  • the second terminal of the output circuit 10 outputs a high-level pulse signal, and the pulse signal output by the second terminal of the output circuit 10 needs to be inverted. Only then can the first MOS transistor Q1 be turned on and the data node DYN be set to high level.
  • the second terminal of the output circuit 10 When the data node DYN or the enable signal is both high level, the second terminal of the output circuit 10 outputs a low level pulse signal, The first MOS transistor Q1 is turned off, and the data node DYN is still high level.
  • FIG. 8 is a schematic diagram of a logic control circuit provided by another embodiment of the present application.
  • the logic control circuit further includes a fifth MOS transistor Q5.
  • the control end of the fifth MOS transistor Q5 is connected to the output end of the first inverter M1.
  • the first end of the fifth MOS transistor Q5 is used to connect to the power supply.
  • the second terminal of the fifth MOS transistor Q5 is connected to the input terminal of the first inverter M1.
  • the signal in the logic control circuit can be kept stable.
  • the specific operation steps of the logic control circuit are the same as those provided in the previous embodiments and will not be described here.
  • Figure 9 is a schematic diagram of a logic control circuit provided by yet another embodiment of the present application.
  • the logic control circuit further includes: a second inverter M3, a sixth MOS transistor Q6, a seventh MOS transistor Q7 and an eighth MOS transistor Q8, wherein the sixth MOS transistor Q6 is a PMOS transistor, and the seventh MOS transistor Q6 is a PMOS transistor. .
  • the eighth MOS tube Q8 is an NMOS tube. The first end of the sixth MOS transistor Q6 is used to connect to the power supply, the second end of the sixth MOS transistor Q6 is connected to the first end of the seventh MOS transistor Q7; the second end of the seventh MOS transistor Q7 is connected to the eighth The first end of the MOS transistor Q8 and the second end of the eighth MOS transistor Q8 are grounded.
  • the control end of the sixth MOS transistor Q6 and the control end of the seventh MOS transistor Q7 are both connected to the output end of the second inverter M3, and the input end of the second inverter M3 is connected to the output circuit 10
  • the first end of the second inverter M3 is also connected to the second end of the sixth MOS transistor Q6; the control end of the eighth MOS transistor Q8 is connected to the control end of the first MOS transistor Q1 end.
  • the control terminal of the first MOS transistor Q1 When the control terminal of the first MOS transistor Q1 receives a low-level pulse signal, the first MOS transistor Q1 is turned on, the eighth MOS transistor Q8 is turned off, and the data node DYN is set to a high level; and through the second inverter M3 performs inversion processing and outputs a low-level signal at the output end of the second inverter M3, so that the sixth MOS transistor Q6 is turned on, the seventh MOS transistor Q7 is turned off, and the second terminal of the sixth MOS transistor Q6 is set. is a high level, that is, the data can be latched in the second terminal of the sixth MOS transistor Q6.
  • the second terminal of the sixth MOS transistor Q6 is also set to a low level.
  • the sixth, seventh, and eighth MOS transistors Q8 can latch data and maintain signal stability.
  • FIG. 10 is a schematic diagram of a logic control circuit provided by yet another embodiment of the present application.
  • the logic control circuit includes: a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3 and an output circuit 10; the first end of the first MOS transistor Q1 is used to connect the power supply, and the first MOS transistor Q1
  • the second end of the tube Q1 is connected to the first end of the second MOS tube Q2; the second end of the second MOS tube Q2 is connected to the first end of the third MOS tube Q3, and the second end of the third MOS tube Q3 is connected to ground;
  • the second end of the second MOS transistor Q2 is also connected to the first end of the output circuit 10.
  • the second end of the output circuit 10 serves as the output end of the logic control circuit, and the second end of the output circuit 10 is also connected to the third MOS transistor Q3.
  • the control terminal controls the on and off of the third MOS transistor Q3 with the pulse signal passing through the second terminal of the output circuit 10;
  • the first MOS transistor Q1 also includes a control end for receiving the first clock signal CLK.
  • the second MOS transistor Q2 also includes a control end for receiving the second clock signal CLKND.
  • CLKND has the same waveform as the first clock signal CLK, and is delayed by a preset time period from the first clock signal CLK;
  • both the first MOS transistor Q1 and the second MOS transistor Q2 are turned on to set the second end of the first MOS transistor Q1 to a high level; when the level of the first clock signal CLK is the same as that of the second When the levels of the clock signal CLKND are different, the The first MOS transistor Q1 or the second MOS transistor Q2 is turned off; and when the third MOS transistor Q3 is turned on, the second terminal of the first MOS transistor Q1 is set to a low level.
  • the second end of the second MOS transistor Q2 serves as the data node DYN, and when the data node DYN is low level, the first MOS transistor Q1 and the second MOS transistor Q2 need to be turned on at the same time to set the data node DYN to high level.
  • the control terminal of the first MOS transistor Q1 receives the first clock signal CLK
  • the control terminal of the second MOS transistor Q2 receives the second clock signal CLKND, where the first clock signal CLK and the second clock signal CLKND are in the same phase state. and the inverted state.
  • the in-phase state is used to indicate that the level of the first clock signal CLK is the same as the level of the second clock signal CLKND, that is, the first clock signal CLK and the second clock signal CLKND are both high-level signals or low-level signals.
  • the flat signal; the inverted state is used to indicate that the level of the first clock signal CLK is opposite to the level of the second clock signal CLKND. It can be understood that in each cycle, there are two in-phase states, and the duration of each in-phase state is a preset duration.
  • the data node DYN can be set to a low level.
  • the first and second MOS transistors Q2 are PMOS transistors
  • the third MOS transistor Q3 is an NMOS transistor.
  • the third MOS transistor Q3 When the control terminal of the third MOS transistor Q3 receives a high-level pulse signal, the third MOS transistor Q3 is controlled to be turned on to set the data node DYN to a low level, and at the next falling edge of the first clock signal CLK Once there, repeat the steps above. It can be understood that the data node DYN is connected to the first end of the output circuit 10, and the second end of the output circuit 10 is connected to the control end of the third MOS transistor Q3. The pulse signal at the output end of the output circuit 10 can control the third MOS transistor Q3.
  • the pulse signal at the output end of the output circuit 10 can be delayed, so that after the second preset time period, the third MOS tube Q3 receives The pulse signal at the output end of the output circuit 10.
  • the first and second MOS transistors Q2 are NMOS transistors
  • the third MOS transistor Q3 is a PMOS transistor.
  • the third MOS transistor Q3 When the control terminal of the third MOS transistor Q3 receives a low-level pulse signal, the third MOS transistor Q3 is controlled to be turned on to set the data node DYN to a low level, and the next rising edge of the first clock signal CLK Once there, repeat the steps above. It can be understood that in this case, if the pulse signal output by the second terminal of the output circuit 10 is in the same phase as the level signal of the data node DYN, when the data node DYN is at a high level, the third MOS transistor Q3 receives a high level. The pulse signal is in the off state, so the data node DYN cannot be set to a low level.
  • the level signal of the data node DYN needs to be inverted, so that the level signal of the data node DYN is consistent with the first level signal.
  • the pulse signal received by the control terminal of the three-MOS transistor Q3 is inverted.
  • inversion processing can be performed in the output circuit 10 , or electronic components for inversion processing, such as an inverter, can be connected between the control terminal of the third MOS transistor Q3 and the second terminal of the output circuit 10 .
  • Figure 11 is a schematic diagram of a logic control circuit provided by an embodiment of the present application.
  • the output circuit 10 includes an inverter M4.
  • the input terminal of the inverter M4 is connected to the second terminal of the second MOS transistor Q2.
  • the output terminal of the inverter M4 serves as the second terminal of the output circuit 10.
  • the second end of the output circuit 10 is connected to the control end of the third MOS transistor Q3 so that at the data node DYN
  • the output terminal of the output circuit 10 outputs a low-level pulse signal, and transmits the low-level pulse signal to the control of the third MOS transistor Q3 terminal, so that the third MOS transistor Q3 is turned on, thereby setting the data node DYN to a low level.
  • the first and second MOS transistors Q2 are PMOS transistors and the third MOS transistor Q3 is an NMOS transistor
  • the second terminal of the output circuit 10 outputs a low level pulse signal, so it is necessary to The pulse signal needs to be inverted, and the processed pulse signal is transmitted to the control end of the third MOS transistor Q3, so that the third MOS transistor Q3 is turned on and the data node DYN is set to low level.
  • the present application also provides a flip-flop, wherein the flip-flop includes a logic control circuit as provided in any of the foregoing embodiments.
  • the pulse generation circuit includes the logic control circuit provided in any of the embodiments corresponding to Figures 1 to 9.
  • the second MOS transistor Q2 and the third MOS transistor Q3 can be connected to the same clock circuit, and a first delay inversion circuit is also connected between the output end of the clock circuit and the control end of the third MOS transistor Q3. T1.
  • the first delay inversion circuit T1 is used to generate the second clock signal CLKND according to the first clock signal CLK, so that the second clock signal CLKND is delayed by a first preset time length compared with the first clock signal CLK, and the first clock signal CLK is different from the first clock signal CLK.
  • the second clock signal CLKND has an in-phase time and an anti-phase time.
  • the second clock signal CLKND is transmitted to the control end of the third MOS transistor Q3 through the first delay inverter circuit T1 to control the on/off state of the third MOS transistor Q3.
  • the first delay inversion circuit T1 may include multiple buffers and inverters to perform delay processing and reverse processing on the first clock signal CLK to generate the second clock signal CLKND.
  • Figure 13 is a schematic diagram of a pulse generation circuit provided by another embodiment of the present application.
  • the first MOS transistor Q1 is a PMOS transistor
  • the second and third MOS transistors Q3 are NMOS transistors.
  • the pulse generation circuit also includes a second delay inverter circuit T2.
  • the input terminal of the second delay inverter circuit T2 is connected to the output terminal of the logic control circuit.
  • the inverter output terminal output1 of the second delay inverter circuit T2 is connected to the first The control terminal of MOS tube Q1 and the non-inverting output terminal output2 of the second delay inverter circuit T2 serve as the output terminal of the pulse generating circuit.
  • the signal output by the inverting output terminal output1 of the second time delay inverter circuit T2 is inverted with the signal received by the input terminal of the second time delay inverter circuit T2, and is passed through the first inverter of the logic control circuit.
  • the pulse signal output from the output terminal of M1 is subjected to time delay processing and inversion processing to delay the control terminal of the first MOS transistor Q1 from receiving the pulse signal output from the second terminal of the output circuit 10 . And ensure that the level signal of the data node DYN is in the same phase as the pulse signal received by the control terminal of the first MOS transistor Q1.
  • the first MOS transistor Q1 is an NMOS transistor
  • the second and third MOS transistors Q3 are PMOS transistors. Since the level signal of the data node DYN and the pulse signal received by the control end of the first MOS transistor Q1 Inversion, so there is no need to perform inversion processing in the pulse generation circuit, only delay processing is required, and the delay circuit is connected between the output terminal of the logic control circuit and the control terminal of the first MOS tube Q1 to control the output The pulse signal output from the second terminal of the circuit 10 undergoes time delay processing.
  • Figure 14 is a timing diagram corresponding to the embodiment of Figure 13. As shown in the figure, the passage of the second MOS transistor Q2 and the third MOS transistor Q3 can be controlled through the first clock signal CLK and the second clock signal CLKND. and the pulse signal passing through the second end of the output circuit 10 controls the on-off of the first MOS transistor Q1, so that the pulse generating circuit generates a periodically changing pulse signal.
  • FIG. 15 is a pulse generation circuit provided by another embodiment of the present application.
  • the pulse generation circuit includes the logic control circuit provided by any embodiment corresponding to FIG. 10-FIG. 11.
  • the pulse generating circuit includes a first delay inverter circuit and a second delay inverter circuit, One end of the first delay inverter circuit is used to receive the first clock signal CLK, and the other end is connected to the control end of the second MOS transistor Q2; the second delay inverter circuit is connected to the second MOS transistor Q2 between the second end of the second end of the output circuit 10 and the control end of the third MOS transistor Q3; the second delay inversion circuit is used to invert and delay the pulse signal at the second end of the output circuit 10, so that the third The pulse signal received by the control end of the MOS transistor Q3 is delayed by a predetermined time longer than the pulse signal at the second end of the second MOS transistor Q2.
  • the specific circuit operation steps are as in the previous embodiment and will not be described here.
  • the pulse generation circuit includes a time delay inverter circuit T3 and a time delay circuit. T4, where one end of the time delay inverter circuit T3 is used to receive the first clock signal CLK, and the other end is connected to the control end of the second MOS transistor Q2; the time delay circuit T4 is connected to the second end of the second MOS transistor Q2 and the second end of the second MOS transistor Q2. Between the control terminals of the three MOS tubes Q3; the delay circuit T4 is used to control the output circuit
  • the pulse signal output by the second terminal is delayed, so that the pulse signal received by the control terminal of the third MOS tube Q3 is delayed by a preset time longer than the pulse signal at the second terminal of the second MOS tube Q2.
  • the specific circuit operation steps are as described above. For example, I will not write about it here.

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Abstract

本申请提供一种逻辑控制电路，触发器及脉冲产生电路，逻辑控制电路包括：第一MOS管、第二MOS管、第三MOS管和输出电路；第一MOS管的第一端连接电源，第一MOS管的第二端连接第二MOS管的第一端；第二MOS管的第二端连接第三MOS管的第一端，第三MOS管的第二端接地；第一MOS管的第二端还用于连接输出电路的第一端，输出电路的第二端作为逻辑控制电路的输出端，且输出电路的第二端还用于连接第一MOS管的控制端；第二MOS管的控制端用于接收第一时钟信号，第三MOS管的控制端用于接收第二时钟信号，第二时钟信号与第一时钟信号波形相同，且比第一时钟信号延迟预设时长。本申请简化了电路的设计，以降低能耗，以及能够减少从接收到时钟信号到生成脉冲信号的时延。

Description

逻辑控制电路、触发器及脉冲产生电路
本申请要求于2022年7月15日提交中国专利局、申请号为202210833730.4、发明名称为“逻辑控制电路、触发器及脉冲产生电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，尤其涉及一种逻辑控制电路、触发器及脉冲产生电路。
背景技术
目前在集成电路技术领域中，触发器所在的电路在实现高速脉冲或过窄脉冲时，输出的响应信号时延较长，增加电路中的传输门或反相器尺寸能够有效减少时延，但增加传输门或反相器尺寸会导致电路功耗的增加，以在低压电路的情况中，响应的时延会更为严重。
发明内容
本申请的主要目的在于提供一种种逻辑控制电路、触发器及脉冲产生电路，旨在减少电路输出的脉冲信号的时延。
第一方面，本申请提供一种逻辑控制电路，所述逻辑控制电路包括：
第一MOS管、第二MOS管、第三MOS管和输出电路；所述第一MOS管的第一端连接电源，所述第一MOS管的第二端连接所述第二MOS管的第一端；所述第二MOS管的第二端连接所述第三MOS管的第一端，所述第三MOS管的第二端接地；
所述第一MOS管的第二端还用于连接所述输出电路的第一端，所述输出电路的第二端作为所述逻辑控制电路的输出端，且所述输出电路的第二端还用于连接所述第一MOS管的控制端，以通过所述输出电路第二端的脉冲信号控制所述第一MOS管的通断；
所述第二MOS管的控制端用于接收第一时钟信号，所述第三MOS管的控制端用于接收第二时钟信号，所述第二时钟信号与所述第一时钟信号波形相同，且比所述第一时钟信号延迟预设时长；
所述第一MOS管导通时，所述第一MOS管第二端的电压信号为高电平；且当所述第一时钟信号的电平与所述第二时钟信号的电平不相同时，所述第二MOS管或所述第三MOS管关断，以使所述第一MOS管第二端保持高电平；
所述第一MOS管关断时，且当所述第一时钟信号的电平与所述第二时钟信号的电平相同时，所述第二MOS管和所述第三MOS管均导通，以将所述第一MOS管第二端的电压置为低电平。
第二方面，本申请还提供另一种逻辑控制电路，所述逻辑控制电路包括：
第一MOS管，第二MOS管、第三MOS管和输出电路；所述第一MOS管的第一端用于连接电源，所述第一MOS管的第二端连接所述第二MOS管的第一端；所述第二MOS管的第二端连接所述第三MOS管的第一端，所述第三MOS管的第二端接地；
所述第二MOS管的第二端还连接所述输出电路的第一端，所述输出电路的第二端作为所述逻辑控制电路的输出端，且所述输出电路的第二端还连接所述第三MOS管的控制端，以通过所述输出电路的第二端的脉冲信号控制所述第三MOS管的通断；
所述第一MOS管还包括用于接收第一时钟信号的控制端，所述第二MOS管还包括用于接收第二时钟信号的控制端，所述第二时钟信号与所述第一时钟信号波形相同，且比所述第一时钟信号延迟预设时长；
当所述第三MOS管关断，且当所述第一时钟信号的电平与所述第二时钟信号的电平相同时，所述第一MOS管和所述第二MOS管均导通，以将所述第一MOS管第二端置为高电平；
当所述第一时钟信号的电平与所述第二时钟信号的电平不相同时，所述第一MOS管或所述第二MOS管关断；且当所述第三MOS管导通时，将所述第一MOS管第二端置为低电平。第三方面，本申请还提供一种触发器，所述触发器包括：
如上述第一方面所述的逻辑控制电路；或者上述第二方面所述的逻辑控制电路。
第四方面，本申请还提供一种脉冲产生电路，所述脉冲产生电路包括：
如上述第一方面所述所述的逻辑控制电路；
第一时延反相电路，所述第一时延反相电路的一端用于接收所述第一时钟信号，另一端连接所述第三MOS管的控制端，以将生成的第二时钟信号输入所述第三MOS管的控制端，以使所述第二时钟信号比所述第一时钟信号延迟第一预设时长。
第五方面，本申请还提供一种脉冲产生电路，所述脉冲产生电路包括：
如上述第二方面所述的逻辑控制电路；
第一时延反相电路，所述时延反相电路的一端用于接收所述第一时钟信号，另一端连接所述第二MOS管的控制端；
第二时延反相电路，所述第二时延反相电路连接于所述第二MOS管的第二端和所述第三MOS管的控制端之间；所述第二时延反相电路用于对所述第二MOS管第二端的脉冲信号进行反相处理和时延处理，以使所述第三MOS管的控制端接收的脉冲信号比所述第二MOS管第二端的脉冲信号延迟预设时长。
第六方面，本申请还提供一种脉冲产生电路，所述脉冲产生电路包括：
如上述第二方面所述的逻辑控制电路；
时延反相电路，所述时延反相电路的一端用于接收所述第一时钟信号，另一端连接所述第二MOS管的控制端；
时延电路，所述时延电路连接于所述第二MOS管的第二端和所述第三MOS管的控制端之间；所述时延电路用于对所述第二MOS管第二端输出的电压信号进行时延处理，以使所述第三MOS管的控制端接收的脉冲信号比所述第二MOS管第二端的脉冲信号延迟预设时长。
本申请提供一种逻辑控制电路、触发器及脉冲产生信号，本申请通过多个MOS管相互配合工作，减少电路中电子元器件的数量以简化电路设计，以及能够在低电压的工作情况下减少响应信号的时延。
附图说明
为了更清楚地说明本申请实施例技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施例提供的一种逻辑控制电路的示意图；
图2为本申请一实施例提供的一种逻辑控制电路的时钟信号的示意图；
图3为本申请另一实施例提供的一种逻辑控制电路的示意图；
图4为本申请一实施例提供的一种逻辑控制电路的示意图；
图5为本申请另一实施例提供的一种逻辑控制电路的示意图；
图6为本申请另一实施例提供的一种逻辑控制电路的示意图；
图7为本申请又一实施例提供的一种逻辑控制电路的示意图；
图8为本申请另一实施例提供的一种逻辑控制电路的示意图；
图9为本申请又一实施例提供的一种逻辑控制电路的示意图；
图10为本申请再一实施例提供的一种逻辑控制电路的示意图；
图11为本申请一实施例提供的一种逻辑控制电路的示意图；
图12为本申请一实施例提供的一种脉冲产生电路的示意图；
图13为本申请另一实施例提供的一种脉冲产生电路的示意图；
图14为图13实施例对应的时序图；
图15为本申请另一实施例提供的一种脉冲产生电路。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
附图标记：
Q1、第一MOS管；Q2、第二MOS管；Q3、第三MOS管；
10、输出电路；Q4、第四MOS管；M1、第一反相器；
M2、与非门；Q5、第五MOS管；M3、第二反相器；
M4、反相器；Q6、第六MOS管；Q7、第七MOS管；
Q8、第八MOS管；T1、第一时延反相电路；T2、第二时延反相电路；
T3、时延反相电路；T4、时延电路；CLK、第一时钟信号；
CLKND、第二时钟信号。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
附图中所示的流程图仅是示例说明，不是必须包括所有的内容和操作/步骤，也不是必须按所描述的顺序执行。例如，有的操作/步骤还可以分解、组合或部分合并，因此实际执行的顺序有可能根据实际情况改变。
下面结合附图，对本申请的一些实施方式作详细说明。在不冲突的情况下，下述的实施例及实施例中的特征可以相互组合。
在现有技术中，一些脉冲产生电路中可能会包括D型触发器，以通过将时钟信号输入至D型触发器中，并通过D型触发器响应于输入的时钟信号，生成对应的脉冲信号以进行输出，但由于D型触发器中逻辑门电子元件较多，生成响应时钟信号的脉冲信号会存在一定的时延，若增加D型触发器中逻辑门电子元件的尺寸或面积，能够减缓一定的时延，但同样也增加了电路的功耗，且不便于集成电路的设计，并且，在低电压的工作情况下，电路中的损耗和时延会进一步凸显。
为了简化电路的设计，以及能够适用于低电压的工作环境，本申请提出了一种逻辑控制电路、触发器以及脉冲产生电路。
请参照图1，图1为本申请一实施例提供的一种逻辑控制电路的示意图。
如图1所示，该逻辑控制电路包括：第一MOS管Q1，第二MOS管Q2，第三MOS管Q3和输出电路10。第一MOS管Q1的第一端连接电源，第一MOS管Q1的第二端连接第二MOS管Q2的第一端；第二MOS管Q2的第二端连接第三MOS管Q3的第一端，第三MOS管Q3的第二端接地。
第一MOS管Q1的第二端还用于连接输出电路10的第一端，输出电路
10的第二端作为逻辑控制电路的输出端，且输出电路10的第二端还用于连接第一MOS管Q1的控制端，可以理解的，输出电路10第二端会输出脉冲信号，从而能够通过在输出电路10第二端输出的脉冲信号控制第一MOS管Q1的通断。为表述方便，下文将第一MOS管Q1接收到的脉冲信号称为CDN信号，可以理解的，CDN信号可以与输出电路10第二端输出的脉冲信号相同，或对输出电路10第二端输出的脉冲信号进行预设处理，得到CDN信号。 其中，第二MOS管Q2的控制端用于接收第一时钟信号CLK，第三MOS管Q3的控制端用于接收第二时钟信号CLKND，如图2所示，图2为本申请一实施例提供的一种逻辑控制电路的时钟信号的示意图，可以理解的，第二时钟信号CLKND与第一时钟信号CLK波形相同，且比第一时钟信号CLK延迟预设时长。
其中，第一时钟信号CLK与第二时钟信号CLKND存在同相状态和反相状态，同相状态用于指示第一时钟信号CLK的电平与第二时钟信号CLKND的电平相同，即第一时钟信号CLK与第二时钟信号CLKND均为高电平信号或低电平信号；反相状态用于指示第一时钟信号CLK的电平与第二时钟信号
CLKND的电平相反。可以理解的，在每一个周期中，存在两次同相状态，且每一次同相状态持续的时长为预设时长。
示例性的，第一时钟信号CLK和第二时钟信号CLKND可以是与逻辑控制电路连接的时钟电路提供的，可以理解的，在一些实施方式中，逻辑控制电路可以与第一时钟电路以及第二时钟电路连接，以接收第一时钟电路传递的第一时钟信号CLK和接收第二时钟电路传递的第二时钟信号CLKND；在另一些实施方式中，逻辑控制电路连接一个时钟电路，以接收同一个时钟电路传递的时钟信号。
在一些实施例中，如图1所示，第一MOS管Q1为PMOS管，第二MOS管Q2、第三MOS管Q3均为NMOS管，输出电路10第二端输出的脉冲信号与第一MOS管Q1的第二端电压信号相同，且为描述方便，引入数据节点DYN，数据节点DYN位于第一MOS管Q1的第二端处，用于指示第一MOS管Q1第二端的电平信号。
可以理解的，在逻辑控制电路中，可以将逻辑控制电路的数据节点DYN为低电平时作为初始状态，可以理解的，此时刻输出电路10第二端输出的脉冲信号为低电平的脉冲信号，并将脉冲信号传递至第一MOS管Q1的控制端，以使第一MOS管Q1导通，从而与第一MOS管Q1的第一端连接的电源能够通过第一MOS管Q1向第一MOS管Q1的第二端施加电压，以将数据节点DYN置为高电平；并且当第一时钟信号CLK的电平和第二时钟信号CLKND的电平不相同时，第二MOS管Q2或第三MOS管Q3关断，以使数据节点DYN能够保持高电平状态。
此时，逻辑控制电路的数据节点DYN为高电平状态，当输出电路10第二端的脉冲信号也为高电平信号，并传递至第一MOS管Q1的控制端时，第一MOS管Q1关断，数据节点DYN仍处于高电平状态，但在第一时钟信号CLK的电平和第二时钟信号CLKND的电平相同时，第二MOS管Q2和第三MOS管Q3均导通，数据节点DYN被置为低电平。
具体的，当第二、第三MOS管Q3为NMOS管，且第一时钟信号CLK为低电平信号时，第二时钟信号CLKND为高电平信号，此时第二MOS管Q2关断，第三MOS管Q3导通，数据节点DYN仍处于高电平状态。当第一时钟信号CLK的上升沿到达，并将第一时钟信号CLK置为高电平信号后，由于第二时钟信号CLKND比第一时钟信号CLK延迟预设时长，第一时钟信号CLK和第二时钟信号CLKND进入同相状态，在该状态下，第二MOS管Q2和第三MOS管Q3均导通，数据节点DYN可视为通过第二MOS管Q2和第三MOS管Q3接地，以使数据节点DYN置为低电平，从而导致输出电路10的第二端输出低电平的脉冲信号，经过预设时长后，第一时钟信号CLK与第二时钟信号CLKND进入反相状态，逻辑控制电路变为初始状态并重复将低电平的脉冲信号传递至第一MOS管Q1的控制端的步骤，在此不再撰述。可以理解的，通过周期性的时钟信号控制第二、第三MOS管Q3的通断以及控制第一MOS管Q1的通断状态，能够控制逻辑控制电路中的数据节点DYN的电平状态，从而在输出电路10的第二端中输出相应的脉冲信号，以达到产生脉冲信号的目的。
请参阅图3，图3为本申请另一实施例提供的一种逻辑控制电路的示意图。
在另一些实施例中，如图3所示，第一MOS管Q1为NMOS管，第二MOS管Q2、第三MOS 管Q3均为PMOS管。
示例性的，由于第一MOS管Q1为NMOS管，当数据节点DYN处于低电平时，若输出电路10的第二端输出低电平的脉冲信号，并传递至第一MOS管Q1的控制端，第一MOS管Q1并不会导通，从而无法将数据节点DYN置为高电平。因此，需要对数据节点DYN的电平进行进行反相处理或对输出电路10第二端输出的脉冲信号进行反相处理，以保证第一MOS管Q1的控制端接收到的CDN信号与数据节点DYN的电平信号反相。
可以认为在输出电路10中，对数据节点DYN的信号进行反相处理，以使输出电路10第二端输出的脉冲信号与数据节点DYN的电平信号反相。
同样的，将逻辑控制电路的数据节点DYN为低电平时作为初始状态，此时刻输出电路10第二端输出的脉冲信号为高电平的脉冲信号，并将脉冲信号传递至第一MOS管Q1的控制端，以使第一MOS管Q1导通，从而与第一MOS管Q1的第一端连接的电源能够通过第一MOS管Q1向第一MOS管Q1的第二端施加电压，以将数据节点DYN置为高电平；并且当第一时钟信号CLK的电平和第二时钟信号CLKND的电平不相同时，第二MOS管Q2或第三MOS管Q3关断，以使数据节点DYN能够保持高电平状态。
此时，逻辑控制电路的数据节点DYN为高电平状态，输出电路10的脉冲信号变为低电平信号，并传递至第一MOS管Q1的控制端时，第一MOS管Q1关断，数据节点DYN仍处于高电平状态，但在第一时钟信号CLK的电平和第二时钟信号CLKND的电平相同时，第二MOS管Q2和第三MOS管Q3均导通，数据节点DYN被置为低电平。
具体的，第二、第三MOS管Q3为PMOS管，且第一时钟信号CLK为高电平信号，第二时钟信号CLKND为低电平信号时，第二MOS管Q2关断，第三MOS管Q3导通，数据节点DYN仍处于高电平状态。当第一时钟信号CLK的下降沿到达，并将第一时钟信号CLK置为低电平信号后，第一时钟信号CLK和第二时钟信号CLKND进入同相状态，在该状态下，第二MOS管Q2和第三MOS管Q3均导通，数据节点DYN可视为通过第二MOS管Q2和第三MOS管Q3接地，以使数据节点DYN置为低电平。经过预设时长后，第一时钟信号CLK与第二时钟信号CLKND进入反相状态，逻辑控制电路变为初始状态并重复将高电平的脉冲信号传递至第一MOS管Q1的控制端的步骤，在此不再撰述。
请结合图1参阅图4，图4为本申请一实施例提供的一种逻辑控制电路的示意图。
在一些实施方式中，如图4所示，输出电路10包括第四MOS管Q4，第四MOS管Q4的控制端作为输出电路10的控制端，并用于接收使能信号EN，第四MOS管Q4的第一端连接电源，第四MOS管Q4的第二端连接第一MOS管Q1的第二端。
可以理解的，第四MOS管Q4可以与第一MOS管Q1连接同一电源。
第四MOS管Q4用于根据使能信号控制输出电路10第二端输出的脉冲信号，可以理解的，当使能信号EN用于指示信号输出时，输出电路10能够通过数据节点DYN的状态生成相应的脉冲信号。当使能信号用于指示无信号输出时，第四MOS管Q4控制输出电路10的第二端无脉冲信号输出，此时第二、第三MOS管Q3仍能接收时钟信号，但输出电路10的第二端无脉冲信号输出。
例如，当使能信号EN为高电平信号时，指示信号输出；当使能信号EN为低电平信号时，指示无信号输出。
请结合图1参阅图5，图5为本申请另一实施例提供的一种逻辑控制电路的示意图。
在一些实施方式中，如图5所示，当第一MOS管Q1为PMOS管、第二MOS管Q2、第三MOS管Q3为NMOS管时，输出电路10还包括第一反相器M1，第一反相器M1的输入端连接第一MOS管Q1的第二端，第一反相器M1的输出端作为输出电路10的第二端。
可以理解的，在输出电路10中设置第一反相器M1，可以对与第一反相器M1输入端连接的数据节点DYN的电平信号进行反相处理，以使输出电路
10的第二端输出的脉冲信号与数据节点DYN的电平信号反相。
当第一MOS管Q1为PMOS管、第二、第三MOS管Q3为NMOS管时，第一MOS管Q1的控制端需要在接收到低电平信号才能使第一MOS管Q1导通，若在数据节点DYN为低电平，且输出电路10的第二端输出的脉冲信号为高电平时，第一MOS管Q1不导通，数据节点DYN保持低电平状态，电路无法运作，因而，需要对输出电路10的第二端输出的脉冲信号进行反相处理，得到输出电路10的第二端输出的脉冲信号的反相信号，以对数据节点DYN的信号进行两次反相处理，从而保证第一MOS管Q1的控制端接收的信号与数据节点DYN的信号同相，以在数据节点DYN为低电平时，第一MOS管Q1能够导通并将数据节点DYN置为高电平，以及执行上述所撰述的步骤，在此不在重复撰述。
可以理解的，经过两次反相处理能够得到稳定的脉冲信号，以避免电路中的第一MOS管Q1或数据节点DYN中的逻辑错误。
可以理解的，对输出电路10的第二端输出的脉冲信号进行反相处理可以在与逻辑控制电路连接的电路中进行，可以利用反相器或其他能够进行反相处理的器件，以使第一MOS管Q1的控制端接收到的脉冲信号与输出电路10第二端输出的脉冲信号反相。
示例性的，图5所提供的的实施例可以与图4提供的实施例结合。
请结合图3参阅图6，图6为本申请另一实施例提供的一种逻辑控制电路的示意图。
在另一些实施方式中，如图6所示，当第一MOS管Q1为NMOS管，第二、第三MOS管Q3为PMOS管时，输出电路10还包括第一反相器M1，第一反相器M1的输入端连接第一MOS管Q1的第二端，第一反相器M1的输出端作为输出电路10的第二端。
可以理解的，当第一MOS管Q1为NMOS管，第二、第三MOS管Q3为PMOS管时，第一MOS管Q1的控制端需要在接收到高电平信号才能使第一MOS管Q1导通，若在数据节点DYN为低电平，且输出电路10中的第一反相器M1进行反相处理，在输出电路10第二端输出的高电平的脉冲信号，第一MOS管Q1接收到高电平的脉冲信号而导通，数据节点DYN置为高电平，以及重复前述步骤，在此不再撰述。
示例性的，图6所提供的实施例可以与图4提供的实施例结合。
请结合图4参阅图7，图7为本申请又一实施例提供的一种逻辑控制电路的示意图。
在一些实施方式中，第一MOS管Q1为NMOS管，第二、第三、第四MOS管Q4为PMOS管，输出电路10还包括与非门M2，与非门M2的第一信号输入端连接第四MOS管Q4的控制端，与非门M2的第二信号输入端连接第四MOS管Q4的第二端，与非门M2的输出端作为输出电路10的第二端。
可以理解的，当数据节点DYN或使能信号EN为低电平时，输出电路10的第二端输出高电平的脉冲信号，以使第一MOS管Q1导通，将数据节点DYN置为高电平。当数据节点DYN和使能信号EN均为高电平时，输出电路10的第二端输出低电平的脉冲信号，以使第一MOS管Q1关断，数据节点DYN保持高电平状态。
当第二MOS管Q2和第三MOS管Q3均导通时，数据节点DYN再次置为低电平。具体的电路运行步骤请参照图3对应的逻辑控制电路，在此不再撰述。
在另一些实施方式中，第一MOS管Q1为PMOS管，第二、第三、第四MOS管Q4为NMOS管，输出电路10还包括与非门M2，与非门M2的第一信号输入端连接第四MOS管Q4的控制端，与非门M2的第二信号输入端连接第四MOS管Q4的第二端，与非门M2的输出端作为输出电路10的第二端。
示例性的，当数据节点DYN或使能信号为低电平时，输出电路10的第二端输出高电平的脉冲信号，需要对输出电路10的第二端输出的脉冲信号进行反相处理，才能使第一MOS管Q1导通，并将数据节点DYN置为高电平。
当数据节点DYN或使能信号均为高电平时，输出电路10的第二端输出低电平的脉冲信号， 第一MOS管Q1关断，数据节点DYN仍为高电平。
当第二MOS管Q2和第三MOS管Q3均导通时，将数据节点DYN置为低电平。具体的电路运行步骤请参照图1对应的逻辑控制电路，在此不再撰述。
请结合图5参阅图8，图8为本申请另一实施例提供的一种逻辑控制电路的示意图。
在一些实施例中，逻辑控制电路还包括，第五MOS管Q5，第五MOS管Q5的控制端连接第一反相器M1的输出端，第五MOS管Q5的第一端用于连接电源，第五MOS管Q5的第二端连接第一反相器M1的输入端。
示例性的，通过接入第五MOS管Q5，能够保持逻辑控制电路中的信号稳定，具体的逻辑控制电路的运行步骤如前述实施例提供的运行步骤，在此不再撰述。
请结合图1参阅图9，图9为本申请又一实施例提供的一种逻辑控制电路的示意图。
在一些实施例中，逻辑控制电路还包括：第二反相器M3，第六MOS管Q6，第七MOS管Q7和第八MOS管Q8，其中，第六MOS管Q6为PMOS管，第七、第八MOS管Q8为NMOS管。第六MOS管Q6的第一端用于连接所述电源，第六MOS管Q6的第二端连接所述第七MOS管Q7的第一端；第七MOS管Q7的第二端连接第八MOS管Q8的第一端，第八MOS管Q8的第二端接地。
第六MOS管Q6的控制端和所述第七MOS管Q7的控制端均连接所述第二反相器M3的输出端，所述第二反相器M3的输入端连接所述输出电路10的第一端，所述第二反相器M3的输入端还连接所述第六MOS管Q6的第二端；所述第八MOS管Q8的控制端连接所述第一MOS管Q1的控制端。
可以理解的，当数据节点DYN为低电平时，通过第二反相器M3进行反相处理，并在第二反相器M3的输出端输出高电平信号，以控制第六MOS管Q6关断，第七MOS管Q7导通，以及当第一MOS管Q1的控制端接收高电平的脉冲信号时，第八MOS管Q8导通，第六MOS管Q6的第二端可视为接地，置为低电平。
当第一MOS管Q1的控制端接收低电平的脉冲信号时，第一MOS管Q1导通，第八MOS管Q8关断，数据节点DYN置为高电平；且通过第二反相器M3进行反相处理，在第二反相器M3输出端输出低电平的信号，以使第六MOS管Q6导通，第七MOS管Q7关断，第六MOS管Q6的第二端置为高电平，也即是能够将数据锁存在第六MOS管Q6的第二端中，当数据节点DYN置为低电平时，第六MOS管Q6的第二端也置为低电平，以完成数据清除的目的。可以理解的，通过第二反相器M3，第六、第七、第八MOS管Q8能够对数据进行锁存处理，以及保持信号的稳定。
请参阅图10，图10为本申请再一实施例提供的一种逻辑控制电路的示意图。
如图10所示，逻辑控制电路包括：第一MOS管Q1，第二MOS管Q2、第三MOS管Q3和输出电路10；第一MOS管Q1的第一端用于连接电源，第一MOS管Q1的第二端连接第二MOS管Q2的第一端；第二MOS管Q2的第二端连接第三MOS管Q3的第一端，第三MOS管Q3的第二端接地；
第二MOS管Q2的第二端还连接输出电路10的第一端，输出电路10的第二端作为逻辑控制电路的输出端，且输出电路10的第二端还连接第三MOS管Q3的控制端，以通过输出电路10的第二端的脉冲信号控制第三MOS管Q3的通断；
第一MOS管Q1还包括用于接收第一时钟信号CLK的控制端，第二MOS管Q2还包括用于接收第二时钟信号CLKND的控制端，第二时钟信号
CLKND与第一时钟信号CLK波形相同，且比第一时钟信号CLK延迟预设时长；
当第三MOS管Q3关断，且当第一时钟信号CLK的电平与第二时钟信号
CLKND的电平相同时，第一MOS管Q1和第二MOS管Q2均导通，以将第一MOS管Q1第二端置为高电平；当第一时钟信号CLK的电平与第二时钟信号CLKND的电平不相同时，第 一MOS管Q1或第二MOS管Q2关断；且当第三MOS管Q3导通时，将第一MOS管Q1第二端置为低电平。
示例性的，第二MOS管Q2的第二端作为数据节点DYN，且当数据节点DYN为低电平时，第一MOS管Q1和第二MOS管Q2需同时导通才能将数据节点DYN置为高电平。
示例性的，第一MOS管Q1的控制端接收第一时钟信号CLK，第二MOS管Q2的控制端接收第二时钟信号CLKND，其中，第一时钟信号CLK与第二时钟信号CLKND存在同相状态和反相状态，同相状态用于指示第一时钟信号CLK的电平与第二时钟信号CLKND的电平相同，即第一时钟信号CLK与第二时钟信号CLKND均为高电平信号或低电平信号；反相状态用于指示第一时钟信号CLK的电平与第二时钟信号CLKND的电平相反。可以理解的，在每一个周期中，存在两次同相状态，且每一次同相状态持续的时长为预设时长。
示例性的，在第三MOS管Q3导通时，可以将数据节点DYN置为低电平。
在一些实施方式中，第一、第二MOS管Q2为PMOS管，第三MOS管Q3为NMOS管，当数据节点DYN为低电平，且当第一时钟信号CLK的下降沿到达，并将第一时钟信号CLK置为低电平信号时，第一时钟信号CLK与第二时钟信号CLKND处于同相状态，第一MOS管Q1和第二MOS管Q2均导通，将数据节点DYN置为高电平；在经过预设时长后，第一时钟信号CLK与第二时钟信号CLKND处于反相状态，第一MOS管Q1或第二MOS管Q2关断，数据节点DYN仍为高电平。
当第三MOS管Q3的控制端接收到高电平的脉冲信号，控制第三MOS管Q3导通，以将数据节点DYN置为低电平，并在第一时钟信号CLK的下一次下降沿到达后，重复上述步骤。可以理解的，数据节点DYN与输出电路10的第一端连接，且输出电路10的第二端与第三MOS管Q3的控制端连接，输出电路10输出端的脉冲信号能够控制第三MOS管Q3的通断，因而，为了避免数据节点DYN电平变化的频率过快，可以对输出电路10输出端的脉冲信号进行时延处理，以在经过第二预设时长后，第三MOS管Q3接收到输出电路10输出端的脉冲信号。
在另一些实施方式中，第一、第二MOS管Q2为NMOS管，第三MOS管Q3为PMOS管，当数据节点DYN为低电平，且当第一时钟信号CLK的上升沿到达，并将第一时钟信号CLK置为高电平信号时，第一时钟信号CLK与第二时钟信号CLKND处于同相状态，第一MOS管Q1和第二MOS管Q2均导通，将数据节点DYN置为高电平；在经过预设时长后，第一时钟信号CLK与第二时钟信号CLKND处于反相状态，第一MOS管Q1或第二MOS管Q2关断，数据节点DYN仍为高电平。
当第三MOS管Q3的控制端接收到低电平的脉冲信号，控制第三MOS管Q3导通，以将数据节点DYN置为低电平，并在第一时钟信号CLK的下一次上升沿到达后，重复上述步骤。可以理解的，在该种情况下，若输出电路10第二端输出的脉冲信号与数据节点DYN的电平信号同相时，数据节点DYN在高电平时，第三MOS管Q3接收高电平的脉冲信号，而处于关断状态，从而无法将数据节点DYN置为低电平，因而，此时需要对数据节点DYN的电平信号进行反相处理，以使数据节点DYN的电平信号与第三MOS管Q3的控制端接收到的脉冲信号反相。例如，可以在输出电路10中进行反相处理，或在第三MOS管Q3的控制端与输出电路10的第二端之间连接用于反相处理的电子元器件，如反相器。
请结合图10参阅图11，图11为本申请一实施例提供的一种逻辑控制电路的示意图。输出电路10包括：反相器M4，反相器M4的输入端连接第二MOS管Q2的第二端，反相器M4的输出端作为输出电路10的第二端。
可以理解的，当第一、第二MOS管Q2为NMOS管，第三MOS管Q3为PMOS管时，输出电路10的第二端与第三MOS管Q3的控制端连接，以在数据节点DYN为高电平时，输出电路10输出端输出低电平的脉冲信号，并将低电平的脉冲信号传递至第三MOS管Q3的控制 端，以使第三MOS管Q3导通，从而将数据节点DYN置为低电平，其余步骤如前述实施例提供的步骤，在此不再撰述。
当第一、第二MOS管Q2为PMOS管，第三MOS管Q3为NMOS管时，若数据节点DYN为高电平，输出电路10的第二端输出低电平的脉冲信号，因而需要对脉冲信号需要进行反相处理，并将处理后的脉冲信号传递至第三MOS管Q3的控制端中，以使第三MOS管Q3导通，并将数据节点DYN置为低电平，其余步骤如前述实施例所提供的的步骤，在此不再撰述。
本申请还提供一种触发器，其中，触发器包括如前述任一实施例提供的逻辑控制电路。
请结合图1参阅图12，本申请还提供了一种脉冲产生电路，脉冲产生电路包括如图1-图9对应的任一实施例提供的逻辑控制电路。
具体的，第二MOS管Q2和第三MOS管Q3可以连接同一个时钟电路，且在时钟电路的输出端和第三MOS管Q3的控制端之间，还连接有第一时延反相电路T1。第一时延反相电路T1用于根据第一时钟信号CLK生成第二时钟信号CLKND，以使第二时钟信号CLKND比第一时钟信号CLK延迟第一预设时长，并且第一时钟信号CLK与第二时钟信号CLKND存在同相的时间和反相的时间。通过第一时延反相电路T1将第二时钟信号CLKND传递至第三MOS管Q3的控制端中，以控制第三MOS管Q3的通断。
示例性的，第一时延反相电路T1可以包括多个缓冲器以及反相器，以将第一时钟信号CLK进行时延处理和反向处理，生成第二时钟信号CLKND。
请结合图12参阅图13，图13为本申请另一实施例提供的一种脉冲产生电路的示意图。该脉冲产生电路中，第一MOS管Q1为PMOS管，第二、第三MOS管Q3为NMOS管。脉冲产生电路还包括第二时延反相电路T2，第二时延反相电路T2的输入端连接逻辑控制电路的输出端，第二时延反相电路T2的反相输出端output1连接第一MOS管Q1的控制端，第二时延反相电路T2的同相输出端output2作为脉冲产生电路的输出端。
可以理解的，第二时延反相电路T2的反相输出端output1输出的信号与第二时延反相电路T2的输入端接收的信号反相，通过对逻辑控制电路的第一反相器M1输出端输出的脉冲信号进行时延处理和反相处理，以延迟第一MOS管Q1的控制端接收输出电路10第二端输出的脉冲信号。并且确保数据节点DYN的电平信号与第一MOS管Q1的控制端接收到的脉冲信号同相。
在另一些实施方式中，第一MOS管Q1为NMOS管，第二、第三MOS管Q3为PMOS管，由于数据节点DYN的电平信号与第一MOS管Q1的控制端接收到的脉冲信号反相，因而不需在脉冲产生电路中进行反相处理，只需进行时延处理，将时延电路连接于逻辑控制电路的输出端和第一MOS管Q1的控制端之间，以对输出电路10第二端输出的脉冲信号进行时延处理。
请参阅图14，图14为图13实施例对应的时序图，如图所示，通过第一时钟信号CLK和第二时钟信号CLKND，能够控制第二MOS管Q2和第三MOS管Q3的通断，以及通过输出电路10第二端的脉冲信号，控制第一MOS管Q1的通断，以使脉冲产生电路产生周期性变化的脉冲信号。
请结合图10参阅图15，图15为本申请另一实施例提供的一种脉冲产生电路，脉冲产生电路包括如图10-图11对应的任一实施例提供的逻辑控制电路。
当第一、第二MOS管Q2为NMOS管，第三MOS管Q3为PMOS管时(图中未示出)，脉冲产生电路包括第一时延反相电路和第二时延反相电路，其中，第一时延反相电路的一端用于接收所述第一时钟信号CLK，另一端连接第二MOS管Q2的控制端；第二时延反相电路连接于所述第二MOS管Q2的第二端和所述第三MOS管Q3的控制端之间；所述第二时延反相电路用于对所述输出电路10的第二端的脉冲信号进行反相处理和时延处理，以使所述第三 MOS管Q3的控制端接收的脉冲信号比所述第二MOS管Q2第二端的脉冲信号延迟预设时长，具体电路运行步骤如前述实施例，在此不再撰述。
在另一些实施方式中，如图15所示，当第一、第二MOS管Q2为PMOS管，第三MOS管Q3为NMOS管时，脉冲产生电路包括时延反相电路T3和时延电路T4，其中，时延反相电路T3的一端用于接收第一时钟信号CLK，另一端连接第二MOS管Q2的控制端；时延电路T4连接于第二MOS管Q2的第二端和第三MOS管Q3的控制端之间；时延电路T4用于对输出电路
10第二端输出的脉冲信号进行时延处理，以使第三MOS管Q3的控制端接收的脉冲信号比第二MOS管Q2第二端的脉冲信号延迟预设时长，具体电路运行步骤如前述实施例，在此不再撰述。
应当理解，在此本申请说明书中所使用的术语仅仅是出于描述特定实施例的目的而并不意在限制本申请。如在本申请说明书和所附权利要求书中所使用的那样，除非上下文清楚地指明其它情况，否则单数形式的“一”、“一个”及“该”意在包括复数形式。
还应当理解，在本申请说明书和所附权利要求书中使用的术语“和/或”是指相关联列出的项中的一个或多个的任何组合以及所有可能组合，并且包括这些组合。需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者系统不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者系统所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者系统中还存在另外的相同要素。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (16)

  1. 一种逻辑控制电路，其特征在于，包括：第一MOS管、第二MOS管、第三MOS管和输出电路；所述第一MOS管的第一端连接电源，所述第一MOS管的第二端连接所述第二MOS管的第一端；所述第二MOS管的第二端连接所述第三MOS管的第一端，所述第三MOS管的第二端接地；
    所述第一MOS管的第二端还用于连接所述输出电路的第一端，所述输出电路的第二端作为所述逻辑控制电路的输出端，且所述输出电路的第二端还用于连接所述第一MOS管的控制端，以通过所述输出电路第二端的脉冲信号控制所述第一MOS管的通断；
    所述第二MOS管的控制端用于接收第一时钟信号，所述第三MOS管的控制端用于接收第二时钟信号，所述第二时钟信号与所述第一时钟信号波形相同，且比所述第一时钟信号延迟预设时长；
    所述第一MOS管导通时，所述第一MOS管第二端为高电平；且当所述第一时钟信号的电平与所述第二时钟信号的电平不相同时，所述第二MOS管或所述第三MOS管关断，以使所述第一MOS管第二端保持高电平；
    所述第一MOS管关断时，且当所述第一时钟信号的电平与所述第二时钟信号的电平相同时，所述第二MOS管和所述第三MOS管均导通，以将所述第一MOS管第二端置为低电平。
  2. 如权利要求1所述的逻辑控制电路，其特征在于，所述输出电路包括：第四MOS管；所述第四MOS管的控制端作为所述输出电路的控制端，并用于接收使能信号，所述第四MOS管的第一端连接所述电源， 所述第四MOS管的第二端连接所述第一MOS管的第二端。
  3. 如权利要求1或2所述的逻辑控制电路，其特征在于，所述第一MOS管为NMOS管，所述第二、第三MOS管为PMOS管，所述输出电路还包括：第一反相器，所述第一反相器的输入端连接所述第一MOS管的第二端，所述第一反相器的输出端作为所述输出电路的第二端。
  4. 如权利要求2所述的逻辑控制电路，其特征在于，所述第一MOS管为NMOS管，所述第二、第三、第四MOS管为PMOS管，所述输出电路还包括：与非门，所述与非门的第一信号输入端连接所述第四MOS管的控制端，所述与非门的第二信号输入端连接所述第四MOS管的第二端，所述与非门的输出端作为所述输出电路的第二端。
  5. 如权利要求3所述的逻辑控制电路，其特征在于，所述逻辑控制电路还包括：第五MOS管，所述第五MOS管的控制端连接所述第一反相器的输出端，所述第五MOS管的第一端用于连接所述电源，所述第五MOS管的第二端连接所述第一反相器的输入端。
  6. 如权利要求1或2所述的逻辑控制电路，其特征在于，所述第一MOS管为PMOS管，所述第二、第三MOS管为NMOS管；所述输出电路还包括：第一反相器，所述第一反相器的输入端连接所述第一MOS管的第二端，所述第一反相器的输出端作为所述输出电路的第二端；所述输出电路的第二端还用于连接所述第一MOS管的控制端，以通过所述输出电路第二端的脉冲信号控制所述第一MOS管的通断，包括：所述第一MOS管的控制端接收所述输出电路第二端的脉冲信号的反相信号，以通过所述输出电路第二端脉冲信号的反相信号控制所述第 一MOS管的通断。
  7. 如权利要求6所述的逻辑控制电路，其特征在于，所述逻辑控制电路还包括：第二反相器，第六MOS管，第七MOS管和第八MOS管，其中，所述第六MOS管为PMOS管，所述第七、第八MOS管为NMOS管；所述第六MOS管的第一端用于连接所述电源，所述第六MOS管的第二端连接所述第七MOS管的第一端；所述第七MOS管的第二端连接所述第八MOS管的第一端，所述第八MOS管的第二端接地；
    所述第六MOS管的控制端和所述第七MOS管的控制端均连接所述第二反相器的输出端，所述第二反相器的输入端连接所述输出电路的第一端，所述第二反相器的输入端还连接所述第六MOS管的第二端；所述第八MOS管的控制端连接所述第一MOS管的控制端。
  8. 一种逻辑控制电路，其特征在于，包括：第一MOS管，第二MOS管、第三MOS管和输出电路；所述第一MOS管的第一端用于连接电源，所述第一MOS管的第二端连接所述第二MOS管的第一端；所述第二MOS管的第二端连接所述第三MOS管的第一端，所述第三MOS管的第二端接地；
    所述第二MOS管的第二端还连接所述输出电路的第一端，所述输出电路的第二端作为所述逻辑控制电路的输出端，且所述输出电路的第二端还连接所述第三MOS管的控制端，以通过所述输出电路的第二端的脉冲信号控制所述第三MOS管的通断；
    所述第一MOS管还包括用于接收第一时钟信号的控制端，所述第二MOS管还包括用于接收第二时钟信号的控制端，所述第二时钟信号与 所述第一时钟信号波形相同，且比所述第一时钟信号延迟预设时长；当所述第三MOS管关断，且当所述第一时钟信号的电平与所述第二时钟信号的电平相同时，所述第一MOS管和所述第二MOS管均导通，以将所述第一MOS管第二端置为高电平；
    当所述第一时钟信号的电平与所述第二时钟信号的电平不相同时，所述第一MOS管或所述第二MOS管关断；且当所述第三MOS管导通时，将所述第一MOS管第二端置为低电平。
  9. 如权利要求8所述的逻辑控制电路，其特征在于，所述第一、第二MOS管为NMOS管，所述第三MOS管为PMOS管；所述输出电路包括：
    反相器，所述反相器的输入端连接所述第二MOS管的第二端，所述反相器的输出端作为所述输出电路的第二端。
  10. 如权利要求8所述的逻辑控制电路，其特征在于，所述第一、第二MOS管为PMOS管，所述第三MOS管为NMOS管；所述输出电路包括：
    反相器，所述反相器的输入端连接所述第二MOS管的第二端，所述反相器的输出端作为所述输出电路的第二端；
    所述输出电路的第二端还连接所述第三MOS管的控制端，以通过所述输出电路第二端输出的脉冲信号控制所述第三MOS管的通断，包括：
    所述第三MOS管的控制端用于接收所述输出电路第二端脉冲信号的反相信号，以通过所述输出电路第二端脉冲信号的反相信号控制所述第三MOS管的通断。
  11. 一种触发器，其特征在于，包括：
    如权利要求1-7任一项所述的逻辑控制电路；或者 如权利要求8-10任一项所述的逻辑控制电路。
  12. 一种脉冲产生电路，其特征在于，所述脉冲产生电路包括：
    如权利要求1-5任一项所述的逻辑控制电路或如权利要求1-2、6-7任一项所述的逻辑控制电路；
    第一时延反相电路，所述第一时延反相电路的一端用于接收所述第一时钟信号，另一端连接所述第三MOS管的控制端，以将生成的第二时钟信号输入所述第三MOS管的控制端，以使所述第二时钟信号比所述第一时钟信号延迟第一预设时长。
  13. 如权利要求12所述的脉冲产生电路，其特征在于，当所述脉冲产生电路包括如权利要求1-5任一项所述的逻辑控制电路，所述脉冲产生电路还包括：时延电路，所述时延电路连接于所述逻辑控制电路的输出端和所述第一MOS管的控制端之间，所述时延电路的输出端还作为所述脉冲产生电路的输出端；所述时延电路用于对所述输出电路第二端的脉冲信号进行时延处理，以使所述第一MOS管的控制端接收的脉冲信号比所述输出电路第二端的脉冲信号延迟第二预设时长。
  14. 如权利要求12所述的脉冲产生电路，其特征在于，当所述脉冲产生电路包括如权利要求1-2、6-7任一项所述的逻辑控制电路，所述脉冲产生电路还包括：第二时延反相电路，所述第二时延反相电路的输入端连接所述逻辑控制电路的输出端，所述第二时延反相电路的反相输出端连接所述第一MOS管的控制端；所述第二时延反相电路的同相输出端作为所述脉冲产生电路的输出端；所述第二时延反相电路用于对所述输出电路第二端输出的脉冲信号进行时延处理和反相处理， 以使所述第一MOS管的控制端接收的脉冲信号比所述输出电路第二端的脉冲信号延迟第二预设时长。
  15. 一种脉冲产生电路，其特征在于，所述脉冲产生电路包括：
    如权利要求8或9所述的逻辑控制电路；
    第一时延反相电路，所述第一时延反相电路的一端用于接收所述第一时钟信号，另一端连接所述第二MOS管的控制端；
    第二时延反相电路，所述第二时延反相电路连接于所述输出电路的第二端和所述第三MOS管的控制端之间；所述第二时延反相电路用于对所述输出电路的第二端的脉冲信号进行反相处理和时延处理，以使所述第三MOS管的控制端接收的脉冲信号比所述第二MOS管第二端的脉冲信号延迟预设时长。
  16. 一种脉冲产生电路，其特征在于，所述脉冲产生电路包括：
    如权利要求8或10所述的逻辑控制电路；
    时延反相电路，所述时延反相电路的一端用于接收所述第一时钟信号，另一端连接所述第二MOS管的控制端；
    时延电路，所述时延电路连接于所述输出电路的第二端和所述第三MOS管的控制端之间；所述时延电路用于对所述输出电路第二端输出的脉冲信号进行时延处理，以使所述第三MOS管的控制端接收的脉冲信号比所述第二MOS管第二端的脉冲信号延迟预设时长。
PCT/CN2023/104495 2022-07-15 2023-06-30 逻辑控制电路、触发器及脉冲产生电路 WO2024012250A1 (zh)

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