WO2024000670A1 - 片式压敏电阻器及其制备方法和应用 - Google Patents

片式压敏电阻器及其制备方法和应用 Download PDF

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WO2024000670A1
WO2024000670A1 PCT/CN2022/105754 CN2022105754W WO2024000670A1 WO 2024000670 A1 WO2024000670 A1 WO 2024000670A1 CN 2022105754 W CN2022105754 W CN 2022105754W WO 2024000670 A1 WO2024000670 A1 WO 2024000670A1
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chip varistor
additive
solvent
crystal phase
porcelain
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PCT/CN2022/105754
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English (en)
French (fr)
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苏财能
刘季超
肖倩
林亚梅
陈樱琳
李耀坤
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深圳振华富电子有限公司
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Publication of WO2024000670A1 publication Critical patent/WO2024000670A1/zh

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    • C04B35/01—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics
    • C04B35/453—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on zinc, tin, or bismuth oxides or solid solutions thereof with other oxides, e.g. zincates, stannates or bismuthates
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H01C7/105—Varistor cores
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    • C04B2235/327—Iron group oxides, their mixed metal oxides, or oxide-forming salts thereof
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Definitions

  • the present application belongs to the technical field of resistors, and in particular relates to a chip varistor and its preparation method and application.
  • the size of the peak current parameter of the chip varistor determines the strength of the product's surge resistance.
  • the larger the parameter the stronger the product's surge resistance and the better the protection effect.
  • This parameter is mainly related to the porcelain material, product size (structural design) and production process. With the trend of miniaturization, only by further increasing the flow density of the porcelain material can the surge protection performance of the product be further improved to meet the requirements. Market demand.
  • this application provides a method for preparing a chip varistor, which includes the following steps:
  • the molar ratio of the additives is (1.0 ⁇ 2.0):(1.0 ⁇ 2.0):(0.4 ⁇ 0.8):(0.4 ⁇ 0.8):(0.4 ⁇ 0.8):(1.0 ⁇ 2.0):(0.8 ⁇ 1.6):(0.2 ⁇ 0.8):(0.01 ⁇ 0.05):(0.02 ⁇ 0.08) Bi2O3, Sb2O3, MnO2, Cr2O3, Co2O3, H3BO3, Zn3(PO4)2 ⁇ 4H2O, Nb2O5, AgNO3 and Al(NO3)3 ⁇ 9H2O;
  • this application provides a chip varistor.
  • the ceramic material of the chip varistor includes a main crystal phase material and an additive.
  • the additive includes a molar ratio of (1.0 ⁇ 2.0):( 1.0 ⁇ 2.0):(0.4 ⁇ 0.8):(0.4 ⁇ 0.8):(0.4 ⁇ 0.8):(1.0 ⁇ 2.0):(0.8 ⁇ 1.6):(0.2 ⁇ 0.8):(0.01 ⁇ 0.05):(0.02 ⁇ 0.08) of Bi2O3, Sb2O3, MnO2, Cr2O3, Co2O3, H3BO3, Zn3(PO4)2 ⁇ 4H2O, Nb2O5, AgNO3 and Al(NO3)3 ⁇ 9H2O.
  • the present application provides an electronic device, which includes the chip varistor prepared by the above method, or the above chip varistor.
  • the preparation method of the chip varistor provided in the first aspect of this application has a simple process, low energy consumption, low cost, and is suitable for industrial large-scale production and application.
  • the porcelain material used in the prepared chip varistor contains a unique formula of additives.
  • Bi2O3 is the main component of the high-resistance grain boundary skeleton structure of the varistor, which is the basis for the nonlinearity of the varistor.
  • Sb2O3 is the main additive component for the production of antimony-zinc spinel phase. Spinel is located at the intersection of grains of main crystalline phase materials such as ZnO, which is beneficial to promote the growth and uniform development of the main crystalline phase, and improve the breakdown voltage and endurance of the device.
  • H3BO3 and Zn3(PO4)2 ⁇ 4H2O have lower melting points.
  • the eutectic compound formed by the two has a significant melting effect, which can promote grain growth and reduce the sintering temperature.
  • the glass oxide formed easily combines with Bi2O3, Sb2O3 and interstitial Zn ions to produce a dense glass phase during the firing process, which reduces the concentration of grain boundary defects and improves the long-term stability of the resistor in an electric field environment.
  • Nb2O5 will segregate at the grain boundaries and form spinel phases such as Zn3Nb2O8 with the main crystal phase materials, which can prevent grain growth.
  • the spinel phase also increases the surface state density of the grain boundaries, so it can increase
  • the height of the grain boundary barrier improves the nonlinearity of the product.
  • the monovalent silver ions of AgNO3 can reduce and clamp the Fermi level. It is a grain boundary stabilizer that can inhibit the migration of interstitial ions, inhibit the diffusion of oxygen atoms, slow down the deterioration of varistor, and extend the service life of the device.
  • the added amount is too large, the leakage current will increase, the varistor voltage will decrease, and the overall performance will deteriorate.
  • Al(NO3)3 ⁇ 9H2O Due to the small ion radius of Al3+ (53.5pm), Al(NO3)3 ⁇ 9H2O easily enters the crystal lattice, which is beneficial to increasing the carrier concentration of the main crystal phase grains and reducing the grain resistance, making the V-I characteristic curve of the varistor move toward The large current area is shifted to reduce the voltage limiting ratio and improve the tolerance of lightning current and large current impact. However, excessive doping will cause the leakage current to increase and the varistor voltage to rise.
  • the electronic device provided in the third aspect of this application includes the above-mentioned chip varistor.
  • the chip varistor has non-linear, high current and voltage gradient through the synergistic effect of the main crystal phase material and the specially formulated additives. Adjustable and low-temperature sintering properties improve the stability of electronic devices.
  • Figure 1 is a schematic flow chart of a method for manufacturing a chip varistor provided by an embodiment of the present application
  • Figure 2 is an SEM image of the chip varistor provided in Embodiment 1 of the present application.
  • Figure 3 is an SEM image of the chip varistor provided in Embodiment 2 of the present application.
  • Figure 4 is an SEM image of the chip varistor provided in Embodiment 3 of the present application.
  • a and/or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. Condition. Where A and B can be singular or plural.
  • the character "/" generally indicates that the related objects are in an "or" relationship.
  • At least one refers to one or more
  • plural refers to two or more.
  • At least one of the following” or similar expressions thereof refers to any combination of these items, including any combination of a single item (items) or a plurality of items (items).
  • at least one of a, b, or c can mean: a, b, c, a-b (that is, a and b), a-c, b-c, or a-b-c, where a, b, and c may be single or multiple respectively.
  • the size of the sequence numbers of the above-mentioned processes does not mean the order of execution. Some or all steps can be executed in parallel or one after another. The execution order of each process should be based on its function and order. The internal logic is determined and should not constitute any limitation on the implementation process of the embodiments of the present application.
  • weights of relevant components mentioned in the description of the embodiments of the present application may not only refer to the specific content of each component, but also represent the proportional relationship of weight between the components. Therefore, as long as the relevant components are combined according to the description of the embodiments of the present application, Any scaling up or down of the content is within the scope disclosed in the examples of this application.
  • the mass in the description of the embodiments of this application may be mass units well known in the chemical industry such as ⁇ g, mg, g, kg, etc.
  • first and second are only used for descriptive purposes to distinguish objects such as substances from each other, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features.
  • first XX may also be called the second XX
  • second XX may also be called the first XX. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • the first aspect of the embodiments of the present application provides a method for preparing a chip varistor, which includes the following steps:
  • the preparation method of the chip varistor in the embodiment of the present application has a simple preparation process, low energy consumption, and low cost, and is suitable for industrial large-scale production and application.
  • the porcelain material used in the prepared chip varistor contains a unique formula of additives.
  • Bi2O3 is the main component of the high-resistance grain boundary skeleton structure of the varistor, which is the basis for the nonlinearity of the varistor.
  • Sb2O3 is the main additive component for the production of antimony-zinc spinel phase. Spinel is located at the intersection of grains of main crystalline phase materials such as ZnO, which is beneficial to promote the growth and uniform development of the main crystalline phase, and improve the breakdown voltage and endurance of the device.
  • H3BO3 and Zn3(PO4)2 ⁇ 4H2O have lower melting points.
  • the eutectic compound formed by the two has a significant melting effect, which can promote grain growth and reduce the sintering temperature.
  • the glass oxide formed easily combines with Bi2O3, Sb2O3 and interstitial Zn ions to produce a dense glass phase during the firing process, which reduces the concentration of grain boundary defects and improves the long-term stability of the resistor in an electric field environment.
  • Nb2O5 will segregate at the grain boundaries and form spinel phases such as Zn3Nb2O8 with the main crystal phase materials, which can prevent grain growth.
  • the spinel phase also increases the surface state density of the grain boundaries, so it can increase
  • the height of the grain boundary barrier improves the nonlinearity of the product.
  • grain boundary defects will increase due to hindering grain growth, which will lead to an increase in leakage current and a decrease in nonlinear coefficients.
  • the monovalent silver ions of AgNO3 can reduce and clamp the Fermi level. They are grain boundary stabilizers that can inhibit the migration of interstitial ions, inhibit the diffusion of oxygen atoms, slow down the deterioration of varistor, and extend the service life of the device.
  • the amount added is too large, the leakage current will increase, the varistor voltage will decrease, and the overall performance will deteriorate.
  • Al(NO3)3 ⁇ 9H2O Due to the small ion radius of Al3+ (53.5pm), Al(NO3)3 ⁇ 9H2O easily enters the crystal lattice, which is beneficial to increasing the carrier concentration of the main crystal phase grains and reducing the grain resistance, making the V-I characteristic curve of the varistor move toward The large current area is shifted to reduce the voltage limiting ratio and improve the tolerance of lightning current and large current impact. However, excessive doping will cause the leakage current to increase and the varistor voltage to rise.
  • the embodiments of this application prepare a chip varistor. Through the synergistic effect of the main crystalline phase material in the porcelain material and the specially formulated additives, on the one hand, the excellent nonlinear structure of the varistor is formed and the ability to withstand impulse current is improved.
  • the low melting point component in the additive can form a eutectic, which has a melting effect and is beneficial to lowering the sintering temperature to below 900°C, and ensuring that the varistor still has good performance at a lower sintering temperature. electrical properties and long-term stability.
  • the doping amount of each component of the additive in the porcelain material, or the ratio of the additive to the main crystal phase material it can meet the requirements of low-voltage, medium-voltage and high-voltage potential gradient applications respectively. demand, and simultaneously realize the production of different types of porcelain materials and chip varistors for low voltage, medium voltage and high voltage, solving the conventional problem of needing to prepare porcelain materials of different formulas for different potential gradient devices, greatly simplifying the production process , improve generation efficiency.
  • the step of preparing the additive includes: weighing the molar ratio as (1.0 ⁇ 2.0):(1.0 ⁇ 2.0):(0.4 ⁇ 0.8):(0.4 ⁇ 0.8):(0.4 ⁇ 0.8 ):(1.0 ⁇ 2.0):(0.8 ⁇ 1.6):(0.2 ⁇ 0.8):(0.01 ⁇ 0.05):(0.02 ⁇ 0.08) of Bi2O3, Sb2O3, MnO2, Cr2O3, Co2O3, H3BO3, Zn3(PO4)2 ⁇ After adding 4H2O, Nb2O5, AgNO3 and Al(NO3)3 ⁇ 9H2O, place the additive powder and 80-120% of the total mass of the powder in water, preferably deionized water, on a planetary ball mill for mixing and grinding. When the particle size reaches After predetermining the requirements, the material can be discharged to a special tray, and the additives can be obtained after drying.
  • the particle size D50 of the additive is not higher than 0.8 ⁇ m, and the particle size D95 is not higher than 2 ⁇ m; additives of this particle size are not only beneficial to the manufacturing process of chip varistors, but also ensure the prepared chip varistor. Nonlinear structure, low temperature, low voltage and other characteristics of varistor. If the particle size is too fine, although it will be helpful in the subsequent sintering process, too fine a particle size will cause the potential gradient of the varistor to be high, which is not conducive to the production of low-temperature and low-voltage series chip varistors. If the particle size is too large, it is not conducive to sintering and is not suitable for the existing tape casting process, affecting the preparation efficiency of chip varistors. In some specific embodiments, the particle size D50 of the additive is no higher than 0.7 ⁇ m, and the particle size D95 is no higher than 1.5 ⁇ m.
  • the main crystal phase material is selected from zinc oxide, thereby preparing a ZnO chip varistor.
  • the main crystal phase material is composed of the divalent element (Zn) and the hexavalent element oxygen (O).
  • the zinc oxide varistor is a "II-VI group oxide semiconductor".
  • the particle size D50 of the main crystal phase material is no higher than 0.8 ⁇ m, and the particle size D95 is no higher than 2 ⁇ m. If the particle size is too fine, although it will be helpful in the subsequent sintering process, too fine a particle size will cause the potential gradient of the varistor to be high, which is not conducive to the production of low-temperature and low-voltage series chip varistors. If the particle size is too large, it is not conducive to sintering and is not suitable for the existing tape casting process, affecting the preparation efficiency of chip varistors.
  • the step of mixing and grinding treatment includes: mixing and grinding an additive with a mass ratio of (90 to 94): (6 to 10) and the main crystal phase material, and then mixing and grinding with a solvent and an auxiliary agent to obtain A porcelain material with a potential of 300V/mm ⁇ 500V/mm can obtain a porcelain material with a low potential gradient.
  • the step of mixing and grinding treatment includes: mixing and grinding an additive with a mass ratio of (86 to 90): (10 to 14) and the main crystal phase material, and then mixing and grinding with a solvent and an auxiliary agent, A porcelain material with a potential of 500V/mm to 1000V/mm is obtained, that is, a porcelain material with a medium potential gradient is obtained.
  • the embodiments of the present application can prepare porcelain materials with low potential gradient, porcelain materials with medium potential gradient, and porcelain materials with high potential gradient, respectively. Meet the application requirements of low-voltage, medium-voltage and high-voltage potential gradients, and simultaneously realize the production of different types of porcelain materials and chip varistors for low-voltage, medium-voltage and high-voltage, solving the conventional need to prepare porcelain materials with different formulas for different potential gradient devices. problem, greatly simplifying the production process and improving production efficiency.
  • the additives include dispersants, binders, and thickeners.
  • the additives are used to adjust the material properties of the porcelain material and improve the stability of the produced chip varistor.
  • the dispersant is selected from acrylic esters. This type of dispersant has many active groups and is combined with main crystal phase materials such as zinc oxide and various components in the additives to make each component uniformly and stably dispersed in the solution. to improve the dispersion stability and uniformity of porcelain materials.
  • acrylate dispersants include disperbyk-182, disperbyk-184 from BYK Chemical Company, and DOPA-22 from Kyeisha Company.
  • the adhesive is selected from the polymethylmethacrylate PMMA system; the material viscosity of this system is relatively high, which is beneficial to the bonding stability of each raw material component in the porcelain body material.
  • the adhesive of the polymethyl methacrylate system includes Rohm and Haas A-21 and B-44.
  • the thickener is selected from at least one of dioctyl phthalate DOP, dibutyl phthalate DBP, and dioctyl adipate DOA; these thickeners can improve the properties of the system
  • the viscosity can keep the material system in a uniform and stable suspended state or opacifying state, or form a gel, which is beneficial to the subsequent production of porcelain materials into green bodies and improves the preparation efficiency of chip varistors.
  • the solvent includes a mixed solvent of toluene or propyl acetate and an alcohol solvent.
  • the combined use of toluene or propyl acetate and alcohol solvents is more conducive to improving the dissolution and dispersion stability of additives, main crystal phase materials and additives in the solvent, thereby improving the stability of the porcelain material.
  • the solvent is selected from a mixed solvent of toluene and absolute ethanol or a mixed solvent of propyl acetate and isobutanol.
  • the mass percentage of the dispersant is 1% to 2%
  • the mass percentage of the binder is 7% to 12%
  • the mass percentage of the thickener is 2% to 2%.
  • the mass percentage of solvent is 50% to 80%.
  • the added amount of the solvent component is between 50% and 80% of the weight of the powder. This is mainly to ensure that the viscosity of the prepared slurry is within an appropriate range for normal casting. , so the amount added is affected by the type and molecular weight of the selected adhesive.
  • the dosage of the dispersant component is 1% to 2% of the weight of the powder; the purpose is to improve the dispersion effect of the powder.
  • the amount of binder component is between 7% and 10% of the powder type, depending on the molecular weight and type of the binder itself, and is matched with the amount of solvent to ensure the appropriate slurry viscosity for normal casting use .
  • the amount of plasticizer is between 2% and 5%. The purpose is to reduce the force between the adhesive molecules, increase the plasticity, and facilitate subsequent processing.
  • the added amounts of these additives and solvents in the porcelain materials of the embodiments of the present application are mainly to ensure the processability of the previous process.
  • the added amounts are inappropriate, such as the viscosity is inappropriate, the casting effect will be poor and the post-production of the product will be affected; If the dispersant is improperly selected and added, the dispersion effect of the powder will be affected, and the consistency of the later product performance will be affected. If the amount of adhesive and plasticizer is improper, it will cause the products to be cut and processed in the later stage to have poor appearance such as sticking sheets and sharp edges.
  • the step of mixing and grinding the additive with the main crystal phase material, solvent and auxiliary agent includes: after mixing the additive with the main crystal phase material, adding the solvent and dispersant, and grinding at a ball milling frequency of 25 to 30 HZ.
  • the step of making the porcelain material into a chip varistor includes: making the porcelain material into a green membrane according to a preset structure, printing internal electrodes, and laminating them in sequence. process, warm water pressure process, cutting process, debinding process, sintering process, terminal electrode process and electroplating process to prepare a chip varistor.
  • the temperature of the sintering process is not lower than 850°C and not higher than 900°C.
  • the low melting point components such as Bi2O3, H3BO3, Zn3(PO4)2 ⁇ 4H2O, etc. in the additives of the porcelain material in the embodiments of the present application can form a eutectic, which has a melting effect and is conducive to reducing the sintering temperature of the porcelain material.
  • the sintering temperature is lower than 900°C, and it ensures that the varistor still has good electrical properties and long-term stability at a lower sintering temperature.
  • the silver paste used in the terminal electrode process contains 60% to 70% silver, and the silver burning temperature is 600°C to 800°C.
  • the internal electrical paste is pure silver paste, and the preferred silver content of the pure silver paste is 85% to 92%, the printing thickness is 5 to 10 ⁇ m, and the sintering temperature is between 850 and 900°C.
  • the second aspect of the embodiment of the present application provides a chip varistor.
  • the ceramic material of the chip varistor includes a main crystal phase material and an additive.
  • the additive includes a molar ratio of (1.0 ⁇ 2.0): (1.0 ⁇ 2.0):(0.4 ⁇ 0.8):(0.4 ⁇ 0.8):(0.4 ⁇ 0.8):(1.0 ⁇ 2.0):(0.8 ⁇ 1.6):(0.2 ⁇ 0.8):(0.01 ⁇ 0.05):(0.02 ⁇ 0.08) Bi2O3, Sb2O3, MnO2, Cr2O3, Co2O3, H3BO3, Zn3(PO4)2 ⁇ 4H2O, Nb2O5, AgNO3 and Al(NO3)3 ⁇ 9H2O.
  • the chip varistor provided in the second aspect of the embodiment of the present application includes a main crystal phase material and an additive.
  • the additive includes a molar ratio of (1.0 ⁇ 2.0): (1.0 ⁇ 2.0): (0.4 ⁇ 0.8): (0.4 ⁇ 0.8):(0.4 ⁇ 0.8):(1.0 ⁇ 2.0):(0.8 ⁇ 1.6):(0.2 ⁇ 0.8):(0.01 ⁇ 0.05):(0.02 ⁇ 0.08) Bi2O3, Sb2O3, MnO2, Cr2O3, Co2O3, H3BO3 , Zn3(PO4)2 ⁇ 4H2O, Nb2O5, AgNO3 and Al(NO3)3 ⁇ 9H2O.
  • the synergistic effect of the main crystal phase material and the specially formulated additives plays a decisive role in the formation of the excellent nonlinear structure of the varistor, the improvement of the ability to withstand impulse current, and the improvement of long-term operating stability.
  • low melting point components such as Bi2O3, H3BO3, Zn3(PO4)2 ⁇ 4H2O in the additives can form a eutectic, which has a melting effect and is beneficial to lowering the sintering temperature to below 900°C and ensuring the varistor. It still has good electrical properties and long-term use stability at lower sintering temperatures.
  • the chip varistor in the embodiment of the present application can be manufactured by the method of the above embodiment.
  • the main crystalline phase material is selected from zinc oxide.
  • the particle size D50 of the main crystal phase material is no higher than 0.8 ⁇ m, and the particle size D95 is no higher than 2 ⁇ m.
  • the particle size D50 of the additive is no higher than 0.8 ⁇ m, and the particle size D95 is no higher than 2 ⁇ m.
  • the mass ratio of the main crystal phase material and the additive is (81-94): (6-19).
  • the potential of the chip varistor is 300V/mm ⁇ 500V/mm.
  • the potential of the chip varistor is 500V/mm ⁇ 1000V/mm.
  • the potential of the chip varistor is 1000V/mm ⁇ 2000V/mm.
  • the main crystal phase material is zinc oxide.
  • the current density of the chip varistor can be as high as 59A/mm2. Since the applied impulse current is very short, when a large current is applied to the ZnO varistor, the pulse capability will be absorbed by the varistors of different small units in a short period of time, and the heat generated will increase the temperature of the product. The heat generated in such a short period of time cannot effectively and quickly diffuse to other parts of the varistor. Therefore, the temperature of the varistor in different small units will rise rapidly in a short period of time. Between two different units, The temperature gradient between them will produce thermal stress on the grain boundaries between them.
  • the microstructure of the varistor is composed of three phases: zinc oxide grains, grain boundary layers and spinel. Since the resistance of zinc oxide grains is (1 ⁇ 10) ⁇ .cm and the resistivity of the grain boundary layer is (1012 ⁇ 1013) ⁇ .cm, the voltage applied to the varistor is basically at the grain boundary layer.
  • the heat release characteristics of the grain boundary layer depend on the heat capacity, thermal conductivity and other heat release characteristics of the zinc oxide grains in contact with it. Therefore, the flow capacity of the high-energy varistor is approximately determined by the heat capacity of the zinc oxide grains. Obviously, the larger the ZnO crystal grains in the chip varistor, that is, the more ZnO content, the greater the flow capacity of the high-energy varistor.
  • the content of additives helps improve the flow capacity of the product.
  • the electronic device provided in the third aspect of the embodiment of the present application includes the above-mentioned chip varistor.
  • the chip varistor has the characteristics of non-linearity, high current flow, Features such as adjustable voltage gradient and low-temperature sintering improve the stability of electronic devices.
  • a chip varistor the preparation of which includes the following steps:
  • the material can be discharged to a special tray and dried in an oven at a temperature of 150°C ⁇ 10°C to obtain additives for use in later batching.
  • the porcelain material After the porcelain material is discharged, it is cast on the PET film to form a green film with a thickness of 40 ⁇ m.
  • dielectric layer thickness 0.14mm and 6 internal electrodes, lamination, warm water pressure, and cutting are completed in sequence. , debinding, sintering, terminal electrode and electroplating processes, and finally obtain chip varistors corresponding to the needs.
  • the internal electrode is printed with pure silver paste with a silver content of 90%, and the printing thickness is 7 to 9 ⁇ m.
  • the maximum sintering temperature is 870°C, and the temperature is maintained for 2 hours; the terminal electrode silver paste is made with a terminal paste with a silver content of 65%, and the silver is burned at the maximum temperature of 750°C to complete the conductive terminal production and obtain a chip varistor. .
  • a chip varistor the preparation of which includes the following steps:
  • the porcelain material After the porcelain material is discharged, it is cast on the PET film to form a green film with a thickness of 40 ⁇ m.
  • dielectric layer thickness 0.14mm and 6 internal electrodes, lamination, warm water pressure, and cutting are completed in sequence. , debinding, sintering, terminal electrode and electroplating processes, and finally obtain chip varistors corresponding to the needs.
  • the internal electrode is printed with pure silver paste with a silver content of 90%, and the printing thickness is 7 to 9 ⁇ m.
  • the maximum sintering temperature is 870°C, and the temperature is maintained for 2 hours; the terminal electrode silver paste is made with a terminal paste with a silver content of 65%, and the silver is burned at the maximum temperature of 750°C to complete the conductive terminal production and obtain a chip varistor. .
  • the porcelain material After the porcelain material is discharged, it is cast on the PET film to form a green film with a thickness of 40 ⁇ m.
  • dielectric layer thickness 0.14mm and 6 internal electrodes, lamination, warm water pressure, and cutting are completed in sequence. , debinding, sintering, terminal electrode and electroplating processes, and finally obtain chip varistors corresponding to the needs.
  • the internal electrode is printed with pure silver paste with a silver content of 90%, and the printing thickness is 7 to 9 ⁇ m.
  • the maximum sintering temperature is 870°C, and the temperature is maintained for 2 hours; the terminal electrode silver paste is made with a terminal paste with a silver content of 65%, and the silver is burned at the maximum temperature of 750°C to complete the conductive terminal production and obtain a chip varistor. .
  • the electrochemical properties such as varistor voltage, leakage current, nonlinear coefficient, peak current, potential gradient, flow density, etc. of the chip varistor prepared in the embodiments, and The morphology was tested as follows:
  • Test method of varistor voltage nominal value of varistor voltage V1mA. This parameter is a parameter of the turning point of the pre-breakdown zone and breakdown zone in the volt-ampere curve of the zinc oxide varistor. Generally, it is a 1mA DC current. Out of date, the voltage value across the product.
  • Leakage current test method current value passing through the product at 75% varistor voltage V1mA.
  • Test method of potential gradient voltage calculated by dividing the varistor voltage value by the thickness of the dielectric layer.
  • Test method for flow density refer to the national standard "GJB 1782A-2015”.
  • Figure 2 shows the chip varistor of Example 1.
  • Figure 3 is an SEM micromorphology image of the chip varistor in Example 2
  • Figure 4 is an SEM micromorphology image of the chip varistor in Example 3. It can be seen from the morphology diagram that the particles in the chip varistor prepared in the embodiment of the present application are evenly distributed and the surface is smooth, which improves the stability of the chip varistor.

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Abstract

一种片式压敏电阻器及制备方法和应用。包括步骤：制备摩尔比为(1.0～2.0):(1.0～2.0):(0.4～0.8):(0.4～0.8):(0.4～0.8):(1.0～2.0):(0.8～1.6):(0.2～0.8):(0.01～0.05):(0.02～0.08)的Bi2O3、Sb2O3、MnO2、Cr2O3、Co2O3、H3BO3、Zn3(PO4)2·4H2O、Nb2O5、AgNO3和Al(NO3)3·9H2O的添加剂；与主晶相材料、溶剂和助剂混合后制成片式压敏电阻器。降低烧结温度，调整添加剂与主晶相材料的配比，能分别制备低中高不同电位梯度电阻器，简单高效。

Description

片式压敏电阻器及其制备方法和应用
本申请要求于2022年7月1日在中国专利局提交的、申请号为202210767580.1的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于电阻器技术领域，尤其涉及一种片式压敏电阻器及其制备方法和应用。
背景技术
现代电子整机设备日趋小型化、轻薄化以及多功能化的趋势，使得其内部电路的集成度和电子元件安装密度大大提高，电子元器件作为电子设备里最基础的部分，其小型化的需求愈发强烈。传统形态的插件式ZnO压敏变阻器具有尺寸大(市面最小为φ5mm)、通流量小等缺陷，使得其应用受到较大限制。而随着材料及工艺技术的提升，片式压敏电阻器因其小型化，优异的浪涌过电压防护能力而越来越受到市场的青睐，在部分使用领域已开始逐渐替代传统的插件压敏，特别是在安防、通讯电源、网通及LED照明等领域方面，已得到更广泛的应用。片式压敏电阻器峰值电流参数的大小决定了产品抗浪涌能力的强弱，参数越大，表明产品抗浪涌能力越强，保护效果越好。而该参数主要由瓷体材料、产品尺寸(结构设计)及生产工艺相关，随着小型化趋势需求，唯有近一步提高瓷体材料通流密度，方能进一步提高产品浪涌防护性能，满足市场需求。
目前的片式压敏电阻器根据应用领域的差异，大抵上可分为直流应用(低压5～30V、中压30V～85V)及交流应用(高压110V～320V)，根据不同的电压范围，制作技术中需要采用不同类别的配方来制作，因多种类别配方在产线上运作，每次制粉制浆料均需要严格对治具和设备进行清洁，或者需要准备多套设备进行分类专用，以此防止多种料别之间的交叉污染，此类操作规程导致生产效率较低，过程复杂，现场管理繁琐等问题存在。目前批量化生产的片式压敏电阻器主要还是采用匹配Pd10/Ag90或Pd20/Ag80内电极浆料的ZnO-Bi系瓷体材料，其烧结温度均需要在900℃及以上温度，此烧结温度对于纯银内浆来说还是偏高，并无法完全有效匹配，如内电极需要印刷达到10μm及以上厚度，防止引出端及内电极烧损，烧结温度调整空间狭小等问题，因此若要完全适配纯银内电极浆料，瓷体材料体系的烧结温度还需要进一步降低至900℃以下。
技术问题
本申请的目的在于提供一种片式压敏电阻器及其制备方法，以及一种电子设备，旨在一定程度上解决不同电压范围的片式压敏电阻器需采用不同类别的配方制作，生产效率低，烧结温度高的问题。
技术解决方案
为实现上述申请目的，本申请采用的技术方案如下：
第一方面，本申请提供一种片式压敏电阻器的制备方法，包括以下步骤：
制备添加剂，所述添加剂中包括摩尔比为(1.0～2.0):(1.0～2.0):(0.4～0.8):(0.4～0.8):(0.4～0.8):(1.0～2.0):(0.8～1.6):(0.2～0.8):(0.01～0.05):(0.02～0.08)的Bi2O3、Sb2O3、MnO2、Cr2O3、Co2O3、H3BO3、Zn3(PO4)2·4H2O、Nb2O5、AgNO3和Al(NO3)3·9H2O；
将所述添加剂与主晶相材料、溶剂和助剂进行混合研磨处理，得到瓷体材料；
将所述瓷体材料制成片式压敏电阻器。
第二方面，本申请提供一种片式压敏电阻器，所述片式压敏电阻器的瓷体材料包括主晶相材料和添加剂，所述添加剂包括摩尔比为(1.0～2.0):(1.0～2.0):(0.4～0.8):(0.4～0.8):(0.4～0.8):(1.0～2.0):(0.8～1.6):(0.2～0.8):(0.01～0.05):(0.02～0.08)的Bi2O3、Sb2O3、MnO2、Cr2O3、Co2O3、H3BO3、Zn3(PO4)2·4H2O、Nb2O5、AgNO3和Al(NO3)3·9H2O。
第三方面，本申请提供一种电子设备，所述电子设备中包含有上述方法制备的片式压敏电阻器，或者上述的片式压敏电阻器。
本申请第一方面提供的片式压敏电阻器的制备方法，工艺简单，能耗小，成本低，适用于工业化大规模生产和应用。制备的片式压敏电阻器采用的瓷体材料中包含有独特配方的添加剂，其中，Bi2O3是构成压敏电阻的高阻晶界骨架结构主要成分，是压敏电阻器产生非线性的基础。Sb2O3是生产锑锌尖晶石相的主要添加物成分，尖晶石位于ZnO等主晶相材料的晶粒交叉处，有利于促进主晶相长大并均匀发育，提高器件击穿电压和耐受方波，提高器件在大电流冲击及长期电场作用下运行的稳定性。若Sb2O3添加过多，将使漏电流增大，并降低产品的通流容量及浪涌过电压能力吸收能力。Cr2O3与Sb2O3同样参与尖晶石的形成，可产生与Sb2O3相似的通道，有助于改善器件的稳定性，若掺杂将会导致点做的电位梯度增高，漏电流增大，压比变差。MnO2、Co2O3等组分对提高片式压敏电阻器的非线性以及降低漏电流起着非常重要的作用，同时也有利于提高其耐受方波、雷电流及大电流冲击作用的耐受能力和稳定性，但若过量掺杂会导致电阻片的压比上升。H3BO3、Zn3(PO4)2·4H2O等组分熔点较低，两者形成的低共熔化合物，助融效果显著，能促进晶粒生长，降低烧结温度。同时其形成的玻璃氧化物，在烧成过程中容易与Bi2O3、Sb2O3和填隙Zn离子生产致密的玻璃相，降低了晶界缺陷浓度，提高电阻片在电场环境下长期稳定性。Nb2O5会在晶界处偏析出来，与主晶相材料形成Zn3Nb2O8等尖晶石相，可以起到阻止晶粒生长的作用，同时尖晶石相也使晶界的表面态密度增加，因此可以增加晶界势垒高度，提高产品的非线性。但当添加量过高时，由于阻碍晶粒生长会导致晶界缺陷增多，进而导致漏电流增大、非线性系数降低。AgNO3一价的银离子能够降低和钳制费米能级，属于晶界稳定剂，能够抑制填隙离子的迁移，抑制氧原子的扩散，减缓压敏电阻器的劣化，延长器件使用寿命。但若添加量过大，将会引起漏电流增大、压敏电压降 低，综合性能变差。Al(NO3)3·9H2O由于Al3+(53.5pm)离子半径小，容易进入晶格中，有利于提高主晶相晶粒载流子浓度，降低晶粒电阻，使得压敏电阻的V-I特性曲线向大电流区偏移，降低限压比，提高雷电流及大电流冲击作用的耐受能力。但过量掺杂，将会引起漏电流增大，压敏电压上升。
本申请第二方面提供的片式压敏电阻器，通过主晶相材料与特殊配方的添加剂的协同作用，对压敏电阻优异非线性结构的形成，耐受冲击电流能力的提高，以及长期运行稳定性的改善等都起着决定性作用。另外，添加剂中Bi2O3、H3BO3、Zn3(PO4)2·4H2O等低熔点组分能够形成低共融物，起到助融效果，有利于降低烧结温度，低于900℃，并保证压敏电阻器在较低的烧结温度下依然具有良好的电性能和长期使用稳定性。在降低烧结温度的条件下，通过调整瓷体材料中添加剂各组分的掺杂量，或者添加剂与主晶相材料的配比，能分别满足低压、中压和高压电位梯度压敏电阻器的应用需求，应用灵活，适应性广。
本申请第三方面提供的电子设备，由于包含有上述片式压敏电阻器，该片式压敏电阻器通过主晶相材料与特殊配方的添加剂的协同作用具有非线性、高通流、电压梯度可调且可低温烧结等特性，从而提高了电子设备的稳定性。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的片式压敏电阻器的制备方法的流程示意图；
图2是本申请实施例1提供的片式压敏电阻器的SEM图；
图3是本申请实施例2提供的片式压敏电阻器的SEM图；
图4是本申请实施例3提供的片式压敏电阻器的SEM图。
本发明的实施方式
为了使本申请要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请中，术语“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况。其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，“a，b或c中的至少一项(个)”，或，“a，b和c中的至少一项(个)”，均可以表示：a，b，c，a-b(即a和b)，a-c，b-c，或a-b-c，其中a，b，c分别可以是单个，也可以是多个。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，部分或全部步骤可以并行执行或先后执行，各过程的执行顺 序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
在本申请实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请实施例和所附权利要求书中所使用的单数形式的“一种”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。
本申请实施例说明书中所提到的相关成分的重量不仅仅可以指代各组分的具体含量，也可以表示各组分间重量的比例关系，因此，只要是按照本申请实施例说明书相关组分的含量按比例放大或缩小均在本申请实施例说明书公开的范围之内。具体地，本申请实施例说明书中的质量可以是μg、mg、g、kg等化工领域公知的质量单位。
术语“第一”、“第二”仅用于描述目的，用来将目的如物质彼此区分开，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。例如，在不脱离本申请实施例范围的情况下，第一XX也可以被称为第二XX，类似地，第二XX也可以被称为第一XX。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。
本申请实施例第一方面提供一种片式压敏电阻器的制备方法，包括以下步骤：
S10.制备添加剂，添加剂中包括摩尔比为(1.0～2.0):(1.0～2.0):(0.4～0.8):(0.4～0.8):(0.4～0.8):(1.0～2.0):(0.8～1.6):(0.2～0.8):(0.01～0.05):(0.02～0.08)的Bi2O3、Sb2O3、MnO2、Cr2O3、Co2O3、H3BO3、Zn3(PO4)2·4H2O、Nb2O5、AgNO3和Al(NO3)3·9H2O；
S20.将添加剂与主晶相材料、溶剂和助剂进行混合研磨处理，得到瓷体材料；
S30.将瓷体材料制成片式压敏电阻器。
本申请实施例第一方面提供的片式压敏电阻器的制备方法，制备包括摩尔比为(1.0～2.0):(1.0～2.0):(0.4～0.8):(0.4～0.8):(0.4～0.8):(1.0～2.0):(0.8～1.6):(0.2～0.8):(0.01～0.05):(0.02～0.08)的Bi2O3、Sb2O3、MnO2、Cr2O3、Co2O3、H3BO3、Zn3(PO4)2·4H2O、Nb2O5、AgNO3和Al(NO3)3·9H2O的添加剂后，将添加剂与主晶相材料、溶剂和助剂进行混合研磨处理制成瓷体材料，再将瓷体材料制成片式压敏电阻器。本申请实施例片式压敏电阻器的制备方法制备工艺简单，能耗小，成本低，适用于工业化大规模生产和应用。制备的片式压敏电阻器采用的瓷体材料中包含有独特配方的添加剂，其中，Bi2O3是构成压敏电阻的高阻晶界骨架结构主要成分，是压敏电阻器产生非线性的基础。Sb2O3是生产锑锌尖晶石相的主要添加物成分，尖晶石位于ZnO等主晶相材料的晶粒交叉处，有利于促进主晶相长大并均匀发育，提高器件击穿电压和耐受方波，提高器件在大电流冲击及长期电场作用下运行的稳定性。若Sb2O3添加过多，将使漏电流增大，并降低产品的通流容量及浪涌过电压能力吸收能力。Cr2O3与Sb2O3同样参与尖晶石的形成，可产生与Sb2O3相似的通道，有助于改善器件的稳定性，若掺杂过多，将导致电位 梯度增高，漏电流增大，压比变差。MnO2、Co2O3等组分对提高片式压敏电阻器的非线性以及降低漏电流起着非常重要的作用，同时也有利于提高其耐受方波、雷电流及大电流冲击作用的耐受能力和稳定性，但若过量掺杂会导致电阻片的压比上升。H3BO3、Zn3(PO4)2·4H2O等组分熔点较低，两者形成的低共熔化合物，助融效果显著，能促进晶粒生长，降低烧结温度。同时其形成的玻璃氧化物，在烧成过程中容易与Bi2O3、Sb2O3和填隙Zn离子生产致密的玻璃相，降低了晶界缺陷浓度，提高电阻片在电场环境下长期稳定性。Nb2O5会在晶界处偏析出来，与主晶相材料形成Zn3Nb2O8等尖晶石相，可以起到阻止晶粒生长的作用，同时尖晶石相也使晶界的表面态密度增加，因此可以增加晶界势垒高度，提高产品的非线性。但当添加量过高时，由于阻碍晶粒生长会导致晶界缺陷增多，进而导致漏电流增大、非线性系数降低。AgNO3一价的银离子能够降低和钳制费米能级，属于晶界稳定剂，能够抑制填隙离子的迁移，抑制氧原子的扩散，减缓压敏电阻器的劣化，延长器件使用寿命。但若添加量过大，将会引起漏电流增大、压敏电压降低，综合性能变差。Al(NO3)3·9H2O由于Al3+(53.5pm)离子半径小，容易进入晶格中，有利于提高主晶相晶粒载流子浓度，降低晶粒电阻，使得压敏电阻的V-I特性曲线向大电流区偏移，降低限压比，提高雷电流及大电流冲击作用的耐受能力。但过量掺杂，将会引起漏电流增大，压敏电压上升。本申请实施例制备片式压敏电阻器，通过瓷体材料中主晶相材料与特殊配方的添加剂的协同作用，一方面，对压敏电阻优异非线性结构的形成，耐受冲击电流能力的提高，以及长期运行稳定性的改善等都起着决定性作用。另一方面，添加剂中低熔点组分能够形成低共融物，起到助融效果，有利于降低烧结温度，低于900℃，并保证压敏电阻器在较低的烧结温度下依然具有良好的电性能和长期使用稳定性。再一方面，在降低烧结温度的条件下，通过调整瓷体材料中添加剂各组分的掺杂量，或者添加剂与主晶相材料的配比，能分别满足低压、中压和高压电位梯度应用需求，同时实现低压、中压和高压不同类瓷体材料及片式压敏电阻器的制作，解决了常规针对不同电位梯度器件需要分别制备不同配方的瓷体材料的问题，大大简化了生产工艺，提高生成效率。
在一些实施例中，上述步骤S10中，制备添加剂的步骤包括：称取摩尔比为(1.0～2.0):(1.0～2.0):(0.4～0.8):(0.4～0.8):(0.4～0.8):(1.0～2.0):(0.8～1.6):(0.2～0.8):(0.01～0.05):(0.02～0.08)的Bi2O3、Sb2O3、MnO2、Cr2O3、Co2O3、H3BO3、Zn3(PO4)2·4H2O、Nb2O5、AgNO3和Al(NO3)3·9H2O后，将添加剂粉体与粉体总质量80～120％的水，优选去离子水置于行星球磨机上进行混合并磨细，当粒径达到预定要求后便可出料至专用托盘，烘干后便得到添加剂。
在一些实施例中，添加剂的粒径D50不高于0.8μm，粒径D95不高于2μm；该粒度大小的添加剂既有利于片式压敏电阻器的制程工艺，又确保了制备的片式压敏电阻器的非线性结构、低温、低压等特性。若粒径太细，虽然有助于后续烧结处理工序，但是太细会使得做出的压敏电阻其电位梯度偏高，不利于制 得低温低压系列的片式压敏电阻器。若粒径过大，则不利于烧结，且不适用于现有流延工艺，影响片式压敏电阻器的制备效率。在一些具体实施例中，添加剂的粒径D50不高于0.7μm，粒径D95不高于1.5μm。
在一些实施例中，上述步骤S20中，主晶相材料选自氧化锌，从而制备ZnO片式压敏电阻器。主晶相材料为二价元素(Zn)和六价元素氧(O)所构成，从材料的角度来看，氧化锌压敏电阻器是一种“Ⅱ-Ⅵ族氧化物半导体”。通过主晶相材料与特定配方添加剂的协同作用，使制得的片式压敏电阻器具有通流容量大、限制电压低、响应速度快、无续流、对称的伏安特性(即产品无极性)、电压温度系数低等特性。
在一些实施例中，主晶相材料的粒径D50不高于0.8μm，粒径D95不高于2μm。若粒径太细，虽然有助于后续烧结处理工序，但是太细会使得做出的压敏电阻其电位梯度偏高，不利于制得低温低压系列的片式压敏电阻器。若粒径过大，则不利于烧结，且不适用于现有流延工艺，影响片式压敏电阻器的制备效率。
本申请述通过实施例研究发现主晶相材料含量越低，添加剂含量越高，瓷体材料的电位梯度越高。
在一些实施例中，混合研磨处理的步骤包括：将质量比为(90～94)：(6～10)的添加剂与主晶相材料混合研磨后，与溶剂和助剂进行混合研磨处理，得到电位为300V/mm～500V/mm的瓷体材料，即得到低电位梯度的瓷体材料。
在另一些实施例中，混合研磨处理的步骤包括：将质量比为(86～90)：(10～14)的添加剂与主晶相材料混合研磨后，与溶剂和助剂进行混合研磨处理，得到电位为500V/mm～1000V/mm的瓷体材料，即得到中电位梯度的瓷体材料。
在另一些实施例中，混合研磨处理的步骤包括：将质量比为(81～86)：(14～19)的添加剂与主晶相材料混合研磨后，与溶剂和助剂进行混合研磨处理，得到电位为1000V/mm～2000V/mm的瓷体材料，即得到高电位梯度的瓷体材料。
本申请实施例通过调节瓷体材料中添加剂和主晶相材料的配比，能够分别制备出低电位梯度的瓷体材料、中电位梯度的瓷体材料和高电位梯度的瓷体材料，分别满足低压、中压和高压电位梯度应用需求，同时实现低压、中压和高压不同类瓷体材料及片式压敏电阻器的制作，解决常规针对不同电位梯度器件需要分别制备不同配方的瓷体材料的问题，大大简化了生产工艺，提高生成效率。
在一些实施例中，助剂包括分散剂、粘合剂和增稠剂，通过助剂调节瓷体材料的料性，提高制得的片式压敏电阻器的稳定性。
在一些实施例中，分散剂选自丙烯酸酯类，该类型的分散剂活性基团多，与氧化锌等主晶相材料和添加剂中各组分结合，使各组分均匀稳定的分散在溶液中，提高瓷体材料的分散稳定性和均一性。在一些具体实施例中，丙烯酸酯类分散剂包括BYK比克化学公司的disperbyk-182、disperbyk-184、共荣社公 司的DOPA-22。
在一些实施例中，粘合剂选自聚甲基丙烯酸甲酯PMMA体系；该体系材料黏度较高，有利于高瓷体材料中各原料组分的结合稳定性。在一些具体实施例中，聚甲基丙烯酸甲酯体系的粘合剂包括罗门哈斯A-21、B-44。
在一些实施例中，增稠剂选自邻苯二甲酸二辛酯DOP、邻苯二甲酸二丁酯DBP、己二酸二辛酯DOA中的至少一种；这些增稠剂可以提高物系黏度，使物系保持均匀稳定的悬浮状态或乳浊状态，或形成凝胶，有利于瓷体材料后续制成生坯，提高片式压敏电阻器制备效率。
在一些实施例中，溶剂包括甲苯或醋酸丙酯与醇类溶剂的混合溶剂。通过甲苯或醋酸丙酯与醇类溶剂的复配使用，更有利于提高添加剂、主晶相材料和助剂在溶剂中的溶解、分散稳定性，从而提高瓷体材料的稳定性。在一些具体实施例中，溶剂选自甲苯和无水乙醇的混合溶剂或者醋酸丙酯和异丁醇混合溶剂。
在一些实施例中，瓷体材料中，分散剂的质量百分含量为1％～2％，粘合剂的质量百分含量为7～12％，增稠剂的质量百分含量为2～5％，溶剂的质量百分含量为50％～80％。本申请实施例瓷体材料中，溶剂组分添加量是粉体重量的50％～80％之间，其主要是保证配制出来的浆料黏度在一合适的范围内，以供正常流延使用，因此其添加量受到所选择的粘合剂种类及分子量影响。分散剂组分用量为粉体重量的1％～2％；目的在于提高粉体的分散效果。粘合剂组分用量为粉体种类的7～10％之间，根据粘合剂本身的分子量和种类而定，与溶剂用量相互搭配，以此保障合适的浆料黏度用于正常流延使用。增塑剂用量为2～5％之间，目的在于降低粘合剂分子间的作用力，增加可塑性，便于后序工艺加工。本申请实施例瓷体材料中这些助剂和溶剂的添加量更多在于保证前工序制作的可加工性能，若添加量不合适，如黏度不合适，则流延效果差，影响产品后期制作；若分散剂选用和添加不当，影响粉体的分散效果，会影响到后期产品性能的一致性。若粘合剂及增塑剂用量不当，会导致后期切割加工产品产生粘片、披锋等外观不良。
在一些实施例中，将添加剂与主晶相材料、溶剂和助剂进行混合研磨处理的步骤包括：将添加剂与主晶相材料混合后，添加溶剂和分散剂，在球磨频率为25～30HZ的条件下行星球磨6～12小时，再添加粘合剂和增稠剂，在球磨频率为25～30HZ的条件下行星球磨6～12小时，得到瓷体材料。充分确保瓷体材料中各组分研磨均匀，分散稳定，有利于后续制成片式压敏电阻器。
在一些实施例中，上述步骤S30中，将瓷体材料制成片式压敏电阻器的步骤包括：将瓷体材料按预设结构制成生胚膜后，印刷内电极，依次进行叠层工序、温水压工序、切割工序、排胶工序、烧结工序、端电极工序及电镀工序，制得片式压敏电阻器。
在一些实施例中，烧结工序的温度不低于850℃，且不高于900℃。本申请实施例瓷体材料的添加剂中Bi2O3、H3BO3、Zn3(PO4)2·4H2O等低熔点组分能够形成低共融物，起到助融效果，有利于降低瓷体材料的烧结温度，使烧 结温度低于900℃，并保证压敏电阻器在较低的烧结温度下依然具有良好的电性能和长期使用稳定性。
在一些实施例中，端电极工序采用的银浆中银含量为60～70％，烧银温度为600～800℃。在一些具体实施例中，内电级浆料为纯银浆，优选的纯银浆银含量为85％～92％，印刷厚度为5～10μm；烧结温度为850～900℃之间。
本申请实施例第二方面提供一种片式压敏电阻器，该片式压敏电阻器的瓷体材料包括主晶相材料和添加剂，添加剂包括摩尔比为(1.0～2.0):(1.0～2.0):(0.4～0.8):(0.4～0.8):(0.4～0.8):(1.0～2.0):(0.8～1.6):(0.2～0.8):(0.01～0.05):(0.02～0.08)的Bi2O3、Sb2O3、MnO2、Cr2O3、Co2O3、H3BO3、Zn3(PO4)2·4H2O、Nb2O5、AgNO3和Al(NO3)3·9H2O。
本申请实施例第二方面提供的片式压敏电阻器，包括主晶相材料和添加剂，添加剂包括摩尔比为(1.0～2.0):(1.0～2.0):(0.4～0.8):(0.4～0.8):(0.4～0.8):(1.0～2.0):(0.8～1.6):(0.2～0.8):(0.01～0.05):(0.02～0.08)的Bi2O3、Sb2O3、MnO2、Cr2O3、Co2O3、H3BO3、Zn3(PO4)2·4H2O、Nb2O5、AgNO3和Al(NO3)3·9H2O。通过主晶相材料与特殊配方的添加剂的协同作用，对压敏电阻优异非线性结构的形成，耐受冲击电流能力的提高，以及长期运行稳定性的改善等都起着决定性作用。另外，添加剂中Bi2O3、H3BO3、Zn3(PO4)2·4H2O等低熔点组分能够形成低共融物，起到助融效果，有利于降低烧结温度，低于900℃，并保证压敏电阻器在较低的烧结温度下依然具有良好的电性能和长期使用稳定性。在降低烧结温度的条件下，通过调整瓷体材料中添加剂各组分的掺杂量，或者添加剂与主晶相材料的配比，能分别满足低压、中压和高压电位梯度压敏电阻器的应用需求，应用灵活，适应性广。
本申请实施例片式压敏电阻器可通过上述实施例方法制得。
在一些实施例中，主晶相材料选自氧化锌。
在一些实施例中，主晶相材料的粒径D50不高于0.8μm，粒径D95不高于2μm。
在一些实施例中，添加剂的粒径D50不高于0.8μm，粒径D95不高于2μm。
在一些实施例中，主晶相材料和添加剂的质量比为(81～94)：(6～19)。
在一些具体实施例中，主晶相材料和添加剂的质量比为(90～94)：(6～10)时，片式压敏电阻器的电位为300V/mm～500V/mm。
在一些具体实施例中，主晶相材料和添加剂的质量比为(86～90)：(10～14)时，片式压敏电阻器的电位为500V/mm～1000V/mm。
在一些具体实施例中，主晶相材料和添加剂的质量比为(81～86)：(14～19)时，片式压敏电阻器的电位为1000V/mm～2000V/mm。
本申请上述实施例的技术效果在前文均有论述，在此不再赘述。
在一些具体实施例中，主晶相材料为氧化锌，氧化锌和添加剂的质量比92：8时，片式压敏电阻器通流密度便可高达59A/mm2。由于施加的冲击电流时间很短，当对ZnO压敏电阻器施加一个大电流时，在短时间内脉冲能力会被不同小单元的压敏电阻器吸收，所产生的热量使产品温度上升，在如此短的 时间内所产生的热量并无法有效快速扩散到压敏电阻器的其他地方去，因此不同小单元的压敏电阻器在很短的时间内温度会迅速升高，两个不同单元之间的温度梯度会在它们之间的晶界上产生热应力。如果电阻器内部不同部分之间的热应力超过临界值，就会发生炸裂破坏而失效。而影响温度扩散程度及相邻两个小单元之间温度梯度差异程度的因素有几个，如微观结构上的均匀性，瓷体材料导热系数、比热常数和比重等。从微观结构上来看，压敏电阻的微观结构由氧化锌晶粒、晶界层和尖晶石三相构成。由于氧化锌晶粒的电阻为(1～10)Ω.cm，晶界层的电阻率为(1012～1013)Ω.cm，所以施加在压敏电阻上的电压基本上是在晶界层，而晶界层的放热特性是依赖与其接触的氧化锌晶粒的热容量、热导率等放热特性，因此高能压敏电阻器的通流容量近似由氧化锌晶粒的热容量决定。显然片式压敏电阻器中ZnO晶粒越大，即ZnO含量越多，高能压敏电阻的通流容量也就越大。通过减少添加剂的含量，晶界层就越薄，其有助于氧化锌晶粒的生长，同时，氧化锌晶粒的热导率和热容量均高于晶界层物质，因此在一定范围内减少添加剂的含量有助于提高产品的通流能力。
本申请实施例第三方面提供一种电子设备，该电子设备中包含有上述方法制备的片式压敏电阻器，或者上述的片式压敏电阻器。
本申请实施例第三方面提供的电子设备，由于包含有上述片式压敏电阻器，该片式压敏电阻器通过主晶相材料与特殊配方的添加剂的协同作用具有非线性、高通流、电压梯度可调且可低温烧结等特性，从而提高了电子设备的稳定性。
为使本申请上述实施细节和操作能清楚地被本领域技术人员理解，以及本申请实施例片式压敏电阻器及其制备方法的进步性能显著的体现，以下通过多个实施例来举例说明上述技术方案。
实施例1
一种片式压敏电阻器，其制备包括步骤：
1)将添加剂按照如下的化学组成及配比(摩尔百分比)：Bi2O3：Sb2O3：MnO2：Cr2O3：Co2O3：H3BO3：Zn3(PO4)2·4H2O：Nb2O5：AgNO3和Al(NO3)3·9H2O＝1.2：1.0：0.5：0.5：1.0：1.2：1.0：0.1：0.02：0.03进行称量，加入与添加剂粉体总质量90％的离子水，一起置于行星球磨机上进行混合磨细16h，当粒径达到预定D50≤0.8μm，D95≤2μm的要求时，便可出料至专用托盘，于烘箱中150℃±10℃温度下进行烘干处理，得到添加剂用于后期配料公用。
2)按照92wt％ZnO+8wt％添加剂的材料配比，称取对应质量的添加剂进行粉碎，将粉碎处理后的添加剂、及对应质量的氧化锌粉体进行混合，同时加入对应质量的溶剂(50％总粉体质量的醋酸丙酯及15％总粉体质量的异丁醇)、加入丙烯酸酯类分散剂(1.5％粉体总质量)后在行星球磨机上按照30HZ，8H的条件进行球磨混合。
3)球磨混合完成后，继续往浆料内添加总粉体质量12％聚甲基丙烯酸甲 酯体系粘合剂和总粉体质量5％的邻苯二甲酸二辛酯增稠剂，并再次于行星球磨机上按照30HZ，8H的条件进行混合分散，得到瓷体材料。
4)瓷体材料出料后于PET膜上流延成40μm厚度的生坯膜，并按照4532尺寸、介质层厚度0.14mm和6个内电极的结构设计，依序完成叠层、温水压、切割、排胶、烧结、端电极及电镀工序制作，最终得到对应需求片式压敏电阻器。其中，内电极采用银含量为90％纯银浆料进行印刷，印刷厚度在7～9μm。烧结最高温度为870℃，保温2h；端电极银浆采用银含量为65％的端浆进行制作，并于最高温度为750℃进行烧银，完成导电端头制作，得到片式压敏电阻器。
实施例2
一种片式压敏电阻器，其制备包括步骤：
1)添加剂制作及组成同实施例1一致，直接取用。
2)按照88％ZnO+12％添加剂的材料配比，称取对应质量的添加剂进行粉碎，将粉碎处理后的添加剂、及对应质量的氧化锌粉体进行混合，同时加入对应质量的溶剂(50％总粉体质量的醋酸丙酯及15％总粉体质量的异丁醇)、加入丙烯酸酯类分散剂(1.5％粉体总质量)后在行星球磨机上按照30HZ，8H的条件进行球磨混合。
3)球磨混合完成后，继续往浆料内添加总粉体质量12％聚甲基丙烯酸甲酯体系粘合剂和总粉体质量5％的邻苯二甲酸二辛酯增稠剂，并再次于行星球磨机上按照30HZ，8H的条件进行混合分散，得到瓷体材料。
4)瓷体材料出料后于PET膜上流延成40μm厚度的生坯膜，并按照4532尺寸、介质层厚度0.14mm和6个内电极的结构设计，依序完成叠层、温水压、切割、排胶、烧结、端电极及电镀工序制作，最终得到对应需求片式压敏电阻器。其中，内电极采用银含量为90％纯银浆料进行印刷，印刷厚度在7～9μm。烧结最高温度为870℃，保温2h；端电极银浆采用银含量为65％的端浆进行制作，并于最高温度为750℃进行烧银，完成导电端头制作，得到片式压敏电阻器。
实施例3
一种片式压敏电阻器，其制备包括步骤：
1)添加剂制作及组成同实施例1一致，直接取用。
2)按照84％ZnO+16％添加剂的材料配比，称取对应质量的添加剂进行粉碎，将粉碎处理后的添加剂、及对应质量的氧化锌粉体进行混合，同时加入对应质量的溶剂(50％总粉体质量的醋酸丙酯及15％总粉体质量的异丁醇)、加入丙烯酸酯类分散剂(1.5％粉体总质量)后在行星球磨机上按照30HZ，8H的条件进行球磨混合。
3)球磨混合完成后，继续往浆料内添加总粉体质量12％聚甲基丙烯酸甲酯体系粘合剂和总粉体质量5％的邻苯二甲酸二辛酯增稠剂，并再次于行星球磨机上按照30HZ，8H的条件进行混合分散，得到瓷体材料。
4)瓷体材料出料后于PET膜上流延成40μm厚度的生坯膜，并按照4532 尺寸、介质层厚度0.14mm和6个内电极的结构设计，依序完成叠层、温水压、切割、排胶、烧结、端电极及电镀工序制作，最终得到对应需求片式压敏电阻器。其中，内电极采用银含量为90％纯银浆料进行印刷，印刷厚度在7～9μm。烧结最高温度为870℃，保温2h；端电极银浆采用银含量为65％的端浆进行制作，并于最高温度为750℃进行烧银，完成导电端头制作，得到片式压敏电阻器。
实施例4
一种片式压敏电阻器，其与实施例1的区别在于：步骤1中Bi2O3：Sb2O3：MnO2：Cr2O3：Co2O3：H3BO3：Zn3(PO4)2·4H2O：Nb2O5：AgNO3和Al(NO3)3·9H2O＝1.5：0.9：0.5：0.5：1.0：1.6：1.5：0.1：0.02：0.03。
进一步的，为了验证本申请实施例的进步性，对实施例制备的片式压敏电阻器的压敏电压、漏电流、非线性系数、峰值电流、电位梯度、流通密度等电化学性能，以及形貌分别进行如下测试：
1、压敏电压的测试方法：压敏电压标称值V1mA，该参数是氧化锌压敏电阻器伏安曲线中预击穿区和击穿区转折点的一个参数，一般情况下是1mA直流电流通过时，产品两端的电压值。
2、漏电流的测试方法：75％压敏电压V1mA下通过产品的电流值。
3、非线性系数的压测试方法：非线性系数α按公式α＝1/(logV1mA/V0.1mA)计算得出。
4、峰值电流的测试方法：产品能够承受规定次数的8/20μS脉冲电流峰值。
5、电位梯度压的测试方法：由压敏电压值除于介质层厚度计算得出。
6、通流密度的测试方法：参考国标《GJB 1782A-2015》。
上述测试结果如下表1所示：
表1
Figure PCTCN2022105754-appb-000001
由上述测试结果可知，本申请实施例制备的片式压敏电阻器均具有较高的流通密度，压敏电压低，漏电流低，非线性系数较高，且电位梯度通过氧化锌主晶相材料与添加剂的配比可灵活调控。通过调节氧化锌主晶相材料与添加剂的配比即可分别制备低电位片式压敏电阻器、中电位片式压敏电阻器和高电位 片式压敏电阻器。在低压、中压和高压范围内，漏电流都很小，表明产品功耗较小，提高器件应用性能，提高了片式压敏电阻器的应用灵活性，简化了制备工艺。另外，非线性系数较高，说明产品的压敏特性明显；峰值电流说明产品浪涌保护能力强。
7、对实施例制备的片式压敏电阻器的形貌分别通过扫描电镜进行了观测，测试结果如附图2～4所示，其中，附图2为实施例1片式压敏电阻器的SEM微观形貌图，附图3为实施例2片式压敏电阻器的SEM微观形貌图，附图4为实施例3片式压敏电阻器的SEM微观形貌图。从形貌图可见，本申请实施例制备的片式压敏电阻器中颗粒分布均匀，表面平整，提高了片式压敏电阻器的稳定性。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种片式压敏电阻器的制备方法，其特征在于，包括以下步骤：
    制备添加剂，所述添加剂中包括摩尔比为(1.0～2.0):(1.0～2.0):(0.4～0.8):(0.4～0.8):(0.4～0.8):(1.0～2.0):(0.8～1.6):(0.2～0.8):(0.01～0.05):(0.02～0.08)的Bi2O3、Sb2O3、MnO2、Cr2O3、Co2O3、H3BO3、Zn3(PO4)2·4H2O、Nb2O5、AgNO3和Al(NO3)3·9H2O；
    将所述添加剂与主晶相材料、溶剂和助剂进行混合研磨处理，得到瓷体材料；
    将所述瓷体材料制成片式压敏电阻器。
  2. 如权利要求1所述的片式压敏电阻器的制备方法，其特征在于，所述主晶相材料选自氧化锌；
    和/或，所述主晶相材料的粒径D50不高于0.8μm，粒径D95不高于2μm；
    和/或，所述添加剂的粒径D50不高于0.8μm，粒径D95不高于2μm。
  3. 如权利要求1或2所述的片式压敏电阻器的制备方法，其特征在于，所述混合研磨处理的步骤包括：
    将质量比为(90～94)：(6～10)的所述添加剂与所述主晶相材料混合研磨后，与所述溶剂和所述助剂进行混合研磨处理，得到电位为300V/mm～500V/mm的瓷体材料；
    或者，
    将质量比为(86～90)：(10～14)的所述添加剂与所述主晶相材料混合研磨后，与所述溶剂和所述助剂进行混合研磨处理，得到电位为500V/mm～1000V/mm的瓷体材料；
    或者，
    将质量比为(81～86)：(14～19)的所述添加剂与所述主晶相材料混合研磨后，与所述溶剂和所述助剂进行混合研磨处理，得到电位为1000V/mm～2000V/mm的瓷体材料。
  4. 如权利要求3所述的片式压敏电阻器的制备方法，其特征在于，所述助剂包括分散剂、粘合剂和增稠剂；
    和/或，所述溶剂包括甲苯或醋酸丙酯与醇类溶剂的混合溶剂。
  5. 如权利要求4所述的片式压敏电阻器的制备方法，其特征在于，所述瓷体材料中，所述分散剂的质量百分含量为1％～2％，所述粘合剂的质量百分含量为7～12％，所述增稠剂的质量百分含量为2～5％，所述溶剂的质量百分含量为50％～80％；
    和/或，所述分散剂选自丙烯酸脂种类；
    和/或，所述粘合剂选自聚甲基丙烯酸甲酯体系；
    和/或，所述增稠剂选自邻苯二甲酸二辛酯、邻苯二甲酸二丁酯、己二酸二辛酯中的至少一种；
    和/或，所述溶剂选自甲苯和无水乙醇的混合溶剂或者醋酸丙酯和异丁醇混合溶剂。
  6. 如权利要求4或5任一项所述的片式压敏电阻器的制备方法，其特征在于，所述混合研磨处理的步骤包括：
    将所述添加剂与所述主晶相材料混合后，添加所述溶剂和所述分散剂，在球磨频率为25～30HZ的条件下行星球磨6～12小时，添加所述粘合剂和所述增稠剂，在球磨频率为25～30HZ的条件下行星球磨6～12小时，得到所述瓷体材料。
  7. 如权利要求6所述的片式压敏电阻器的制备方法，其特征在于，将所述瓷体材料制成片式压敏电阻器的步骤包括：将所述瓷体材料按预设结构制成生胚膜后，印刷内电极，依次进行叠层工序、温水压工序、切割工序、排胶工序、烧结工序、端电极工序及电镀工序，制得片式压敏电阻器。
  8. 如权利要求7所述的片式压敏电阻器的制备方法，其特征在于，所述烧结工序的温度不低于850℃，且不高于900℃；
    和/或，所述端电极工序采用的银浆中银含量为60～70％，烧银温度为600～800℃。
  9. 一种片式压敏电阻器，其特征在于，所述片式压敏电阻器的瓷体材料包括主晶相材料和添加剂，所述添加剂包括摩尔比为(1.0～2.0):(1.0～2.0):(0.4～0.8):(0.4～0.8):(0.4～0.8):(1.0～2.0):(0.8～1.6):(0.2～0.8):(0.01～0.05):(0.02～0.08)的Bi2O3、Sb2O3、MnO2、Cr2O3、Co2O3、H3BO3、Zn3(PO4)2·4H2O、Nb2O5、AgNO3和Al(NO3)3·9H2O。
  10. 一种电子设备，其特征在于，所述电子设备中包含有如权利要求1～8任一项所述方法制备的片式压敏电阻器，或者如权利要求9所述的片式压敏电阻器。
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