CN1694187A - 纳米材料制备的多层片式ZnO压敏电阻器及其制造方法 - Google Patents
纳米材料制备的多层片式ZnO压敏电阻器及其制造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 239000002086 nanomaterial Substances 0.000 title claims description 38
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- 230000000996 additive effect Effects 0.000 claims abstract description 21
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- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical group [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 70
- 239000010410 layer Substances 0.000 claims description 37
- 239000000919 ceramic Substances 0.000 claims description 35
- 229910052763 palladium Inorganic materials 0.000 claims description 35
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- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 claims description 14
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- BNGXYYYYKUGPPF-UHFFFAOYSA-M (3-methylphenyl)methyl-triphenylphosphanium;chloride Chemical compound [Cl-].CC1=CC=CC(C[P+](C=2C=CC=CC=2)(C=2C=CC=CC=2)C=2C=CC=CC=2)=C1 BNGXYYYYKUGPPF-UHFFFAOYSA-M 0.000 claims 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 1
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- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 83
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- TYIXMATWDRGMPF-UHFFFAOYSA-N dibismuth;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Bi+3].[Bi+3] TYIXMATWDRGMPF-UHFFFAOYSA-N 0.000 description 1
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- 239000011573 trace mineral Substances 0.000 description 1
- 235000013619 trace mineral Nutrition 0.000 description 1
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Abstract
本发明公开了一种纳米材料制备的多层片式ZnO压敏电阻器，一种纳米材料制备的ZnO瓷料和内电极层交错排布共同烧结而成，其主要特点是ZnO瓷料的主体材料的颗粒形貌为球形或近似球形，平均粒径为1～99nm的ZnO纳米粉体，加入3～8％(摩尔百分比)的颗粒形貌为球形或近似球形的纳米粉体添加剂，所述的内电极层是钯/银内电极层，其中钯的比例占钯/银内电极重量的11～25％，银的比例占钯/银内电极重量的75～89％，该ZnO瓷料和钯/银内电级层交错排布，并在950～1100℃的温度范围内烧结而成。本发明还公开了一种上述纳米材料制备的多层片式ZnO压敏电阻器的制造方法。本发明制备的1005规格的多层片式ZnO压敏电阻器的非线性系数α大于20，漏电流IL小于2.0微安。
Description
技术领域
本发明涉及一种多层片式压敏电阻器，特别是涉及一种纳米材料制备的多层片式ZnO压敏电阻器；本发明还涉及这种纳米材料制备的多层片式ZnO压敏电阻器的制造方法。
背景技术
在现有的技术中，压敏电阻器按烧结温度可分为高温烧成和低温烧成：高温烧成为1150℃～1250℃；低温烧成为900℃左右的低温段。传统的多层片式ZnO压敏电阻器瓷料的烧成温度超过1150℃，因此必须用银钯、银铂等贵金属含量较高的昂贵电极浆料，成本较高。高温烧结所用的内电极是70％银/30％钯内电极，甚至用纯钯或者纯铂内电极，贵金属韵含量比较高，内电极的成本高，因而生产成本高。国外比较多专利报道高温烧成的压敏电阻器。低温烧成使用钯/银或纯银内电极，成本比较低。降低压敏电阻器瓷体的烧结温度的途径主要有两种：一种为使用纳米材料；国内外尚未发现有关纳米材料制备多层片式ZnO压敏电阻器的专利报道。另一种为调整配方，添加降低烧结温度的元素添加剂，但这势必使压敏电阻的性能变差，而且大多低温烧成的瓷料中均需要添加一定量的有毒元素铅，来达到降温烧成的目的。如美国专利US5973589“可低温烧结的ZnO压敏电阻器”，主要通过在配方中添加V2O5，使多层片式压敏电阻器可在900～950℃的温度范围内烧结，从而降低多层压敏电阻瓷体中钯/银内电极中贵金属钯的含量，降低生产成本高，但配方中需添加有毒元素铅。日本专利(特开平9-320814)报道的是低温与纯银电极共烧。该“氧化锌压敏电阻器的制造”专利提出把三氧化二铋与三氧化二锑等微量添加剂预先在350℃～730℃预烧，可实现与纯银内电极共烧。中国专利CN1564270A“低温烧结ZnO多层片式压敏电阻器及其制造方法”，公开了一种低温烧结添加剂(主要由Bi2O3、Sb2O3、B2O3、TiO2组成)来降低压敏电阻陶瓷烧结温度的方法，但B2O3与水起反应，使球磨混料工艺中的材料处理困难，TiO2会减小压敏电阻的非线性系数及增加压敏电阻的漏流，使压敏电阻的性能变差。
发明内容
本发明的目的在于提供一种生产成本低，且可靠性高的纳米材料制备的多层片式ZnO压敏电阻器。
本发明的另一目的在于提供一种上述纳米材料制备的多层片式ZnO压敏电阻器的制造方法。
本发明的第一个目的通过以下技术方案予以实现。
本发明的一种纳米材料制备的多层片式ZnO压敏电阻器，它是由ZnO瓷料和内电极层交错排布烧结而成，其特征在于：所述的ZnO瓷料的主体材料为平均粒径为1～99nm的ZnO纳米粉体，加入3～8％(摩尔百分比)的纳米粉体添加剂，所述的内电极层是钯/银内电极层，其中钯的比例占钯/银内电极重量的11～25％，银的比例占钯/银内电极重量的75～89％，该ZnO瓷料和钯/银内电级层交错排布，并在950～1100℃的温度范围内烧结而成。由于采用了ZnO纳米粉体，使产品的微观结构均匀性大大改善，对提高压敏电阻器通流容量重要指标特别有利；由于在钯/银内电极中大大降低了贵重金属钯的使用量，使得本发明可以在实现纳米材料制备和降低成本的同时，克服了因纯银内电极中的银离子容易迁移而造成压敏电阻可靠性较差的缺陷。较好地兼容解决了瓷料与电极的低温共烧以及提高产品性能两个相互制约的问题，并且在瓷料中不添加任何形式的有毒元素-铅。
为进一步提高本发明的性能，可在上述ZnO瓷料中加入3～8％(摩尔百分比)的纳米粉体添加剂，所述的纳米粉体添加剂的颗粒形貌为球形或近似球形，平均粒径为1～99nm，最佳为30～50nm，纳米粉体添加剂主要由Bi2O3、Sb2O3、MnCO3、SiO2、Cr2O3、Co3O4、Ni2O3中的任意五种或五种以上组合而成。所述的纳米粉体添加剂在ZnO瓷料中所占比例为3～8％(摩尔百分比)，其中纳米Bi2O30.1～2％、Sb2O30.5～2％、MnCO30.1～1％、SiO20.01～2％、Cr2O30.01～1％、Co3O40.1～1.5％、Ni2O30.1～1.5％(摩尔百分比)。
本发明的第二个目的通过以下技术方案予以实现：
一种上述纳米材料制备的多层片式ZnO压敏电阻器的制造方法，它包括以下步骤：
(1)配料；
(2)将配好的物料添加溶剂(二甲苯或乙醇)、粘合剂、分散剂球磨混合，使其成为为流延浆料；
(3)将流延浆料流延制得陶瓷膜带；
(4)对陶瓷膜带稍稍施压，制成陶瓷膜带保护层；
(5)在陶瓷膜带保护层的内端面上印刷内电极；
(6)在内电极上再覆盖一层陶瓷膜带形成有效层；
(7)在有效层上印刷与前次印刷的内电极错位的内电极；
(8)重复步骤(6)和步骤(7)，直到有效层的数目达到设计要求的巴块；
(9)重复步骤(4)，制成陶瓷膜带上保护层；
(10)将巴块等静压，切割巴块成为生坯片；
(11)将生坯片加热排胶；
(12)将排胶后的生坯在950～1100℃的温度范围内烧成。
(13)将烧成后的片式压敏电阻瓷片在球磨机中加磨料球磨，消除压敏电阻瓷片锐角，进行倒角工艺。
(14)将倒角后的压敏电阻瓷片涂端电极(钯/银)。
(15)将涂过端电极的压敏电阻瓷片进行烧银处理。
所述的步骤(1)配料，是在92-97％(摩尔百分比)的ZnO粉体中添加3-8％(摩尔百分比)的其它由金属组成的纳米粉体添加剂，所述的纳米材料的颗粒形貌为球形或近似球形，可为下列三种组成的任一种情况：(1)由单一的ZnO纳米粉体和单一的纳米粉体添加剂Bi2O3、Sb2O3、MnCO3、SiO2、Cr2O3、Co3O4、Ni2O3氧化物中的任意五种或五种以上组合的纳米粉体组成；(2)由通过化学法合成或其它方法合成的按配方规定的主要含Zn和Bi、Sb、Mn、Si、Cr、Co、Ni元素中的任意五种或五种以上组合的复合纳米氧化物粉体组成；(3)由单一的ZnO纳米粉体和由通过化学法合成或其它方法合成的按配方规定的含Bi、Sb、Mn、Si、Cr、Co、Ni元素中的任意五种或五种以上组合的复合纳米氧化物添加剂粉体组成。
所述的纳米粉体添加剂的颗粒形貌为球形或近似球形，平均粒径为1～99nm，最佳为30～50nm，纳米粉体添加剂主要由Bi2O3、Sb2O3、MnCO3、SiO2、Cr2O3、Co3O4、Ni2O3中的任意五种或五种以上组合而成。所述的纳米粉体添加剂在ZnO瓷料中所占比例为3～8％(摩尔百分比)，其中纳米Bi2O30.1～2％、Sb2O30.5～2％、MnCO30.1～1％、SiO20.01～2％、Cr2O30.01～1％、Co3O40.1～1.5％、Ni2O30.1～1.5％(摩尔百分比)。
所述的步骤(3)是消泡流延出5-50μm的厚度均匀的陶瓷膜带。
所述的步骤(4)是将步骤(3)中的部分陶瓷膜带预压成3-20倍单层陶瓷膜带厚度的保护层。
所述的步骤(5)中的内电极是钯/银内电极，其中钯的比例占钯/银内电极重量的11～25％，银的比例占钯/银内电极重量的75～89％。
所述的步骤(6)是在步骤(5)中的钯/银内电极上覆盖一层陶瓷膜带，并稍微加压而形成。
所述的步骤(12)优选在960-1060℃的温度范围内烧结而成。
纳米材料是一种高性能新材料，通常认为纳米是指三维中任意一维的长度小于100nm，由于其纳米尺寸效应表现出许多优异的性能，如纳米磁性材料具有很大的磁化率等，用纳米材料制备电子元器件，可使电子元器件的性能大幅提高。如用纳米材料制备出的敏感元件，其灵敏度比用普通材料高许多；纳米材料还具有降低陶瓷的烧结温度、改善陶瓷产品的脆性等优点。对于多层片式ZnO压敏电阻，使用纳米材料可以大大降低烧结温度，可采用低温电极材料，极大地度降低产品的成本费用。同时，随着片式元件尺寸的缩小，瓷体厚度越来越小(＜10um)，就要求ZnO压敏电阻薄膜更加均匀一致，粉粒更加细小均匀。应用纳米材料，有利于获得均匀的ZnO压敏电阻薄膜。因此，用纳米材料制备片式元件，是一种获得高性能、低成本器件的有效途径。
本发明的优点是：(1)由于采用了ZnO纳米粉体，使产品的微观结构均匀性大大改善，对提高压敏电阻器通流容量重要指标特别有利。(2)采用颗粒粒径较小的纳米粉体，从而实现了不改变传统配方和不添加有毒元素铅而达到较低温度制备的目的。(3)在制造过程中，ZnO瓷料不需经过预烧处理，节省了生产步骤，提高了效率，最重要的是确保了配比的准确性。(4)由于在钯/银内电极中大大降低了的贵重金属钯的使用量，在降低成本的同时，并且克服了因纯银内电极中的银离子容易迁移而造成压敏电阻器可靠性较差的缺陷，较好地兼容解决了瓷料与电极的低温共烧以及提高产品性能两个相互制约的问题。(5)制成的多层片式ZnO压敏电阻器的V1mA在3-120V之间可任意调整，非线性系数α大于20，漏电流IL小于2微安。该多层片式ZnO压敏电阻器具有体积小，温度特性好，非线性系数高，成本低，适用于表面安装等优点。
附图说明
图1是本发明的纳米材料制备的多层片式ZnO压敏电阻器的结构示意图；
图2本发明的制造方法的流程图。
具体实施方式
下面结合附图和具体实施例对本发明作进一步的说明。
实施例一
如图1所示结构、图2所示的制造方法流程，以及按照配方表一，准确称取平均粒径为99nm的纳米ZnO粉料和平均粒径为99nm的各种纳米粉体添加剂的氧化物，将称好的物料放入球磨机里并加入适量的二甲苯、粘合剂、分散剂和锆球，球磨12个小时得到流延浆料，然后流延出厚度为25微米的陶瓷膜带，十层陶瓷膜带稍微加压制得厚度约为250微米的膜带保护层a，在膜带保护层a上印刷重量比为75％银、25％钯的合金内电极b，叠层后再错位印刷另一层内电极，直至有效层c为8层，经过等静水压后切割出烧结后尺寸为1.0×0.5mm的生坯，把这些生坯放在专用的承烧板上放入炉内，缓慢升温(30℃/hr)至350℃保温3个小时，后再缓慢升温(30℃/hr)至550℃保温5个小时，排完胶后在1100℃保温2个小时，然后涂上端电极d，得到V1mA为10V，非线性系数为25，漏电流为1.5微安的纳米材料制备的多层片式ZnO压敏电阻器。
表一、实施例一配方表
| 物料名称 | ZnO | Bi2O3 | Sb2O3 | Ni2O3 | SiO2 | Co3O4 | Cr2O3 | MnCO3 | Al2O3 |
| 比例(摩尔％) | 94.99 | 0.5 | 1.0 | 1.0 | 0.5 | 1.0 | 0.5 | 0.5 | 0.01 |
实施例二
如图1所示结构、图2所示的制造方法流程，以及按照配方表二，准确称取平均粒径为1nm的纳米ZnO粉料和平均粒径为1nm的各种纳米粉体添加剂的氧化物，将称好的物料放入球磨机里并加入适量的二甲苯、粘合剂、分散剂和锆球，球磨12个小时得到流延浆料，然后流延出厚度为25微米的陶瓷膜带，十层陶瓷膜带稍微加压制得厚度约为250微米的膜带保护层a，在膜带保护层a上印刷重量比为89％银、11％钯的合金内电极b，叠层后再错位印刷另一层内电极，直至有效层c为8层，经过等静水压后切割出烧结后尺寸为1.0×0.5mm的生坯，把这些生坯放在专用的承烧板上放入炉内，缓慢升温(30℃/hr)至350℃保温3个小时，后再缓慢升温(30℃/hr)至550℃保温5个小时，排完胶后在950℃保温2个小时，然后涂上端电极d，得到V1mA为10V，非线性系数为23，漏电流为0.7微安的纳米材料制备的多层片式ZnO压敏电阻器。
表二、实施例二配方表
| 物料名称 | ZnO | Bi2O3 | Sb2O3 | Co3O4 | Cr2O3 | MnCO3 |
| 比例(摩尔％) | 97.0 | 0.5 | 0.5 | 1.0 | 0.5 | 0.5 |
实施例三
如图1所示结构、图2所示的制造方法流程，准确称取按照配方表三所规定的已制备好的平均粒径为40nm的含Zn和Bi、Sb、Mn、Si、Cr、Co、Ni、Al等元素的复合纳米氧化物粉体，将称好的物料放入球磨机里并加入适量的二甲苯、粘合剂、分散剂和锆球，球磨12个小时得到流延浆料，然后流延出厚度为25微米的陶瓷膜带，十层陶瓷膜带稍微加压制得厚度约为250微米的膜带保护层a，在膜带保护层a上印刷重量比为85％银、15％钯的合金内电极b，叠层后再错位印刷另一层内电极，直至有效层c为8层，经过等静水压后切割出烧结后尺寸为1.0×0.5mm的生坯，把这些生坯放在专用的承烧板上放入炉内，缓慢升温(30℃/hr)至350℃保温3个小时，后再缓慢升温(30℃/hr)至550℃保温5个小时，排完胶后在1000℃保温2个小时，然后涂上端电极d，得到V1mA为10V，非线性系数为27，漏电流为1.7微安的纳米材料制备的多层片式ZnO压敏电阻器。
表三、实施例三配方表
| 物料名称 | ZnO | Bi2O3 | Sb2O3 | Ni2O3 | SiO2 | Co3O4 | Cr2O3 | MnCO3 | Al2O3 |
| 比例(摩尔％) | 92 | 2 | 2 | 1.29 | 0.01 | 1.5 | 1 | 0.1 | 0.1 |
实施例四
如图1所示结构、图2所示的制造方法流程，以及按照配方表四，准确称取平均粒径为40nm的纳米ZnO粉料和平均粒径为40nm的复合纳米氧化物添加剂粉体，将称好的物料放入球磨机里并加入适量的二甲苯、粘合剂、分散剂和锆球，球磨12个小时得到流延浆料，然后流延出厚度为25微米的陶瓷膜带，十层陶瓷膜带稍微加压制得厚度约为250微米的膜带保护层a，在膜带保护层a上印刷重量比为85％银、15％钯的合金内电极b，叠层后再错位印刷另一层内电极，直至有效层c为8层，经过等静水压后切割出烧结后尺寸为1.0×0.5mm的生坯，把这些生坯放在专用的承烧板上放入炉内，缓慢升温(30℃/hr)至350℃保温3个小时，后再缓慢升温(30℃/hr)至550℃保温5个小时，排完胶后在1000℃保温2个小时，然后涂上端电极d，得到V1mA为10V，非线性系数为26，漏电流为1.4微安的纳米材料制备的多层片式ZnO压敏电阻器。
表四、实施例四配方表
| 物料名称 | ZnO | Bi2O3 | Sb2O3 | Ni2O3 | SiO2 | Co3O4 | Cr2O3 | MnCO3 | Al2O3 |
| 比例(摩尔％) | 94.78 | 0.1 | 0.5 | 1.5 | 2.0 | 0.1 | 0.01 | 1 | 0.01 |
比较例
按照配方表五，准确称取各种物料，各种氧化物材料的平均粒度均在5微米以下。将称好的物料放入搅拌球磨机里，加入适量的去离子水和锆球，球磨6个小时可得到平均粒径为0.50微米的物料。将球磨好的物料放在不锈钢盘里于120℃左右烘干10个小时后，加入适量加入适量的二甲苯、粘合剂、分散剂和锆球，球磨24个小时制得均匀稳定的流延浆料。然后流延出厚度为25微米的陶瓷膜带，十层陶瓷膜带稍微加压制得厚度约为250微米的膜带保护层a，在膜带保护层a上印刷重量比为70％银、30％钯的合金内电极b，叠层后再错位印刷另一层内电极，直至有效层c为8层，经过等静水压后切割出烧结后尺寸为1.0×0.5mm的生坯，把这些生坯放在专用的承烧板上放入炉内，缓慢升温(30℃/hr)至350℃保温3个小时，后再缓慢升温(30℃/hr)至550℃保温5个小时，排完胶后在1150℃保温2个小时，然后涂上端电极d，得到V1mA为8V，非线性系数为22，漏电流为1.8微安的传统材料(非纳米材料)制备的多层片式ZnO压敏电阻器。
表五、比较例配方表
| 物料名称 | ZnO | Bi2O3 | Sb2O3 | Ni2O3 | SiO2 | Co3O4 | Cr2O3 | MnCO3 | Al2O3 |
| 比例(摩尔％) | 94.99 | 0.5 | 1.0 | 1.0 | 0.5 | 1.0 | 0.5 | 0.5 | 0.01 |
Claims (10)
1、一种纳米材料制备的多层片式ZnO压敏电阻器，它是由ZnO瓷料和内电极层交错排布共同烧结而成，其特征在于：所述的ZnO瓷料的主要材料为平均粒径为1～99nm的ZnO纳米粉体，加入3～8％(摩尔百分比)的纳米粉体添加剂，所述的内电极层是钯/银内电极层，其中钯的比例占钯/银内电极重量的11～25％，银的比例占钯/银内电极重量的75～89％，该ZnO瓷料和钯/银内电极层交错排布，并在950～1100℃的温度范围内烧结而成。
2、根据权利要求1所述的纳米材料制备的多层片式ZnO压敏电阻器，其特征在于：所述的ZnO粉体的颗粒形貌为球形或近似球形，平均粒径为1～99nm，最佳为30～50nm，在ZnO瓷料中所占比例为92～97％(摩尔百分比)。
3、根据权利要求1所述的纳米材料制备的多层片式ZnO压敏电阻器，其特征在于：所述的纳米粉体添加剂的颗粒形貌为球形或近似球形，平均粒径为1～99nm，最佳为30～50nm，纳米粉体添加剂主要由Bi2O3、Sb2O3、MnCO3、SiO2、Cr2O3、Co3O4、Ni2O3中的任意五种或五种以上组合而成。
4、根据权利要求1或3所述的纳米材料制备的多层片式ZnO压敏电阻器，其特征在于：所述的纳米粉体添加剂在ZnO瓷料中所占比例为3～8％(摩尔百分比)，其中纳米Bi2O30.1～2％、Sb2O30.5～2％、MnCO30.1～1％、SiO20.01～2％、Cr2O30.01～1％、Co3O40.1～1.5％、Ni2O30.1～1.5％(摩尔百分比)。
5、根据权利要求1或3所述的纳米材料制备的多层片式ZnO压敏电阻器，其特征在于：所述的纳米材料由单一的ZnO纳米粉体和单一的纳米粉体添加剂Bi2O3、Sb2O3、MnCO3、SiO2、Cr2O3、Co3O4、Ni2O3等氧化物中的任意五种或五种以上组合的纳米粉体组成。
6、根据权利要求1或3所述的纳米材料制备的多层片式ZnO压敏电阻器，其特征在于：所述的纳米材料由通过化学法合成或其它方法合成的按配方规定的主要含Zn和Bi、Sb、Mn、Si、Cr、Co、Ni元素中的任意五种或五种以上组合的复合纳米氧化物粉体组成。
7、根据权利要求1或3所述的纳米材料制备的多层片式ZnO压敏电阻器，其特征在于：所述的纳米材料由单一的ZnO纳米粉体和由通过化学法合成或其它方法合成的按配方规定的含Bi、Sb、Mn、Si、Cr、Co、Ni元素中的任意五种或五种以上组合的复合纳米氧化物添加剂粉体组成。
8、一种权利要求1所述的纳米材料制备的多层片式ZnO压敏电阻器的制造方法，它包括以下步骤：(1)配料；(2)将配好的物料添加溶剂(二甲苯或乙醇)、粘合剂、分散剂球磨混合，使其成为为流延浆料；(3)将流延浆料流延制得陶瓷膜带；(4)对陶瓷膜带稍稍施压，制成陶瓷膜带下保护层；(5)在陶瓷膜带保护层的内端面上印刷内电极；(6)在内电极上再覆盖一层陶瓷膜带形成有效层；(7)在有效层上印刷与前次印刷的内电极错位的内电极；(8)重复步骤(6)和步骤(7)，直到有效层的数目达到设计要求的巴块；(9)重复步骤(4)，制成陶瓷膜带上保护层；(10)将巴块等静压，把巴块切割成为生坯片；(11)将生坯片加热排胶；(12)将排胶后的生坯在950～1100℃的温度范围内烧成；(13)将烧成后的片式压敏电阻瓷片在球磨机中加磨料球磨，消除压敏电阻瓷片锐角，进行倒角工艺；(14)将倒角后的压敏电阻瓷片涂端电极(钯/银)；(15)将涂过端电极的压敏电阻瓷片进行烧银处理。
9、根据权利要求6所述的纳米材料制备的多层片式ZnO压敏电阻器的制造方法，其特征在于：所述的步骤(1)中可以添加占配料0.001～0.1％(摩尔百分比)的硝酸铝(或含等摩尔铝元素的Al2O3)，所述的步骤(5)中的内电极是钯-银内电极，其中钯的比例占钯/银内电极重量的11～25％，银的比例占钯/银内电极重量的75～89％。
10、根据权利要求6所述的纳米材料制备的多层片式ZnO压敏电阻器的制造方法，其特征在于：所述的步骤(12)是在950～1100℃的温度范围内采用瓷体与内电极共烧工艺烧结而成。
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