WO2023280314A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2023280314A1
WO2023280314A1 PCT/CN2022/104688 CN2022104688W WO2023280314A1 WO 2023280314 A1 WO2023280314 A1 WO 2023280314A1 CN 2022104688 W CN2022104688 W CN 2022104688W WO 2023280314 A1 WO2023280314 A1 WO 2023280314A1
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WIPO (PCT)
Prior art keywords
transistor
node
capacitor
pole
control
Prior art date
Application number
PCT/CN2022/104688
Other languages
English (en)
French (fr)
Inventor
刘苗
郝学光
许静波
姚星
王景泉
吴新银
李新国
王志冲
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/275,012 priority Critical patent/US20240112623A1/en
Priority to KR1020237028712A priority patent/KR20240032702A/ko
Priority to EP22837059.9A priority patent/EP4280202A1/en
Publication of WO2023280314A1 publication Critical patent/WO2023280314A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • This article relates to but not limited to the field of display technology, especially a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT Thin Film Transistor
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • an embodiment of the present disclosure provides a display substrate, including: a base substrate and a scan driving control circuit disposed in a non-display area of the base substrate.
  • the scanning driving control circuit includes: an input circuit, an output control circuit and an output circuit.
  • the output control circuit is connected with the input circuit and the output circuit.
  • the output control circuit includes: a first node control capacitor and a second node control capacitor. The length L C1k of the first node control capacitor in the first direction, the length L C2k of the second node control capacitor in the first direction, and the length L Y of the scan driving control circuit in the first direction satisfy :
  • the first node control capacitor includes: a first capacitor and a third capacitor.
  • the lengths of the first capacitor, the third capacitor, the second node control capacitor and the scan drive control circuit in the first direction satisfy:
  • L C1 is the length of the first capacitor in the first direction
  • L C3 is the length of the third capacitor in the first direction
  • L C2k is the length of the second node control capacitor in the first direction
  • the length, LY is the length of the scan driving control circuit in the first direction.
  • the length of the first capacitor and the scan driving control circuit in the first direction satisfies:
  • the length of the second node control capacitor and the scan drive control circuit in the first direction satisfies:
  • the lengths of the third capacitor and the scan driving control circuit in the first direction satisfy:
  • the lengths of the first capacitor, the second node control capacitor, and the third capacitor in the first direction satisfy:
  • the third capacitor is connected to the first power line; the projection of the third capacitor and the first power line on the base substrate overlaps, and the overlapping area satisfies:
  • S C3 is the projected area of the third capacitor on the base substrate
  • S C3-1 is the overlapping area of the projection of the third capacitor and the first power line on the base substrate
  • the second node control capacitor includes a second capacitor
  • S C2 is a projected area of the second capacitor on the substrate.
  • the second node control capacitor overlaps with the projection of the first power line on the base substrate, and the overlapping area satisfies:
  • S C2k-1 is the overlapping area of the second node control capacitor and the projection of the first power line on the substrate
  • X2 is the length of the first power line in the first direction
  • L5 The length in the second direction of the overlapping region of one of the capacitances of the second node control capacitor and the projection of the first power line on the substrate; the second direction intersects the first direction .
  • the input circuit is connected to the second power line; the second node control capacitor overlaps with the projection of the second power line on the substrate, and the overlapping area satisfies:
  • S C2k-2 is the overlapping area of the second node control capacitor and the projection of the second power line on the substrate
  • X3 is the length of the second power line in the first direction
  • L6 The length in the second direction of the overlapping area of one of the capacitances of the second node control capacitor and the projection of the second power line on the substrate; the second direction intersects the first direction .
  • the projection of the first capacitor on the base substrate is located between the projections of the first power line and the second power line on the base substrate.
  • the distance L7 between the center of the first capacitor in the first direction and the side of the first power line away from the first capacitor in the first direction is greater than that of the first capacitor in the first direction
  • the distance L8 between the center of the second power line and the side of the second power line close to the first capacitor in the first direction and L7 ⁇ 2*L8.
  • the input circuit includes: a first transistor; the control pole of the first transistor is connected to the first clock signal line, the first pole is connected to the signal input terminal, and the second pole is connected to the second node connect.
  • the active layer of the first transistor is adjacent to the second power line.
  • the distance L2 between the side of the channel region of the active layer of the first transistor close to the second power supply line and the side of the second power supply line away from the first transistor satisfies: 0 ⁇ L2 ⁇ 4W PL2 ; wherein, W PL2 is the width of the second power line.
  • the input circuit includes: a third transistor; the control electrode of the third transistor is connected to the first clock signal line, the first electrode is connected to the second power line, the second electrode is connected to the third node connection.
  • the second power line is located on a side of the third transistor away from the first clock signal line or the second clock signal line.
  • the distance L3 between the side of the channel region of the active layer of the third transistor close to the second power line and the side of the second power line away from the third transistor satisfies: 0 ⁇ L3 ⁇ 4W PL2 ; wherein, W PL2 is the width of the second power line.
  • the input circuit is connected to the first clock signal line and the second power supply line, and the output control circuit is connected to the second clock signal line;
  • the input circuit includes: a second transistor; the The control pole of the second transistor is connected to the second node, the first pole is connected to the first clock signal line, and the second pole is connected to the third node.
  • the second power line is located on a side of the second transistor away from the first clock signal line.
  • the active layer of the second transistor is adjacent to the second power line; the side of the channel region of the active layer of the second transistor close to the second power line is away from the second power line
  • the distance L4 between the sides of the second transistor satisfies: 0 ⁇ L4 ⁇ 3W PL2 ; wherein, W PL2 is the width of the second power line.
  • the output control circuit includes: a first output control sub-circuit.
  • the first output control sub-circuit includes: a fourth transistor and a fifth transistor; the control pole of the fourth transistor is connected to the second node, the first pole of the fourth transistor is connected to the second pole of the fifth transistor, and the control pole of the fourth transistor is connected to the second pole of the fifth transistor.
  • the second pole of the four transistors is connected to the second clock signal line; the control pole of the fifth transistor is connected to the third node, and the first pole is connected to the first power line.
  • the fourth transistor and the fifth transistor are located on a side of the second power line away from the second clock signal line.
  • the included angle between the extending direction of the active layer of the fourth transistor and the extending direction of the active layer of the fifth transistor is greater than 85° and less than 95°.
  • the width W T4 of the channel region of the active layer of the fourth transistor and the width W T5 of the channel region of the active layer of the fifth transistor satisfy: 2W T4 ⁇ W T5 .
  • the angle between the extending direction of the active layer of the fourth transistor and the extending direction of the active layer of the first transistor of the input circuit is greater than 85° and less than 95°.
  • the output control circuit includes a second output control subcircuit, and the second output control subcircuit includes a seventh transistor.
  • the control electrode of the seventh transistor is connected to the second electrode of the first capacitor, and the first electrode of the seventh transistor is connected to the first node.
  • the seventh transistor is adjacent to the first capacitor, and the seventh transistor is located between the first capacitor and the first power line.
  • the second output control subcircuit further includes: a sixth transistor; the control electrode of the sixth transistor is connected to the first electrode of the first capacitor, and the second electrode of the sixth transistor is connected to the first electrode of the first capacitor.
  • the second poles of the seven transistors are connected, and the first pole of the sixth transistor is connected with the second signal terminal.
  • the extending direction of the active layer of the seventh transistor is approximately parallel to the extending direction of the active layer of the sixth transistor.
  • the output control circuit includes: a third output control subcircuit, the third output control subcircuit includes an eighth transistor and a third capacitor; the control electrode of the eighth transistor is connected to the second The nodes are connected, the first pole is connected to the first power line, the second pole is connected to the first node; the first pole of the third capacitor is connected to the first node, and the second pole is connected to the first power line.
  • the input circuit includes a first transistor. The first transistor, the eighth transistor and the third capacitor are sequentially arranged along the first direction, and the extending direction of the active layer of the first transistor is similar to the extending direction of the active layer of the eighth transistor parallel.
  • the distance L9 between the side of the active layer of the eighth transistor close to the third capacitor and the side of the third capacitor close to the eighth transistor satisfies: W CLK ⁇ L9 ⁇ W PL1 ; Wherein, W CLK is the width of the clock signal line, and W PL1 is the width of the first power line.
  • the input circuit is connected to the first clock signal line; the output control circuit is connected to the second clock signal line and the first power line; the output circuit is connected to the first power line and the third Power cord connection.
  • the first clock signal line, the second clock signal line, the initial signal line, the first power line and the third power line are sequentially arranged along the first direction.
  • the capacitance values of the first capacitor, the third capacitor and the second node control capacitor satisfy:
  • C 1 is the capacitance value of the first capacitor
  • C 3 is the capacitance value of the third capacitor
  • C 2k is the capacitance value of the second node control capacitor.
  • the first pole of the first capacitor is connected to the third node, and the second pole of the first capacitor is connected to the seventh transistor.
  • a first pole of the third capacitor is connected to the first node, and a second pole of the third capacitor is connected to the first power line.
  • the first pole of the second node control capacitor is connected to the second node. The sum of the capacitance values of the first capacitor and the third capacitor is smaller than the capacitance value of the second node control capacitor.
  • the second node control capacitor includes a second capacitor, a first pole of the second capacitor is connected to the second node, and a second pole of the second capacitor is connected to the signal output end.
  • the second node control capacitor further includes: a fourth capacitor, the first pole of the fourth capacitor is connected to the second node, and the second pole of the fourth capacitor is connected to the fourth transistor connected to the fifth transistor.
  • the first pole of the second capacitor of the current scan driving control circuit and the first pole of the fourth capacitor of the next scan driving control circuit have an integral structure.
  • the output circuit includes a tenth transistor; the second node control capacitor includes a second capacitor, and the first pole of the second capacitor is integrated with the control pole of the tenth transistor.
  • an embodiment of the present disclosure provides a display device, including the above-mentioned display substrate.
  • an embodiment of the present disclosure provides a display substrate including a scan driving control circuit.
  • the scan driving control circuit includes: an input circuit, an output control circuit and an output circuit.
  • the input circuit is connected to the signal input terminal, the first clock signal terminal, the first voltage terminal and the output control circuit, configured to transmit the signal at the signal input terminal to the output control circuit under the control of the first clock signal terminal, and The signal of the first clock signal terminal or the first voltage terminal is transmitted to the output control circuit.
  • the output control circuit is connected to the first signal terminal, the second signal terminal, the second clock signal terminal, the second voltage terminal, the first node, the second node and the input circuit, and is configured to store The signal of the first signal terminal, under the control of the input circuit and the second clock signal terminal, transmits the signal of the second signal terminal to the first node; or, under the control of the input circuit, stores the signal of the second clock signal terminal, and transmits the signal at the second Under the control of the node, the signal of the second voltage terminal is transmitted to the first node.
  • the output circuit is connected to the first voltage terminal, the second voltage terminal, the signal output terminal, the first node and the second node, and is configured to output the signal of the first voltage terminal to the signal output terminal under the control of the second node, Or, under the control of the first node, the signal of the second voltage terminal is output to the signal output terminal.
  • the input circuit includes: a first input subcircuit and a second input subcircuit;
  • the output control circuit includes: a first output control subcircuit, a second output control subcircuit and a third output A control subcircuit;
  • the output circuit includes: a first output subcircuit and a second output subcircuit.
  • the first input subcircuit is connected to the signal input terminal, the first clock signal terminal and the first output control subcircuit, and is configured to transmit the signal of the signal input terminal to the first output control subcircuit under the control of the first clock signal terminal circuit.
  • the second input subcircuit is connected to the first voltage terminal, the first clock signal terminal, the first input subcircuit and the second output control subcircuit, and is configured to be controlled by the first input subcircuit or the first clock signal terminal , transmitting the signal of the first clock signal terminal or the first voltage terminal to the second output control sub-circuit.
  • the first output control subcircuit is connected to the first signal terminal, the second clock signal terminal, the second node, the first input subcircuit and the second input subcircuit, and is configured to be connected to the first input subcircuit or the second input subcircuit Under the control of the sub-circuit, the signal of the first signal terminal or the second clock signal terminal is stored.
  • the second output control subcircuit is connected to the second signal terminal, the second clock signal terminal, the first node and the second input subcircuit, and is configured to, under the control of the second input subcircuit and the second clock signal terminal, send The first node transmits the signal of the second signal terminal.
  • the third output control subcircuit is connected to the second voltage terminal, the first node and the second node, and is configured to transmit the signal of the second voltage terminal to the first node under the control of the second node.
  • the first output sub-circuit is connected to the first voltage terminal, the signal output terminal and the second node, and is configured to output the signal of the first voltage terminal to the signal output terminal under the control of the second node.
  • the second output sub-circuit is connected to the second voltage terminal, the signal output terminal and the first node, and is configured to output the signal of the second voltage terminal to the signal output terminal under the control of the first node.
  • the first input sub-circuit includes: a first transistor; the control pole of the first transistor is connected to the first clock signal terminal, the first pole is connected to the signal input terminal, and the second pole is connected to the signal input terminal.
  • the second node is connected.
  • the second input sub-circuit includes: a second transistor and a third transistor; the control pole of the second transistor is connected to the second node, the first pole is connected to the first clock signal terminal, and the second pole is connected to the third node ;
  • the control pole of the third transistor is connected to the first clock signal terminal, the first pole is connected to the first voltage terminal, and the second pole is connected to the third node.
  • the first output control sub-circuit includes: a fourth transistor and a fifth transistor; the control pole of the fourth transistor is connected to the second node, and the first pole of the fourth transistor is connected to the second clock signal terminal, so The second pole of the fourth transistor is connected to the second pole of the fifth transistor; the control pole of the fifth transistor is connected to the third node, and the first pole of the fifth transistor is connected to the first signal terminal.
  • the first output sub-circuit includes: a tenth transistor; the control pole of the tenth transistor is connected to the second node, the first pole is connected to the first voltage terminal, and the second pole is connected to the signal output terminal.
  • the first input sub-circuit includes: a first transistor; the control pole of the first transistor is connected to the first clock signal terminal, the first pole is connected to the signal input terminal, and the second pole is connected to the signal input terminal.
  • the fourth node is connected.
  • the second input sub-circuit includes: a second transistor and a third transistor; the control pole of the second transistor is connected to the fourth node, the first pole is connected to the first clock signal terminal, and the second pole is connected to the third node ;
  • the control pole of the third transistor is connected to the first clock signal terminal, the first pole is connected to the first voltage terminal, and the second pole is connected to the third node.
  • the first output control sub-circuit includes: a fourth transistor, a fifth transistor and an eleventh transistor; the control pole of the fourth transistor is connected to the second node, and the first pole of the fourth transistor is connected to the second clock connected to the signal terminal, the second pole of the fourth transistor is connected to the second pole of the fifth transistor; the control pole of the fifth transistor is connected to the third node, and the first pole is connected to the first signal terminal; The control electrode of the eleventh transistor is connected to the first voltage terminal, the first electrode is connected to the fourth node, and the second electrode is connected to the second node.
  • the first output sub-circuit includes: a tenth transistor; the control pole of the tenth transistor is connected to the second node, the first pole is connected to the first voltage terminal, and the second pole is connected to the signal output terminal.
  • the second output control sub-circuit further includes: a fourth capacitor; a first electrode of the fourth capacitor is connected to control electrodes of the fourth transistor and the tenth transistor.
  • the second pole of the fourth capacitor is connected to the fifth transistor.
  • the first output control sub-circuit further includes: a second capacitor; a first pole of the second capacitor is connected to a second node.
  • the second pole of the second capacitor is connected to the signal output terminal.
  • the second input sub-circuit is connected to a third node.
  • the second output control sub-circuit includes: a sixth transistor, a seventh transistor and a first capacitor.
  • the control pole of the sixth transistor is connected to the third node, the first pole of the sixth transistor is connected to the second signal terminal, and the second pole of the sixth transistor is connected to the second pole of the seventh transistor;
  • the control electrode of the seventh transistor is connected to the second clock signal terminal, and the first electrode is connected to the first node.
  • the first pole of the first capacitor is connected to the control pole of the sixth transistor, and the second pole is connected to the seventh transistor.
  • the second input sub-circuit is connected to a fifth node.
  • the second output control sub-circuit includes: a first capacitor, a sixth transistor, a seventh transistor and a twelfth transistor.
  • the control pole of the sixth transistor is connected to the third node, the first pole of the sixth transistor is connected to the second signal terminal, and the second pole of the sixth transistor is connected to the second pole of the seventh transistor;
  • the control electrode of the seventh transistor is connected to the second clock signal terminal, and the first electrode is connected to the first node.
  • the control pole of the twelfth transistor is connected to the first voltage terminal, the first pole is connected to the fifth node, and the second pole is connected to the third node.
  • the first pole of the first capacitor is connected to the control pole of the sixth transistor, and the second pole is connected to the seventh transistor.
  • the third output control subcircuit includes: an eighth transistor and a third capacitor.
  • the control pole of the eighth transistor is connected to the second node, the first pole is connected to the second voltage terminal, and the second pole is connected to the first node.
  • the first pole of the third capacitor is connected to the first node, and the second pole is connected to the second voltage terminal.
  • the second output sub-circuit includes: a ninth transistor; the control pole of the ninth transistor is connected to the first node, the first pole is connected to the second voltage terminal, and the second pole is connected to the signal output terminal.
  • the first signal terminal is connected to the second voltage terminal or the first clock signal terminal.
  • the second signal terminal is connected to the first voltage terminal or the second clock signal terminal.
  • an embodiment of the present disclosure provides a method for driving a display substrate, which is applied to the above-mentioned display substrate.
  • the driving method includes: the input circuit transmits the signal at the signal input terminal to the The output control circuit transmits the signal of the first clock signal terminal or the first voltage terminal to the output control circuit; the output control circuit stores the signal of the first signal terminal under the control of the input circuit, and the input circuit and the second clock signal Under the control of the terminal, the signal of the second signal terminal is transmitted to the first node, and the output circuit outputs the signal of the second voltage terminal to the signal output terminal under the control of the first node; the output control circuit is under the control of the input circuit, storing the signal of the second clock signal terminal, and transmitting the signal of the second voltage terminal to the first node under the control of the second node; the output circuit outputs the signal of the first voltage terminal to the signal output terminal under the control of the second node .
  • FIG. 1 is a schematic structural diagram of a scan driving control circuit according to at least one embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a scan driving control circuit according to at least one embodiment of the present disclosure
  • FIG. 3 is an equivalent circuit diagram of the first input subcircuit, the second input subcircuit, the first output control subcircuit and the first output subcircuit of the scan drive control circuit in at least one embodiment of the present disclosure
  • FIG. 4 is another equivalent circuit diagram of the first input subcircuit, the second input subcircuit, the first output control subcircuit and the first output subcircuit of the scan drive control circuit in at least one embodiment of the present disclosure
  • 5 is an equivalent circuit diagram of a second output control sub-circuit of the scan drive control circuit in at least one embodiment of the present disclosure
  • FIG. 6 is another equivalent circuit diagram of the second output control sub-circuit of the scan drive control circuit in at least one embodiment of the present disclosure
  • FIG. 7 is an equivalent circuit diagram of a third output control subcircuit and a second output subcircuit of the scan drive control circuit in at least one embodiment of the present disclosure
  • FIG. 8 is an equivalent circuit diagram of a scan driving control circuit in at least one embodiment of the present disclosure.
  • FIG. 9 is a working sequence diagram of the scanning drive control circuit shown in FIG. 8.
  • FIG. 10 is another working sequence diagram of the scanning drive control circuit shown in FIG. 8;
  • FIG. 11 is another equivalent circuit diagram of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • FIG. 12 is another equivalent circuit diagram of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • FIG. 13 is a flowchart of a method for driving a display substrate according to at least one embodiment of the present disclosure
  • FIG. 14 is a schematic diagram of a cascaded scan driving control circuit according to at least one embodiment of the present disclosure.
  • FIG. 15 is a schematic top view of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • Fig. 16 is a schematic partial cross-sectional view along the direction of P-P' in Fig. 15;
  • FIG. 17 is a top view of a scan driving control circuit after forming a first semiconductor layer according to at least one embodiment of the present disclosure
  • FIG. 18 is a top view of a scan driving control circuit after forming a first conductive layer according to at least one embodiment of the present disclosure
  • FIG. 19 is a top view of a scan driving control circuit after forming a second conductive layer according to at least one embodiment of the present disclosure
  • FIG. 20 is a top view of a scan driving control circuit after forming a third insulating layer according to at least one embodiment of the present disclosure
  • FIG. 21 is a top view of a scan driving control circuit after forming a third conductive layer according to at least one embodiment of the present disclosure
  • 22 is a top view of two cascaded scan drive control circuits according to at least one embodiment of the present disclosure.
  • FIG. 23 is a top view of the first conductive layer in FIG. 22;
  • FIG. 24 is another top view of the scan driving control circuit according to at least one embodiment of the present disclosure.
  • FIG. 25 is another top view of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • FIG. 26 is a schematic structural diagram of a display device according to at least one embodiment of the present disclosure.
  • FIG. 27 is another schematic structural diagram of a display device according to at least one embodiment of the present disclosure.
  • Embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. Embodiments may be embodied in many different forms. Those skilled in the art can easily understand the fact that the manner and contents can be changed into one or more forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the contents described in the following embodiments. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily.
  • connection should be interpreted in a broad sense unless otherwise specified and limited. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • electrically connected includes the situation that the constituent elements are connected together through an element having some kind of electrical function.
  • the “element having some kind of electrical function” is not particularly limited as long as it can transmit electrical signals between connected components. Examples of “elements having some kind of electrical function” include not only electrodes and wirings but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.
  • a transistor refers to an element including at least three terminals of a gate electrode (gate), a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • one of the electrodes is called the first pole, and the other electrode is called the second pole.
  • the first pole can be the source electrode or the drain electrode
  • the second pole can be A drain electrode or a source electrode
  • a gate electrode of a transistor is called a gate electrode.
  • parallel means a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus may include a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state in which the angle formed by two straight lines is 80° to 100°, and therefore, an angle of 85° to 95° may be included.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • the display substrate may include: a display area and a non-display area.
  • the non-display area may be located on the periphery of the display area.
  • the display area at least includes: a plurality of pixel circuits arranged regularly, a plurality of gate lines extending along the first direction (for example, including: scanning lines, reset lines, light emission control lines), a plurality of data lines extending along the second direction and power cable.
  • the first direction and the second direction are located in the same plane, and the first direction intersects the second direction, for example, the first direction is perpendicular to the second direction.
  • the non-display area is provided with a plurality of scanning driving control circuits, and the scanning driving control circuits can be configured to provide gate driving signals to the pixel circuits in the display area.
  • FIG. 1 is a schematic structural diagram of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • the scan driving control circuit provided in this embodiment includes: an input circuit, an output control circuit and an output circuit.
  • the input circuit is connected with the signal input terminal IN, the first clock signal terminal CK, the first voltage terminal V1 and the output control circuit, and is configured to transmit the signal of the signal input terminal IN to the output under the control of the first clock signal terminal CK control circuit, and transmit the signal of the first clock signal terminal CK or the first voltage terminal V1 to the output control circuit.
  • the output control circuit is connected to the first signal terminal SIG1, the second signal terminal SIG2, the second clock signal terminal CB, the second voltage terminal V2, the first node N1, the second node N2 and the input circuit, configured to be connected to the input circuit Under the control, store the signal of the first signal terminal SIG1, and transmit the signal of the second signal terminal SIG2 to the first node N1 under the control of the input circuit and the second clock signal terminal CB; or, under the control of the input circuit, store The signal of the second clock signal terminal CB, and under the control of the second node N2, transmits the signal of the second voltage terminal V2 to the first node N1.
  • the output circuit is connected to the first voltage terminal V1, the second voltage terminal V2, the signal output terminal OUT, the first node N1 and the second node N2, and is configured to output the first voltage to the signal output terminal OUT under the control of the second node N2.
  • the signal at the first voltage terminal V1, or, under the control of the first node N1, outputs the signal at the second voltage terminal V2 to the signal output terminal OUT.
  • the input signals of the signal input terminal IN, the first clock signal terminal CK and the second clock signal terminal CB may be pulse signals.
  • the first voltage terminal V1 can continuously provide a low-level signal
  • the second voltage terminal V2 can continuously provide a high-level signal.
  • this embodiment does not limit it.
  • the first signal terminal SIG1 may be connected to the second voltage terminal V2 or the first clock signal terminal CK.
  • the second signal terminal SIG2 may be connected to the first voltage terminal V1 or the second clock signal terminal CB.
  • this embodiment does not limit it.
  • the output signal of the scan driving control circuit provided in this embodiment may be provided as a gate driving signal (for example, a scan signal or a reset signal, or a light emission control signal) to the pixel circuit in the display area.
  • the scan driving control circuit of this embodiment can be applied to a low temperature polycrystalline oxide (LTPO, Low Temperature Polycrystalline Oxide) display substrate, and can provide gate driving signals to N-type transistors in the pixel circuits in the display area.
  • LTPO Low Temperature Polycrystalline Oxide
  • the scan driving control circuit provided in this embodiment can improve the stability of the first node N1 and the second node N2 through the output control circuit, thereby improving the output stability of the output circuit.
  • FIG. 2 is a schematic structural diagram of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • the input circuit includes: a first input subcircuit and a second input subcircuit;
  • the output control circuit includes: a first output control subcircuit, a second output control subcircuit, and a second output control subcircuit.
  • the output circuit includes: a first output subcircuit and a second output subcircuit.
  • the first input subcircuit is connected to the signal input terminal IN, the first clock signal terminal CK and the first output control subcircuit, and is configured to transmit the signal of the signal input terminal IN to the first output control subcircuit under the control of the first clock signal terminal CK.
  • the second input subcircuit is connected to the first voltage terminal V1, the first clock signal terminal CK, the first input subcircuit and the second output control subcircuit, and is configured to be connected to the first input subcircuit or the first clock signal terminal CK. Under control, the signal of the first clock signal terminal CK or the first voltage terminal V1 is transmitted to the second output control sub-circuit.
  • the first output control subcircuit is connected to the first signal terminal SIG1, the second clock signal terminal CB, the second node N2, the first input subcircuit and the second input subcircuit, and is configured to be connected to the first input subcircuit or the second Under the control of the input sub-circuit, the signal of the first signal terminal SIG1 or the second clock signal terminal CB is stored.
  • the second output control subcircuit is connected to the second signal terminal SIG2, the second clock signal terminal CB, the first node N1 and the second input subcircuit, and is configured to control the second input subcircuit and the second clock signal terminal CB Next, the signal of the second signal terminal SIG2 is transmitted to the first node N1.
  • the third output control subcircuit is connected to the second voltage terminal V2, the first node N1 and the second node N2, and is configured to transmit the signal of the second voltage terminal V2 to the first node N1 under the control of the second node N2.
  • the first output sub-circuit is connected to the first voltage terminal V1, the signal output terminal OUT and the second node N2, configured to output the signal of the first voltage terminal V1 to the signal output terminal OUT under the control of the second node N2.
  • the second output sub-circuit is connected to the second voltage terminal V2, the signal output terminal OUT and the first node N1, and is configured to output the signal of the second voltage terminal V2 to the signal output terminal OUT under the control of the first node N1.
  • both the first input subcircuit and the first output control subcircuit are connected to the second node N2.
  • the second input subcircuit, the first output control subcircuit and the second output control subcircuit are all connected to the third node.
  • this embodiment does not limit it.
  • FIG. 3 is an equivalent circuit diagram of the input circuit, the first output control sub-circuit and the first output sub-circuit of the scan driving control circuit according to at least one embodiment of the present disclosure.
  • the first input sub-circuit of the scan driving control circuit provided in this exemplary embodiment includes: a first transistor T1 .
  • the control pole of the first transistor T1 is connected to the first clock signal terminal CK, the first pole is connected to the signal input terminal IN, and the second pole is connected to the second node N2.
  • the second input sub-circuit includes: a second transistor T2 and a third transistor T3.
  • the control electrode of the second transistor T2 is connected to the second node N2, the first electrode is connected to the first clock signal terminal CK, and the second electrode is connected to the third node N3.
  • the control pole of the third transistor T3 is connected to the first clock signal terminal CK, the first pole is connected to the first voltage terminal V1, and the second pole is connected to the third node N3.
  • the first output sub-circuit includes: a tenth transistor T10.
  • the control pole of the tenth transistor T10 is connected to the second node N2, the first pole is connected to the first voltage terminal V1, and the second pole is connected to the signal output terminal OUT.
  • the first output control sub-circuit includes: a fourth transistor T4, a fifth transistor T5, a second capacitor C2 and a fourth capacitor C4.
  • the control electrode of the fourth transistor T4 is connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the second clock signal terminal CB, and the second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5.
  • the control electrode of the fifth transistor T5 is connected to the third node N3, and the first electrode of the fifth transistor T5 is connected to the first signal terminal SIG1.
  • a first pole of the second capacitor C2 is connected to the second node N2, and a second pole of the second capacitor C2 is connected to the signal output terminal OUT.
  • the first electrode of the fourth capacitor C4 is connected to the control electrode of the fourth transistor T4 and the control electrode of the tenth transistor T10 (that is, connected to the second node N2), and the second electrode of the fourth capacitor C4 is connected to the first electrode of the fifth transistor T5.
  • the diode is connected to the second pole of the fourth transistor T4.
  • the potential of the second node N2 can be kept stable when the tenth transistor T10 is turned on, so that the first output sub-circuit can provide a stable output .
  • FIG. 3 shows an exemplary structure of the input circuit, the first output control sub-circuit and the first output sub-circuit.
  • the implementation manners of the input circuit, the first output control subcircuit and the first output subcircuit are not limited thereto, as long as their functions can be realized.
  • the first input sub-circuit of the scan driving control circuit includes: a first transistor T1 .
  • the control pole of the first transistor T1 is connected to the first clock signal terminal CK, the first pole is connected to the signal input terminal IN, and the second pole is connected to the fourth node N4.
  • the second input sub-circuit includes: a second transistor T2 and a third transistor T3.
  • the control electrode of the second transistor T2 is connected to the fourth node N4, the first electrode is connected to the first clock signal terminal CK, and the second electrode is connected to the third node N3.
  • the control pole of the third transistor T3 is connected to the first clock signal terminal CK, the first pole is connected to the first voltage terminal V1, and the second pole is connected to the third node N3.
  • the first output sub-circuit includes: a tenth transistor T10.
  • the control pole of the tenth transistor T10 is connected to the second node N2, the first pole is connected to the first voltage terminal V1, and the second pole is connected to the signal output terminal OUT.
  • the first output control subcircuit includes: a fourth transistor T4 , a fifth transistor T5 , an eleventh transistor T11 , a second capacitor C2 and a fourth capacitor C4 .
  • the control electrode of the fourth transistor T4 is connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the second clock signal terminal CB, and the second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5.
  • the control electrode of the fifth transistor T5 is connected to the third node N3, and the first electrode is connected to the first signal terminal SIG1.
  • the control electrode of the eleventh transistor T11 is connected to the first voltage terminal V1, the first electrode is connected to the fourth node N4, and the second electrode is connected to the second node N2.
  • a first pole of the second capacitor C2 is connected to the second node N2, and a second pole of the second capacitor C2 is connected to the signal output terminal OUT.
  • the first electrode of the fourth capacitor C4 is connected to the control electrode of the fourth transistor T4 and the control electrode of the tenth transistor T10 (that is, connected to the second node N2), and the second electrode of the fourth capacitor C4 is connected to the first electrode of the fourth transistor T4.
  • the diode is connected to the second pole of the fifth transistor T5.
  • the potential of the second node N2 can be kept stable when the tenth transistor T10 is turned on, so that the first output sub-circuit provides stable output.
  • the eleventh transistor T11 By setting the eleventh transistor T11, the influence of the second node N2 on the fourth node N4 can be isolated.
  • FIG. 4 shows an exemplary structure of the input circuit, the first output control sub-circuit and the first output sub-circuit.
  • the implementation manners of the input circuit, the first output control subcircuit and the first output subcircuit are not limited thereto, as long as their functions can be realized.
  • FIG. 5 is an equivalent circuit diagram of a second output control subcircuit of the scan driving control circuit according to at least one embodiment of the present disclosure.
  • the second output control subcircuit of the scan driving control circuit provided in this exemplary embodiment includes: a sixth transistor T6 , a seventh transistor T7 and a first capacitor C1 .
  • the control electrode of the sixth transistor T6 is connected to the third node N3, the first electrode of the sixth transistor T6 is connected to the second signal terminal SIG2, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7.
  • the control electrode of the seventh transistor T7 is connected to the second clock signal terminal CB, and the first electrode is connected to the first node N1.
  • the first electrode of the first capacitor C1 is connected to the control electrode of the sixth transistor T6, and the second electrode is connected to the control electrode of the seventh transistor T7.
  • the second signal terminal SIG2 may provide a low-level signal, so that the potential of the first node N1 remains stable when the transistor of the second output sub-circuit is turned on, so that the second output sub-circuit provides a stable output.
  • FIG. 5 an exemplary structure of the second output control sub-circuit is shown in FIG. 5 .
  • the implementation of the second output control subcircuit is not limited thereto, as long as its function can be realized.
  • FIG. 6 is another equivalent circuit diagram of the second output control subcircuit of the scan driving control circuit according to at least one embodiment of the present disclosure.
  • the second output control subcircuit of the scan driving control circuit provided in this exemplary embodiment includes: a sixth transistor T6 , a seventh transistor T7 , a twelfth transistor T12 and a first capacitor C1 .
  • the control electrode of the sixth transistor T6 is connected to the third node N3, the first electrode of the sixth transistor T6 is connected to the second signal terminal SIG2, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7.
  • the control electrode of the seventh transistor T7 is connected to the second clock signal terminal CB, and the first electrode is connected to the first node N1.
  • the first electrode of the first capacitor C1 is connected to the control electrode of the sixth transistor T6, and the second electrode is connected to the control electrode of the seventh transistor T7.
  • the control electrode of the twelfth transistor T12 is connected to the first power supply terminal V1, the first electrode is connected to the fifth node N5, and the second electrode is connected to the third node N3.
  • the fifth node N5 is also connected to the first input subcircuit and the first output control subcircuit.
  • the second signal terminal SIG2 may provide a low-level signal, so that the potential of the first node N1 remains stable when the transistor of the second output sub-circuit is turned on, so that the second output sub-circuit provides a stable output.
  • the influence of the third node N3 on the fifth node N5 can be isolated.
  • FIG. 6 another exemplary structure of the second output control subcircuit is shown in FIG. 6 .
  • the implementation of the second output control subcircuit is not limited thereto, as long as its function can be realized.
  • the third output control subcircuit of the scan driving control circuit includes: an eighth transistor T8 and a third capacitor C3 .
  • the control electrode of the eighth transistor T8 is connected to the second node N2, the first electrode is connected to the second voltage terminal V2, and the second electrode is connected to the first node N1.
  • a first pole of the third capacitor C3 is connected to the first node N1, and a second pole is connected to the second voltage terminal V2.
  • the second output sub-circuit includes: a ninth transistor T9.
  • the control pole of the ninth transistor T9 is connected to the first node N1, the first pole is connected to the second voltage terminal V2, and the second pole is connected to the signal output terminal OUT.
  • FIG. 7 an exemplary structure of the third output control subcircuit and the second output subcircuit is shown in FIG. 7 .
  • the implementation manners of the third output control subcircuit and the second output subcircuit are not limited thereto, as long as their functions can be realized.
  • FIG. 8 is an equivalent circuit diagram of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • the scan drive control circuit provided by this exemplary embodiment includes: a first input subcircuit, a second input subcircuit, a first output control subcircuit, a second output control subcircuit, a third output control subcircuit circuit, a first output subcircuit and a second output subcircuit.
  • the first input subcircuit includes a first transistor T1.
  • the second input sub-circuit includes a second transistor T2 and a third transistor T3.
  • the first output control sub-circuit includes: a fourth transistor T4, a fifth transistor T5, a second capacitor C2 and a fourth capacitor C4.
  • the second output control sub-circuit includes: a sixth transistor T6, a seventh transistor T7 and a first capacitor C1.
  • the third output control sub-circuit includes: an eighth transistor T8 and a third capacitor C3.
  • the first output sub-circuit includes a tenth transistor T10.
  • the second output sub-circuit includes a ninth transistor T9.
  • the first signal terminal SIG1 is connected to the second voltage terminal V2
  • the second signal terminal SIG2 is connected to the first voltage terminal V1.
  • the control electrode of the first transistor T1 is connected to the first clock signal terminal CK, the first electrode is connected to the signal input terminal IN, and the second electrode is connected to the second node N2.
  • the control electrode of the second transistor T2 is connected to the second node N2, the first electrode is connected to the first clock signal terminal CK, and the second electrode is connected to the third node N3.
  • the control pole of the third transistor T3 is connected to the first clock signal terminal CK, the first pole is connected to the first voltage terminal V1, and the second pole is connected to the third node N3.
  • the control electrode of the fourth transistor T4 is connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the second clock signal terminal CB, and the second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5.
  • the control electrode of the fifth transistor T5 is connected to the third node N3, and the first electrode is connected to the second voltage terminal V2.
  • the control electrode of the sixth transistor T6 is connected to the third node N3, the first electrode of the sixth transistor T6 is connected to the first voltage terminal V1, and the second electrode of the sixth transistor T6 is connected to the first electrode of the seventh transistor T7.
  • the control electrode of the seventh transistor T7 is connected to the second clock signal terminal CB, and the second electrode is connected to the first node N1.
  • the control electrode of the eighth transistor T8 is connected to the second node N2, the first electrode is connected to the second voltage terminal V2, and the second electrode is connected to the first node N1.
  • the control pole of the ninth transistor T9 is connected to the first node N1, the first pole is connected to the second voltage terminal V2, and the second pole is connected to the signal output terminal OUT.
  • the control pole of the tenth transistor T10 is connected to the second node N2, the first pole is connected to the first voltage terminal V1, and the second pole is connected to the signal output terminal OUT.
  • a first electrode of the first capacitor C1 is connected to the third node N3, and a second electrode is connected to the control electrode of the seventh transistor T7.
  • the first electrode of the second capacitor C2 is connected to the second node N2, and the second electrode is connected to the signal output terminal OUT.
  • a first pole of the third capacitor C3 is connected to the first node N1, and a second pole is connected to the second voltage terminal V2.
  • the first pole of the fourth capacitor C4 is connected to the second node N2, and the second pole is connected to the second pole of the fifth transistor T5.
  • the first node N1, the second node N2, and the third node N3 are confluence points representing relevant electrical connections in the circuit diagram.
  • these nodes are nodes equivalent to the confluence of related electrical connections in the circuit diagram.
  • the first transistor T1 to the tenth transistor T10 in the scan driving control circuit may all be P-type thin film transistors, such as low temperature polysilicon (LTPS, Low Temperature Poly-silicon) thin film transistors.
  • LTPS low temperature polysilicon
  • the embodiment of the present disclosure may choose a thin film transistor with a bottom gate structure or a thin film transistor with a top gate structure, as long as the switching function can be realized. This embodiment does not limit it.
  • FIG. 9 is a working timing diagram of the scan driving control circuit shown in FIG. 8 .
  • the scan driving control circuit of this exemplary embodiment includes 10 transistor units (such as the first transistor T1 to the tenth transistor T10), 4 capacitor units (that is, the first capacitor C1 to the fourth Capacitor C4), 3 input terminals (i.e. signal input terminal IN, first clock signal terminal CK, second clock signal terminal CB), 1 output terminal (i.e.
  • first voltage terminal V1 continuously provides a low-level signal, for example, the voltage is VGL
  • second voltage terminal V2 continuously provides a high-level signal, for example, the voltage is VGH.
  • the working process of the scanning driving control circuit will be described below by taking the scanning signal or reset signal provided by the scanning driving control circuit of this embodiment to the N-type transistor of the pixel circuit as an example.
  • the working process of the scan driving control circuit provided by this exemplary embodiment includes the following stages.
  • a high-level signal is input to the first clock signal terminal CK
  • a low-level signal is input to the second clock signal terminal CB
  • a low-level signal is input to the signal input terminal IN.
  • the first clock signal terminal CK inputs a high-level signal, the first transistor T1 and the third transistor T3 are turned off, the second node N2 maintains the low potential of the previous stage, the second transistor T2, the fourth transistor T4, the eighth transistor T8 and The tenth transistor T10 is turned on.
  • the high-level signal input from the first clock signal terminal CK is transmitted to the third node N3 through the turned-on second transistor T2, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the low-level signal input by the second clock signal terminal CB is transmitted to the second pole of the fourth capacitor C4 through the turned-on fourth transistor T4.
  • the first pole of the fourth capacitor C4 (that is, the second node N2) maintains a lower potential.
  • the eighth transistor T8 is turned on, so that the potential of the first node N1 is a high potential (for example, VGH), and the ninth transistor T9 is turned off.
  • the tenth transistor T10 is turned on, so that the signal output terminal OUT outputs the low-level signal provided by the first voltage terminal V1.
  • a low-level signal is input to the first clock signal terminal CK
  • a high-level signal is input to the second clock signal terminal CB
  • a high-level signal is input to the signal input terminal IN.
  • the first clock signal terminal CK inputs a low-level signal
  • the first transistor T1 and the third transistor T3 are turned on
  • the turned-on first transistor T1 transmits the high-level signal provided by the signal input terminal IN to the second node N2, so that The potential of the second node N2 is pulled up to VGH.
  • the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off.
  • the turned-on third transistor T3 transmits the low-level signal input from the first voltage terminal V1 to the third node N3, and the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the high-level signal provided by the second voltage terminal V2 is transmitted to the second pole of the fourth capacitor C4 through the turned-on fifth transistor T5.
  • the first pole of the fourth capacitor (ie The second node N2) maintains a stable high potential.
  • the second clock signal terminal CB inputs a high-level signal, the seventh transistor T7 is turned off, the first node N1 maintains the high potential provided by the second voltage terminal V2 under the storage function of the third capacitor C3, and the ninth transistor T9 is turned off. Since both the ninth transistor T9 and the tenth transistor T10 are turned off, the signal output terminal OUT maintains the previous low level output.
  • a high-level signal is input to the first clock signal terminal CK
  • a low-level signal is input to the second clock signal terminal CB
  • a low-level signal is input to the signal input terminal IN.
  • the first clock signal terminal CK inputs a high level signal
  • the first transistor T1 and the third transistor T3 are turned off, and the second node N2 maintains the high potential of the previous stage.
  • the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off.
  • the second clock signal terminal CB inputs a low-level signal, and the potential of the first electrode of the first capacitor C1 (that is, the third node N3 ) jumps from the low potential VGL in the previous stage to a lower potential 2VGL-VGH.
  • the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the high-level signal provided by the second voltage terminal V2 is transmitted to the second electrode of the fourth capacitor C4 through the turned-on fifth transistor T5, so that the second node N2 maintains a stable high potential.
  • the second clock signal terminal CB inputs a low-level signal
  • the seventh transistor T7 is turned on
  • the low-level signal input from the first voltage terminal V1 is transmitted to the first node N1 through the turned-on sixth transistor T6 and seventh transistor T7
  • the ninth transistor T9 is turned on, and outputs the high-level signal provided by the second voltage terminal V2 to the signal output terminal OUT.
  • the first clock signal terminal CK inputs a low-level signal
  • the second clock signal terminal CB inputs a high-level signal
  • the signal input terminal IN inputs a low-level signal.
  • the first clock signal terminal CK inputs a low-level signal
  • the first transistor T1 and the third transistor T3 are turned on, and the turned-on first transistor T1 transmits the low-level signal input from the signal input terminal IN to the second node N2, so that The potential of the second node N2 is pulled down to VGL.
  • the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned on.
  • the turned-on eighth transistor T8 transmits the high-level signal provided by the second voltage terminal V2 to the first node N1, and the ninth transistor T9 is turned off.
  • the turned-on tenth transistor T10 transmits the low-level signal provided by the first voltage terminal V1 to the signal output terminal OUT.
  • the turned-on second transistor T2 transmits the low-level signal provided by the first clock signal terminal CK to the third node N3, and the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the second clock signal terminal CB inputs a high-level signal, and the seventh transistor T7 is turned off.
  • a high-level signal is input to the first clock signal terminal CK
  • a low-level signal is input to the second clock signal terminal CB
  • a low-level signal is input to the signal input terminal IN.
  • the first clock signal terminal CK inputs a high-level signal, and the first transistor T1 and the third transistor T3 are turned off.
  • the second node N2 maintains the low potential of the previous node, and the second transistor T2 , the fourth transistor T4 , the eighth transistor T8 and the tenth transistor T10 are turned on.
  • the turned-on fourth transistor T4 transmits the low-level signal input from the second clock signal terminal CB to the second pole of the fourth capacitor C4, so that the potential of the first pole of the fourth capacitor C4 (that is, the second node N2) changes. It is a lower potential than VGL.
  • the turned-on second transistor T2 transmits the high-level signal provided by the first clock signal terminal CK to the third node N3, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the turned-on eighth transistor T8 transmits the high-level signal provided by the second voltage terminal V2 to the first node N1, the potential of the first node N1 is VGH, and the ninth transistor T9 is turned off.
  • the tenth transistor T10 is turned on, and provides the low-level signal provided by the first voltage terminal V1 to the signal output terminal OUT.
  • the fourth stage t14 and the fifth stage t15 can be repeated until the signal input terminal IN inputs a high-level signal, and then restart from the second stage t12.
  • the signal output terminal OUT outputs a high-level signal, and in the remaining stages, the signal output terminal OUT outputs a low-level signal.
  • both the first clock signal input to the first clock signal terminal CK and the second clock signal input to the second clock signal terminal CB are pulse signals, and the pulse width of the first clock signal and the second clock signal
  • the pulse widths of the signals can be approximately the same.
  • the duty cycle of the first clock signal and the second clock signal may be greater than 1/2, for example, may be about 1/3.
  • the duty cycle refers to the proportion of the high-level duration in the entire pulse period within a pulse period (including the high-level duration and the low-level duration).
  • FIG. 10 is another working timing diagram of the scan driving control circuit shown in FIG. 8 .
  • the working process of the scan drive control circuit will be described by taking the scan drive control circuit of this embodiment to provide light emission control signals to the pixel circuits as an example.
  • the working process of the scan driving control circuit provided in this exemplary embodiment may include the following stages.
  • a high-level signal is input to the first clock signal terminal CK
  • a low-level signal is input to the second clock signal terminal CB
  • a low-level signal is input to the signal input terminal IN.
  • the first clock signal terminal CK inputs a high-level signal, the first transistor T1 and the third transistor T3 are turned off, the second node N2 maintains the low potential of the previous stage, the second transistor T2, the fourth transistor T4, the eighth transistor T8 and The tenth transistor T10 is turned on.
  • the high-level signal input from the first clock signal terminal CK is transmitted to the third node N3 through the turned-on second transistor T2, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the low-level signal input by the second clock signal terminal CB is transmitted to the second pole of the fourth capacitor C4 through the turned-on fourth transistor T4.
  • the first pole of the fourth capacitor C4 (that is, the second node N2) maintains a lower potential.
  • the eighth transistor T8 is turned on, so that the potential of the first node N1 is pulled up to VGH, and the ninth transistor T9 is turned off.
  • the tenth transistor T10 is turned on, so that the signal output terminal OUT outputs the low-level signal provided by the first voltage terminal V1.
  • a low-level signal is input to the first clock signal terminal CK
  • a high-level signal is input to the second clock signal terminal CB
  • a high-level signal is input to the signal input terminal IN.
  • the first clock signal terminal CK inputs a low-level signal, and the first transistor T1 and the third transistor T3 are turned on.
  • the turned-on first transistor T1 transmits the high-level signal provided by the signal input terminal IN to the second node N2, so that the potential of the second node N2 is pulled up to VGH.
  • the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off.
  • the turned-on third transistor T3 transmits the low-level signal input from the first voltage terminal V1 to the third node N3, and the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the high-level signal provided by the second voltage terminal V2 is transmitted to the second pole of the fourth capacitor C4 through the turned-on fifth transistor T5.
  • the first pole of the fourth capacitor (ie The second node N2) maintains a stable high level.
  • the second clock signal terminal CB inputs a high-level signal, the seventh transistor T7 is turned off, the first node N1 maintains the high potential VGH provided by the second voltage terminal V2 under the storage function of the third capacitor C3, and the ninth transistor T9 is turned off. Since both the ninth transistor T9 and the tenth transistor T10 are turned off, the signal output terminal OUT maintains the previous low level output.
  • the first clock signal terminal CK inputs a high-level signal
  • the second clock signal terminal CB inputs a low-level signal
  • the signal input terminal IN inputs a high-level signal.
  • the first clock signal terminal CK inputs a high level signal
  • the first transistor T1 and the third transistor T3 are turned off, and the second node N2 maintains the high potential of the previous stage.
  • the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off.
  • the second clock signal terminal CB inputs a low-level signal, and the potential of the first electrode of the first capacitor C1 (that is, the third node N3 ) jumps from the low potential VGL in the previous stage to a lower potential 2VGL-VGH.
  • the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the high-level signal provided by the second voltage terminal V2 is transmitted to the second electrode of the fourth capacitor C4 through the turned-on fifth transistor T5, so that the second node N2 maintains a stable high potential.
  • the second clock signal terminal CB inputs a low-level signal
  • the seventh transistor T7 is turned on
  • the low-level signal input from the first voltage terminal V1 is transmitted to the first node N1 through the turned-on sixth transistor T6 and seventh transistor T7
  • the ninth transistor T9 is turned on, and provides the high-level signal provided by the second voltage terminal V2 to the signal output terminal OUT.
  • the first clock signal terminal CK inputs a low-level signal
  • the second clock signal terminal CB inputs a high-level signal
  • the signal input terminal IN inputs a high-level signal.
  • the first clock signal terminal CK inputs a low-level signal, and the first transistor T1 and the third transistor T3 are turned on.
  • the turned-on first transistor T1 transmits the high-level signal input from the signal input terminal IN to the second node N2, and the potential of the second node N2 remains the high potential VGH of the previous stage.
  • the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off.
  • the turned-on third transistor T3 transmits the low-level signal provided by the first voltage terminal V1 to the third node N3, and the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the turned-on fifth transistor T5 transmits the high-level signal provided by the second voltage terminal V2 to the second pole of the fourth capacitor C4, and under the action of the jump of the fourth capacitor C4, the first pole of the fourth capacitor C4 ( That is, the second node N2) maintains a stable high potential.
  • the second clock signal terminal CB inputs a high-level signal
  • the seventh transistor T7 is turned off
  • the first node N1 is kept at the low potential of the previous stage under the storage effect of the third capacitor C3
  • the ninth transistor T9 is turned on
  • the signal output terminal OUT outputs a high-level signal provided by the second voltage terminal V2.
  • the first clock signal terminal CK inputs a high-level signal
  • the second clock signal terminal CB inputs a low-level signal
  • the signal input terminal IN inputs a low-level signal.
  • the first clock signal terminal CK inputs a high level signal
  • the first transistor T1 and the third transistor T3 are turned off, and the second node N2 maintains the high potential of the previous stage.
  • the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off.
  • the second clock signal terminal CB inputs a low-level signal, and the potential of the second pole of the first capacitor C1 jumps from VGH in the previous stage to VGL. Due to the jump effect of the first capacitor C1, the first capacitor of the first capacitor C1
  • the potential of the pole (that is, the third node N3) jumps from VGL in the previous stage to a lower 2VGL-VGH, and the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the turned-on fifth transistor T5 transmits the high-level signal provided by the second voltage terminal V2 to the second pole of the fourth capacitor C4, so that the second node N2 maintains a stable high potential.
  • the second clock signal terminal CB inputs a low-level signal, and the seventh transistor T7 is turned on.
  • the turned-on sixth transistor T6 and seventh transistor T7 transmit the low-level signal provided by the first voltage terminal V1 to the first node N1, the ninth transistor T9 is turned on, and the signal output terminal OUT outputs the signal provided by the second voltage terminal V2. high level signal.
  • the first clock signal terminal CK inputs a low-level signal
  • the second clock signal terminal CB inputs a high-level signal
  • the signal input terminal IN inputs a low-level signal.
  • the first clock signal terminal CK inputs a low-level signal, and the first transistor T1 and the third transistor T3 are turned on.
  • the turned-on first transistor T1 transmits the low-level signal input from the signal input terminal IN to the second node N2, and the potential of the second node N2 is pulled down to VGL.
  • the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned on.
  • the turned-on eighth transistor T8 transmits the high-level signal provided by the second voltage terminal V2 to the first node N1, and the ninth transistor T9 is turned off.
  • the turned-on tenth transistor T10 transmits the low-level signal provided by the first voltage terminal V1 to the signal output terminal OUT.
  • the turned-on second transistor T2 transmits the low-level signal provided by the first clock signal terminal CK to the third node N3, and the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the second clock signal terminal CB inputs a high-level signal, and the seventh transistor T7 is turned off.
  • a high-level signal is input to the first clock signal terminal CK
  • a low-level signal is input to the second clock signal terminal CB
  • a low-level signal is input to the signal input terminal IN.
  • the first clock signal terminal CK inputs a high-level signal, and the first transistor T1 and the third transistor T3 are turned off.
  • the second node N2 maintains the low potential of the previous node, and the second transistor T2 , the fourth transistor T4 , the eighth transistor T8 and the tenth transistor T10 are turned on.
  • the turned-on fourth transistor T4 transmits the low-level signal input from the second clock signal terminal CB to the second pole of the fourth capacitor C4, so that the potential of the first pole of the fourth capacitor C4 (that is, the second node N2) changes. It is a lower potential than VGL.
  • the turned-on second transistor T2 transmits the high-level signal provided by the first clock signal terminal CK to the third node N3, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the turned-on eighth transistor T8 transmits the high-level signal provided by the second voltage terminal V2 to the first node N1, the potential of the first node N1 is VGH, and the ninth transistor T9 is turned off.
  • the tenth transistor T10 is turned on, and outputs the low-level signal provided by the first voltage terminal V1 to the signal output terminal OUT.
  • the sixth stage t26 and the seventh stage t27 can be repeated until the signal input terminal OUT inputs a high-level signal, and then restart from the second stage t22.
  • the signal output terminal OUT can output a high-level signal during the third stage t23 to the fifth stage t25, and the signal output terminal OUT can output a low-level signal in other stages.
  • the scanning drive control circuit provided in this exemplary embodiment can keep the potential of the second node N2 stable when the tenth transistor T10 is turned on through the first output control subcircuit, so as to improve the output stability of the tenth transistor T10, through the first output control subcircuit
  • the two-output control sub-circuit can keep the potential of the first node N1 stable when the ninth transistor T9 is turned on, so as to improve the output stability of the ninth transistor T9.
  • FIG. 11 is another equivalent circuit diagram of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • the scan drive control circuit provided by this exemplary embodiment includes: a first input subcircuit, a second input subcircuit, a first output control subcircuit, a second output control subcircuit, a third output control subcircuit circuit, a first output subcircuit and a second output subcircuit.
  • the first input subcircuit includes a first transistor T1.
  • the second input sub-circuit includes a second transistor T2 and a third transistor T3.
  • the first output control sub-circuit includes: a fourth transistor T4, a fifth transistor T5, an eleventh transistor T11, a second capacitor C2 and a fourth capacitor C4.
  • the second output control sub-circuit includes: a twelfth transistor T12, a sixth transistor T6, a seventh transistor T7 and a first capacitor C1.
  • the third output control sub-circuit includes: an eighth transistor T8 and a third capacitor C3.
  • the first output sub-circuit includes: a tenth transistor T10.
  • the second output sub-circuit includes a ninth transistor T9. In this exemplary embodiment, the first signal terminal is connected to the second voltage terminal V2, and the second signal terminal is connected to the first voltage terminal V1.
  • the control electrode of the first transistor T1 is connected to the first clock signal terminal CK, the first electrode is connected to the signal input terminal IN, and the second electrode is connected to the fourth node N4.
  • the control electrode of the second transistor T2 is connected to the fourth node N4, the first electrode is connected to the first clock signal terminal CK, and the second electrode is connected to the third node N3.
  • the control pole of the third transistor T3 is connected to the first clock signal terminal CK, the first pole is connected to the first voltage terminal V1, and the second pole is connected to the fifth node N5.
  • the control electrode of the fourth transistor T4 is connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the second clock signal terminal CB, and the second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5.
  • the control electrode of the fifth transistor T5 is connected to the fifth node N5, and the first electrode is connected to the second voltage terminal V2.
  • the control electrode of the sixth transistor T6 is connected to the third node N3, the first electrode of the sixth transistor T6 is connected to the first voltage terminal V1, and the second electrode of the sixth transistor T6 is connected to the first electrode of the seventh transistor T7.
  • the control electrode of the seventh transistor T7 is connected to the second clock signal terminal CB, and the second electrode is connected to the first node N1.
  • the control electrode of the eighth transistor T8 is connected to the second node N2, the first electrode is connected to the second voltage terminal V2, and the second electrode is connected to the first node N1.
  • the control pole of the ninth transistor T9 is connected to the first node N1, the first pole is connected to the second voltage terminal V2, and the second pole is connected to the signal output terminal OUT.
  • the control pole of the tenth transistor T10 is connected to the second node N2, the first pole is connected to the first voltage terminal V1, and the second pole is connected to the signal output terminal OUT.
  • the control electrode of the eleventh transistor T11 is connected to the first voltage terminal V1, the first electrode is connected to the fourth node N4, and the second electrode is connected to the second node N2.
  • the control electrode of the twelfth transistor T12 is connected to the first voltage terminal V1, the first electrode is connected to the fifth node N5, and the second electrode is connected to the third node N3.
  • a first electrode of the first capacitor C1 is connected to the third node N3, and a second electrode is connected to the control electrode of the seventh transistor T7.
  • the first electrode of the second capacitor C2 is connected to the second node N2, and the second electrode is connected to the signal output terminal OUT.
  • a first pole of the third capacitor C3 is connected to the first node N1, and a second pole is connected to the second voltage terminal V2.
  • the first pole of the fourth capacitor C4 is connected to the second node N2, and the second pole is connected to the second pole of the fifth transistor T5.
  • the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5 represent confluence points of related electrical connections in the circuit diagram.
  • these nodes are nodes equivalent to the confluence of related electrical connections in the circuit diagram.
  • the first transistor T1 to the twelfth transistor T12 in the scan driving control circuit may all be P-type thin film transistors, such as low temperature polycrystalline silicon (LTPS, Low Temperature Poly-silicon) thin film transistors .
  • LTPS low temperature polycrystalline silicon
  • the embodiment of the present disclosure may choose a thin film transistor with a bottom gate structure or a thin film transistor with a top gate structure, as long as the switching function can be realized. This embodiment does not limit it.
  • the influence of the second node N2 on the fourth node N4 can be isolated through the eleventh transistor T11, and the third node N3 can be isolated from the fifth node N5 through the twelfth transistor T12. Impact.
  • FIG. 12 is another equivalent circuit diagram of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • the scan drive control circuit provided by this exemplary embodiment includes: a first input subcircuit, a second input subcircuit, a first output control subcircuit, a second output control subcircuit, a third output control subcircuit circuit, a first output subcircuit and a second output subcircuit.
  • the first input subcircuit includes a first transistor T1.
  • the second input sub-circuit includes a second transistor T2 and a third transistor T3.
  • the first output control sub-circuit includes: a fourth transistor T4, a fifth transistor T5, an eleventh transistor T11, a second capacitor C2 and a fourth capacitor C4.
  • the second output control sub-circuit includes: a twelfth transistor T12, a sixth transistor T6, a seventh transistor T7 and a first capacitor C1.
  • the third output control sub-circuit includes: an eighth transistor T8 and a third capacitor C3.
  • the first output sub-circuit includes: a tenth transistor T10.
  • the second output sub-circuit includes a ninth transistor T9.
  • the first signal terminal is connected to the first clock signal terminal CK
  • the second signal terminal is connected to the second clock signal terminal CB. That is, the second pole of the fifth transistor T5 is connected to the first clock signal terminal CK, and the first pole of the sixth transistor T6 is connected to the second clock signal terminal CB.
  • the first signal terminal SIG1 of the scan driving control circuit may be connected to the first clock signal terminal CK, and the second signal terminal SIG2 may be connected to the first voltage terminal V1 or the second clock signal terminal CB;
  • the first signal terminal SIG1 may be connected to the second voltage terminal V2, and the second signal terminal SIG2 may be connected to the first voltage terminal V1 or the second clock signal terminal CB.
  • this embodiment does not limit it.
  • FIG. 13 is a flowchart of a method for driving a display substrate according to an embodiment of the present disclosure. As shown in FIG. 13 , the method for driving a display substrate provided in this embodiment is applied to the display substrate provided in the foregoing embodiments.
  • the driving method provided in this embodiment may include the following steps.
  • Step S101 the input circuit transmits the signal of the signal input terminal to the output control circuit under the control of the first clock signal terminal, and transmits the signal of the first clock signal terminal or the first voltage terminal to the output control circuit;
  • Step S102 the output control circuit stores the signal of the first signal terminal under the control of the input circuit, and transmits the signal of the second signal terminal to the first node under the control of the input circuit and the second clock signal terminal, and the output circuit is at the first node Under control, output the signal of the second voltage terminal to the signal output terminal;
  • Step S103 the output control circuit stores the signal of the second clock signal terminal under the control of the input circuit, and transmits the signal of the second voltage terminal to the first node under the control of the second node, and the output circuit is under the control of the second node , to output the signal of the first voltage terminal to the signal output terminal.
  • FIG. 14 is a schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure.
  • the gate driving circuit provided by this exemplary embodiment includes a plurality of cascaded scan driving control circuits GOA.
  • the scanning driving control circuit can be implemented as described in the foregoing embodiments, and its implementation principles and types of effects are not repeated here.
  • the signal input terminal IN of the first-level scan drive control circuit is connected to the initial signal line STV, and the signal input terminal IN of the n+1-th scan drive control circuit is connected to the signal of the n-th scan drive control circuit.
  • the output terminal is connected, wherein, n is an integer.
  • the first clock signal terminals CK of the plurality of scan driving control circuits are connected to the first clock signal line CKL and configured to receive the first clock signal
  • the second clock signal terminal CB is connected to the second clock signal line CBL connection configured to receive a second clock signal.
  • the first voltage terminal V1 is connected to the power line continuously providing the low-level signal VGL
  • the second voltage terminal V2 is connected to the power line continuously providing the high-level signal VGH.
  • this embodiment does not limit it.
  • FIG. 15 is a top view of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • Fig. 16 is a schematic partial cross-sectional view along the P-P' direction in Fig. 15 .
  • the equivalent circuit diagram of the scan driving control circuit shown in FIG. 15 may be shown in FIG. 8 .
  • the first signal terminal is connected to the second voltage terminal
  • the second signal terminal is connected to the first voltage terminal
  • the first clock signal terminal CK is connected to the first clock signal line CKL
  • the second clock signal terminal CB is connected to the second clock signal line CBL.
  • the second voltage terminal is connected to the first power line PL1 providing a high level signal.
  • the first voltage terminal connected to the first output sub-circuit is connected to the third power line PL3 providing a low level signal.
  • the first voltage end connected to the second input sub-circuit and the second output control sub-circuit is connected to the second power line PL2 providing a low level signal.
  • the first clock signal line CKL, the second clock signal line CBL, the initial signal line STV, the second power line PL2, the first The power line PL1 and the third power line PL3 are sequentially arranged along the first direction X.
  • the first clock signal line CKL, the second clock signal line CBL, the initial signal line STV, the second power line PL2 , the first power line PL1 and the third power line PL3 all extend along the second direction Y.
  • the first direction X crosses the second direction Y, for example, the first direction X is perpendicular to the second direction Y.
  • the signal output terminal OUT in a plane parallel to the display substrate, is located on the side of the tenth transistor T10 away from the ninth transistor T9 in the second direction Y.
  • the signal output terminal OUT may extend along the first direction X.
  • this embodiment does not limit it.
  • the second input sub-circuit (including the second transistor T2 and the third transistor T3 ) is located on the initial signal line in the first direction X between STV and the second power line PL2.
  • the first output sub-circuit (including the tenth transistor T10) and the second output sub-circuit (including the ninth transistor T9) are located between the first power line PL1 and the third power line PL3 in the first direction X.
  • the second transistor T2 and the third transistor T3 are adjacent in the second direction Y.
  • the ninth transistor T9 and the tenth transistor T10 are adjacent in the second direction Y.
  • the first transistor T1 , the fourth transistor T4 and the fifth transistor T5 are located on a side of the second power line PL2 away from the second clock signal line CBL.
  • the seventh transistor T7 is adjacent to the first capacitor C1, and the seventh transistor T7 is located between the first capacitor C1 and the first power line PL1.
  • the sixth transistor T6 is adjacent to the first power line PL1, and the sixth transistor T6 is located between the seventh transistor T7 and the first power line PL1.
  • the eighth transistor T8 is located between the first power line PL1 and the first transistor T1.
  • the first capacitor C1 is located between the first power line PL1 and the second power line PL2, and the orthographic projection of the first capacitor C1 on the base substrate is located at the projection of the first power line PL1 and the second power line PL2 on the base substrate Between, and the projection of the first capacitor C1 on the base substrate does not overlap with the projections of the first power line PL1 and the second power line PL2 on the base substrate.
  • "A and B are adjacent" means that there is no other transistor or capacitor between A and B.
  • the non-display area of the display substrate may include: a base substrate 30 , a first semiconductor layer sequentially disposed on the base substrate 30 , the first conductive layer, the second conductive layer and the third conductive layer.
  • the first insulating layer 31 is disposed between the first conductive layer and the first semiconductor layer.
  • the second insulating layer 32 is disposed between the first conductive layer and the second conductive layer.
  • the third insulating layer 33 is disposed between the second conductive layer and the third conductive layer.
  • the first insulating layer 31 to the third insulating layer 33 may all be inorganic insulating layers. However, this embodiment does not limit it.
  • FIG. 17 is a top view of the scan driving control circuit after forming the first semiconductor layer according to at least one embodiment of the present disclosure.
  • the first semiconductor layer in the non-display area at least includes: an active layer of a plurality of transistors of the scan driving control circuit.
  • the first semiconductor layer at least includes: the active layer 110 of the first transistor T1, the active layer 120 of the second transistor T2, the active layer 130 of the third transistor T3, the active layer 140 of the fourth transistor T4, the The active layer 150 of the fifth transistor T5, the active layer 160 of the sixth transistor T6, the active layer 170 of the seventh transistor T7, the active layer 180 of the eighth transistor T8, the active layer of the ninth transistor T9 and the tenth transistor Active layer of T10.
  • the active layer 130 of the third transistor T3, the active layer 110 of the first transistor T1, the active layer 150 of the fifth transistor T5, and the active layer 150 of the sixth transistor T6 may extend in the second direction Y.
  • the active layer 140 of the fourth transistor T4 may extend in the first direction X. Referring to FIG.
  • the included angle between the extending direction of the active layer 140 of the fourth transistor T4 and the extending direction of the active layer 110 of the first transistor T1 is greater than 85° and less than 95°.
  • the included angle between the extending direction of the active layer 140 of the fourth transistor T4 and the extending direction of the active layer 150 of the fifth transistor T5 is larger than 85° and smaller than 95°.
  • this embodiment does not limit it.
  • the active layer 130 of the third transistor T3 and the active layer 120 of the second transistor T2 are adjacent in the second direction Y.
  • the active layer 110 of the first transistor T1 is located between the active layer 130 of the third transistor T3 and the active layer 180 of the eighth transistor T8 in the first direction X.
  • the active layer 140 of the fourth transistor T4 is located between the active layer 110 of the first transistor T1 and the active layer 150 of the fifth transistor T5 in the second direction Y.
  • the active layer 160 of the sixth transistor T6 is located on a side of the active layer 170 of the seventh transistor T7 away from the active layer 150 of the fifth transistor T5 in the first direction X.
  • the active layer of the ninth transistor T9 and the active layer of the tenth transistor T10 are sequentially arranged in the second direction Y.
  • the active layer of the ninth transistor T9 is located on the side of the active layer 180 of the eighth transistor T8 away from the active layer 110 of the first transistor T1 in the first direction X, and the active layer of the tenth transistor T10 is in the first direction X.
  • X is located on a side where the active layer 160 of the sixth transistor T6 is away from the active layer 170 of the seventh transistor T7.
  • the active layer of the ninth transistor T9 includes the first subregion 190-1 and the second subregion 190-2; the active layer of the tenth transistor T10 includes the third subregion 200 -1 and the fourth division 200-2.
  • the first subregion 190-1 of the active layer of the ninth transistor T9 and the third subregion 200-1 of the active layer of the tenth transistor T10 may have an integrated structure, such as a rectangle.
  • the second subregion 190-2 of the active layer of the ninth transistor T9 and the fourth subregion 200-2 of the active layer of the tenth transistor T10 may have an integral structure, such as a rectangle.
  • this embodiment does not limit the number of divisions and the shape of at least one division of the active layer of the ninth transistor T9 and the tenth transistor T10 .
  • the orthographic projection of the active layer 120 of the second transistor T2 on the base substrate may be U-shaped.
  • the active layer 110 of the first transistor T1, the active layer 130 of the third transistor T3, the active layer 140 of the fourth transistor T4, the active layer 150 of the fifth transistor T5 and the active layer 160 of the sixth transistor T6 are in The orthographic projection on the substrate substrate can be dumbbell shaped.
  • the active layer 170 of the seventh transistor T7 and the active layer 180 of the eighth transistor T8 may have an integrated structure. However, this embodiment does not limit it.
  • the material of the first semiconductor layer may include polysilicon, for example.
  • the active layer may include at least one channel region and a plurality of doped regions.
  • the channel region may not be doped with impurities and has semiconductor characteristics.
  • a plurality of doped regions may be on both sides of the channel region, and be doped with impurities and thus have conductivity. Impurities can vary depending on the type of transistor.
  • the doped region of the active layer may be interpreted as a source electrode or a drain electrode of a transistor.
  • the source electrode of the first transistor T1 may correspond to the periphery of the channel region 110a of the active layer 110 and the first doped region 110b doped with impurities
  • the drain electrode of the first transistor T1 may correspond to the periphery of the active layer 110.
  • the periphery of the channel region 110a corresponds to the second doped region 110c doped with impurities.
  • the part of the active layer between the transistors can be interpreted as a wiring doped with impurities, which can be used to electrically connect the transistors.
  • the output capability of a transistor is related to the ratio of the width to the length of the channel region of the transistor, and the ratio of the width to the length of the channel region of a transistor with a strong output capability is large.
  • the width of the channel region 140a of the active layer 140 of the fourth transistor T4 (that is, the length of the channel region 140a along the second direction Y) is W T4
  • the width of the active layer 150 of the fifth transistor T5 is
  • the width of the channel region 150 a ie, the length of the channel region 150 a along the first direction X) is W T5 .
  • the width of the channel region 150a of the active layer 150 of the fifth transistor T5 and the width of the channel region 140a of the active layer 140 of the fourth transistor T4 satisfy: 2W T4 ⁇ W T5 .
  • the "width" of A indicates the characteristic dimension of A perpendicular to the extending direction.
  • FIG. 18 is a top view of the scan driving control circuit after forming the first conductive layer according to at least one embodiment of the present disclosure.
  • the first conductive layer in the non-display area at least includes: control electrodes of multiple transistors and first electrodes of multiple capacitors of the scan driving control circuit.
  • the first conductive layer may include: the control electrode 113 of the first transistor T1, the control electrode 123 of the second transistor T2, the control electrode 133 of the third transistor T3, the control electrode 143 of the fourth transistor T4, and the control electrode 143 of the fifth transistor T5.
  • the control electrode 133 of the third transistor T3 and the control electrode 113 of the first transistor T1 may have an integral structure.
  • the control electrode 123 of the second transistor T2, the control electrode 203 of the tenth transistor T10, and the first electrode C2-1 of the second capacitor C2 may have an integrated structure.
  • the control electrode 153 of the fifth transistor T5 , the control electrode 163 of the sixth transistor T6 and the first electrode C1 - 1 of the first capacitor C1 may have an integrated structure.
  • the control electrode 183 of the eighth transistor T8, the control electrode 143 of the fourth transistor T4, and the first electrode C4-1 of the fourth capacitor C4 may have an integrated structure.
  • the control electrodes 193a and 193b of the ninth transistor T9 and the first electrode C3-1 of the third capacitor C3 may be of an integral structure. However, this embodiment does not limit it.
  • the ninth transistor T9 may be a double-gate transistor to prevent and reduce leakage current.
  • this embodiment does not limit it.
  • FIG. 19 is a top view of the scan driving control circuit after forming the second conductive layer according to at least one embodiment of the present disclosure.
  • the second conductive layer in the non-display area at least includes: the second poles of multiple capacitors of the scan driving control circuit, a signal input terminal and a signal input terminal.
  • the second conductive layer may include: the second pole C1-2 of the first capacitor C1, the second pole C2-2 of the second capacitor C2, the second pole C3-2 of the third capacitor C3, and the second pole C3-2 of the fourth capacitor C4.
  • the second pole C2-2 of the second capacitor C2 and the signal output terminal OUT may be in an integral structure. However, this embodiment does not limit it.
  • the projection of the second pole C1 - 2 of the first capacitor C1 on the base substrate overlaps with the projection of the first pole C1 - 1 on the base substrate.
  • the projection of the second pole C2-2 of the second capacitor C2 on the substrate overlaps with the projection of the first pole C2-1 on the substrate.
  • the projection of the second pole C3 - 2 of the third capacitor C3 on the substrate overlaps with the projection of the first pole C3 - 1 on the substrate.
  • the projection of the second pole C4-2 of the fourth capacitor C4 on the substrate overlaps with the projection of the first pole C4-1 on the substrate.
  • FIG. 20 is a top view of a scan driving control circuit after forming a third insulating layer according to at least one embodiment of the present disclosure.
  • a plurality of via holes are formed on the third insulating layer 33 in the non-display area.
  • the plurality of vias may include: a plurality of first vias F1 to F25 , a plurality of second vias K1 to K10 , and a plurality of third vias D1 to D5 .
  • the third insulating layer 33, the second insulating layer 32 and the first insulating layer 31 in the plurality of first via holes F1 to F25 are etched away, exposing the surface of the first semiconductor layer.
  • the third insulating layer 33 and the second insulating layer 32 in the plurality of second via holes K1 to K10 are etched away, exposing the surface of the first conductive layer.
  • the third insulating layer 33 in the plurality of third via holes D1 to D5 is etched away, exposing the surface of the second conductive layer.
  • FIG. 21 is a top view of the scan driving control circuit after forming the third conductive layer according to at least one embodiment of the present disclosure.
  • the third conductive layer in the non-display area at least includes: first poles and second poles of a plurality of transistors of the scan driving control circuit, a plurality of clock signal lines and a plurality of power supply lines.
  • the third conductive layer may include: the first pole and the second pole of the first transistor T1 to the tenth transistor T10, the first clock signal line CKL, the second clock signal line CBL, the initial signal line STV, the first power supply line PL1 , the second power line PL2 , the third power line PL3 , the first connection electrode 211 and the second connection electrode 212 .
  • the first pole 131 of the third transistor T3, the first pole 161 of the sixth transistor T6 and the second power line PL2 may have an integrated structure.
  • the second pole 121 of the second transistor T2 and the second pole 132 of the third transistor T3 may have an integral structure.
  • the second pole 142 of the fourth transistor T4 and the second pole 152 of the fifth transistor T5 may have an integrated structure.
  • the first pole 151 of the fifth transistor T5 , the first pole 181 of the eighth transistor T8 , the first pole 191 of the ninth transistor T9 and the first power line PL1 may have an integrated structure.
  • the second pole 162 of the sixth transistor T6 and the second pole 172 of the seventh transistor T7 may have an integral structure.
  • the second pole 192 of the ninth transistor T9 and the second pole 202 of the tenth transistor T10 may have an integrated structure.
  • the first pole 201 of the tenth transistor T10 and the third power line PL3 may have an integral structure.
  • the first connection electrode 211 is connected to the first pole C2-1 of the second capacitor C2 through the second via hole K9, and connected to the fourth capacitor C4 through the second via hole K7.
  • the first pole C4-1 of the first transistor T1 is connected to the second doped region 110c of the active layer 110 of the first transistor T1 through the first via hole F6, and is also connected to the control electrode 143 of the fourth transistor T4 through the second via hole K6 connect.
  • the projection of the first connection electrode 211 on the base substrate is located between the projections of the first power line PL1 and the second power line PL2 on the base substrate.
  • the second connection electrode 212 is connected to the second electrode C1-2 of the first capacitor C1 through the third via hole D3, and is also connected to the control electrode 173 of the seventh transistor T7 through the second via hole K5.
  • the first power line PL1 is connected to the second pole C3 - 2 of the third capacitor C3 through a plurality of (for example, three) third via holes D4 arranged vertically.
  • this embodiment does not limit it.
  • the first transistor T1 includes: an active layer 110 , a control electrode 113 , a first electrode 111 and a second electrode 112 .
  • the active layer 110 of the first transistor T1 includes: a channel region 110a, a first doped region 110b and a second doped region 110c.
  • the active layer 110 of the first transistor T1 is adjacent to the second power line PL2.
  • the distance L2 between the channel region 110a of the active layer 110 of the first transistor T1 close to the side of the second power line PL2 and the side of the second power line PL2 away from the first transistor T1 satisfies: 0 ⁇ L2 ⁇ 4W PL2 ;
  • W PL2 is the width of the second power line PL2 (that is, the length X3 of the second power line PL2 along the first direction X).
  • the first electrode 111 of the first transistor T1 is connected to the first doped region 110b of the active layer 110 of the first transistor T1 through the first via hole F5, and is also connected to the signal input terminal IN through the third via hole D1.
  • the control electrode 113 of the first transistor T1 and the control electrode 133 of the third transistor T3 have an integrated structure, and the first clock signal line CKL is connected to the control electrode 113 of the first transistor T1 through two second via holes K1 arranged vertically. In order to realize that the control electrode 113 of the first transistor T1 receives the first clock signal.
  • arranged side by side may mean arranged in sequence along the first direction X
  • “arranged vertically” may mean arranged in sequence along the second direction Y.
  • the second transistor T2 includes: an active layer 120 , a control electrode 123 , a first electrode 121 and a second electrode 122 .
  • the active layer 120 of the second transistor T2 includes: a channel region 120a, a first doped region 120b and a second doped region 120c.
  • the control electrode 123 of the second transistor T2, the first electrode C2-1 of the second capacitor C2, and the control electrode 203 of the tenth transistor T10 are integrated.
  • the first electrode 121 of the second transistor T2 is connected to the first doped region 120b of the active layer 120 of the second transistor T2 through the first via hole F4, and is also connected to the control electrode 113 of the first transistor T1 through the second via hole K2.
  • the second pole 122 of the second transistor T2 is integrated with the second pole 132 of the third transistor T3.
  • the second electrode 122 of the second transistor T2 is connected to the second doped region 120c of the active layer 120 of the second transistor T2 through the first via hole F3, and is also connected to the control electrode 153 of the fifth transistor T5 through the second via hole K8. connect.
  • the second power line PL2 is located on a side of the second transistor T2 away from the first clock signal line CKL.
  • the active layer 120 of the second transistor T2 is adjacent to the second power line PL2.
  • the distance L4 between the channel region 120a of the active layer 120 of the second transistor T2 close to the second power line PL2 and the side of the second power line PL2 away from the second transistor T2 satisfies: 0 ⁇ L4 ⁇ 3W PL2 ;
  • W PL2 is the width of the second power line PL2.
  • the third transistor T3 includes: an active layer 130 , a control electrode 133 , a first electrode 131 and a second electrode 132 .
  • the active layer 130 of the third transistor T3 includes: a channel region 130a, a first doped region 130b and a second doped region 130c.
  • the first pole 131 of the third transistor T3 is integrated with the second power line PL2.
  • the first electrode 131 of the third transistor T3 is connected to the first doped region 130b of the active layer 130 of the third transistor T3 through the first via hole F1.
  • the second pole 132 of the third transistor T3 is connected to the second doped region 130c of the active layer 130 of the third transistor T3 through the first via hole F2.
  • the second power line PL2 is located on a side of the third transistor T3 away from the initial signal line STV.
  • the distance L3 between the channel region 130a of the active layer 130 of the third transistor T3 close to the side of the second power line PL2 and the side of the second power line PL2 away from the third transistor T3 satisfies: 0 ⁇ L3 ⁇ 4W PL2 ;
  • W PL2 is the width of the second power line PL2.
  • the fourth transistor T4 includes: an active layer 140 , a control electrode 143 , a first electrode 141 and a second electrode 142 .
  • the active layer 140 of the fourth transistor T4 includes: a channel region 140a, a first doped region 140b and a second doped region 140c.
  • the control electrode 143 of the fourth transistor T4 and the first electrode C4-1 of the fourth capacitor C4 are integrally formed.
  • the first electrode 141 of the fourth transistor T4 is connected to the first doped region 140b of the active layer 140 of the fourth transistor T4 through the first via hole F7, and is also connected to the control electrode 173 of the seventh transistor T7 through the second via hole K4. connect.
  • the second pole 142 of the fourth transistor T4 is integrated with the second pole 152 of the fifth transistor T5.
  • the second pole 142 of the fourth transistor T4 is connected to the second doped region 140c of the active layer 140 of the fourth transistor T4 through the first via hole F8, and is also connected to the second pole of the fourth capacitor C4 through the third via hole D2. C4-2 connection.
  • the fifth transistor T5 includes: an active layer 150 , a control electrode 153 , a first electrode 151 and a second electrode 152 .
  • the active layer 150 of the fifth transistor T5 includes: a channel region 150a, a first doped region 150b and a second doped region 150c.
  • the control electrode 153 of the fifth transistor T5 and the control electrode 163 of the sixth transistor T6 are integrated.
  • the first pole 151 of the fifth transistor T5 is integrated with the first power line PL1.
  • the first pole 151 of the fifth transistor T5 is connected to the first doped region 150b of the active layer 150 of the fifth transistor T5 through the first via hole F10.
  • the second pole 152 of the fifth transistor T5 is connected to the second doped region 150c of the active layer 150 of the fifth transistor T5 through the first via hole F9.
  • the sixth transistor T6 includes: an active layer 160 , a control electrode 163 , a first electrode 161 and a second electrode 162 .
  • the active layer 160 of the sixth transistor T6 includes: a channel region 160a, a first doped region 160b and a second doped region 160c.
  • the first pole 161 of the sixth transistor T6 is integrated with the second power line PL2.
  • the first pole 161 of the sixth transistor T6 is connected to the first doped region 160b of the active layer 160 of the sixth transistor T6 through the first via hole F14.
  • the second pole 162 of the sixth transistor T6 and the second pole 172 of the seventh transistor T7 are integrally formed.
  • the second pole 162 of the sixth transistor T6 is connected to the second doped region 160c of the active layer 160 of the sixth transistor T6 through the first via hole F15.
  • the seventh transistor T7 includes: an active layer 170 , a control electrode 173 , a first electrode 171 and a second electrode 172 .
  • the active layer 170 of the seventh transistor T7 and the active layer 180 of the eighth transistor T8 are integrally structured.
  • the active layer 170 of the seventh transistor T7 includes: a channel region 170a, a first doped region 170b and a second doped region 170c.
  • the first doped region 170b of the active layer 170 of the seventh transistor T7 is connected to the second doped region 180c of the active layer 180 of the eighth transistor T8.
  • the first electrode 171 of the seventh transistor T7 is connected to the first doped region 170b of the active layer 170 of the seventh transistor T7 through the first via hole F12, and is also connected to the first electrode of the third capacitor C3 through the second via hole K10. C3-1 connection.
  • the second pole 172 of the seventh transistor T7 is connected to the second doped region 170c of the active layer 170 of the seventh transistor T7 through the first via hole F13.
  • the second clock signal line CBL is connected to the control electrode 173 of the seventh transistor T7 through two second via holes K3 arranged vertically.
  • the eighth transistor T8 includes: an active layer 180 , a control electrode 183 and a first electrode 181 .
  • the active layer 180 of the eighth transistor T8 includes: a channel region 180a, a first doped region 180b and a second doped region 180c.
  • the control electrode 183 of the eighth transistor T8 and the first electrode C4-1 of the fourth capacitor C4 are integrated.
  • the first pole 181 of the eighth transistor T8 is integrated with the first power line PL1.
  • the first electrode 181 of the eighth transistor T8 is connected to the first doped region 180b of the active layer 180 of the eighth transistor T8 through the first via hole F11.
  • the ninth transistor T9 includes: an active layer, control electrodes 193 a and 193 b , a first electrode 191 and a second electrode 192 .
  • the active layer of the ninth transistor T9 includes a first partition 190-1 and a second partition 190-2.
  • the first subregion 190-1 of the ninth transistor T9 includes: channel regions 190-1a1 and 190-1a2, a first doped region 190-1b, a second doped region 190-1c, and a third doped region 190-1d .
  • the second subregion 190-2 of the ninth transistor T9 includes: channel regions 190-2a1 and 190-2a2, a first doped region 190-2b, a second doped region 190-2c, and a third doped region 190-2d .
  • the first pole 191 of the ninth transistor T9 is integrated with the first power line PL1.
  • the first electrode 191 of the ninth transistor T9 is connected to the first doped region 190-1b of the first subregion 190-1 of the ninth transistor T9 through a plurality of (for example, three) first vias F18 arranged side by side.
  • the second pole 192 of the ninth transistor T9 and the second pole 202 of the tenth transistor T10 are integrally formed.
  • the second pole 192 of the ninth transistor T9 is connected to the second doped region 190-1c of the first subregion 190-1 of the ninth transistor T9 through a plurality of (for example, three) first vias F16 arranged side by side.
  • the second doped region 190-2c of the second subregion 190-2 of the ninth transistor T9 is connected through a plurality of (for example, three) first via holes F17 arranged side by side, and also through a plurality of (for example, three) Three) first vias F20 are connected to the third doped region 190-1d of the first subregion 190-1 of the ninth transistor T9, and are connected to The third doped region 190-2d of the second subregion 190-2 of the ninth transistor T9 is connected.
  • the tenth transistor T10 includes: an active layer, a control electrode 203 , a first electrode 201 and a second electrode 202 .
  • the active layer of the tenth transistor T10 includes: a third partition 200-1 and a fourth partition 200-2.
  • the third subregion 200-1 of the tenth transistor T10 includes: channel regions 200-1a1 and 200-1a2, a first doped region 200-1b, a second doped region 200-1c, and a third doped region 200-1d .
  • the fourth subregion 200-2 of the tenth transistor T10 includes: a channel region 200-2a, a first doped region 200-2b and a second doped region 200-2c.
  • the third subregion 200-1 of the tenth transistor T10 and the first subregion 190-1 of the ninth transistor T9 have an integral structure, and the second doped region 200-1c of the third subregion 200-1 and the first subregion 190-1 of the ninth transistor The third doped region 190-1d of 190-1 is connected.
  • the fourth subregion 200-2 of the tenth transistor T10 and the second subregion 190-2 of the ninth transistor T9 have an integrated structure, and the second doped region 200-2c of the fourth subregion 200-2 and the second doped region 200-2c of the ninth transistor T9
  • the third doped region 190-2d of the partition 190-2 is connected.
  • the first pole 201 of the tenth transistor T10 is integrated with the third power line PL3.
  • the first electrode 201 of the tenth transistor T10 is connected to the first doped region 200-1b of the third subregion 200-1 of the tenth transistor T10 through a plurality of (for example, three) first vias F22 arranged side by side, and It is connected to the first doped region 200-2b of the fourth subregion 200-2 of the tenth transistor T10 through a plurality of (for example, three) first vias F23 arranged side by side.
  • the second pole 202 of the tenth transistor T10 is connected to the third doped region 200-1d of the third subregion 200-1 of the tenth transistor T10 through a plurality of (for example, three) first vias F24 arranged side by side.
  • the second pole 202 of the tenth transistor T10 is also connected to the signal output terminal OUT through two third via holes D5 arranged side by side.
  • the output control circuit of the scan driving control circuit includes: a first node control capacitor and a second node control capacitor.
  • the first node control capacitor may be configured to control the potential of the first node N1
  • the second node control capacitor may be configured to control the potential of the second node N2.
  • the first node control capacitor includes a first capacitor C1 and a third capacitor C3.
  • the second node control capacitor includes a second capacitor C2 and a fourth capacitor C4.
  • the potential of the second node N2 can be made more stable, so that the tenth transistor T10 can realize a stable output.
  • the general function of the capacitor is to stabilize the potential of the node, and the area of the capacitor is related to the range in which the potential of the node controlled by the capacitor needs to be maintained.
  • capacitors need to be properly arranged in a smaller space to realize their functions.
  • the ratio of the width of the capacitor for example, the length along the first direction
  • the width of the scan drive control circuit it is possible to ensure or even optimize the scan rate under the premise of efficient use of space. performance of the drive control circuit.
  • the lengths of the first node control capacitor, the second node control capacitor and the scan driving control circuit in the first direction satisfy:
  • L C1k is the length of the first node control capacitor in the first direction
  • L C2k is the length of the second node control capacitor in the first direction
  • LY is the length of the scan driving control circuit in the first direction.
  • the length LY of the scan driving control circuit in the first direction is the distance between the side of the clock signal line or the start signal line away from the display area and the side of the power line close to the display area.
  • the wiring on the side away from the display area shall prevail.
  • the side close to the display area has a power supply line and other lines (for example, the line extending from the signal output end to the display area)
  • the line close to the display area shall prevail.
  • the length LY of the scan driving control circuit in the first direction X is the side of the first clock signal line CKL away from the display area and the side of the third power line PL3 close to the display area. the distance between.
  • the length L C1k of the first node control capacitor in the first direction may be the shorter of the length of the first capacitor C1 in the first direction and the length of the third capacitor C3 in the first direction. the big one.
  • the length L C2k of the second node control capacitor in the first direction may be the larger of the length of the second capacitor C2 in the first direction and the length of the fourth capacitor C4 in the first direction.
  • the length of the capacitor in the first direction may be the maximum value of the length of the capacitor in the first direction.
  • the lengths of the first capacitor, the third capacitor, the second node control capacitor and the scan driving control circuit in the first direction satisfy:
  • L C1 is the length of the first capacitor in the first direction
  • L C3 is the length of the third capacitor in the first direction
  • L C2k is the length of the second node control capacitor in the first direction
  • LY is the scan The length of the drive control circuit in the first direction.
  • the length of the first capacitor and the scan driving control circuit in the first direction satisfies:
  • the length of the second node control capacitor and the scan drive control circuit in the first direction satisfies:
  • the length of the third capacitor and the scan drive control circuit in the first direction satisfies:
  • the capacitor may overlap with the projection of the power line or the clock signal line on the base substrate.
  • the projection of the third capacitor and the first power line on the base substrate overlaps, and the overlapping area satisfies:
  • S C3 is the projected area of the third capacitor on the base substrate
  • S C3-1 is the overlapping area of the projection of the third capacitor and the first power line on the base substrate
  • S C2 is the projection area of the second capacitor on the substrate. The projected area on the base substrate.
  • the second node control capacitor overlaps with the projection of the first power line on the base substrate, and the overlapping area satisfies:
  • S C2k-1 is the overlapping area of the second node control capacitor and the projection of the first power line on the substrate
  • X2 is the length of the first power line in the first direction
  • L5 is the second node control capacitor The length in the second direction of the overlapping area of one of the capacitors and the projection of the first power line on the base substrate.
  • the projected area of the second node control capacitor may be the sum of the projected area of the second capacitor and the projected area of the fourth capacitor.
  • L5' is the length in the second direction Y of the overlapping area of the projection of the second capacitor C2 and the first power line PL1 on the base substrate.
  • L5" is the length in the second direction Y of the overlapping area of the projection of the fourth capacitor C4 and the first power line PL1 on the substrate substrate.
  • One of the capacitors of the second node control capacitor and the first power line are on the substrate
  • the length L5 of the projected overlapping area on the substrate in the second direction may be L5' or L5".
  • the second node control capacitor overlaps with the projection of the second power line on the base substrate, and the overlapping area satisfies:
  • S C2k-2 is the overlapping area of the second node control capacitor and the projection of the second power line on the substrate
  • X3 is the length of the second power line in the first direction
  • L6 is the second node control capacitor The length in the second direction of the overlapping area of one of the capacitors and the projection of the second power line on the base substrate.
  • L6' is the length in the second direction Y of the overlapping area of the projection of the second capacitor C2 and the second power line PL2 on the base substrate.
  • L6" is the length in the second direction Y of the overlapping area of the fourth capacitor C4 and the projection of the second power line PL2 on the substrate.
  • One of the capacitors of the second node control capacitor and the second power line are on the substrate
  • the length L6 of the projected overlapping area on the substrate in the second direction may be L6' or L6".
  • the distance between the center of the first capacitor C1 in the first direction X and the side of the first power line PL1 away from the first capacitor C1 in the first direction X L7 is greater than the distance L8 between the center of the first capacitor C1 in the first direction X and the side of the second power line PL2 close to the first capacitor C1 in the first direction X, and L7 ⁇ 2*L8.
  • the distance L9 between the side of the active layer 180 of the eighth transistor T8 close to the third capacitor C3 and the side of the third capacitor C3 close to the eighth transistor T8 satisfies : W CLK ⁇ L9 ⁇ W PL1 ; wherein, W CLK is the width of the clock signal line, and W PL1 is the width of the first power line.
  • W CLK may be the width of the first clock signal line CKL or may be the width of the second clock signal line CBL.
  • the width W PL1 of the first power line PL1 is the length X2 of the first power line PL1 in the first direction X.
  • the side of the capacitor is the outermost side.
  • L9 may be the distance between the side of the active layer 180 of the eighth transistor T8 close to the third capacitor C3 and the side of the third capacitor C3 closest to the eighth transistor T8.
  • the capacitance values of the first capacitor, the third capacitor and the second node control capacitor satisfy:
  • C 1 is the capacitance value of the first capacitor
  • C 3 is the capacitance value of the third capacitor
  • C 2k is the capacitance value of the second node control capacitor.
  • the capacitance of the second node control capacitor may be the sum of the capacitances of the second capacitor C2 and the fourth capacitor C4.
  • FIG. 22 is a top view of a cascaded scan driving control circuit according to at least one embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram of the first conductive layer shown in FIG. 22 .
  • the first pole C2-1 of the second capacitor C2 of the nth-level scan drive control circuit and the fourth capacitor of the n+1-th scan drive control circuit may have an integral structure.
  • the stability of the second node can be improved while simplifying the process.
  • the signal output terminal OUT of the nth level scan driving control circuit and the input terminal IN of the n+1th level scan driving control circuit may have an integrated structure.
  • FIG. 24 is another top view of the scan driving control circuit according to at least one embodiment of the present disclosure.
  • the signal output terminal OUT is located on a side of the ninth transistor T9 and the tenth transistor T10 away from the first power line PL1 .
  • the signal output terminal OUT and the second pole of the second capacitor C2 may have an integral structure.
  • the signal output terminal OUT may have three protrusions protruding toward a side close to the first power line PL1 along the first direction X.
  • the second pole 192 of the ninth transistor T9 can be connected to the first protruding part of the signal output terminal OUT through the third via hole D6, and can also be connected to the second protruding part of the signal output terminal OUT through the third via hole D7.
  • the second pole 202 of the tenth transistor T10 can be connected to the third protrusion of the signal output terminal OUT through the third via hole D8.
  • this embodiment does not limit it.
  • the length LY of the scan driving control circuit in the first direction X may be the extension distance of the first clock signal line CKL away from the side of the display area and the signal output terminal OUT. The distance between the sides of the line close to the display area.
  • FIG. 25 is another top view of the scan driving control circuit according to at least one embodiment of the present disclosure.
  • the boundary of the first conductive layer of the scan driving control circuit is closer to the display area than the side of the third power line PL3 .
  • the length LY of the scan driving control circuit in the first direction X may be the side of the first clock signal line CKL away from the display area and the side of the first conductive layer of the scan driving control circuit close to the display area (
  • the control electrode 203 of the tenth transistor T10 is close to the distance between the sides of the display area).
  • the structure of the display substrate will be described below through an example of the manufacturing process of the display substrate with reference to FIGS. 15 to 21 .
  • the “patterning process” mentioned in this disclosure includes deposition of film layer, coating of photoresist, mask exposure, development, etching and stripping of photoresist. Any one or more of sputtering, evaporation and chemical vapor deposition can be used for deposition, any one or more of spray coating and spin coating can be used for coating, and any of dry etching and wet etching can be used for etching. one or more.
  • “Film” refers to a layer of film produced by depositing or coating a certain material on a substrate.
  • the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • a and B are arranged in the same layer in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the projection of A includes the projection of B means that the boundary of the projection of B falls within the boundary range of the projection of A, or the boundary of the projection of A overlaps with the boundary of the projection of B.
  • the manufacturing process of the display substrate of this exemplary embodiment includes the following steps.
  • the substrate substrate 30 may be a rigid substrate or a flexible substrate.
  • the rigid substrate may comprise one or more of glass, metal foil.
  • Flexible substrates may include polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide One or more of amine, polyvinyl chloride, polyethylene, textile fiber.
  • a first semiconductor thin film is deposited on the base substrate 30, and the first semiconductor thin film is patterned through a patterning process to form a first semiconductor layer pattern, as shown in FIG. 17 .
  • the first semiconductor layer pattern includes at least: an active layer of a plurality of transistors (for example, transistors T1 to T10 ) in the scan driving control circuit.
  • the active layer may include at least one channel region and a plurality of doped regions.
  • the channel region may not be doped with impurities and has semiconductor characteristics.
  • the doped region is doped with impurities and thus has conductivity. Impurities may vary depending on the type of transistor (eg, N-type or P-type).
  • the material of the first semiconductor thin film may be polysilicon.
  • a first insulating film and a first conductive film are sequentially deposited on the base substrate 30 with the aforementioned pattern, and the first conductive film is patterned by a patterning process to form a first semiconductor layer covering the pattern.
  • the first conductive layer pattern may include: control electrodes of multiple transistors (eg, transistors T1 to T10 ) of the scan driving control circuit, multiple capacitors (eg, first capacitors C1 to The first pole of four capacitors C4).
  • a second insulating film and a second conductive film are sequentially deposited on the base substrate 30 formed with the aforementioned pattern, and the second conductive film is patterned by a patterning process to form a second insulating film covering the first conductive layer.
  • the insulating layer 32 and the second conductive layer pattern disposed on the second insulating layer 32 are shown in FIG. 19 .
  • the second conductive layer pattern may include: second poles of a plurality of capacitors (eg, first capacitors C1 to fourth capacitors C4 ) of the scan driving control circuit, a signal input terminal IN and a signal output terminal OUT.
  • a third insulating film is deposited on the base substrate 30 with the aforementioned pattern, and the third insulating film is patterned by a patterning process to form a pattern of the third insulating layer 33 covering the second conductive layer, such as Figure 20 shows.
  • a plurality of via holes are opened on the third insulating layer 33 .
  • the plurality of vias at least include: a plurality of first vias F1 to F25 , a plurality of second vias K1 to K10 , and a plurality of third vias D1 to D5 .
  • the third insulating layer 33 , the second insulating layer 32 and the first insulating layer 31 in the plurality of first via holes F1 to F25 are etched away, exposing the surface of the first semiconductor layer.
  • the third insulating layer 33 and the second insulating layer 32 in the plurality of second via holes K1 to K10 are etched away, exposing the surface of the first conductive layer.
  • the third insulating layer 33 in the plurality of third via holes D1 to D5 is etched away, exposing the surface of the second conductive layer.
  • a third conductive film is deposited on the base substrate 30 with the aforementioned pattern formed, and the third conductive film is patterned by a patterning process to form a third conductive layer pattern on the third insulating layer 33, such as Figure 21.
  • the third conductive layer pattern may include: first and second electrodes of a plurality of transistors (eg, transistors T1 to T10 ) of the scan driving control circuit, a first connection electrode 211 and a second connection electrode 212 .
  • the pixel circuit may be formed in the display area.
  • the first semiconductor layer of the display area may include the active layer of the transistor of the pixel circuit
  • the first conductive layer of the display area may include the control electrode of the transistor of the pixel circuit and the first electrode of the storage capacitor
  • the second conductive layer of the display area may include The layer may include at least the second electrode of the storage capacitor of the pixel circuit
  • the third conductive layer of the display area may include at least the first electrode and the second electrode of the transistor of the pixel circuit.
  • a second semiconductor layer may be formed in the display area, and an insulating layer is disposed between the second semiconductor layer and the first conductive layer.
  • the material of the second semiconductor thin film can be metal oxide, for example, IGZO.
  • the present embodiment does not limit the position of the second semiconductor layer.
  • a fourth insulating layer, an anode layer, a pixel definition layer, an organic light emitting layer, a cathode layer, and an encapsulation layer pattern may be sequentially formed in the display region.
  • a fourth insulating film is coated on the base substrate formed with the aforementioned pattern, and a fourth insulating layer pattern is formed by masking, exposing and developing the fourth insulating film.
  • an anode film is deposited on the substrate of the display area with the aforementioned pattern formed, and the anode film is patterned by a patterning process to form an anode pattern on the fourth insulating layer.
  • a pixel definition film is coated on the base substrate with the aforementioned pattern, and a pixel definition layer (PDL, Pixel Define Layer) pattern is formed through masking, exposure and development processes, and the pixel definition layer is formed on each sub-pixel in the display area , the pixel definition layer in each sub-pixel is formed with a pixel opening exposing the anode.
  • PDL Pixel Define Layer
  • an organic light-emitting layer is formed in the aforementioned pixel opening, and the organic light-emitting layer is connected to the anode.
  • a cathode thin film is deposited, and the cathode thin film is patterned through a patterning process to form a cathode pattern.
  • an encapsulation layer is formed on the cathode, and the encapsulation layer may include a stacked structure of inorganic material/organic material/inorganic material.
  • the first conductive layer, the second conductive layer, and the third conductive layer can use metal materials, such as any of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • metal materials such as any of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • metal materials such as any of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • metal materials such as any of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • metal materials such as any of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer 31, the second insulating layer 32 and the third insulating layer 33 can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can Is single layer, multilayer or composite layer. Organic materials such as polyimide, acrylic or polyethylene terephthalate can be used for the fourth insulating layer.
  • the first insulating layer 31 and the second insulating layer 32 are called a gate insulating (GI) layer
  • the third insulating layer 33 is called an interlayer insulating (ILD) layer
  • the fourth insulating layer is called a planarization layer.
  • the pixel definition layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate.
  • the anode can use transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the cathode can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or any one or more of the above metals alloy. However, this embodiment does not limit it.
  • reflective materials such as metal can be used for the anode
  • transparent conductive materials can be used for the cathode.
  • the structure shown in this exemplary embodiment and its preparation process are only exemplary illustrations. In some exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the preparation process of this exemplary embodiment can be realized by using currently mature preparation equipment, and is well compatible with the existing preparation process. The process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield.
  • an embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate.
  • the display substrate may be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.
  • the display device can be any product or component with a display function, such as an OLED display device, a watch, a mobile phone, a tablet computer, a television set, a monitor, a notebook computer, a digital photo frame, a navigator, and the like. However, this embodiment does not limit it.
  • FIG. 25 is a schematic structural diagram of a display device according to at least one embodiment of the present disclosure.
  • the display device may include: a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, and the pixel array may include a plurality of scan lines (such as GL1 to GLn), A plurality of data signal lines (eg, DL1 to DLn), a plurality of light emission control lines (eg, EL1 to ELn), and a plurality of sub-pixels 10 .
  • Each sub-pixel 10 may be connected to a corresponding data signal line, a corresponding scan line, and a corresponding light emission control line.
  • the timing controller may provide grayscale values and control signals suitable for the specification of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the
  • the scan driver can supply a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting driver to the light-emitting driver.
  • the data driver may generate data voltages to be supplied to the data signal lines DL1, DL2, DL3, . . . and DLm using gray values and control signals received from the timing controller, and m may be an integer.
  • the data driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data signal lines DL1 to DLm in units of pixel rows.
  • the scan driver may generate scan signals to be supplied to the scan lines GL1, GL2, GL3, . . . and GLn by receiving a clock signal, a scan start signal, etc. from the timing controller, and n may be an integer.
  • the scan driver may sequentially supply scan signals having turn-on level pulses to the scan lines GL1 to GLn.
  • the scan driver can be configured in the form of a shift register, and can generate scan signals in such a manner as to sequentially transmit scan start signals supplied in the form of on-level pulses to the next-stage circuit under the control of a clock signal .
  • the light emission driver may generate emission signals to be supplied to the light emission control lines EL1, EL2, EL3, . . . , and ELn by receiving a clock signal, an emission stop signal, etc. from the timing controller.
  • the light emission driver may sequentially supply emission signals having off-level pulses to the light emission control lines EL1 to ELn.
  • the light emitting driver may be configured in the form of a shift register, and may generate light emitting signals in such a manner as to sequentially transmit light emitting stop signals provided in the form of off-level pulses to the next-stage circuit under the control of a clock signal.
  • the light emitting driver may include multiple cascaded scan driving control circuits as provided in the above embodiments. In this example, the working sequence of the scan driving control circuit can be shown in FIG. 10 .
  • the shape of the sub-pixel 10 may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the three sub-pixels can be arranged horizontally, vertically or squarely; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically or squarely .
  • this embodiment does not limit it.
  • one pixel unit in the display area may include three sub-pixels, and the three sub-pixels may be red sub-pixels, green sub-pixels and blue sub-pixels respectively.
  • this embodiment does not limit it.
  • one pixel unit may include four sub-pixels, and the four sub-pixels are respectively a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel.
  • a timing controller, a data driver, a scan driver, and a light emitting driver may be disposed in the non-display area.
  • the scan driver and the light-emitting driver can be arranged on opposite sides of the display area, for example, the left side and the right side of the display area; the timing controller and the data driver can be arranged on one side of the display area, for example, the lower side of the display area .
  • this embodiment is not limited to this.
  • a subpixel includes pixel circuitry.
  • the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • a pixel circuit may include N-type transistors and P-type transistors.
  • the N-type transistor can be, for example, an oxide thin film transistor
  • the P-type transistor can be, for example, a low temperature polysilicon thin film transistor.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current.
  • the low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (LTPO) , Low Temperature Polycrystalline Oxide) display substrate, can take advantage of the advantages of both, can achieve low-frequency drive, can reduce power consumption, and can improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • Low Temperature Polycrystalline Oxide Low Temperature Polycrystalline Oxide
  • FIG. 27 is another schematic structural diagram of a display device according to at least one embodiment of the present disclosure.
  • the scan driver can provide driving signals to the P-type transistors of the pixel circuit through the first group of scan lines GL1 to GLn, and can also provide driving signals to the pixel circuits through the second group of scan lines SL1 to SLn.
  • the N-type transistor of the circuit provides the drive signal.
  • the light emitting driver may provide light emitting signals to the pixel circuits through the light emitting control lines EL1 to ELn.
  • the scan driver may include a plurality of cascaded scan drive control circuits as described in the above embodiments to provide drive signals to the N-type transistors of the pixel circuit through the second set of scan lines SL1 to SLn.
  • the working sequence of the scan driving control circuit can be shown in FIG. 9 .

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Abstract

一种显示基板，包括：衬底基板（30）和设置在衬底基板（30）的非显示区域的扫描驱动控制电路。扫描驱动控制电路包括：输入电路、输出控制电路和输出电路。输出控制电路与输入电路和输出电路连接。输出控制电路包括：第一节点控制电容和第二节点控制电容。第一节点控制电容在第一方向上的长度L C1k、第二节点控制电容在第一方向上的长度L C2k、以及扫描驱动控制电路在第一方向上的长度L Y满足(aa)。

Description

显示基板及显示装置
本申请要求于2021年7月9日提交中国专利局、申请号为202110774729.4、发明名称为“显示基板及显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diode，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示基板及显示装置。
一方面，本公开实施例提供一种显示基板，包括：衬底基板和设置在衬底基板的非显示区域的扫描驱动控制电路。扫描驱动控制电路包括：输入电路、输出控制电路和输出电路。输出控制电路与输入电路和输出电路连接。输出控制电路包括：第一节点控制电容和第二节点控制电容。第一节点控制电容在第一方向上的长度L C1k、第二节点控制电容在第一方向上的长度L C2k、以及扫描驱动控制电路在第一方向上的长度L Y满足：
Figure PCTCN2022104688-appb-000001
在一些示例性实施方式中，所述第一节点控制电容包括：第一电容和第三电容。所述第一电容、所述第三电容、所述第二节点控制电容和所述扫描驱动控制电路在第一方向上的长度满足：
Figure PCTCN2022104688-appb-000002
Figure PCTCN2022104688-appb-000003
其中，L C1为所述第一电容在第一方向上的长度，L C3为所述第三电容在第一方向上的长度，L C2k为所述第二节点控制电容在第一方向上的长度，L Y为所述扫描驱动控制电路在第一方向上的长度。
在一些示例性实施方式中，所述第一电容和所述扫描驱动控制电路在第一方向上的长度满足：
Figure PCTCN2022104688-appb-000004
所述第二节点控制电容和所述扫描驱动控制电路在第一方向上的长度满足：
Figure PCTCN2022104688-appb-000005
所述第三电容和所述扫描驱动控制电路在第一方向上的长度满足：
Figure PCTCN2022104688-appb-000006
在一些示例性实施方式中，
Figure PCTCN2022104688-appb-000007
为以下之一：0.09、0.10、0.14；
Figure PCTCN2022104688-appb-000008
为以下之一：0.22、0.35、0.48；
Figure PCTCN2022104688-appb-000009
为以下之一：0.07、0.06、0.05。
在一些示例性实施方式中，
Figure PCTCN2022104688-appb-000010
在一些示例性实施方式中，
Figure PCTCN2022104688-appb-000011
在一些示例性实施方式中，
Figure PCTCN2022104688-appb-000012
在一些示例性实施方式中，所述第一电容、所述第二节点控制电容以及所述第三电容在第一方向上的长度满足：
Figure PCTCN2022104688-appb-000013
在一些示例性实施方式中，所述第三电容与第一电源线连接；所述第三电容与第一电源线在所述衬底基板上的投影存在交叠，且交叠面积满足：
Figure PCTCN2022104688-appb-000014
其中，S C3为所述第三电容在所述衬底基板上的投影面积，S C3-1为所述第三电容和第一电源线在所述衬底基板上的投影的交叠面积；所述第二节点控制电容包括第二电容，S C2为所述第二电容在所述衬底基板上的投影面积。
在一些示例性实施方式中，所述第二节点控制电容与第一电源线在所述衬底基板上的投影存在交叠，且交叠面积满足：
Figure PCTCN2022104688-appb-000015
其中，S C2k-1为所述第二节点控制电容和第一电源线在所述衬底基板上的投影的交叠面积，X2为所述第一电源线在第一方向上的长度，L5为所述第二节点控制电容的其中一个电容与第一电源线在所述衬底基板上的投影的交叠区域在第二方向上的长度；所述第二方向与所述第一方向交叉。
在一些示例性实施方式中，所述输入电路与第二电源线连接；所述第二节点控制电容与第二电源线在所述衬底基板上的投影存在交叠，且交叠面积满足：
Figure PCTCN2022104688-appb-000016
其中，S C2k-2为所述第二节点控制电容和第二电源线在所述衬底基板上的投影的交叠面积，X3为所述第二电源线在第一方向上的长度，L6为所述第二节点控制电容的其中一个电容与第二电源线在所述衬底基板上的投影的交叠区域在第二方向上的长度；所述第二方向与所述第一方向交叉。
在一些示例性实施方式中，所述第一电容在所述衬底基板上的投影位于所述第一电源线和第二电源线在所述衬底基板上的投影之间。所述第一电容在第一方向上的中心与所述第一电源线在第一方向上远离所述第一电容的侧边之间的距离L7，大于所述第一电容在第一方向上的中心与所述第二电源线在第一方向上靠近所述第一电容的侧边之间的距离L8，且L7≥2*L8。
在一些示例性实施方式中，所述输入电路包括：第一晶体管；所述第一晶体管的控制极与第一时钟信号线连接，第一极与信号输入端连接，第二极与第二节点连接。所述第一晶体管的有源层和第二电源线相邻。所述第一晶体管的有源层的沟道区靠近所述第二电源线的侧边与所述第二电源线远离所述第一晶体管的侧边之间的距离L2满足：0≤L2≤4W PL2；其中，W PL2为所述第二电源线的宽度。
在一些示例性实施方式中，所述输入电路包括：第三晶体管；所述第三晶体管的控制极与第一时钟信号线连接，第一极与第二电源线连接，第二极与第三节点连接。所述第二电源线位于所述第三晶体管远离第一时钟信号线或第二时钟信号线的一侧。所述第三晶体管的有源层的沟道区靠近所述第二电源线的侧边与所述第二电源线远离所述第三晶体管的侧边之间的距离L3满足：0≤L3≤4W PL2；其中，W PL2为所述第二电源线的宽度。
在一些示例性实施方式中，所述输入电路与第一时钟信号线和第二电源线连接，所述输出控制电路与第二时钟信号线连接；所述输入电路包括：第二晶体管；所述第二晶体管的控制极与第二节点连接，第一极与第一时钟信号线连接，第二极与第三节点连接。所述第二电源线位于所述第二晶体管远离所述第一时钟信号线的一侧。所述第二晶体管的有源层和所述第二电源线相邻；所述第二晶体管的有源层的沟道区靠近所述第二电源线的侧边与所述第二电源线远离所述第二晶体管的侧边之间的距离L4满足：0≤L4≤3W PL2；其中，W PL2为所述第二电源线的宽度。
在一些示例性实施方式中，所述输出控制电路包括：第一输出控制子电路。所述第一输出控制子电路包括：第四晶体管和第五晶体管；所述第四晶体管的控制极与第二节点连接，第四晶体管的第一极与第五晶体管的第二极连接，第四晶体管的第二极与第二时钟信号线连接；所述第五晶体管的控制极与第三节点连接，第一极与第一电源线连接。所述第四晶体管和第五晶体管位于第二电源线远离第二时钟信号线的一侧。所述第四晶体管的有源层的延伸方向与第五晶体管的有源层的延伸方向的夹角大于85°且小于95°。
在一些示例性实施方式中，所述第四晶体管的有源层的沟道区的宽度W T4和所述第五晶体管的有源层的沟道区的宽度W T5满足：2W T4<W T5。
在一些示例性实施方式中，所述第四晶体管的有源层的延伸方向与所述输入电路的第一晶体管的有源层的延伸方向的夹角大于85°且小于95°。
在一些示例性实施方式中，所述输出控制电路包括第二输出控制子电路，所述第二输出控制子电路包括第七晶体管。所述第七晶体管的控制极与第一电容的第二极连接，第七晶体管的第一极与第一节点连接。所述第七晶体管与所述第一电容相邻，且所述第七晶体管位于所述第一电容和第一电源线之间。
在一些示例性实施方式中，所述第二输出控制子电路还包括：第六晶体管；所述第六晶体管的控制极与第一电容的第一极连接，第六晶体管的第二极与第七晶体管的第二极连接，第六晶体管的第一极与第二信号端连接。所述第七晶体管的有源层的延伸方向与所述第六晶体管的有源层的延伸方向近似平行。
在一些示例性实施方式中，所述输出控制电路包括：第三输出控制子电路，所述第三输出控制子电路包括第八晶体管和第三电容；所述第八晶体管的控制极与第二节点连接，第一极与第一电源线连接，第二极与第一节点连接；所述第三电容的第一极与第一节点连接，第二极与第一电源线连接。所述输入电路包括第一晶体管。所述第一晶体管、所述第八晶体管和第三电容沿着第一方向依次排布，所述第一晶体管的有源层的延伸方向与所述第八晶体管的有源层的延伸方向近似平行。
在一些示例性实施方式中，所述第八晶体管的有源层靠近第三电容的侧边与第三电容靠近第八晶体管的侧边之间的距离L9满足：W CLK<L9≤W PL1；其中，W CLK为时钟信号线的宽度，W PL1为第一电源线的宽度。
在一些示例性实施方式中，所述输入电路与第一时钟信号线连接；所述输出控制电路与第二时钟信号线和第一电源线连接；所述输出电路与第一电源线和第三电源线连接。所述第一时钟信号线、第二时钟信号线、初始信号线、第一电源线和第三电源线沿第一方向依次排布。
在一些示例性实施方式中，所述第一电容、第三电容和第二节点控制电容的电容值满足：
C 1<C 3<C 2k；
Figure PCTCN2022104688-appb-000017
其中，C 1为第一电容的电容值，C 3为第三电容的电容值，C 2k为第二节点控制电容的电容值。
在一些示例性实施方式中，所述第一电容的第一极与第三节点连接，所述第一电容的第二极与第七晶体管连接。所述第三电容的第一极与第一节点连接，所述第三电容的第二极与第一电源线连接。所述第二节点控制电容的第一极与第二节点连接。所述第一电容和第三电容的电容值之和小于所述第二节点控制电容的电容值。
在一些示例性实施方式中，所述第二节点控制电容包括第二电容，所述第二电容的第一极与第二节点连接，所述第二电容的第二极与信号输出端连接。
在一些示例性实施方式中，所述第二节点控制电容还包括：第四电容，所述第四电容的第一极与第二节点连接，所述第四电容的第二极与第四晶体管和第五晶体管连接。
在一些示例性实施方式中，本级扫描驱动控制电路的第二电容的第一极与下一级扫描驱动控制电路的第四电容的第一极为一体结构。
在一些示例性实施方式中，所述输出电路包括第十晶体管；所述第二节点控制电容包括第二电容，所述第二电容的第一极与第十晶体管的控制极为一体结构。
另一方面，本公开实施例提供一种显示装置，包括如上所述的显示基板。
另一方面，本公开实施例提供一种显示基板，包括扫描驱动控制电路。所述扫描驱动控制电路，包括：输入电路、输出控制电路和输出电路。所述输入电路，与信号输入端、第一时钟信号端、第一电压端和输出控制电路连接，配置为在第一时钟信号端的控制下，将信号输入端的信号传输至输出控制电路，以及将第一时钟信号端或第一电压端的信号传输至输出控制电路。所述输出控制电路，与第一信号端、第二信号端、第二时钟信号端、第二电压端、第一节点、第二节点和输入电路连接，配置为在输入电路的控制下，存储第一信号端的信号，在输入电路和第二时钟信号端的控制下，向第一节 点传输第二信号端的信号；或者，在输入电路的控制下，存储第二时钟信号端的信号，并在第二节点的控制下，向第一节点传输第二电压端的信号。所述输出电路，与第一电压端、第二电压端、信号输出端、第一节点和第二节点连接，配置为在第二节点的控制下，向信号输出端输出第一电压端的信号，或者，在第一节点的控制下，向信号输出端输出第二电压端的信号。
在一些示例性实施方式中，所述输入电路包括：第一输入子电路和第二输入子电路；所述输出控制电路包括：第一输出控制子电路、第二输出控制子电路和第三输出控制子电路；所述输出电路包括：第一输出子电路和第二输出子电路。所述第一输入子电路，与信号输入端、第一时钟信号端和第一输出控制子电路连接，配置为在第一时钟信号端的控制下，将信号输入端的信号传输至第一输出控制子电路。所述第二输入子电路，与第一电压端、第一时钟信号端、第一输入子电路和第二输出控制子电路连接，配置为在第一输入子电路或第一时钟信号端的控制下，将第一时钟信号端或第一电压端的信号传输至第二输出控制子电路。所述第一输出控制子电路，与第一信号端、第二时钟信号端、第二节点、第一输入子电路和第二输入子电路连接，配置为在第一输入子电路或第二输入子电路的控制下，存储第一信号端或第二时钟信号端的信号。所述第二输出控制子电路，与第二信号端、第二时钟信号端、第一节点和第二输入子电路连接，配置为在第二输入子电路和第二时钟信号端的控制下，向第一节点传输第二信号端的信号。所述第三输出控制子电路，与第二电压端、第一节点和第二节点连接，配置为在第二节点的控制下，向第一节点传输第二电压端的信号。所述第一输出子电路，与第一电压端、信号输出端和第二节点连接，配置为在第二节点的控制下，向信号输出端输出第一电压端的信号。所述第二输出子电路，与第二电压端、信号输出端和第一节点连接，配置为在第一节点的控制下，向信号输出端输出第二电压端的信号。
在一些示例性实施方式中，所述第一输入子电路包括：第一晶体管；所述第一晶体管的控制极与第一时钟信号端连接，第一极与信号输入端连接，第二极与第二节点连接。所述第二输入子电路包括：第二晶体管和第三晶体管；所述第二晶体管的控制极与第二节点连接，第一极与第一时钟信号端连 接，第二极与第三节点连接；所述第三晶体管的控制极与第一时钟信号端连接，第一极与第一电压端连接，第二极与第三节点连接。所述第一输出控制子电路包括：第四晶体管和第五晶体管；所述第四晶体管的控制极与第二节点连接，所述第四晶体管的第一极与第二时钟信号端连接，所述第四晶体管的第二极与第五晶体管的第二极连接；所述第五晶体管的控制极与第三节点连接，所述第五晶体管的第一极与第一信号端连接。所述第一输出子电路包括：第十晶体管；所述第十晶体管的控制极与第二节点连接，第一极与第一电压端连接，第二极与信号输出端连接。
在一些示例性实施方式中，所述第一输入子电路包括：第一晶体管；所述第一晶体管的控制极与第一时钟信号端连接，第一极与信号输入端连接，第二极与第四节点连接。所述第二输入子电路包括：第二晶体管和第三晶体管；所述第二晶体管的控制极与第四节点连接，第一极与第一时钟信号端连接，第二极与第三节点连接；所述第三晶体管的控制极与第一时钟信号端连接，第一极与第一电压端连接，第二极与第三节点连接。所述第一输出控制子电路包括：第四晶体管、第五晶体管和第十一晶体管；所述第四晶体管的控制极与第二节点连接，所述第四晶体管的第一极与第二时钟信号端连接，所述第四晶体管的第二极与第五晶体管的第二极连接；所述第五晶体管的控制极与第三节点连接，第一极与第一信号端连接；所述第十一晶体管的控制极与第一电压端连接，第一极与第四节点连接，第二极与第二节点连接。所述第一输出子电路包括：第十晶体管；所述第十晶体管的控制极与第二节点连接，第一极与第一电压端连接，第二极与信号输出端连接。
在一些示例性实施方式中，所述第二输出控制子电路还包括：第四电容；所述第四电容的第一极与第四晶体管和第十晶体管的控制极连接。
在一些示例性实施方式中，所述第四电容的第二极与第五晶体管连接。
在一些示例性实施方式中，所述第一输出控制子电路还包括：第二电容；所述第二电容的第一极与第二节点连接。
在一些示例性实施方式中，所述第二电容的第二极与信号输出端连接。
在一些示例性实施方式中，所述第二输入子电路与第三节点连接。所述第二输出控制子电路包括：第六晶体管、第七晶体管和第一电容。所述第六 晶体管的控制极与第三节点连接，所述第六晶体管的第一极与第二信号端连接，所述第六晶体管的第二极与第七晶体管的第二极连接；所述第七晶体管的控制极与第二时钟信号端连接，第一极与第一节点连接。所述第一电容的第一极与第六晶体管的控制极连接，第二极与第七晶体管连接。
在一些示例性实施方式中，所述第二输入子电路与第五节点连接。所述第二输出控制子电路包括：第一电容、第六晶体管、第七晶体管和第十二晶体管。所述第六晶体管的控制极与第三节点连接，所述第六晶体管的第一极与第二信号端连接，所述第六晶体管的第二极与第七晶体管的第二极连接；所述第七晶体管的控制极与第二时钟信号端连接，第一极与第一节点连接。所述第十二晶体管的控制极与第一电压端连接，第一极与第五节点连接，第二极与第三节点连接。所述第一电容的第一极与第六晶体管的控制极连接，第二极与第七晶体管连接。
在一些示例性实施方式中，所述第三输出控制子电路包括：第八晶体管和第三电容。所述第八晶体管的控制极与第二节点连接，第一极与第二电压端连接，第二极与第一节点连接。所述第三电容的第一极与第一节点连接，第二极与第二电压端连接。所述第二输出子电路包括：第九晶体管；所述第九晶体管的控制极与第一节点连接，第一极与第二电压端连接，第二极与信号输出端连接。
在一些示例性实施方式中，所述第一信号端与第二电压端或第一时钟信号端连接。
在一些示例性实施方式中，所述第二信号端与第一电压端或第二时钟信号端连接。
另一方面，本公开实施例提供一种显示基板的驱动方法，应用于如上所述的显示基板，所述驱动方法包括：输入电路在第一时钟信号端的控制下，将信号输入端的信号传输至输出控制电路，并将第一时钟信号端或第一电压端的信号传输至输出控制电路；所述输出控制电路在输入电路的控制下，存储第一信号端的信号，在输入电路和第二时钟信号端的控制下，向第一节点传输第二信号端的信号，所述输出电路在第一节点的控制下，向信号输出端输出第二电压端的信号；所述输出控制电路在输入电路的控制下，存储第二 时钟信号端的信号，并在第二节点的控制下，向第一节点传输第二电压端的信号；所述输出电路在第二节点的控制下，向信号输出端输出第一电压端的信号。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中一个或多个部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开至少一实施例的扫描驱动控制电路的结构示意图；
图2为本公开至少一实施例的扫描驱动控制电路的结构示意图；
图3为本公开至少一实施例的扫描驱动控制电路的第一输入子电路、第二输入子电路、第一输出控制子电路和第一输出子电路的一种等效电路图；
图4为本公开至少一实施例的扫描驱动控制电路的第一输入子电路、第二输入子电路、第一输出控制子电路和第一输出子电路的另一种等效电路图；
图5为本公开至少一实施例的扫描驱动控制电路的第二输出控制子电路的一种等效电路图；
图6为本公开至少一实施例的扫描驱动控制电路的第二输出控制子电路的另一等效电路图；
图7为本公开至少一实施例的扫描驱动控制电路的第三输出控制子电路和第二输出子电路的等效电路图；
图8为本公开至少一实施例的扫描驱动控制电路的一种等效电路图；
图9为图8所示的扫描驱动控制电路的一种工作时序图；
图10为图8所示的扫描驱动控制电路的另一种工作时序图；
图11为本公开至少一实施例的扫描驱动控制电路的另一种等效电路图；
图12为本公开至少一实施例的扫描驱动控制电路的另一种等效电路图；
图13为本公开至少一实施例的显示基板的驱动方法的流程图；
图14为本公开至少一实施例的扫描驱动控制电路的级联示意图；
图15为本公开至少一实施例的扫描驱动控制电路的一种俯视示意图；
图16为图15中沿P-P’方向的局部剖面示意图；
图17为本公开至少一实施例的形成第一半导层后的扫描驱动控制电路的俯视图；
图18为本公开至少一实施例的形成第一导电层后的扫描驱动控制电路的俯视图；
图19为本公开至少一实施例的形成第二导电层后的扫描驱动控制电路的俯视图；
图20为本公开至少一实施例的形成第三绝缘层后的扫描驱动控制电路的俯视图；
图21为本公开至少一实施例的形成第三导电层后的扫描驱动控制电路的俯视图；
图22为本公开至少一实施例的两个级联的扫描驱动控制电路的俯视图；
图23为图22中的第一导电层的俯视图；
图24为本公开至少一实施例的扫描驱动控制电路的另一俯视图；
图25为本公开至少一实施例的扫描驱动控制电路的另一俯视图；
图26为本公开至少一实施例的显示装置的结构示意图；
图27为本公开至少一实施例的显示装置的另一结构示意图。
具体实施方式
下文将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为一种或多种形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相 互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本公开中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。其中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有一种或多种功能的元件等。
在本公开中，晶体管是指至少包括栅电极(栅极)、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏极)与源电极(源电极端子、源区域或源极)之间具有沟道区，并且电流能够流过漏电极、沟道区以及源电极。在本公开中，沟道区是指电流主要流过的区域。
在本公开中，为区分晶体管除栅电极之外的两极，将其中一个电极称为 第一极，另一电极称为第二极，第一极可以为源电极或者漏电极，第二极可以为漏电极或源电极，另外，将晶体管的栅电极称为控制极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。
在本公开中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，可以包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，可以包括85°以上且95°以下的角度的状态。
在本公开中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”、“大致”、“近似”，是指不严格限定界限，允许工艺和测量误差范围内的情况。
在一些示例性实施方式中，显示基板可以包括：显示区域和非显示区域。例如，非显示区域可以位于显示区域的外围。然而，本实施例对此并不限定。显示区域至少包括：规则排布的多个像素电路、沿第一方向延伸的多条栅线(例如包括：扫描线、复位线、发光控制线)、沿第二方向延伸的多条数据线和电源线。其中，第一方向和第二方向位于同一平面内，且第一方向与第二方向交叉，例如，第一方向垂直于第二方向。
在一些示例性实施方式中，非显示区域设置有多个扫描驱动控制电路，扫描驱动控制电路可以配置为向显示区域的像素电路提供栅极驱动信号。
图1为本公开至少一实施例的扫描驱动控制电路的结构示意图。如图1所示，本实施例提供的扫描驱动控制电路包括：输入电路、输出控制电路和输出电路。
输入电路，与信号输入端IN、第一时钟信号端CK、第一电压端V1和输出控制电路连接，配置为在第一时钟信号端CK的控制下，将信号输入端IN的信号传输至输出控制电路，以及将第一时钟信号端CK或第一电压端V1的信号传输至输出控制电路。
输出控制电路，与第一信号端SIG1、第二信号端SIG2、第二时钟信号端CB、第二电压端V2、第一节点N1、第二节点N2和输入电路连接，配置为在输入电路的控制下，存储第一信号端SIG1的信号，在输入电路和第二时钟信号端CB的控制下，向第一节点N1传输第二信号端SIG2的信号；或者，在输入电路的控制下，存储第二时钟信号端CB的信号，并在第二节点N2的控制下，向第一节点N1传输第二电压端V2的信号。
输出电路，与第一电压端V1、第二电压端V2、信号输出端OUT、第一节点N1和第二节点N2连接，配置为在第二节点N2的控制下，向信号输出端OUT输出第一电压端V1的信号，或者，在第一节点N1的控制下，向信号输出端OUT输出第二电压端V2的信号。
在一些示例性实施方式中，信号输入端IN、第一时钟信号端CK和第二时钟信号端CB的输入信号可以为脉冲信号。第一电压端V1可以持续提供低电平信号，第二电压端V2可以持续提供高电平信号。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一信号端SIG1可以与第二电压端V2或第一时钟信号端CK连接。第二信号端SIG2可以与第一电压端V1或第二时钟信号端CB连接。然而，本实施例对此并不限定。
在一些示例性实施方式中，本实施例提供的扫描驱动控制电路的输出信号可以作为栅极驱动信号(例如，扫描信号或复位信号，或者发光控制信号)提供给显示区域的像素电路。在一些示例中，本实施例的扫描驱动控制电路可以适用于低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide)显示基板，可以给显示区域的像素电路中的N型晶体管提供栅极驱动信号。然而，本实施例对此并不限定。
本实施例提供的扫描驱动控制电路，通过输出控制电路可以提高第一节点N1和第二节点N2的稳定性，进而提高输出电路的输出稳定性。
图2为本公开至少一实施例的扫描驱动控制电路的示例性结构示意图。在一些示例性实施方式中，如图2所示，输入电路包括：第一输入子电路和第二输入子电路；输出控制电路包括：第一输出控制子电路、第二输出控制子电路和第三输出控制子电路；输出电路包括：第一输出子电路和第二输出 子电路。第一输入子电路，与信号输入端IN、第一时钟信号端CK和第一输出控制子电路连接，配置为在第一时钟信号端CK的控制下，将信号输入端IN的信号传输至第一输出控制子电路。第二输入子电路，与第一电压端V1、第一时钟信号端CK、第一输入子电路和第二输出控制子电路连接，配置为在第一输入子电路或第一时钟信号端CK的控制下，将第一时钟信号端CK或第一电压端V1的信号传输至第二输出控制子电路。第一输出控制子电路，与第一信号端SIG1、第二时钟信号端CB、第二节点N2、第一输入子电路和第二输入子电路连接，配置为在第一输入子电路或第二输入子电路的控制下，存储第一信号端SIG1或第二时钟信号端CB的信号。第二输出控制子电路，与第二信号端SIG2、第二时钟信号端CB、第一节点N1和第二输入子电路连接，配置为在第二输入子电路和第二时钟信号端CB的控制下，向第一节点N1传输第二信号端SIG2的信号。第三输出控制子电路，与第二电压端V2、第一节点N1和第二节点N2连接，配置为在第二节点N2的控制下，向第一节点N1传输第二电压端V2的信号。
第一输出子电路，与第一电压端V1、信号输出端OUT和第二节点N2连接，配置为在第二节点N2的控制下，向信号输出端OUT输出第一电压端V1的信号。第二输出子电路，与第二电压端V2、信号输出端OUT和第一节点N1连接，配置为在第一节点N1的控制下，向信号输出端OUT输出第二电压端V2的信号。
在一些示例性实施方式中，第一输入子电路和第一输出控制子电路均与第二节点N2连接。第二输入子电路、第一输出控制子电路以及第二输出控制子电路均与第三节点连接。然而，本实施例对此并不限定。
图3为本公开至少一实施例的扫描驱动控制电路的输入电路、第一输出控制子电路和第一输出子电路的一种等效电路图。如图3所示，本示例性实施例提供的扫描驱动控制电路的第一输入子电路包括：第一晶体管T1。第一晶体管T1的控制极与第一时钟信号端CK连接，第一极与信号输入端IN连接，第二极与第二节点N2连接。
如图3所示，第二输入子电路包括：第二晶体管T2和第三晶体管T3。第二晶体管T2的控制极与第二节点N2连接，第一极与第一时钟信号端CK 连接，第二极与第三节点N3连接。第三晶体管T3的控制极与第一时钟信号端CK连接，第一极与第一电压端V1连接，第二极与第三节点N3连接。
如图3所示，第一输出子电路包括：第十晶体管T10。第十晶体管T10的控制极与第二节点N2连接，第一极与第一电压端V1连接，第二极与信号输出端OUT连接。
如图3所示，第一输出控制子电路包括：第四晶体管T4、第五晶体管T5、第二电容C2和第四电容C4。第四晶体管T4的控制极与第二节点N2连接，第四晶体管T4的第一极与第二时钟信号端CB连接，第四晶体管T4的第二极与第五晶体管T5的第二极连接。第五晶体管T5的控制极与第三节点N3连接，第五晶体管T5的第一极与第一信号端SIG1连接。第二电容C2的第一极与第二节点N2连接，第二电容C2的第二极与信号输出端OUT连接。第四电容C4的第一极与第四晶体管T4的控制极和第十晶体管T10的控制极连接(即与第二节点N2连接)，第四电容C4的第二极与第五晶体管T5的第二极和第四晶体管T4的第二极连接。
本示例性实施方式中，通过串联设置的第二电容C2和第四电容C4，可以使得第二节点N2的电位在第十晶体管T10导通时保持稳定，以使第一输出子电路提供稳定输出。
在本示例性实施例中，图3示出了输入电路、第一输出控制子电路和第一输出子电路的一种示例性结构。本领域技术人员容易理解的是，输入电路、第一输出控制子电路和第一输出子电路的实现方式不限于此，只要能够实现其功能即可。
图4为本公开至少一实施例的扫描驱动控制电路的输入电路、第一输出控制子电路和第一输出子电路的另一种等效电路图。如图4所示，本示例性实施例提供的扫描驱动控制电路的第一输入子电路包括：第一晶体管T1。第一晶体管T1的控制极与第一时钟信号端CK连接，第一极与信号输入端IN连接，第二极与第四节点N4连接。
如图4所示，第二输入子电路包括：第二晶体管T2和第三晶体管T3。第二晶体管T2的控制极与第四节点N4连接，第一极与第一时钟信号端CK连接，第二极与第三节点N3连接。第三晶体管T3的控制极与第一时钟信号 端CK连接，第一极与第一电压端V1连接，第二极与第三节点N3连接。
如图4所示，第一输出子电路包括：第十晶体管T10。第十晶体管T10的控制极与第二节点N2连接，第一极与第一电压端V1连接，第二极与信号输出端OUT连接。
如图4所示，第一输出控制子电路包括：第四晶体管T4、第五晶体管T5、第十一晶体管T11、第二电容C2和第四电容C4。第四晶体管T4的控制极与第二节点N2连接，第四晶体管T4的第一极与第二时钟信号端CB连接，第四晶体管T4的第二极与第五晶体管T5的第二极连接。第五晶体管T5的控制极与第三节点N3连接，第一极与第一信号端SIG1连接。第十一晶体管T11的控制极与第一电压端V1连接，第一极与第四节点N4连接，第二极与第二节点N2连接。第二电容C2的第一极与第二节点N2连接，第二电容C2的第二极与信号输出端OUT连接。第四电容C4的第一极与第四晶体管T4的控制极和第十晶体管T10的控制极连接(即与第二节点N2连接)，第四电容C4的第二极与第四晶体管T4的第二极和第五晶体管T5的第二极连接。
在本示例性实施方式中，通过串联设置的第二电容C2和第四电容C4，可以使得第二节点N2的电位在第十晶体管T10导通时保持稳定，以使第一输出子电路提供稳定输出。通过设置第十一晶体管T11，可以隔离第二节点N2对第四节点N4的影响。
在本示例性实施例中，图4示出了输入电路、第一输出控制子电路和第一输出子电路的一种示例性结构。本领域技术人员容易理解的是，输入电路、第一输出控制子电路和第一输出子电路的实现方式不限于此，只要能够实现其功能即可。
图5为本公开至少一实施例的扫描驱动控制电路的第二输出控制子电路的一种等效电路图。如图5所示，本示例性实施例提供的扫描驱动控制电路的第二输出控制子电路包括：第六晶体管T6、第七晶体管T7和第一电容C1。第六晶体管T6的控制极与第三节点N3连接，第六晶体管T6的第一极与第二信号端SIG2连接，第六晶体管T6的第二极与第七晶体管T7的第二极连接。第七晶体管T7的控制极与第二时钟信号端CB连接，第一极与第一节点 N1连接。第一电容C1的第一极与第六晶体管T6的控制极连接，第二极与第七晶体管T7的控制极连接。
在一些示例性实施方式中，第二信号端SIG2可以提供低电平信号，使得第一节点N1的电位在第二输出子电路的晶体管导通时保持稳定，以使第二输出子电路提供稳定输出。
在本示例性实施例中，图5中示出了第二输出控制子电路的一种示例性结构。本领域技术人员容易理解的是，第二输出控制子电路的实现方式不限于此，只要能够实现其功能即可。
图6为本公开至少一实施例的扫描驱动控制电路的第二输出控制子电路的另一种等效电路图。如图6所示，本示例性实施例提供的扫描驱动控制电路的第二输出控制子电路包括：第六晶体管T6、第七晶体管T7、第十二晶体管T12和第一电容C1。第六晶体管T6的控制极与第三节点N3连接，第六晶体管T6的第一极与第二信号端SIG2连接，第六晶体管T6的第二极与第七晶体管T7的第二极连接。第七晶体管T7的控制极与第二时钟信号端CB连接，第一极与第一节点N1连接。第一电容C1的第一极与第六晶体管T6的控制极连接，第二极与第七晶体管T7的控制极连接。第十二晶体管T12的控制极与第一电源端V1连接，第一极与第五节点N5连接，第二极与第三节点N3连接。第五节点N5还与第一输入子电路和第一输出控制子电路连接。
在一些示例性实施方式中，第二信号端SIG2可以提供低电平信号，使得第一节点N1的电位在第二输出子电路的晶体管导通时保持稳定，以使第二输出子电路提供稳定输出。在本示例性实施方式中，通过设置第十二晶体管T12，可以隔离第三节点N3对第五节点N5的影响。
在本示例性实施例中，图6中示出了第二输出控制子电路的另一种示例性结构。本领域技术人员容易理解的是，第二输出控制子电路的实现方式不限于此，只要能够实现其功能即可。
图7为本公开至少一实施例的扫描驱动控制电路的第三输出控制子电路和第二输出子电路的等效电路图。如图7所示，本示例性实施例提供的扫描驱动控制电路的第三输出控制子电路包括：第八晶体管T8和第三电容C3。第八晶体管T8的控制极与第二节点N2连接，第一极与第二电压端V2连接， 第二极与第一节点N1连接。第三电容C3的第一极与第一节点N1连接，第二极与第二电压端V2连接。
如图7所示，第二输出子电路包括：第九晶体管T9。第九晶体管T9的控制极与第一节点N1连接，第一极与第二电压端V2连接，第二极与信号输出端OUT连接。
在本示例性实施例中，图7中示出了第三输出控制子电路和第二输出子电路的一种示例性结构。本领域技术人员容易理解的是，第三输出控制子电路和第二输出子电路的实现方式不限于此，只要能够实现其功能即可。
图8为本公开至少一实施例的扫描驱动控制电路的一种等效电路图。如图8所示，本示例性实施例提供的扫描驱动控制电路包括：第一输入子电路、第二输入子电路、第一输出控制子电路、第二输出控制子电路、第三输出控制子电路、第一输出子电路和第二输出子电路。第一输入子电路包括第一晶体管T1。第二输入子电路包括第二晶体管T2和第三晶体管T3。第一输出控制子电路包括：第四晶体管T4、第五晶体管T5、第二电容C2和第四电容C4。第二输出控制子电路包括：第六晶体管T6、第七晶体管T7和第一电容C1。第三输出控制子电路包括：第八晶体管T8和第三电容C3。第一输出子电路包括第十晶体管T10。第二输出子电路包括第九晶体管T9。在本示例性实施方式中，第一信号端SIG1与第二电压端V2连接，第二信号端SIG2与第一电压端V1连接。
在本示例性实施方式中，第一晶体管T1的控制极与第一时钟信号端CK连接，第一极与信号输入端IN连接，第二极与第二节点N2连接。第二晶体管T2的控制极与第二节点N2连接，第一极与第一时钟信号端CK连接，第二极与第三节点N3连接。第三晶体管T3的控制极与第一时钟信号端CK连接，第一极与第一电压端V1连接，第二极与第三节点N3连接。第四晶体管T4的控制极与第二节点N2连接，第四晶体管T4的第一极与第二时钟信号端CB连接，第四晶体管T4的第二极与第五晶体管T5的第二极连接。第五晶体管T5的控制极与第三节点N3连接，第一极与第二电压端V2连接。第六晶体管T6的控制极与第三节点N3连接，第六晶体管T6的第一极与第一电压端V1连接，第六晶体管T6的第二极与第七晶体管T7的第一极连接。 第七晶体管T7的控制极与第二时钟信号端CB连接，第二极与第一节点N1连接。第八晶体管T8的控制极与第二节点N2连接，第一极与第二电压端V2连接，第二极与第一节点N1连接。第九晶体管T9的控制极与第一节点N1连接，第一极与第二电压端V2连接，第二极与信号输出端OUT连接。第十晶体管T10的控制极与第二节点N2连接，第一极与第一电压端V1连接，第二极与信号输出端OUT连接。第一电容C1的第一极与第三节点N3连接，第二极与第七晶体管T7的控制极连接。第二电容C2的第一极与第二节点N2连接，第二电极与信号输出端OUT连接。第三电容C3的第一极与第一节点N1连接，第二极与第二电压端V2连接。第四电容C4的第一极与第二节点N2连接，第二极与第五晶体管T5的第二极连接。
在本示例性实施方式中，第一节点N1、第二节点N2和第三节点N3，是表示电路图中相关电连接的汇合点。换言之，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
在一些示例性实施方式中，扫描驱动控制电路中的第一晶体管T1至第十晶体管T10可以均为P型薄膜晶体管，例如可以为低温多晶体硅(LTPS，Low Temperature Poly-silicon)薄膜晶体管。另外，本公开实施例可以选择底栅结构的薄膜晶体管或者顶栅结构的薄膜晶体管，只要能够实现开关功能即可。本实施例对此并不限定。
下面通过扫描驱动控制电路的工作过程进一步说明本实施例的技术方案。下面以第一级扫描驱动控制电路的工作过程为例进行说明，第一级扫描驱动控制电路的信号输入端IN与初始信号线STV连接。图9为图8所示的扫描驱动控制电路的一种工作时序图。如图8和图9所示，本示例性实施例的扫描驱动控制电路包括10个晶体管单元(例如第一晶体管T1至第十晶体管T10)、4个电容单元(即第一电容C1至第四电容C4)、3个输入端(即信号输入端IN、第一时钟信号端CK、第二时钟信号端CB)、1个输出端(即信号输出端OUT)以及2个电源端(即第一电压端V1和第二电压端V2)。在一些示例中，第一电压端V1持续提供低电平信号，例如电压为VGL；第二电压端V2持续提供高电平信号，例如电压为VGH。
下面以本实施例的扫描驱动控制电路给像素电路的N型晶体管提供扫描 信号或复位信号为例，说明扫描驱动控制电路的工作过程。本示例性实施例提供的扫描驱动控制电路的工作过程包括以下多个阶段。
在第一阶段t11，第一时钟信号端CK输入高电平信号，第二时钟信号端CB输入低电平信号，信号输入端IN输入低电平信号。
第一时钟信号端CK输入高电平信号，第一晶体管T1和第三晶体管T3截止，第二节点N2保持上一阶段的低电位，第二晶体管T2、第四晶体管T4、第八晶体管T8和第十晶体管T10导通。第一时钟信号端CK输入的高电平信号经过导通的第二晶体管T2传输到第三节点N3，使得第五晶体管T5和第六晶体管T6截止。第二时钟信号端CB输入的低电平信号经过导通的第四晶体管T4传输到第四电容C4的第二极，由于电容保持作用，使得第四电容C4的第一极(即第二节点N2)保持更低的电位。第八晶体管T8导通，使得第一节点N1的电位为高电位(例如，VGH)，第九晶体管T9截止。第十晶体管T10导通，使得信号输出端OUT输出第一电压端V1提供的低电平信号。
在第二阶段t12，第一时钟信号端CK输入低电平信号，第二时钟信号端CB输入高电平信号，信号输入端IN输入高电平信号。
第一时钟信号端CK输入低电平信号，第一晶体管T1和第三晶体管T3导通，导通的第一晶体管T1将信号输入端IN提供的高电平信号传输至第二节点N2，使得第二节点N2的电位被拉升为VGH。第二晶体管T2、第四晶体管T4、第八晶体管T8和第十晶体管T10截止。导通的第三晶体管T3将第一电压端V1输入的低电平信号传输至第三节点N3，第五晶体管T5和第六晶体管T6导通。第二电压端V2提供的高电平信号经过导通的第五晶体管T5传输至第四电容C4的第二极，在第四电容C4的跳变作用下，第四电容的第一极(即第二节点N2)保持稳定的高电位。第二时钟信号端CB输入高电平信号，第七晶体管T7截止，第一节点N1在第三电容C3的存储作用下保持在第二电压端V2提供的高电位，第九晶体管T9截止。由于第九晶体管T9和第十晶体管T10均截止，信号输出端OUT保持之前的低电平输出。
在第三阶段t13，第一时钟信号端CK输入高电平信号，第二时钟信号端CB输入低电平信号，信号输入端IN输入低电平信号。
第一时钟信号端CK输入高电平信号，第一晶体管T1和第三晶体管T3 截止，第二节点N2保持上一阶段的高电位。第二晶体管T2、第四晶体管T4、第八晶体管T8和第十晶体管T10截止。第二时钟信号端CB输入低电平信号，第一电容C1的第一极(即第三节点N3)的电位由上一阶段的低电位VGL跳变为更低的电位2VGL-VGH。第五晶体管T5和第六晶体管T6导通。第二电压端V2提供的高电平信号经过导通的第五晶体管T5传输到第四电容C4的第二极，使得第二节点N2保持稳定的高电位。第二时钟信号端CB输入低电平信号，第七晶体管T7导通，第一电压端V1输入的低电平信号经过导通的第六晶体管T6和第七晶体管T7传输到第一节点N1，第九晶体管T9导通，向信号输出端OUT输出第二电压端V2提供的高电平信号。
在第四阶段t14，第一时钟信号端CK输入低电平信号，第二时钟信号端CB输入高电平信号，信号输入端IN输入低电平信号。
第一时钟信号端CK输入低电平信号，第一晶体管T1和第三晶体管T3导通，导通的第一晶体管T1将信号输入端IN输入的低电平信号传输至第二节点N2，使得第二节点N2的电位被拉低至VGL。第二晶体管T2、第四晶体管T4、第八晶体管T8和第十晶体管T10导通。导通的第八晶体管T8将第二电压端V2提供的高电平信号传输至第一节点N1，第九晶体管T9截止。导通的第十晶体管T10将第一电压端V1提供的低电平信号传输至信号输出端OUT。导通的第二晶体管T2将第一时钟信号端CK提供的低电平信号传输至第三节点N3，第五晶体管T5和第六晶体管T6导通。第二时钟信号端CB输入高电平信号，第七晶体管T7截止。
在第五阶段t15，第一时钟信号端CK输入高电平信号，第二时钟信号端CB输入低电平信号，信号输入端IN输入低电平信号。
第一时钟信号端CK输入高电平信号，第一晶体管T1和第三晶体管T3截止。第二节点N2保持上一节点的低电位，第二晶体管T2、第四晶体管T4、第八晶体管T8和第十晶体管T10导通。导通的第四晶体管T4将第二时钟信号端CB输入的低电平信号传输到第四电容C4的第二极，使得第四电容C4的第一极(即第二节点N2)的电位变为比VGL更低的电位。导通的第二晶体管T2将第一时钟信号端CK提供的高电平信号传输到第三节点N3，使得第五晶体管T5和第六晶体管T6截止。导通的第八晶体管T8将第二电压端 V2提供的高电平信号传输到第一节点N1，第一节点N1的电位为VGH，第九晶体管T9截止。第十晶体管T10导通，向信号输出端OUT提供第一电压端V1提供的低电平信号。
在第五阶段t15之后，可以重复第四阶段t14和第五阶段t15，直至信号输入端IN输入高电平信号，再从第二阶段t12重新开始。
根据上述扫描驱动控制电路的工作过程可知，在第三阶段t13，信号输出端OUT输出高电平信号，在其余阶段，信号输出端OUT输出低电平信号。
在一些示例性实施方式中，第一时钟信号端CK输入的第一时钟信号和第二时钟信号端CB输入的第二时钟信号均为脉冲信号，且第一时钟信号的脉宽和第二时钟信号的脉宽可以大致相同。第一时钟信号和第二时钟信号的占空比可以大于1/2，例如可以约为1/3。在本实施例中，占空比是指一个脉冲周期(包括高电平时长和低电平时长)内高电平时长在整个脉冲周期所占的比例。
图10为图8所示的扫描驱动控制电路的另一种工作时序图。下面参照图8和图10，以本实施例的扫描驱动控制电路给像素电路提供发光控制信号为例，说明扫描驱动控制电路的工作过程。本示例性实施例提供的扫描驱动控制电路的工作过程可以包括以下多个阶段。
在第一阶段t21，第一时钟信号端CK输入高电平信号，第二时钟信号端CB输入低电平信号，信号输入端IN输入低电平信号。
第一时钟信号端CK输入高电平信号，第一晶体管T1和第三晶体管T3截止，第二节点N2保持上一阶段的低电位，第二晶体管T2、第四晶体管T4、第八晶体管T8和第十晶体管T10导通。第一时钟信号端CK输入的高电平信号经过导通的第二晶体管T2传输到第三节点N3，使得第五晶体管T5和第六晶体管T6截止。第二时钟信号端CB输入的低电平信号经过导通的第四晶体管T4传输到第四电容C4的第二极，由于电容保持作用，使得第四电容C4的第一极(即第二节点N2)保持更低的电位。第八晶体管T8导通，使得第一节点N1的电位被拉升至VGH，第九晶体管T9截止。第十晶体管T10导通，使得信号输出端OUT输出第一电压端V1提供的低电平信号。
在第二阶段t22，第一时钟信号端CK输入低电平信号，第二时钟信号端 CB输入高电平信号，信号输入端IN输入高电平信号。
第一时钟信号端CK输入低电平信号，第一晶体管T1和第三晶体管T3导通。导通的第一晶体管T1将信号输入端IN提供的高电平信号传输至第二节点N2，使得第二节点N2的电位被拉升至VGH。第二晶体管T2、第四晶体管T4、第八晶体管T8和第十晶体管T10截止。导通的第三晶体管T3将第一电压端V1输入的低电平信号传输至第三节点N3，第五晶体管T5和第六晶体管T6导通。第二电压端V2提供的高电平信号经过导通的第五晶体管T5传输至第四电容C4的第二极，在第四电容C4的跳变作用下，第四电容的第一极(即第二节点N2)保持稳定的高电平。第二时钟信号端CB输入高电平信号，第七晶体管T7截止，第一节点N1在第三电容C3的存储作用下保持第二电压端V2提供的高电位VGH，第九晶体管T9截止。由于第九晶体管T9和第十晶体管T10均截止，信号输出端OUT保持之前的低电平输出。
在第三阶段t23，第一时钟信号端CK输入高电平信号，第二时钟信号端CB输入低电平信号，信号输入端IN输入高电平信号。
第一时钟信号端CK输入高电平信号，第一晶体管T1和第三晶体管T3截止，第二节点N2保持上一阶段的高电位。第二晶体管T2、第四晶体管T4、第八晶体管T8和第十晶体管T10截止。第二时钟信号端CB输入低电平信号，第一电容C1的第一极(即第三节点N3)的电位由上一阶段的低电位VGL跳变为更低的电位2VGL-VGH。第五晶体管T5和第六晶体管T6导通。第二电压端V2提供的高电平信号经过导通的第五晶体管T5传输到第四电容C4的第二极，使得第二节点N2保持稳定的高电位。第二时钟信号端CB输入低电平信号，第七晶体管T7导通，第一电压端V1输入的低电平信号经过导通的第六晶体管T6和第七晶体管T7传输到第一节点N1，第九晶体管T9导通，向信号输出端OUT提供第二电压端V2提供的高电平信号。
在第四阶段t24，第一时钟信号端CK输入低电平信号，第二时钟信号端CB输入高电平信号，信号输入端IN输入高电平信号。
第一时钟信号端CK输入低电平信号，第一晶体管T1和第三晶体管T3导通。导通的第一晶体管T1将信号输入端IN输入的高电平信号传输至第二节点N2，第二节点N2的电位保持上一阶段的高电位VGH。第二晶体管T2、 第四晶体管T4、第八晶体管T8和第十晶体管T10截止。导通的第三晶体管T3将第一电压端V1提供的低电平信号传输至第三节点N3，第五晶体管T5和第六晶体管T6导通。导通的第五晶体管T5将第二电压端V2提供的高电平信号传输至第四电容C4的第二极，在第四电容C4的跳变作用下，第四电容C4的第一极(即第二节点N2)保持稳定的高电位。第二时钟信号端CB输入高电平信号，第七晶体管T7截止，第一节点N1在第三电容C3的存储作用下保持为上一阶段的低电位，第九晶体管T9导通，信号输出端OUT输出第二电压端V2提供的高电平信号。
在第五阶段t25，第一时钟信号端CK输入高电平信号，第二时钟信号端CB输入低电平信号，信号输入端IN输入低电平信号。
第一时钟信号端CK输入高电平信号，第一晶体管T1和第三晶体管T3截止，第二节点N2保持上一阶段的高电位。第二晶体管T2、第四晶体管T4、第八晶体管T8和第十晶体管T10截止。第二时钟信号端CB输入低电平信号，第一电容C1的第二极的电位由上一阶段的VGH跳变为VGL，由于第一电容C1的跳变作用，第一电容C1的第一极(即第三节点N3)的电位由上一阶段的VGL跳变为更低的2VGL-VGH，第五晶体管T5和第六晶体管T6导通。导通的第五晶体管T5将第二电压端V2提供的高电平信号传输至第四电容C4的第二极，使得第二节点N2保持稳定的高电位。第二时钟信号端CB输入低电平信号，第七晶体管T7导通。导通的第六晶体管T6和第七晶体管T7将第一电压端V1提供的低电平信号传输至第一节点N1，第九晶体管T9导通，信号输出端OUT输出第二电压端V2提供的高电平信号。
在第六阶段t26，第一时钟信号端CK输入低电平信号，第二时钟信号端CB输入高电平信号，信号输入端IN输入低电平信号。
第一时钟信号端CK输入低电平信号，第一晶体管T1和第三晶体管T3导通。导通的第一晶体管T1将信号输入端IN输入的低电平信号传输至第二节点N2，第二节点N2的电位被拉低至VGL。第二晶体管T2、第四晶体管T4、第八晶体管T8和第十晶体管T10导通。导通的第八晶体管T8将第二电压端V2提供的高电平信号传输至第一节点N1，第九晶体管T9截止。导通的第十晶体管T10将第一电压端V1提供的低电平信号传输至信号输出端 OUT。导通的第二晶体管T2将第一时钟信号端CK提供的低电平信号传输至第三节点N3，第五晶体管T5和第六晶体管T6导通。第二时钟信号端CB输入高电平信号，第七晶体管T7截止。
在第七阶段t27，第一时钟信号端CK输入高电平信号，第二时钟信号端CB输入低电平信号，信号输入端IN输入低电平信号。
第一时钟信号端CK输入高电平信号，第一晶体管T1和第三晶体管T3截止。第二节点N2保持上一节点的低电位，第二晶体管T2、第四晶体管T4、第八晶体管T8和第十晶体管T10导通。导通的第四晶体管T4将第二时钟信号端CB输入的低电平信号传输到第四电容C4的第二极，使得第四电容C4的第一极(即第二节点N2)的电位变为比VGL更低的电位。导通的第二晶体管T2将第一时钟信号端CK提供的高电平信号传输到第三节点N3，使得第五晶体管T5和第六晶体管T6截止。导通的第八晶体管T8将第二电压端V2提供的高电平信号传输到第一节点N1，第一节点N1的电位为VGH，第九晶体管T9截止。第十晶体管T10导通，向信号输出端OUT输出第一电压端V1提供的低电平信号。
在第七阶段t27之后，可以重复第六阶段t26和第七阶段t27，直至信号输入端OUT输入高电平信号，再从第二阶段t22重新开始。
根据上述扫描驱动控制电路的工作过程可知，在第三阶段t23至第五阶段t25，信号输出端OUT可以输出高电平信号，其余阶段，信号输出端OUT输出低电平信号。
本示例性实施例提供的扫描驱动控制电路，通过第一输出控制子电路可以在第十晶体管T10导通时保持第二节点N2的电位稳定，以提高第十晶体管T10的输出稳定性，通过第二输出控制子电路可以在第九晶体管T9导通时保持第一节点N1的电位稳定，以提高第九晶体管T9的输出稳定性。
图11为本公开至少一实施例的扫描驱动控制电路的另一种等效电路图。如图11所示，本示例性实施例提供的扫描驱动控制电路包括：第一输入子电路、第二输入子电路、第一输出控制子电路、第二输出控制子电路、第三输出控制子电路、第一输出子电路和第二输出子电路。第一输入子电路包括第一晶体管T1。第二输入子电路包括第二晶体管T2和第三晶体管T3。第一输 出控制子电路包括：第四晶体管T4、第五晶体管T5、第十一晶体管T11、第二电容C2和第四电容C4。第二输出控制子电路包括：第十二晶体管T12、第六晶体管T6、第七晶体管T7和第一电容C1。第三输出控制子电路包括：第八晶体管T8和第三电容C3。第一输出子电路包括：第十晶体管T10。第二输出子电路包括第九晶体管T9。在本示例性实施方式中，第一信号端与第二电压端V2连接，第二信号端与第一电压端V1连接。
在本示例性实施方式中，第一晶体管T1的控制极与第一时钟信号端CK连接，第一极与信号输入端IN连接，第二极与第四节点N4连接。第二晶体管T2的控制极与第四节点N4连接，第一极与第一时钟信号端CK连接，第二极与第三节点N3连接。第三晶体管T3的控制极与第一时钟信号端CK连接，第一极与第一电压端V1连接，第二极与第五节点N5连接。第四晶体管T4的控制极与第二节点N2连接，第四晶体管T4的第一极与第二时钟信号端CB连接，第四晶体管T4的第二极与第五晶体管T5的第二极连接。第五晶体管T5的控制极与第五节点N5连接，第一极与第二电压端V2连接。第六晶体管T6的控制极与第三节点N3连接，第六晶体管T6的第一极与第一电压端V1连接，第六晶体管T6的第二极与第七晶体管T7的第一极连接。第七晶体管T7的控制极与第二时钟信号端CB连接，第二极与第一节点N1连接。第八晶体管T8的控制极与第二节点N2连接，第一极与第二电压端V2连接，第二极与第一节点N1连接。第九晶体管T9的控制极与第一节点N1连接，第一极与第二电压端V2连接，第二极与信号输出端OUT连接。第十晶体管T10的控制极与第二节点N2连接，第一极与第一电压端V1连接，第二极与信号输出端OUT连接。第十一晶体管T11的控制极与第一电压端V1连接，第一极与第四节点N4连接，第二极与第二节点N2连接。第十二晶体管T12的控制极与第一电压端V1连接，第一极与第五节点N5连接，第二极与第三节点N3连接。第一电容C1的第一极与第三节点N3连接，第二极与第七晶体管T7的控制极连接。第二电容C2的第一极与第二节点N2连接，第二电极与信号输出端OUT连接。第三电容C3的第一极与第一节点N1连接，第二极与第二电压端V2连接。第四电容C4的第一极与第二节点N2连接，第二极与第五晶体管T5的第二极连接。
在本示例性实施方式中，第一节点N1、第二节点N2、第三节点N3、第四节点N4和第五节点N5表示电路图中相关电连接的汇合点。换言之，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
在一些示例性实施方式中，扫描驱动控制电路中的第一晶体管T1至第十二晶体管T12可以均为P型薄膜晶体管，例如可以为低温多晶体硅(LTPS，Low Temperature Poly-silicon)薄膜晶体管。另外，本公开实施例可以选择底栅结构的薄膜晶体管或者顶栅结构的薄膜晶体管，只要能够实现开关功能即可。本实施例对此并不限定。
本示例性实施例提供的扫描驱动控制电路中，通过第十一晶体管T11可以隔离第二节点N2对第四节点N4的影响，通过第十二晶体管T12可以隔离第三节点N3对第五节点N5的影响。
关于本实施例的扫描驱动控制电路的工作过程可以参照前述实施例的说明，故于此不再赘述。
图12为本公开至少一实施例的扫描驱动控制电路的另一种等效电路图。如图12所示，本示例性实施例提供的扫描驱动控制电路包括：第一输入子电路、第二输入子电路、第一输出控制子电路、第二输出控制子电路、第三输出控制子电路、第一输出子电路和第二输出子电路。第一输入子电路包括第一晶体管T1。第二输入子电路包括第二晶体管T2和第三晶体管T3。第一输出控制子电路包括：第四晶体管T4、第五晶体管T5、第十一晶体管T11、第二电容C2和第四电容C4。第二输出控制子电路包括：第十二晶体管T12、第六晶体管T6、第七晶体管T7和第一电容C1。第三输出控制子电路包括：第八晶体管T8和第三电容C3。第一输出子电路包括：第十晶体管T10。第二输出子电路包括第九晶体管T9。在本示例性实施方式中，第一信号端与第一时钟信号端CK连接，第二信号端与第二时钟信号端CB连接。即，第五晶体管T5的第二极与第一时钟信号端CK连接，第六晶体管T6的第一极与第二时钟信号端CB连接。
关于本实施例的扫描驱动控制电路的电路结构和工作过程可以参照前述实施例的说明，故于此不再赘述。
在另一些示例性实施方式中，扫描驱动控制电路的第一信号端SIG1可 以与第一时钟信号端CK连接，第二信号端SIG2可以为第一电压端V1或第二时钟信号端CB连接；或者，第一信号端SIG1可以与第二电压端V2连接，第二信号端SIG2可以与第一电压端V1或第二时钟信号端CB连接。然而，本实施例对此并不限定。
本公开实施例还提供一种显示基板的驱动方法。图13为本公开一实施例的显示基板的驱动方法的流程图。如图13所示，本实施例提供的显示基板的驱动方法，应用于上述实施例提供的显示基板中。本实施例提供的驱动方法可以包括以下多个步骤。
步骤S101、输入电路在第一时钟信号端的控制下，将信号输入端的信号传输至输出控制电路，并将第一时钟信号端或第一电压端的信号传输至输出控制电路；
步骤S102、输出控制电路在输入电路的控制下，存储第一信号端的信号，在输入电路和第二时钟信号端的控制下，向第一节点传输第二信号端的信号，输出电路在第一节点的控制下，向信号输出端输出第二电压端的信号；
步骤S103、输出控制电路在输入电路的控制下，存储第二时钟信号端的信号，并在第二节点的控制下，向第一节点传输第二电压端的信号，输出电路在第二节点的控制下，向信号输出端输出第一电压端的信号。
本示例性实施例提供的显示基板的驱动方法、扫描驱动控制电路的结构及其工作过程，已在上述实施例中说明，这里不再赘述。
本公开实施例还提供一种栅极驱动电路。图14为本公开至少一实施例的栅极驱动电路的示意图。如图14所示，本示例性实施例提供的栅极驱动电路包括多个级联的扫描驱动控制电路GOA。扫描驱动控制电路可以如前述实施例所述，其实现原理和实现效果类型，故于此不再赘述。
在本示例性实施方式中，第一级扫描驱动控制电路的信号输入端IN与初始信号线STV连接，第n+1级扫描驱动控制电路的信号输入端与第n级扫描驱动控制电路的信号输出端连接，其中，n为整数。
在一些示例性实施方式中，多个扫描驱动控制电路的第一时钟信号端CK与第一时钟信号线CKL连接，配置为接收第一时钟信号，第二时钟信号 端CB与第二时钟信号线CBL连接，配置为接收第二时钟信号。第一电压端V1与持续提供低电平信号VGL的电源线连接，第二电压端V2与持续提供高电平信号VGH的电源线连接。然而，本实施例对此并不限定。
图15为本公开至少一实施例的扫描驱动控制电路的一种俯视图。图16为图15中沿P-P’方向的局部剖面示意图。图15所示的扫描驱动控制电路的等效电路图可以如图8所示。在本示例性实施方式中，第一信号端与第二电压端连接，第二信号端与第一电压端连接，第一时钟信号端CK与第一时钟信号线CKL连接，第二时钟信号端CB与第二时钟信号线CBL连接。第二电压端与提供高电平信号的第一电源线PL1连接。第一输出子电路连接的第一电压端与提供低电平信号的第三电源线PL3连接。第二输入子电路和第二输出控制子电路连接的第一电压端与提供低电平信号的第二电源线PL2连接。
在本示例性实施方式中，以扫描驱动控制电路中的多个晶体管均为P型晶体管，且为低温多晶硅薄膜晶体管为例进行说明。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图15所示，在平行于显示基板的平面内，第一时钟信号线CKL、第二时钟信号线CBL、初始信号线STV、第二电源线PL2、第一电源线PL1和第三电源线PL3沿第一方向X依次排布。第一时钟信号线CKL、第二时钟信号线CBL、初始信号线STV、第二电源线PL2、第一电源线PL1和第三电源线PL3均沿第二方向Y延伸。其中，第一方向X与第二方向Y交叉，例如，第一方向X垂直于第二方向Y。
在一些示例性实施方式中，如图15所示，在平行于显示基板的平面内，信号输出端OUT在第二方向Y上位于第十晶体管T10远离第九晶体管T9的一侧。信号输出端OUT可以沿第一方向X延伸。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图15所示，在平行于显示基板的平面内，第二输入子电路(包括第二晶体管T2和第三晶体管T3)在第一方向X上位于初始信号线STV和第二电源线PL2之间。第一输出子电路(包括第十晶体管T10)和第二输出子电路(包括第九晶体管T9)在第一方向X上位于第 一电源线PL1和第三电源线PL3之间。第二晶体管T2和第三晶体管T3在第二方向Y上相邻。第九晶体管T9和第十晶体管T10在第二方向Y上相邻。第一晶体管T1、第四晶体管T4和第五晶体管T5位于第二电源线PL2远离第二时钟信号线CBL的一侧。第七晶体管T7与第一电容C1相邻，且第七晶体管T7位于第一电容C1和第一电源线PL1之间。第六晶体管T6与第一电源线PL1相邻，且第六晶体管T6位于第七晶体管T7和第一电源线PL1之间。第八晶体管T8位于第一电源线PL1和第一晶体管T1之间。第一电容C1位于第一电源线PL1和第二电源线PL2之间，第一电容C1在衬底基板上的正投影位于第一电源线PL1和第二电源线PL2在衬底基板上的投影之间，且第一电容C1在衬底基板上的投影与第一电源线PL1和第二电源线PL2在衬底基板上的投影没有交叠。在本实施例中，“A和B相邻”表示A和B之间没有其他的晶体管或电容。
在一些示例性实施方式中，如图16所示，在垂直于显示基板的平面内，显示基板的非显示区域可以包括：衬底基板30、依次设置在衬底基板30上的第一半导体层、第一导电层、第二导电层以及第三导电层。其中，第一绝缘层31设置在第一导电层和第一半导体层之间。第二绝缘层32设置在第一导电层和第二导电层之间。第三绝缘层33设置在第二导电层和第三导电层之间。在一些示例中，第一绝缘层31至第三绝缘层33可以均为无机绝缘层。然而，本实施例对此并不限定。
图17为本公开至少一实施例的形成第一半导体层后的扫描驱动控制电路的俯视图。如图15至图17所示，非显示区域的第一半导体层至少包括：扫描驱动控制电路的多个晶体管的有源层。例如，第一半导体层至少包括：第一晶体管T1的有源层110、第二晶体管T2的有源层120、第三晶体管T3的有源层130、第四晶体管T4的有源层140、第五晶体管T5的有源层150、第六晶体管T6的有源层160、第七晶体管T7的有源层170、第八晶体管T8的有源层180、第九晶体管T9的有源层第十晶体管T10的有源层。
在一些示例性实施方式中，如图17所示，第三晶体管T3的有源层130、第一晶体管T1的有源层110、第五晶体管T5的有源层150、第六晶体管T6的有源层160、第七晶体管T7的有源层170、第八晶体管T8的有源层180、 第九晶体管T9的有源层以及第十晶体管T10的有源层可以沿第二方向Y延伸。第四晶体管T4的有源层140可以沿第一方向X延伸。在一些示例中，第四晶体管T4的有源层140的延伸方向与第一晶体管T1的有源层110的延伸方向的夹角大于85°且小于95°。第四晶体管T4的有源层140的延伸方向和第五晶体管T5的有源层150的延伸方向的夹角大于85°且小于95°。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图17所示，第三晶体管T3的有源层130和第二晶体管T2的有源层120在第二方向Y上相邻。第一晶体管T1的有源层110在第一方向X上位于第三晶体管T3的有源层130和第八晶体管T8的有源层180之间。第四晶体管T4的有源层140在第二方向Y上位于第一晶体管T1的有源层110和第五晶体管T5的有源层150之间。第六晶体管T6的有源层160在第一方向X上位于第七晶体管T7的有源层170远离第五晶体管T5的有源层150的一侧。第九晶体管T9的有源层和第十晶体管T10的有源层在第二方向Y上依次排布。第九晶体管T9的有源层在第一方向X上位于第八晶体管T8的有源层180远离第一晶体管T1的有源层110的一侧，第十晶体管T10的有源层在第一方向X上位于第六晶体管T6的有源层160远离第七晶体管T7的有源层170的一侧。
在一些示例性实施方式中，如图17所示，第九晶体管T9的有源层包括第一分区190-1和第二分区190-2；第十晶体管T10的有源层包括第三分区200-1和第四分区200-2。其中，第九晶体管T9的有源层的第一分区190-1和第十晶体管T10的有源层的第三分区200-1可以为一体结构，例如可以为矩形。第九晶体管T9的有源层的第二分区190-2和第十晶体管T10的有源层的第四分区200-2可以为一体结构，例如可以为矩形。本示例性实施方式中，通过将第九晶体管T9和第十晶体管T10的有源层分区，可以实现更好的散热效果，或者，可以防止过热。然而，本实施例对于第九晶体管T9和第十晶体管T10的有源层的分区数目以及至少一个分区的形状并不限定。
在一些示例性实施方式中，如图17所示，第二晶体管T2的有源层120在衬底基板上的正投影可以为U型。第一晶体管T1的有源层110、第三晶体管T3的有源层130、第四晶体管T4的有源层140、第五晶体管T5的有源 层150和第六晶体管T6的有源层160在衬底基板上的正投影可以为哑铃型。第七晶体管T7的有源层170和第八晶体管T8的有源层180可以为一体结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，第一半导体层的材料例如可以包括多晶硅。有源层可以包括至少一个沟道区和多个掺杂区。沟道区可以不掺杂杂质，并具有半导体特性。多个掺杂区可以在沟道区的两侧，并且掺杂有杂质，并因此具有导电性。杂质可以根据晶体管的类型而变化。
在一些示例性实施方式中，有源层的掺杂区可以被解释为晶体管的源电极或漏电极。例如，第一晶体管T1的源电极可以与有源层110的沟道区110a的周边、掺杂有杂质的第一掺杂区110b对应，第一晶体管T1的漏电极可以与有源层110的沟道区110a的周边、掺杂有杂质的第二掺杂区110c对应。另外，晶体管之间的有源层的部分可以被解释为掺杂有杂质的布线，可以用于电连接晶体管。
在一些示例性实施方式中，晶体管的输出能力与晶体管沟道区的宽与长的比有关，输出能力强的晶体管的沟道区的宽与长的比较大。如图17所示，第四晶体管T4的有源层140的沟道区140a的宽度(即沟道区140a沿第二方向Y的长度)为W T4，第五晶体管T5的有源层150的沟道区150a的宽度(即沟道区150a沿第一方向X的长度)为W T5。第五晶体管T5的有源层150的沟道区150a的宽度和第四晶体管T4的有源层140的沟道区140a的宽度满足：2W T4<W T5。
在本公开实施例中，A的“宽度”表示A在垂直于延伸方向的特征尺寸。
图18为本公开至少一实施例的形成第一导电层后的扫描驱动控制电路的俯视图。如图15至图18所示，非显示区域的第一导电层至少包括：扫描驱动控制电路的多个晶体管的控制极、多个电容的第一极。例如，第一导电层可以包括：第一晶体管T1的控制极113、第二晶体管T2的控制极123、第三晶体管T3的控制极133、第四晶体管T4的控制极143、第五晶体管T5的控制极153、第六晶体管T6的控制极163、第七晶体管T7的控制极173、第八晶体管T8的控制极183、第九晶体管T9的控制极193a和193b、第十晶体管T10的控制极203、第一电容C1的第一极C1-1、第二电容C2的第一 极C2-1、第三电容C3的第一极C3-1以及第四电容C4的第一极C4-1。
在一些示例性实施方式中，如图18所示，第三晶体管T3的控制极133与第一晶体管T1的控制极113可以为一体结构。第二晶体管T2的控制极123、第十晶体管T10的控制极203和第二电容C2的第一极C2-1可以为一体结构。第五晶体管T5的控制极153、第六晶体管T6的控制极163和第一电容C1的第一极C1-1可以为一体结构。第八晶体管T8的控制极183、第四晶体管T4的控制极143和第四电容C4的第一极C4-1可以为一体结构。第九晶体管T9的控制极193a和193b和第三电容C3的第一极C3-1可以为一体结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，第九晶体管T9可以为双栅晶体管，以防止和减少漏电流的发生。然而，本实施例对此并不限定。
图19为本公开至少一实施例的形成第二导电层后的扫描驱动控制电路的俯视图。如图15至图19所示，非显示区域的第二导电层至少包括：扫描驱动控制电路的多个电容的第二极、信号输入端和信号输入端。例如，第二导电层可以包括：第一电容C1的第二极C1-2、第二电容C2的第二极C2-2、第三电容C3的第二极C3-2、第四电容C4的第二极C4-2、信号输入端IN和信号输出端OUT。其中，第二电容C2的第二极C2-2与信号输出端OUT可以为一体结构。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图19所示，第一电容C1的第二极C1-2在衬底基板上的投影与第一极C1-1在衬底基板上的投影存在交叠。第二电容C2的第二极C2-2在衬底基板上的投影与第一极C2-1在衬底基板上的投影存在交叠。第三电容C3的第二极C3-2在衬底基板上的投影与第一极C3-1在衬底基板上的投影存在交叠。第四电容C4的第二极C4-2在衬底基板上的投影与第一极C4-1在衬底基板上的投影存在交叠。
图20为本公开至少一实施例的形成第三绝缘层后的扫描驱动控制电路的俯视图。如图15至图20所示，非显示区域的第三绝缘层33上形成有多个过孔。例如，多个过孔可以包括：多个第一过孔F1至F25、多个第二过孔K1至K10、以及多个第三过孔D1至D5。多个第一过孔F1至F25内的第三绝缘层33、第二绝缘层32和第一绝缘层31被刻蚀掉，暴露出第一半导体层 的表面。多个第二过孔K1至K10内的第三绝缘层33和第二绝缘层32被刻蚀掉，暴露出第一导电层的表面。多个第三过孔D1至D5内的第三绝缘层33被刻蚀掉，暴露出第二导电层的表面。
图21为本公开至少一实施例的形成第三导电层后的扫描驱动控制电路的俯视图。如图15至图21所示，非显示区域的第三导电层至少包括：扫描驱动控制电路的多个晶体管的第一极和第二极、多条时钟信号线和多条电源线。例如，第三导电层可以包括：第一晶体管T1至第十晶体管T10的第一极和第二极、第一时钟信号线CKL、第二时钟信号线CBL、初始信号线STV、第一电源线PL1、第二电源线PL2、第三电源线PL3、第一连接电极211以及第二连接电极212。
在一些示例性实施方式中，如图21所示，第三晶体管T3的第一极131、第六晶体管T6的第一极161和第二电源线PL2可以为一体结构。第二晶体管T2的第二极121和第三晶体管T3的第二极132可以为一体结构。第四晶体管T4的第二极142和第五晶体管T5的第二极152可以为一体结构。第五晶体管T5的第一极151、第八晶体管T8的第一极181、第九晶体管T9的第一极191和第一电源线PL1可以为一体结构。第六晶体管T6的第二极162和第七晶体管T7的第二极172可以为一体结构。第九晶体管T9的第二极192和第十晶体管T10的第二极202可以为一体结构。第十晶体管T10的第一极201和第三电源线PL3可以为一体结构。
在一些示例性实施方式中，如图21所示，第一连接电极211通过第二过孔K9与第二电容C2的第一极C2-1连接，通过第二过孔K7与第四电容C4的第一极C4-1连接，通过第一过孔F6与第一晶体管T1的有源层110的第二掺杂区110c连接，还通过第二过孔K6与第四晶体管T4的控制极143连接。第一连接电极211在衬底基板上的投影位于第一电源线PL1和第二电源线PL2在衬底基板上的投影之间。第二连接电极212通过第三过孔D3与第一电容C1的第二极C1-2连接，还通过第二过孔K5与第七晶体管T7的控制极173连接。第一电源线PL1通过竖排设置的多个(例如，三个)第三过孔D4与第三电容C3的第二极C3-2连接。然而，本实施例对此并不限定。
在一些示例性实施方式中，如图15至图21所示，第一晶体管T1包括： 有源层110、控制极113、第一极111和第二极112。第一晶体管T1的有源层110包括：沟道区110a、第一掺杂区110b和第二掺杂区110c。第一晶体管T1的有源层110和第二电源线PL2相邻。第一晶体管T1的有源层110的沟道区110a靠近第二电源线PL2的侧边与第二电源线PL2远离第一晶体管T1的侧边之间的距离L2满足：0≤L2≤4W PL2；其中，W PL2为第二电源线PL2的宽度(即第二电源线PL2沿第一方向X的长度X3)。第一晶体管T1的第一极111通过第一过孔F5和第一晶体管T1的有源层110的第一掺杂区110b连接，还通过第三过孔D1与信号输入端IN连接。第一晶体管T1的控制极113和第三晶体管T3的控制极133为一体结构，第一时钟信号线CKL通过竖排设置的两个第二过孔K1与第一晶体管T1的控制极113连接，以实现第一晶体管T1的控制极113接收第一时钟信号。
在本公开实施例中，“并排设置”可以表示沿第一方向X依次设置，“竖排设置”可以表示沿第二方向Y依次设置。
在一些示例性实施方式中，如图15至图21所示，第二晶体管T2包括：有源层120、控制极123、第一极121和第二极122。第二晶体管T2的有源层120包括：沟道区120a、第一掺杂区120b和第二掺杂区120c。第二晶体管T2的控制极123、第二电容C2的第一极C2-1和第十晶体管T10的控制极203为一体结构。第二晶体管T2的第一极121通过第一过孔F4与第二晶体管T2的有源层120的第一掺杂区120b连接，还通过第二过孔K2与第一晶体管T1的控制极113连接，以实现与第一时钟信号线CKL的电连接。第二晶体管T2的第二极122与第三晶体管T3的第二极132为一体结构。第二晶体管T2的第二极122通过第一过孔F3与第二晶体管T2的有源层120的第二掺杂区120c连接，还通过第二过孔K8与第五晶体管T5的控制极153连接。
在一些示例中，第二电源线PL2位于第二晶体管T2远离第一时钟信号线CKL的一侧。第二晶体管T2的有源层120和第二电源线PL2相邻。第二晶体管T2的有源层120的沟道区120a靠近第二电源线PL2的侧边与第二电源线PL2远离第二晶体管T2的侧边之间的距离L4满足：0≤L4≤3W PL2；其中，W PL2为第二电源线PL2的宽度。
在一些示例性实施方式中，如图15至图21所示，第三晶体管T3包括：有源层130、控制极133、第一极131和第二极132。第三晶体管T3的有源层130包括：沟道区130a、第一掺杂区130b和第二掺杂区130c。第三晶体管T3的第一极131与第二电源线PL2为一体结构。第三晶体管T3的第一极131通过第一过孔F1与第三晶体管T3的有源层130的第一掺杂区130b连接。第三晶体管T3的第二极132通过第一过孔F2与第三晶体管T3的有源层130的第二掺杂区130c连接。在一些示例中，第二电源线PL2位于第三晶体管T3远离初始信号线STV的一侧。第三晶体管T3的有源层130的沟道区130a靠近第二电源线PL2的侧边与第二电源线PL2远离第三晶体管T3的侧边之间的距离L3满足：0≤L3≤4W PL2；其中，W PL2为第二电源线PL2的宽度。
在一些示例性实施方式中，如图15至图21所示，第四晶体管T4包括：有源层140、控制极143、第一极141和第二极142。第四晶体管T4的有源层140包括：沟道区140a、第一掺杂区140b和第二掺杂区140c。第四晶体管T4的控制极143和第四电容C4的第一极C4-1为一体结构。第四晶体管T4的第一极141通过第一过孔F7与第四晶体管T4的有源层140的第一掺杂区140b连接，还通过第二过孔K4与第七晶体管T7的控制极173连接。第四晶体管T4的第二极142与第五晶体管T5的第二极152为一体结构。第四晶体管T4的第二极142通过第一过孔F8与第四晶体管T4的有源层140的第二掺杂区140c连接，还通过第三过孔D2与第四电容C4的第二极C4-2连接。
在一些示例性实施方式中，如图15至图21所示，第五晶体管T5包括：有源层150、控制极153、第一极151和第二极152。第五晶体管T5的有源层150包括：沟道区150a、第一掺杂区150b和第二掺杂区150c。第五晶体管T5的控制极153和第六晶体管T6的控制极163为一体结构。第五晶体管T5的第一极151与第一电源线PL1为一体结构。第五晶体管T5的第一极151通过第一过孔F10与第五晶体管T5的有源层150的第一掺杂区150b连接。第五晶体管T5的第二极152通过第一过孔F9与第五晶体管T5的有源层150的第二掺杂区150c连接。
在一些示例性实施方式中，如图15至图21所示，第六晶体管T6包括： 有源层160、控制极163、第一极161和第二极162。第六晶体管T6的有源层160包括：沟道区160a、第一掺杂区160b和第二掺杂区160c。第六晶体管T6的第一极161与第二电源线PL2为一体结构。第六晶体管T6的第一极161通过第一过孔F14与第六晶体管T6的有源层160的第一掺杂区160b连接。第六晶体管T6的第二极162和第七晶体管T7的第二极172为一体结构。第六晶体管T6的第二极162通过第一过孔F15与第六晶体管T6的有源层160的第二掺杂区160c连接。
在一些示例性实施方式中，如图15至图21所示，第七晶体管T7包括：有源层170、控制极173、第一极171和第二极172。第七晶体管T7的有源层170和第八晶体管T8的有源层180为一体结构。第七晶体管T7的有源层170包括：沟道区170a、第一掺杂区170b和第二掺杂区170c。第七晶体管T7的有源层170的第一掺杂区170b和第八晶体管T8的有源层180的第二掺杂区180c连接。第七晶体管T7的第一极171通过第一过孔F12与第七晶体管T7的有源层170的第一掺杂区170b连接，还通过第二过孔K10与第三电容C3的第一极C3-1连接。第七晶体管T7的第二极172通过第一过孔F13与第七晶体管T7的有源层170的第二掺杂区170c连接。第二时钟信号线CBL通过竖排设置的两个第二过孔K3与第七晶体管T7的控制极173连接。
在一些示例性实施方式中，如图15至图21所示，第八晶体管T8包括：有源层180、控制极183和第一极181。第八晶体管T8的有源层180包括：沟道区180a、第一掺杂区180b和第二掺杂区180c。第八晶体管T8的控制极183和第四电容C4的第一极C4-1为一体结构。第八晶体管T8的第一极181与第一电源线PL1为一体结构。第八晶体管T8的第一极181通过第一过孔F11与第八晶体管T8的有源层180的第一掺杂区180b连接。
在一些示例性实施方式中，如图15至图21所示，第九晶体管T9包括：有源层、控制极193a和193b、第一极191和第二极192。第九晶体管T9的有源层包括第一分区190-1和第二分区190-2。第九晶体管T9的第一分区190-1包括：沟道区190-1a1和190-1a2、第一掺杂区190-1b、第二掺杂区190-1c和第三掺杂区190-1d。第九晶体管T9的第二分区190-2包括：沟道区190-2a1和190-2a2、第一掺杂区190-2b、第二掺杂区190-2c和第三掺杂区190-2d。 第九晶体管T9的第一极191和第一电源线PL1为一体结构。第九晶体管T9的第一极191通过并排设置的多个(例如，三个)第一过孔F18与第九晶体管T9的第一分区190-1的第一掺杂区190-1b连接，还通过并排设置的多个(例如，三个)第一过孔F19与第九晶体管T9的第二分区190-2的第一掺杂区190-2b连接。第九晶体管T9的第二极192和第十晶体管T10的第二极202为一体结构。第九晶体管T9的第二极192通过并排设置的多个(例如，三个)第一过孔F16与第九晶体管T9的第一分区190-1的第二掺杂区190-1c连接，还通过并排设置的多个(例如，三个)第一过孔F17与第九晶体管T9的第二分区190-2的第二掺杂区190-2c连接，还通过并排设置的多个(例如，三个)第一过孔F20与第九晶体管T9的第一分区190-1的第三掺杂区190-1d连接，还通过并排设置的多个(例如，三个)第一过孔F21与第九晶体管T9的第二分区190-2的第三掺杂区190-2d连接。
在一些示例性实施方式中，如图15至图21所示，第十晶体管T10包括：有源层、控制极203、第一极201和第二极202。第十晶体管T10的有源层包括：第三分区200-1和第四分析200-2。第十晶体管T10的第三分区200-1包括：沟道区200-1a1和200-1a2、第一掺杂区200-1b、第二掺杂区200-1c和第三掺杂区200-1d。第十晶体管T10的第四分区200-2包括：沟道区200-2a、第一掺杂区200-2b和第二掺杂区200-2c。第十晶体管T10的第三分区200-1和第九晶体管T9的第一分区190-1为一体结构，第三分区200-1的第二掺杂区200-1c与第九晶体管的第一分区190-1的第三掺杂区190-1d连接。第十晶体管T10的第四分区200-2和第九晶体管T9的第二分区190-2为一体结构，第四分区200-2的第二掺杂区200-2c与第九晶体管T9的第二分区190-2的第三掺杂区190-2d连接。第十晶体管T10的第一极201与第三电源线PL3为一体结构。第十晶体管T10的第一极201通过并排设置的多个(例如，三个)第一过孔F22与第十晶体管T10的第三分区200-1的第一掺杂区200-1b连接，还通过并排设置的多个(例如，三个)第一过孔F23与第十晶体管T10的第四分区200-2的第一掺杂区200-2b连接。第十晶体管T10的第二极202通过并排设置的多个(例如，三个)第一过孔F24与第十晶体管T10的第三分区200-1的第三掺杂区200-1d连接，还通过并排设置的多个(例如，三个)第一过孔F25与第十晶体管T10的第四分区200-2的第二掺杂区200-2c连接。 第十晶体管T10的第二极202还通过并排设置的两个第三过孔D5与信号输出端OUT连接。
在一些示例性实施方式中，扫描驱动控制电路的输出控制电路包括：第一节点控制电容和第二节点控制电容。第一节点控制电容可以配置为控制第一节点N1的电位，第二节点控制电容可以配置为控制第二节点N2的电位。第一节点控制电容包括第一电容C1和第三电容C3。第二节点控制电容包括第二电容C2和第四电容C4。本示例性实施方式中，通过第二电容C2和第四电容C4的串联设计，可以使得第二节点N2的电位更稳定，从而使得第十晶体管T10实现稳定输出。
在一些示例性实施方式中，电容一般的作用是稳定节点的电位，电容的面积与该电容所控制的节点的电位需要保持的范围有关。为了实现窄边框，需要在更小的空间内合理布局电容来实现其所起的作用。本实施例提供的显示基板，通过设置电容的宽度(例如，沿第一方向的长度)与扫描驱动控制电路宽度的比符合一定的条件，能够实现在高效利用空间的前提下，确保甚至优化扫描驱动控制电路的性能。
在一些示例性实施方式中，第一节点控制电容、第二节点控制电容和扫描驱动控制电路在第一方向上的长度满足：
Figure PCTCN2022104688-appb-000018
Figure PCTCN2022104688-appb-000019
其中，L C1k为第一节点控制电容在第一方向上的长度，L C2k为第二节点控制电容在第一方向上的长度，L Y为扫描驱动控制电路在第一方向上的长度。
在一些示例性实施方式中，扫描驱动控制电路在第一方向上的长度L Y为时钟信号线或起始信号线远离显示区域的一侧和电源线靠近显示区域一侧之间的距离。当远离显示区域的一侧具有时钟信号线和起始信号线，以远离显示区域一侧的走线为准。当靠近显示区域的一侧具有电源线和其余走线(例如，信号输出端向显示区域延伸的走线)，以靠近显示区域一侧的走线为准。在一些示例中，如图15所示，扫描驱动控制电路在第一方向X上的长度L Y为第一时钟信号线CKL远离显示区域的侧边和第三电源线PL3靠近显示区 域的侧边之间的距离。
在一些示例性实施方式中，第一节点控制电容在第一方向上的长度L C1k可以为第一电容C1在第一方向上的长度和第三电容C3在第一方向上的长度中的较大者。第二节点控制电容在第一方向上的长度L C2k可以为第二电容C2在第一方向上的长度和第四电容C4在第一方向上的长度中的较大者。针对形状不规则的电容，则该电容在第一方向上的长度可以为该电容在第一方向上的长度的最大值。
在一些示例性实施方式中，第一电容、第三电容、第二节点控制电容和扫描驱动控制电路在第一方向上的长度满足：
Figure PCTCN2022104688-appb-000020
Figure PCTCN2022104688-appb-000021
其中，L C1为第一电容在第一方向上的长度，L C3为第三电容在第一方向上的长度，L C2k为第二节点控制电容在第一方向上的长度，L Y为扫描驱动控制电路在第一方向上的长度。
在一些示例性实施方式中，第一电容和扫描驱动控制电路在第一方向上的长度满足：
Figure PCTCN2022104688-appb-000022
第二节点控制电容和扫描驱动控制电路在第一方向上的长度满足：
Figure PCTCN2022104688-appb-000023
第三电容和扫描驱动控制电路在第一方向上的长度满足：
Figure PCTCN2022104688-appb-000024
在一些示例性实施方式中，
Figure PCTCN2022104688-appb-000025
为以下之一：0.09、0.10、0.14；
Figure PCTCN2022104688-appb-000026
为以下之一：0.22、0.35、0.48；
Figure PCTCN2022104688-appb-000027
为以下之一：0.07、0.06、0.05。
在一些示例性实施方式中，
Figure PCTCN2022104688-appb-000028
在一些示例性实施方式中，
Figure PCTCN2022104688-appb-000029
在一些示例性实施方式中，
Figure PCTCN2022104688-appb-000030
进一步地，为了提高空间利用率，电容可以与电源线或时钟信号线在衬底基板上的投影有交叠。
在一些示例性实施方式中，第三电容与第一电源线在衬底基板上的投影存在交叠，且交叠面积满足：
Figure PCTCN2022104688-appb-000031
其中，S C3为第三电容在衬底基板上的投影面积，S C3-1为第三电容和第一电源线在衬底基板上的投影的交叠面积，S C2为第二电容在衬底基板上的投影面积。
在一些示例性实施方式中，第二节点控制电容与第一电源线在衬底基板上的投影存在交叠，且交叠面积满足：
Figure PCTCN2022104688-appb-000032
其中，S C2k-1为第二节点控制电容和第一电源线在衬底基板上的投影的交叠面积，X2为第一电源线在第一方向上的长度，L5为第二节点控制电容的其中一个电容与第一电源线在衬底基板上的投影的交叠区域在第二方向上的长度。在一些示例性实施方式中，第二节点控制电容的投影面积可以为第二电容的投影面积和第四电容的投影面积之和。
在一些示例性实施方式中，如图15所示，L5’为第二电容C2与第一电源线PL1在衬底基板上的投影的交叠区域在第二方向Y上的长度。L5”为第四电容C4与第一电源线PL1在衬底基板上的投影的交叠区域在第二方向Y上的长度。第二节点控制电容的其中一个电容与第一电源线在衬底基板上的投影的交叠区域在第二方向上的长度L5可以为L5’或L5”。
在一些示例性实施方式中，第二节点控制电容与第二电源线在衬底基板上的投影存在交叠，且交叠面积满足：
Figure PCTCN2022104688-appb-000033
其中，S C2k-2为第二节点控制电容和第二电源线在衬底基板上的投影的交叠面积，X3为第二电源线在第一方向上的长度，L6为第二节点控制电容的 其中一个电容与第二电源线在衬底基板上的投影的交叠区域在第二方向上的长度。
在一些示例性实施方式中，如图15所示，L6’为第二电容C2与第二电源线PL2在衬底基板上的投影的交叠区域在第二方向Y上的长度。L6”为第四电容C4与第二电源线PL2在衬底基板上的投影的交叠区域在第二方向Y上的长度。第二节点控制电容的其中一个电容与第二电源线在衬底基板上的投影的交叠区域在第二方向上的长度L6可以为L6’或L6”。
在一些示例性实施方式中，如图15所示，第一电容C1在第一方向X上的中心与第一电源线PL1在第一方向X上远离第一电容C1的侧边之间的距离L7，大于第一电容C1在第一方向X上的中心与第二电源线PL2在第一方向X上靠近第一电容C1的侧边之间的距离L8，且L7≥2*L8。
在一些示例性实施方式中，如图15所示，第八晶体管T8的有源层180靠近第三电容C3的侧边与第三电容C3靠近第八晶体管T8的侧边之间的距离L9满足：W CLK<L9≤W PL1；其中，W CLK为时钟信号线的宽度，W PL1为第一电源线的宽度。在一些示例中，W CLK可以为第一时钟信号线CKL的宽度或者可以为第二时钟信号线CBL的宽度。第一电源线PL1的宽度W PL1即为第一电源线PL1在第一方向X上的长度X2。针对形状不规则的电容，电容的侧边即为最边缘的侧边。例如，L9可以为第八晶体管T8的有源层180靠近第三电容C3的侧边与第三电容C3最靠近第八晶体管T8的侧边之间的距离。
在一些示例性实施方式中，第一电容、第三电容和第二节点控制电容的电容值满足：
Figure PCTCN2022104688-appb-000034
Figure PCTCN2022104688-appb-000035
其中，C 1为第一电容的电容值，C 3为第三电容的电容值，C 2k为第二节点控制电容的电容值。在一些示例中，第二节点控制电容的电容值可以为第二电容C2和第四电容C4的电容值之和。
图22为本公开至少一实施例的级联的扫描驱动控制电路的俯视图。图23为图22所示的第一导电层的示意图。在一些示例性实施方式中，如图22 和图23所示，第n级扫描驱动控制电路的第二电容C2的第一极C2-1和第n+1级扫描驱动控制电路的第四电容C4的第一极C4-1可以为一体结构。本示例性实施方式，可以在简化工艺的同时，提升第二节点的稳定性。
在一些示例性实施方式中，如图22所示，第n级扫描驱动控制电路的信号输出端OUT和第n+1级扫描驱动控制电路的输入端IN可以为一体结构。
关于本实施例的扫描驱动控制电路的其余结构可以参照前述实施例的说明，故于此不再赘述。
图24为本公开至少一实施例的扫描驱动控制电路的另一俯视图。在一些示例性实施方式中，如图24所示，信号输出端OUT位于第九晶体管T9和第十晶体管T10远离第一电源线PL1的一侧。信号输出端OUT与第二电容C2的第二极可以为一体结构。信号输出端OUT可以具有三个沿第一方向X向靠近第一电源线PL1一侧凸出的凸出部。第九晶体管T9的第二极192可以通过第三过孔D6与信号输出端OUT的第一个凸出部连接，还可以通过第三过孔D7与信号输出端OUT的第二个凸出部连接，第十晶体管T10的第二极202可以通过第三过孔D8与信号输出端OUT的第三个凸出部连接。然而，本实施例对此并不限定。
在本示例性实施方式中，如图24所示，扫描驱动控制电路在第一方向X上的长度L Y可以为第一时钟信号线CKL远离显示区域的侧边和信号输出端OUT的延伸走线靠近显示区域的侧边之间的距离。
关于本实施例的扫描驱动控制电路的其余结构可以参照前述实施例的说明，故于此不再赘述。
图25为本公开至少一实施例的扫描驱动控制电路的另一俯视图。在一些示例性实施方式中，如图25所示，在第一方向X上，扫描驱动控制电路的第一导电层的边界比第三电源线PL3的侧边更靠近显示区域。在本示例中，扫描驱动控制电路在第一方向X上的长度L Y可以为第一时钟信号线CKL远离显示区域的侧边和扫描驱动控制电路的第一导电层靠近显示区域的侧边(例如，第十晶体管T10的控制极203靠近显示区域的侧边)之间的距离。
关于本实施例的扫描驱动控制电路的其余结构可以参照前述实施例的说明，故于此不再赘述。
下面参照图15至图21通过显示基板的制备过程的示例说明显示基板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶处理。沉积可以采用溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用喷涂和旋涂中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程中该“薄膜”需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。
本公开所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“A的投影包含B的投影”，是指B的投影的边界落入A的投影的边界范围内，或者A的投影的边界与B的投影的边界重叠。
本示例性实施例的显示基板的制备过程包括以下步骤。
(1)、提供衬底基板。
在一些示例性实施方式中，衬底基板30可以为刚性衬底或柔性衬底。刚性衬底可以包括玻璃、金属箔片中的一种或多种。柔性衬底可以包括聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
(2)、形成第一半导体层图案。
在一些示例性实施方式中，在衬底基板30上沉积第一半导体薄膜，通过构图工艺对第一半导体薄膜进行构图，形成第一半导体层图案，如图17所示。第一半导体层图案至少包括：扫描驱动控制电路中的多个晶体管(例如，晶体管T1至T10)的有源层。有源层可以包括至少一个沟道区和多个掺杂区。沟道区可以不掺杂杂质，并具有半导体特性。掺杂区掺杂有杂质，并因此具有导电性。杂质可以根据晶体管的类型(例如，N型或P型)而变化。在一些示例中，第一半导体薄膜的材料可以为多晶硅。
(3)、形成第一导电层图案。
在一些示例性实施方式中，在形成前述图案的衬底基板30上依次沉积第一绝缘薄膜和第一导电薄膜，通过构图工艺对第一导电薄膜进行构图，形成覆盖第一半导体层图案的第一绝缘层31，以及设置在第一绝缘层31上的第一导电层图案，如图18所示。在一些示例中，第一导电层图案可以包括：扫描驱动控制电路的多个晶体管(例如，晶体管T1至T10)的控制极、扫描驱动控制电路的多个电容(例如，第一电容C1至第四电容C4)的第一极。
(4)、形成第二导电层图案。
在一些示例性实施方式中，在形成前述图案的衬底基板30上依次沉积第二绝缘薄膜和第二导电薄膜，通过构图工艺对第二导电薄膜进行构图，形成覆盖第一导电层的第二绝缘层32，以及设置在第二绝缘层32上的第二导电层图案，如图19所示。在一些示例中，第二导电层图案可以包括：扫描驱动控制电路的多个电容(例如，第一电容C1至第四电容C4)的第二极、信号输入端IN和信号输出端OUT。
(5)、形成第三绝缘层图案。
在一些示例性实施方式中，在形成前述图案的衬底基板30上沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行构图，形成覆盖第二导电层的第三绝缘层33图案，如图20所示。在一些示例中，第三绝缘层33上开设有多个过孔。多个过孔至少包括：多个第一过孔F1至F25、多个第二过孔K1至K10、以及多个第三过孔D1至D5。多个第一过孔F1至F25内的第三绝缘层33、第二绝缘层32和第一绝缘层31被刻蚀掉，暴露出第一半导体层的表面。多个第二过孔K1至K10内的第三绝缘层33和第二绝缘层32被刻蚀掉，暴露出第一导电层的表面。多个第三过孔D1至D5内的第三绝缘层33被刻蚀掉，暴露出第二导电层的表面。
(6)、形成第三导电层图案。
在一些示例性实施方式中，在形成前述图案的衬底基板30上沉积第三导电薄膜，通过构图工艺对第三导电薄膜进行构图，在第三绝缘层33上形成第三导电层图案，如图21所示。在一些示例中，第三导电层图案可以包括：扫描驱动控制电路的多个晶体管(例如，晶体管T1至T10)的第一极和第二极、第一连接电极211和第二连接电极212。
在一些示例性实施方式中，在非显示区域形成扫描驱动控制电路的同时，可以在显示区域形成像素电路。例如，显示区域的第一半导体层可以包括像素电路的晶体管的有源层，显示区域的第一导电层可以包括像素电路的晶体管的控制极以及存储电容的第一电极，显示区域的第二导电层可以至少包括像素电路的存储电容的第二电极，显示区域的第三导电层可以至少包括像素电路的晶体管的第一极和第二极。在形成第一导电层之后可以在显示区域形成第二半导体层，第二半导体层和第一导电层之间设置有绝缘层。第二半导体薄膜的材料可以为金属氧化物，例如，IGZO。然而，本实施例对于第二半导体层的位置并不限定。
在一些示例性实施方式中，在形成第三导电层之后，可以在显示区域依次形成第四绝缘层、阳极层、像素定义层、有机发光层、阴极层和封装层图案。在一些示例中，在形成有前述图案的衬底基底上，涂覆第四绝缘薄膜，通过对第四绝缘薄膜的掩膜、曝光和显影，形成第四绝缘层图案。随后，在形成有前述图案的显示区域的衬底基底上，沉积阳极薄膜，通过构图工艺对阳极薄膜进行构图，在第四绝缘层上形成阳极图案。然后，在形成前述图案的衬底基底上涂覆像素定义薄膜，通过掩膜、曝光和显影工艺形成像素定义层(PDL，Pixel Define Layer)图案，像素定义层形成在在显示区域的每个子像素中，每个子像素中的像素定义层形成有暴露出阳极的像素开口。随后，在前述形成的像素开口内形成有机发光层，有机发光层与阳极连接。随后，沉积阴极薄膜，通过构图工艺对阴极薄膜进行构图，形成阴极图案。随后，在阴极上形成封装层，封装层可以包括无机材料/有机材料/无机材料的叠层结构。
在一些示例性实施方式中，第一导电层、第二导电层和第三导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层31、第二绝缘层32以及第三绝缘层33可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第四绝缘层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。 第一绝缘层31和第二绝缘层32称之为栅绝缘(GI)层，第三绝缘层33称之为层间绝缘(ILD)层，第四绝缘层称之为平坦层。像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等有机材料。阳极可以采用氧化铟锡(ITO)或氧化铟锌(IZO)等透明导电材料。阴极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或更多种，或采用上述金属中任意一种或多种制成的合金。然而，本实施例对此并不限定。例如，阳极可以采用金属等反射材料，阴极可以采用透明导电材料。
本示例性实施例所示结构及其制备过程仅仅是一种示例性说明。在一些示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。本示例性实施例的制备工艺可以利用目前成熟的制备设备即可实现，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开实施例还提供一种显示装置，包括如上所述的显示基板。在一些示例性实施方式中，显示基板可以为OLED显示基板、QLED显示基板、Micro-LED显示基板、或者Mini-LED显示基板。显示装置可以为：OLED显示装置、手表、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
图25为本公开至少一实施例的显示装置的结构示意图。在一些示例性实施方式中，如图25所示，显示装置可以包括：时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，像素阵列可以包括多个扫描线(例如GL1到GLn)、多个数据信号线(例如，DL1到DLn)、多个发光控制线(例如，EL1到ELn)和多个子像素10。每个子像素10可以连接到对应的数据信号线、对应的扫描线和对应的发光控制线。
在一些示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线DL1、 DL2、DL3、……和DLm的数据电压，m可以是整数。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线DL1至DLm。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描线GL1、GL2、GL3、……和GLn的扫描信号，n可以是整数。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描线GL1至GLn。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光控制线EL1、EL2、EL3、……和ELn的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光控制线EL1至ELn。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发光停止信号传输到下一级电路的方式产生发光信号。在一些示例中，发光驱动器可以包括如上述实施例提供的多个级联的扫描驱动控制电路。在本示例中，扫描驱动控制电路的工作时序可以参照图10所示。
在一些示例性实施方式中，子像素10的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
在一些示例性实施方式中，显示区域内的一个像素单元可以包括三个子像素，三个子像素可以分别为红色子像素、绿色子像素和蓝色子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。
在一些示例实施方式中，时序控制器、数据驱动器、扫描驱动器和发光驱动器可以设置在非显示区域。其中，扫描驱动器和发光驱动器可以分别设置在显示区域的相对两侧，例如，显示区域的左侧和右侧；时序控制器和数据驱动器可以设置在显示区域的一侧，例如显示区域的下侧。然而，本实施 例对此并不限定。
在一些示例性实施方式中，子像素包括像素电路。像素电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C结构。然而，本实施例对此并不限定。例如，像素电路可以包括N型晶体管和P型晶体管。N型晶体管例如可以为氧化物薄膜晶体管，P型晶体管例如可以为低温多晶硅薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(LTPO，Low Temperature Polycrystalline Oxide)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
图27为本公开至少一实施例的显示装置的另一结构示意图。在一些示例性实施方式中，如图27所示，扫描驱动器可以通过第一组扫描线GL1至GLn向像素电路的P型晶体管提供驱动信号，还可以通过第二组扫描线SL1至SLn向像素电路的N型晶体管提供驱动信号。发光驱动器可以通过发光控制线EL1至ELn向像素电路提供发光信号。在一些示例中，扫描驱动器可以包括如上述实施例所述的多个级联的扫描驱动控制电路，以通过第二组扫描线SL1至SLn向像素电路的N型晶体管提供驱动信号。在本示例中，扫描驱动控制电路的工作时序可以参照图9所示。关于本实施例的显示装置的其他说明可以参照前述实施例的说明，故于此不再赘述。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (44)

  1. 一种显示基板，包括：
    衬底基板；
    扫描驱动控制电路，设置在所述衬底基板的非显示区域；
    所述扫描驱动控制电路包括：输入电路、输出控制电路和输出电路；所述输出控制电路与所述输入电路和输出电路连接；
    所述输出控制电路包括：第一节点控制电容和第二节点控制电容；
    所述第一节点控制电容、所述第二节点控制电容和所述扫描驱动控制电路在第一方向上的长度满足：
    Figure PCTCN2022104688-appb-100001
    Figure PCTCN2022104688-appb-100002
    其中，L C1k为所述第一节点控制电容在第一方向上的长度，L C2k为所述第二节点控制电容在第一方向上的长度，L Y为所述扫描驱动控制电路在第一方向上的长度。
  2. 根据权利要求1所述的显示基板，其中，所述第一节点控制电容包括：第一电容和第三电容；
    所述第一电容、所述第三电容、所述第二节点控制电容和所述扫描驱动控制电路在第一方向上的长度满足：
    Figure PCTCN2022104688-appb-100003
    Figure PCTCN2022104688-appb-100004
    其中，L C1为所述第一电容在第一方向上的长度，L C3为所述第三电容在第一方向上的长度，L C2k为所述第二节点控制电容在第一方向上的长度，L Y为所述扫描驱动控制电路在第一方向上的长度。
  3. 根据权利要求2所述的显示基板，其中，
    所述第一电容和所述扫描驱动控制电路在第一方向上的长度满足：
    Figure PCTCN2022104688-appb-100005
    所述第二节点控制电容和所述扫描驱动控制电路在第一方向上的长度满足：
    Figure PCTCN2022104688-appb-100006
    所述第三电容和所述扫描驱动控制电路在第一方向上的长度满足：
    Figure PCTCN2022104688-appb-100007
  4. 根据权利要求2或3所述的显示基板，其中，
    Figure PCTCN2022104688-appb-100008
    为以下之一：0.09、0.10、0.14；
    Figure PCTCN2022104688-appb-100009
    为以下之一：0.22、0.35、0.48；
    Figure PCTCN2022104688-appb-100010
    为以下之一：0.07、0.06、0.05。
  5. 根据权利要求2或3所述的显示基板，其中，
    Figure PCTCN2022104688-appb-100011
  6. 根据权利要求2或3所述的显示基板，其中，
    Figure PCTCN2022104688-appb-100012
  7. 根据权利要求2或3所述的显示基板，其中，
    Figure PCTCN2022104688-appb-100013
  8. 根据权利要求2至7中任一项所述的显示基板，其中，所述第一电容、所述第二节点控制电容以及所述第三电容在第一方向上的长度满足：
    Figure PCTCN2022104688-appb-100014
  9. 根据权利要求2至8中任一项所述的显示基板，其中，所述第三电容与第一电源线连接；所述第三电容与第一电源线在所述衬底基板上的投影存在交叠，且交叠面积满足：
    Figure PCTCN2022104688-appb-100015
    其中，S C3为所述第三电容在所述衬底基板上的投影面积，S C3-1为所述第三电容和第一电源线在所述衬底基板上的投影的交叠面积；
    所述第二节点控制电容包括第二电容，S C2为所述第二电容在所述衬底基 板上的投影面积。
  10. 根据权利要求2至8中任一项所述的显示基板，其中，所述第二节点控制电容与第一电源线在所述衬底基板上的投影存在交叠，且交叠面积满足：
    Figure PCTCN2022104688-appb-100016
    其中，S C2k-1为所述第二节点控制电容和第一电源线在所述衬底基板上的投影的交叠面积，X2为所述第一电源线在第一方向上的长度，L5为所述第二节点控制电容的其中一个电容与第一电源线在所述衬底基板上的投影的交叠区域在第二方向上的长度；所述第二方向与所述第一方向交叉。
  11. 根据权利要求2至8中任一项所述的显示基板，其中，所述输入电路与第二电源线连接；所述第二节点控制电容与第二电源线在所述衬底基板上的投影存在交叠，且交叠面积满足：
    Figure PCTCN2022104688-appb-100017
    其中，S C2k-2为所述第二节点控制电容和第二电源线在所述衬底基板上的投影的交叠面积，X3为所述第二电源线在第一方向上的长度，L6为所述第二节点控制电容的其中一个电容与第二电源线在所述衬底基板上的投影的交叠区域在第二方向上的长度；所述第二方向与所述第一方向交叉。
  12. 根据权利要求2至11中任一项所述的显示基板，其中，所述第一电容在所述衬底基板上的投影位于所述第一电源线和第二电源线在所述衬底基板上的投影之间；
    所述第一电容在第一方向上的中心与所述第一电源线在第一方向上远离所述第一电容的侧边之间的距离L7，大于所述第一电容在第一方向上的中心与所述第二电源线在第一方向上靠近所述第一电容的侧边之间的距离L8，且L7≥2*L8。
  13. 根据权利要求2至12中任一项所述的显示基板，其中，所述输入电路包括：第一晶体管；所述第一晶体管的控制极与第一时钟信号线连接，第一极与信号输入端连接，第二极与第二节点连接；
    所述第一晶体管的有源层和第二电源线相邻；
    所述第一晶体管的有源层的沟道区靠近所述第二电源线的侧边与所述第二电源线远离所述第一晶体管的侧边之间的距离L2满足：0≤L2≤4W PL2；
    其中，W PL2为所述第二电源线的宽度。
  14. 根据权利要求2至12中任一项所述的显示基板，其中，所述输入电路包括：第三晶体管；所述第三晶体管的控制极与第一时钟信号线连接，第一极与第二电源线连接，第二极与第三节点连接；
    所述第二电源线位于所述第三晶体管远离第一时钟信号线或第二时钟信号线的一侧；
    所述第三晶体管的有源层的沟道区靠近所述第二电源线的侧边与所述第二电源线远离所述第三晶体管的侧边之间的距离L3满足：0≤L3≤4W PL2；
    其中，W PL2为所述第二电源线的宽度。
  15. 根据权利要求2至14中任一项所述的显示基板，其中，所述输入电路与第一时钟信号线和第二电源线连接，所述输出控制电路与第二时钟信号线连接；所述输入电路包括：第二晶体管；所述第二晶体管的控制极与第二节点连接，第一极与第一时钟信号线连接，第二极与第三节点连接；
    所述第二电源线位于所述第二晶体管远离所述第一时钟信号线的一侧；所述第二晶体管的有源层和所述第二电源线相邻；所述第二晶体管的有源层的沟道区靠近所述第二电源线的侧边与所述第二电源线远离所述第二晶体管的侧边之间的距离L4满足：0≤L4≤3W PL2；其中，W PL2为所述第二电源线的宽度。
  16. 根据权利要求2至15中任一项所述的显示基板，其中，所述输出控制电路包括：第一输出控制子电路；
    所述第一输出控制子电路包括：第四晶体管和第五晶体管；所述第四晶体管的控制极与第二节点连接，所述第四晶体管的第一极与第五晶体管的第二极连接，所述第四晶体管的第二极与第二时钟信号线连接；所述第五晶体管的控制极与第三节点连接，第一极与第一电源线连接；
    所述第四晶体管和第五晶体管位于第二电源线远离第二时钟信号线的一侧；
    所述第四晶体管的有源层的延伸方向与第五晶体管的有源层的延伸方向的夹角大于85°且小于95°。
  17. 根据权利要求16所述的显示基板，其中，所述第四晶体管的有源层的沟道区的宽度W T4和所述第五晶体管的有源层的沟道区的宽度W T5满足：2W T4<W T5。
  18. 根据权利要求16所述的显示基板，其中，所述第四晶体管的有源层的延伸方向与所述输入电路的第一晶体管的有源层的延伸方向的夹角大于85°且小于95°。
  19. 根据权利要求2至18中任一项所述的显示基板，其中，所述输出控制电路包括第二输出控制子电路，所述第二输出控制子电路包括第七晶体管；
    所述第七晶体管的控制极与第一电容的第二极连接，所述第七晶体管的第一极与第一节点连接；
    所述第七晶体管与所述第一电容相邻，且所述第七晶体管位于所述第一电容和第一电源线之间。
  20. 根据权利要求19所述的显示基板，其中，所述第二输出控制子电路还包括：第六晶体管；所述第六晶体管的控制极与第一电容的第一极连接，第六晶体管的第二极与第七晶体管的第二极连接，第六晶体管的第一极与第二信号端连接；
    所述第七晶体管的有源层的延伸方向与所述第六晶体管的有源层的延伸方向近似平行。
  21. 根据权利要求2至20中任一项所述的显示基板，其中，所述输出控制电路包括：第三输出控制子电路，所述第三输出控制子电路包括第八晶体管和第三电容；所述第八晶体管的控制极与第二节点连接，第一极与第一电源线连接，第二极与第一节点连接；所述第三电容的第一极与第一节点连接，第二极与第一电源线连接；
    所述输入电路包括第一晶体管；
    所述第一晶体管、所述第八晶体管和第三电容沿着第一方向依次排布，所述第一晶体管的有源层的延伸方向与所述第八晶体管的有源层的延伸方向 近似平行。
  22. 根据权利要求21所述的显示基板，其中，所述第八晶体管的有源层靠近第三电容的侧边与第三电容靠近第八晶体管的侧边之间的距离L9满足：W CLK<L9≤W PL1；其中，W CLK为时钟信号线的宽度，W PL1为第一电源线的宽度。
  23. 根据权利要求1至22中任一项所述的显示基板，其中，所述输入电路与第一时钟信号线连接；所述输出控制电路与第二时钟信号线和第一电源线连接；所述输出电路与第一电源线和第三电源线连接；
    所述第一时钟信号线、第二时钟信号线、初始信号线、第一电源线和第三电源线沿第一方向依次排布。
  24. 根据权利要求2至23中任一项所述的显示基板，其中，所述第一电容、第三电容和第二节点控制电容的电容值满足：
    C 1<C 3<C 2k；
    Figure PCTCN2022104688-appb-100018
    其中，C 1为第一电容的电容值，C 3为第三电容的电容值，C 2k为第二节点控制电容的电容值。
  25. 根据权利要求24所述的显示基板，其中，所述第一电容的第一极与第三节点连接，所述第一电容的第二极与第七晶体管连接；
    所述第三电容的第一极与第一节点连接，所述第三电容的第二极与第一电源线连接；
    所述第二节点控制电容的第一极与第二节点连接；
    所述第一电容和第三电容的电容值之和小于所述第二节点控制电容的电容值。
  26. 根据权利要求25所述的显示基板，其中，所述第二节点控制电容包括第二电容，所述第二电容的第一极与第二节点连接，所述第二电容的第二极与信号输出端连接。
  27. 根据权利要求26所述的显示基板，其中，所述第二节点控制电容还 包括：第四电容，所述第四电容的第一极与第二节点连接，所述第四电容的第二极与第四晶体管和第五晶体管连接。
  28. 根据权利要求27所述的显示基板，其中，本级扫描驱动控制电路的第二电容的第一极与下一级扫描驱动控制电路的第四电容的第一极为一体结构。
  29. 根据权利要求24所述的显示基板，其中，所述输出电路包括第十晶体管；所述第二节点控制电容包括第二电容，所述第二电容的第一极与第十晶体管的控制极为一体结构。
  30. 一种显示装置，包括如权利要求1至29中任一项所述的显示基板。
  31. 一种显示基板，包括扫描驱动控制电路，所述扫描驱动控制电路包括：输入电路、输出控制电路和输出电路；
    所述输入电路，与信号输入端、第一时钟信号端、第一电压端和输出控制电路连接，配置为在第一时钟信号端的控制下，将信号输入端的信号传输至输出控制电路，以及将第一时钟信号端或第一电压端的信号传输至输出控制电路；
    所述输出控制电路，与第一信号端、第二信号端、第二时钟信号端、第二电压端、第一节点、第二节点和输入电路连接，配置为在输入电路的控制下，存储第一信号端的信号，在输入电路和第二时钟信号端的控制下，向第一节点传输第二信号端的信号；或者，在输入电路的控制下，存储第二时钟信号端的信号，并在第二节点的控制下，向第一节点传输第二电压端的信号；
    所述输出电路，与第一电压端、第二电压端、信号输出端、第一节点和第二节点连接，配置为在第二节点的控制下，向信号输出端输出第一电压端的信号，或者，在第一节点的控制下，向信号输出端输出第二电压端的信号。
  32. 根据权利要求31所述的显示基板，其中，所述输入电路包括：第一输入子电路和第二输入子电路；所述输出控制电路包括：第一输出控制子电路、第二输出控制子电路和第三输出控制子电路；所述输出电路包括：第一输出子电路和第二输出子电路；
    所述第一输入子电路，与信号输入端、第一时钟信号端和第一输出控制 子电路连接，配置为在第一时钟信号端的控制下，将信号输入端的信号传输至第一输出控制子电路；
    所述第二输入子电路，与第一电压端、第一时钟信号端、第一输入子电路和第二输出控制子电路连接，配置为在第一输入子电路或第一时钟信号端的控制下，将第一时钟信号端或第一电压端的信号传输至第二输出控制子电路；
    所述第一输出控制子电路，与第一信号端、第二时钟信号端、第二节点、第一输入子电路和第二输入子电路连接，配置为在第一输入子电路或第二输入子电路的控制下，存储第一信号端或第二时钟信号端的信号；
    所述第二输出控制子电路，与第二信号端、第二时钟信号端、第一节点和第二输入子电路连接，配置为在第二输入子电路和第二时钟信号端的控制下，向第一节点传输第二信号端的信号；
    所述第三输出控制子电路，与第二电压端、第一节点和第二节点连接，配置为在第二节点的控制下，向第一节点传输第二电压端的信号；
    所述第一输出子电路，与第一电压端、信号输出端和第二节点连接，配置为在第二节点的控制下，向信号输出端输出第一电压端的信号；
    所述第二输出子电路，与第二电压端、信号输出端和第一节点连接，配置为在第一节点的控制下，向信号输出端输出第二电压端的信号。
  33. 根据权利要求32所述的显示基板，其中，所述第一输入子电路包括：第一晶体管；所述第一晶体管的控制极与第一时钟信号端连接，第一极与信号输入端连接，第二极与第二节点连接；
    所述第二输入子电路包括：第二晶体管和第三晶体管；所述第二晶体管的控制极与第二节点连接，第一极与第一时钟信号端连接，第二极与第三节点连接；所述第三晶体管的控制极与第一时钟信号端连接，第一极与第一电压端连接，第二极与第三节点连接；
    所述第一输出控制子电路包括：第四晶体管和第五晶体管；所述第四晶体管的控制极与第二节点连接，所述第四晶体管的第一极与第二时钟信号端连接，所述第四晶体管的第二极与所述第五晶体管的第二极连接；所述第五 晶体管的控制极与第三节点连接，所述第五晶体管的第一极与第一信号端连接；
    所述第一输出子电路包括：第十晶体管；所述第十晶体管的控制极与第二节点连接，第一极与第一电压端连接，第二极与信号输出端连接。
  34. 根据权利要求32所述的显示基板，其中，所述第一输入子电路包括：第一晶体管；所述第一晶体管的控制极与第一时钟信号端连接，第一极与信号输入端连接，第二极与第四节点连接；
    所述第二输入子电路包括：第二晶体管和第三晶体管；所述第二晶体管的控制极与第四节点连接，第一极与第一时钟信号端连接，第二极与第三节点连接；所述第三晶体管的控制极与第一时钟信号端连接，第一极与第一电压端连接，第二极与第三节点连接；
    所述第一输出控制子电路包括：第四晶体管、第五晶体管和第十一晶体管；所述第四晶体管的控制极与第二节点连接，所述第四晶体管的第一极与第二时钟信号端连接，所述第四晶体管的第二极与所述第五晶体管的第二极连接；所述第五晶体管的控制极与第三节点连接，所述第五晶体管的第一极与第一信号端连接；所述第十一晶体管的控制极与第一电压端连接，所述第十一晶体管的第一极与第四节点连接，所述第十一晶体管的第二极与第二节点连接；
    所述第一输出子电路包括：第十晶体管；所述第十晶体管的控制极与第二节点连接，第一极与第一电压端连接，第二极与信号输出端连接。
  35. 根据权利要求33或34所述的显示基板，其中，所述第二输出控制子电路还包括：第四电容；所述第四电容的第一极与第四晶体管和第十晶体管的控制极连接。
  36. 根据权利要求35所述的显示基板，其中，所述第四电容的第二极与第五晶体管连接。
  37. 根据权利要求33或34所述的显示基板，其中，所述第一输出控制子电路还包括：第二电容；所述第二电容的第一极与第二节点连接。
  38. 根据权利要求37所述的显示基板，其中，所述第二电容的第二极与 信号输出端连接。
  39. 根据权利要求32所述的显示基板，其中，所述第二输入子电路与第三节点连接；
    所述第二输出控制子电路包括：第六晶体管、第七晶体管和第一电容；
    所述第六晶体管的控制极与第三节点连接，所述第六晶体管的第一极与第二信号端连接，所述第六晶体管的第二极与所述第七晶体管的第二极连接；所述第七晶体管的控制极与第二时钟信号端连接，所述第七晶体管的第一极与第一节点连接；
    所述第一电容的第一极与所述第六晶体管的控制极连接，所述第一电容的第二极与所述第七晶体管连接。
  40. 根据权利要求32所述的显示基板，其中，所述第二输入子电路与第五节点连接；
    所述第二输出控制子电路包括：第一电容、第六晶体管、第七晶体管和第十二晶体管；
    所述第六晶体管的控制极与第三节点连接，所述第六晶体管的第一极与第二信号端连接，所述第六晶体管的第二极与所述第七晶体管的第二极连接；所述第七晶体管的控制极与第二时钟信号端连接，所述第七晶体管的第一极与第一节点连接；
    所述第十二晶体管的控制极与第一电压端连接，第一极与第五节点连接，第二极与第三节点连接；
    所述第一电容的第一极与第六晶体管的控制极连接，所述第一电容的第二极与第七晶体管连接。
  41. 根据权利要求32所述的显示基板，其中，所述第三输出控制子电路包括：第八晶体管和第三电容；
    所述第八晶体管的控制极与第二节点连接，第一极与第二电压端连接，第二极与第一节点连接；
    所述第三电容的第一极与第一节点连接，第二极与第二电压端连接；
    所述第二输出子电路包括：第九晶体管；所述第九晶体管的控制极与第一节点连接，第一极与第二电压端连接，第二极与信号输出端连接。
  42. 根据权利要求31或32所述的显示基板，其中，所述第一信号端与第二电压端或第一时钟信号端连接。
  43. 根据权利要求31或32所述的显示基板，其中，所述第二信号端与第一电压端或第二时钟信号端连接。
  44. 一种显示基板的驱动方法，应用于如权利要求31至43中任一项所述的显示基板，所述驱动方法包括：
    输入电路在第一时钟信号端的控制下，将信号输入端的信号传输至输出控制电路，并将第一时钟信号端或第一电压端的信号传输至输出控制电路；
    所述输出控制电路在输入电路的控制下，存储第一信号端的信号，在输入电路和第二时钟信号端的控制下，向第一节点传输第二信号端的信号，所述输出电路在第一节点的控制下，向信号输出端输出第二电压端的信号；
    所述输出控制电路在输入电路的控制下，存储第二时钟信号端的信号，并在第二节点的控制下，向第一节点传输第二电压端的信号；所述输出电路在第二节点的控制下，向信号输出端输出第一电压端的信号。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115274769A (zh) * 2021-04-29 2022-11-01 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置
CN113241040B (zh) * 2021-07-09 2021-09-24 北京京东方技术开发有限公司 显示基板及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000187461A (ja) * 1998-12-22 2000-07-04 Sharp Corp シフトレジスタ回路および画像表示装置
CN101853705A (zh) * 2010-05-27 2010-10-06 友达光电股份有限公司 移位缓存器电路
CN111243650A (zh) * 2020-02-05 2020-06-05 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路
CN111445832A (zh) * 2020-05-07 2020-07-24 合肥京东方卓印科技有限公司 移位寄存单元、信号生成单元电路、驱动方法和显示装置
CN111477181A (zh) * 2020-05-22 2020-07-31 京东方科技集团股份有限公司 栅极驱动电路、显示基板、显示装置和栅极驱动方法
CN111816691A (zh) * 2020-08-28 2020-10-23 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN113241040A (zh) * 2021-07-09 2021-08-10 北京京东方技术开发有限公司 显示基板及显示装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101393635B1 (ko) * 2007-06-04 2014-05-09 삼성디스플레이 주식회사 표시 장치의 구동 장치 및 이를 포함하는 표시 장치
WO2009084271A1 (ja) * 2007-12-27 2009-07-09 Sharp Kabushiki Kaisha シフトレジスタ
KR101881853B1 (ko) * 2012-02-29 2018-07-26 삼성디스플레이 주식회사 에미션 구동 유닛, 에미션 구동부 및 이를 포함하는 유기 발광 표시 장치
CN104821153B (zh) * 2015-05-29 2017-06-16 京东方科技集团股份有限公司 栅极驱动电路及oled显示装置
CN105719613B (zh) * 2016-04-22 2018-06-01 上海天马微电子有限公司 阵列基板、显示面板及显示装置
CN107093414B (zh) * 2017-07-03 2019-04-30 京东方科技集团股份有限公司 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
CN207489447U (zh) * 2017-12-11 2018-06-12 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路、显示装置
CN108538256B (zh) * 2018-04-23 2021-06-01 上海天马有机发光显示技术有限公司 移位寄存单元及其驱动方法、扫描驱动电路和显示装置
CN109935269B (zh) * 2018-05-31 2023-05-16 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN109584799A (zh) * 2019-02-02 2019-04-05 京东方科技集团股份有限公司 一种像素驱动电路、像素电路、显示面板和显示装置
CN109658865B (zh) * 2019-02-25 2021-01-05 合肥京东方卓印科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN110164352B (zh) * 2019-04-28 2021-03-23 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路和显示面板
CN114300029A (zh) * 2019-08-08 2022-04-08 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路和显示装置
CN210956110U (zh) * 2019-12-24 2020-07-07 北京京东方技术开发有限公司 一种显示装置
CN111128080B (zh) * 2020-03-30 2020-08-04 京东方科技集团股份有限公司 显示基板及显示装置
CN111415624B (zh) * 2020-04-29 2021-05-14 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置
CN112419960B (zh) * 2020-12-15 2022-09-23 云谷（固安）科技有限公司 移位寄存器、显示面板及显示装置
CN112687230B (zh) * 2021-01-29 2022-06-10 云谷（固安）科技有限公司 移位寄存器、栅极驱动电路和显示面板

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000187461A (ja) * 1998-12-22 2000-07-04 Sharp Corp シフトレジスタ回路および画像表示装置
CN101853705A (zh) * 2010-05-27 2010-10-06 友达光电股份有限公司 移位缓存器电路
CN111243650A (zh) * 2020-02-05 2020-06-05 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路
CN111445832A (zh) * 2020-05-07 2020-07-24 合肥京东方卓印科技有限公司 移位寄存单元、信号生成单元电路、驱动方法和显示装置
CN111477181A (zh) * 2020-05-22 2020-07-31 京东方科技集团股份有限公司 栅极驱动电路、显示基板、显示装置和栅极驱动方法
CN111816691A (zh) * 2020-08-28 2020-10-23 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN113241040A (zh) * 2021-07-09 2021-08-10 北京京东方技术开发有限公司 显示基板及显示装置
CN113920937A (zh) * 2021-07-09 2022-01-11 北京京东方技术开发有限公司 显示基板及显示装置

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