WO2023280314A1 - Substrat d'affichage et dispositif d'affichage - Google Patents

Substrat d'affichage et dispositif d'affichage Download PDF

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Publication number
WO2023280314A1
WO2023280314A1 PCT/CN2022/104688 CN2022104688W WO2023280314A1 WO 2023280314 A1 WO2023280314 A1 WO 2023280314A1 CN 2022104688 W CN2022104688 W CN 2022104688W WO 2023280314 A1 WO2023280314 A1 WO 2023280314A1
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WO
WIPO (PCT)
Prior art keywords
transistor
node
capacitor
pole
control
Prior art date
Application number
PCT/CN2022/104688
Other languages
English (en)
Chinese (zh)
Inventor
刘苗
郝学光
许静波
姚星
王景泉
吴新银
李新国
王志冲
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/275,012 priority Critical patent/US20240112623A1/en
Priority to EP22837059.9A priority patent/EP4280202A1/fr
Priority to KR1020237028712A priority patent/KR20240032702A/ko
Publication of WO2023280314A1 publication Critical patent/WO2023280314A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • This article relates to but not limited to the field of display technology, especially a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diode
  • TFT Thin Film Transistor
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • an embodiment of the present disclosure provides a display substrate, including: a base substrate and a scan driving control circuit disposed in a non-display area of the base substrate.
  • the scanning driving control circuit includes: an input circuit, an output control circuit and an output circuit.
  • the output control circuit is connected with the input circuit and the output circuit.
  • the output control circuit includes: a first node control capacitor and a second node control capacitor. The length L C1k of the first node control capacitor in the first direction, the length L C2k of the second node control capacitor in the first direction, and the length L Y of the scan driving control circuit in the first direction satisfy :
  • the first node control capacitor includes: a first capacitor and a third capacitor.
  • the lengths of the first capacitor, the third capacitor, the second node control capacitor and the scan drive control circuit in the first direction satisfy:
  • L C1 is the length of the first capacitor in the first direction
  • L C3 is the length of the third capacitor in the first direction
  • L C2k is the length of the second node control capacitor in the first direction
  • the length, LY is the length of the scan driving control circuit in the first direction.
  • the length of the first capacitor and the scan driving control circuit in the first direction satisfies:
  • the length of the second node control capacitor and the scan drive control circuit in the first direction satisfies:
  • the lengths of the third capacitor and the scan driving control circuit in the first direction satisfy:
  • the lengths of the first capacitor, the second node control capacitor, and the third capacitor in the first direction satisfy:
  • the third capacitor is connected to the first power line; the projection of the third capacitor and the first power line on the base substrate overlaps, and the overlapping area satisfies:
  • S C3 is the projected area of the third capacitor on the base substrate
  • S C3-1 is the overlapping area of the projection of the third capacitor and the first power line on the base substrate
  • the second node control capacitor includes a second capacitor
  • S C2 is a projected area of the second capacitor on the substrate.
  • the second node control capacitor overlaps with the projection of the first power line on the base substrate, and the overlapping area satisfies:
  • S C2k-1 is the overlapping area of the second node control capacitor and the projection of the first power line on the substrate
  • X2 is the length of the first power line in the first direction
  • L5 The length in the second direction of the overlapping region of one of the capacitances of the second node control capacitor and the projection of the first power line on the substrate; the second direction intersects the first direction .
  • the input circuit is connected to the second power line; the second node control capacitor overlaps with the projection of the second power line on the substrate, and the overlapping area satisfies:
  • S C2k-2 is the overlapping area of the second node control capacitor and the projection of the second power line on the substrate
  • X3 is the length of the second power line in the first direction
  • L6 The length in the second direction of the overlapping area of one of the capacitances of the second node control capacitor and the projection of the second power line on the substrate; the second direction intersects the first direction .
  • the projection of the first capacitor on the base substrate is located between the projections of the first power line and the second power line on the base substrate.
  • the distance L7 between the center of the first capacitor in the first direction and the side of the first power line away from the first capacitor in the first direction is greater than that of the first capacitor in the first direction
  • the distance L8 between the center of the second power line and the side of the second power line close to the first capacitor in the first direction and L7 ⁇ 2*L8.
  • the input circuit includes: a first transistor; the control pole of the first transistor is connected to the first clock signal line, the first pole is connected to the signal input terminal, and the second pole is connected to the second node connect.
  • the active layer of the first transistor is adjacent to the second power line.
  • the distance L2 between the side of the channel region of the active layer of the first transistor close to the second power supply line and the side of the second power supply line away from the first transistor satisfies: 0 ⁇ L2 ⁇ 4W PL2 ; wherein, W PL2 is the width of the second power line.
  • the input circuit includes: a third transistor; the control electrode of the third transistor is connected to the first clock signal line, the first electrode is connected to the second power line, the second electrode is connected to the third node connection.
  • the second power line is located on a side of the third transistor away from the first clock signal line or the second clock signal line.
  • the distance L3 between the side of the channel region of the active layer of the third transistor close to the second power line and the side of the second power line away from the third transistor satisfies: 0 ⁇ L3 ⁇ 4W PL2 ; wherein, W PL2 is the width of the second power line.
  • the input circuit is connected to the first clock signal line and the second power supply line, and the output control circuit is connected to the second clock signal line;
  • the input circuit includes: a second transistor; the The control pole of the second transistor is connected to the second node, the first pole is connected to the first clock signal line, and the second pole is connected to the third node.
  • the second power line is located on a side of the second transistor away from the first clock signal line.
  • the active layer of the second transistor is adjacent to the second power line; the side of the channel region of the active layer of the second transistor close to the second power line is away from the second power line
  • the distance L4 between the sides of the second transistor satisfies: 0 ⁇ L4 ⁇ 3W PL2 ; wherein, W PL2 is the width of the second power line.
  • the output control circuit includes: a first output control sub-circuit.
  • the first output control sub-circuit includes: a fourth transistor and a fifth transistor; the control pole of the fourth transistor is connected to the second node, the first pole of the fourth transistor is connected to the second pole of the fifth transistor, and the control pole of the fourth transistor is connected to the second pole of the fifth transistor.
  • the second pole of the four transistors is connected to the second clock signal line; the control pole of the fifth transistor is connected to the third node, and the first pole is connected to the first power line.
  • the fourth transistor and the fifth transistor are located on a side of the second power line away from the second clock signal line.
  • the included angle between the extending direction of the active layer of the fourth transistor and the extending direction of the active layer of the fifth transistor is greater than 85° and less than 95°.
  • the width W T4 of the channel region of the active layer of the fourth transistor and the width W T5 of the channel region of the active layer of the fifth transistor satisfy: 2W T4 ⁇ W T5 .
  • the angle between the extending direction of the active layer of the fourth transistor and the extending direction of the active layer of the first transistor of the input circuit is greater than 85° and less than 95°.
  • the output control circuit includes a second output control subcircuit, and the second output control subcircuit includes a seventh transistor.
  • the control electrode of the seventh transistor is connected to the second electrode of the first capacitor, and the first electrode of the seventh transistor is connected to the first node.
  • the seventh transistor is adjacent to the first capacitor, and the seventh transistor is located between the first capacitor and the first power line.
  • the second output control subcircuit further includes: a sixth transistor; the control electrode of the sixth transistor is connected to the first electrode of the first capacitor, and the second electrode of the sixth transistor is connected to the first electrode of the first capacitor.
  • the second poles of the seven transistors are connected, and the first pole of the sixth transistor is connected with the second signal terminal.
  • the extending direction of the active layer of the seventh transistor is approximately parallel to the extending direction of the active layer of the sixth transistor.
  • the output control circuit includes: a third output control subcircuit, the third output control subcircuit includes an eighth transistor and a third capacitor; the control electrode of the eighth transistor is connected to the second The nodes are connected, the first pole is connected to the first power line, the second pole is connected to the first node; the first pole of the third capacitor is connected to the first node, and the second pole is connected to the first power line.
  • the input circuit includes a first transistor. The first transistor, the eighth transistor and the third capacitor are sequentially arranged along the first direction, and the extending direction of the active layer of the first transistor is similar to the extending direction of the active layer of the eighth transistor parallel.
  • the distance L9 between the side of the active layer of the eighth transistor close to the third capacitor and the side of the third capacitor close to the eighth transistor satisfies: W CLK ⁇ L9 ⁇ W PL1 ; Wherein, W CLK is the width of the clock signal line, and W PL1 is the width of the first power line.
  • the input circuit is connected to the first clock signal line; the output control circuit is connected to the second clock signal line and the first power line; the output circuit is connected to the first power line and the third Power cord connection.
  • the first clock signal line, the second clock signal line, the initial signal line, the first power line and the third power line are sequentially arranged along the first direction.
  • the capacitance values of the first capacitor, the third capacitor and the second node control capacitor satisfy:
  • C 1 is the capacitance value of the first capacitor
  • C 3 is the capacitance value of the third capacitor
  • C 2k is the capacitance value of the second node control capacitor.
  • the first pole of the first capacitor is connected to the third node, and the second pole of the first capacitor is connected to the seventh transistor.
  • a first pole of the third capacitor is connected to the first node, and a second pole of the third capacitor is connected to the first power line.
  • the first pole of the second node control capacitor is connected to the second node. The sum of the capacitance values of the first capacitor and the third capacitor is smaller than the capacitance value of the second node control capacitor.
  • the second node control capacitor includes a second capacitor, a first pole of the second capacitor is connected to the second node, and a second pole of the second capacitor is connected to the signal output end.
  • the second node control capacitor further includes: a fourth capacitor, the first pole of the fourth capacitor is connected to the second node, and the second pole of the fourth capacitor is connected to the fourth transistor connected to the fifth transistor.
  • the first pole of the second capacitor of the current scan driving control circuit and the first pole of the fourth capacitor of the next scan driving control circuit have an integral structure.
  • the output circuit includes a tenth transistor; the second node control capacitor includes a second capacitor, and the first pole of the second capacitor is integrated with the control pole of the tenth transistor.
  • an embodiment of the present disclosure provides a display device, including the above-mentioned display substrate.
  • an embodiment of the present disclosure provides a display substrate including a scan driving control circuit.
  • the scan driving control circuit includes: an input circuit, an output control circuit and an output circuit.
  • the input circuit is connected to the signal input terminal, the first clock signal terminal, the first voltage terminal and the output control circuit, configured to transmit the signal at the signal input terminal to the output control circuit under the control of the first clock signal terminal, and The signal of the first clock signal terminal or the first voltage terminal is transmitted to the output control circuit.
  • the output control circuit is connected to the first signal terminal, the second signal terminal, the second clock signal terminal, the second voltage terminal, the first node, the second node and the input circuit, and is configured to store The signal of the first signal terminal, under the control of the input circuit and the second clock signal terminal, transmits the signal of the second signal terminal to the first node; or, under the control of the input circuit, stores the signal of the second clock signal terminal, and transmits the signal at the second Under the control of the node, the signal of the second voltage terminal is transmitted to the first node.
  • the output circuit is connected to the first voltage terminal, the second voltage terminal, the signal output terminal, the first node and the second node, and is configured to output the signal of the first voltage terminal to the signal output terminal under the control of the second node, Or, under the control of the first node, the signal of the second voltage terminal is output to the signal output terminal.
  • the input circuit includes: a first input subcircuit and a second input subcircuit;
  • the output control circuit includes: a first output control subcircuit, a second output control subcircuit and a third output A control subcircuit;
  • the output circuit includes: a first output subcircuit and a second output subcircuit.
  • the first input subcircuit is connected to the signal input terminal, the first clock signal terminal and the first output control subcircuit, and is configured to transmit the signal of the signal input terminal to the first output control subcircuit under the control of the first clock signal terminal circuit.
  • the second input subcircuit is connected to the first voltage terminal, the first clock signal terminal, the first input subcircuit and the second output control subcircuit, and is configured to be controlled by the first input subcircuit or the first clock signal terminal , transmitting the signal of the first clock signal terminal or the first voltage terminal to the second output control sub-circuit.
  • the first output control subcircuit is connected to the first signal terminal, the second clock signal terminal, the second node, the first input subcircuit and the second input subcircuit, and is configured to be connected to the first input subcircuit or the second input subcircuit Under the control of the sub-circuit, the signal of the first signal terminal or the second clock signal terminal is stored.
  • the second output control subcircuit is connected to the second signal terminal, the second clock signal terminal, the first node and the second input subcircuit, and is configured to, under the control of the second input subcircuit and the second clock signal terminal, send The first node transmits the signal of the second signal terminal.
  • the third output control subcircuit is connected to the second voltage terminal, the first node and the second node, and is configured to transmit the signal of the second voltage terminal to the first node under the control of the second node.
  • the first output sub-circuit is connected to the first voltage terminal, the signal output terminal and the second node, and is configured to output the signal of the first voltage terminal to the signal output terminal under the control of the second node.
  • the second output sub-circuit is connected to the second voltage terminal, the signal output terminal and the first node, and is configured to output the signal of the second voltage terminal to the signal output terminal under the control of the first node.
  • the first input sub-circuit includes: a first transistor; the control pole of the first transistor is connected to the first clock signal terminal, the first pole is connected to the signal input terminal, and the second pole is connected to the signal input terminal.
  • the second node is connected.
  • the second input sub-circuit includes: a second transistor and a third transistor; the control pole of the second transistor is connected to the second node, the first pole is connected to the first clock signal terminal, and the second pole is connected to the third node ;
  • the control pole of the third transistor is connected to the first clock signal terminal, the first pole is connected to the first voltage terminal, and the second pole is connected to the third node.
  • the first output control sub-circuit includes: a fourth transistor and a fifth transistor; the control pole of the fourth transistor is connected to the second node, and the first pole of the fourth transistor is connected to the second clock signal terminal, so The second pole of the fourth transistor is connected to the second pole of the fifth transistor; the control pole of the fifth transistor is connected to the third node, and the first pole of the fifth transistor is connected to the first signal terminal.
  • the first output sub-circuit includes: a tenth transistor; the control pole of the tenth transistor is connected to the second node, the first pole is connected to the first voltage terminal, and the second pole is connected to the signal output terminal.
  • the first input sub-circuit includes: a first transistor; the control pole of the first transistor is connected to the first clock signal terminal, the first pole is connected to the signal input terminal, and the second pole is connected to the signal input terminal.
  • the fourth node is connected.
  • the second input sub-circuit includes: a second transistor and a third transistor; the control pole of the second transistor is connected to the fourth node, the first pole is connected to the first clock signal terminal, and the second pole is connected to the third node ;
  • the control pole of the third transistor is connected to the first clock signal terminal, the first pole is connected to the first voltage terminal, and the second pole is connected to the third node.
  • the first output control sub-circuit includes: a fourth transistor, a fifth transistor and an eleventh transistor; the control pole of the fourth transistor is connected to the second node, and the first pole of the fourth transistor is connected to the second clock connected to the signal terminal, the second pole of the fourth transistor is connected to the second pole of the fifth transistor; the control pole of the fifth transistor is connected to the third node, and the first pole is connected to the first signal terminal; The control electrode of the eleventh transistor is connected to the first voltage terminal, the first electrode is connected to the fourth node, and the second electrode is connected to the second node.
  • the first output sub-circuit includes: a tenth transistor; the control pole of the tenth transistor is connected to the second node, the first pole is connected to the first voltage terminal, and the second pole is connected to the signal output terminal.
  • the second output control sub-circuit further includes: a fourth capacitor; a first electrode of the fourth capacitor is connected to control electrodes of the fourth transistor and the tenth transistor.
  • the second pole of the fourth capacitor is connected to the fifth transistor.
  • the first output control sub-circuit further includes: a second capacitor; a first pole of the second capacitor is connected to a second node.
  • the second pole of the second capacitor is connected to the signal output terminal.
  • the second input sub-circuit is connected to a third node.
  • the second output control sub-circuit includes: a sixth transistor, a seventh transistor and a first capacitor.
  • the control pole of the sixth transistor is connected to the third node, the first pole of the sixth transistor is connected to the second signal terminal, and the second pole of the sixth transistor is connected to the second pole of the seventh transistor;
  • the control electrode of the seventh transistor is connected to the second clock signal terminal, and the first electrode is connected to the first node.
  • the first pole of the first capacitor is connected to the control pole of the sixth transistor, and the second pole is connected to the seventh transistor.
  • the second input sub-circuit is connected to a fifth node.
  • the second output control sub-circuit includes: a first capacitor, a sixth transistor, a seventh transistor and a twelfth transistor.
  • the control pole of the sixth transistor is connected to the third node, the first pole of the sixth transistor is connected to the second signal terminal, and the second pole of the sixth transistor is connected to the second pole of the seventh transistor;
  • the control electrode of the seventh transistor is connected to the second clock signal terminal, and the first electrode is connected to the first node.
  • the control pole of the twelfth transistor is connected to the first voltage terminal, the first pole is connected to the fifth node, and the second pole is connected to the third node.
  • the first pole of the first capacitor is connected to the control pole of the sixth transistor, and the second pole is connected to the seventh transistor.
  • the third output control subcircuit includes: an eighth transistor and a third capacitor.
  • the control pole of the eighth transistor is connected to the second node, the first pole is connected to the second voltage terminal, and the second pole is connected to the first node.
  • the first pole of the third capacitor is connected to the first node, and the second pole is connected to the second voltage terminal.
  • the second output sub-circuit includes: a ninth transistor; the control pole of the ninth transistor is connected to the first node, the first pole is connected to the second voltage terminal, and the second pole is connected to the signal output terminal.
  • the first signal terminal is connected to the second voltage terminal or the first clock signal terminal.
  • the second signal terminal is connected to the first voltage terminal or the second clock signal terminal.
  • an embodiment of the present disclosure provides a method for driving a display substrate, which is applied to the above-mentioned display substrate.
  • the driving method includes: the input circuit transmits the signal at the signal input terminal to the The output control circuit transmits the signal of the first clock signal terminal or the first voltage terminal to the output control circuit; the output control circuit stores the signal of the first signal terminal under the control of the input circuit, and the input circuit and the second clock signal Under the control of the terminal, the signal of the second signal terminal is transmitted to the first node, and the output circuit outputs the signal of the second voltage terminal to the signal output terminal under the control of the first node; the output control circuit is under the control of the input circuit, storing the signal of the second clock signal terminal, and transmitting the signal of the second voltage terminal to the first node under the control of the second node; the output circuit outputs the signal of the first voltage terminal to the signal output terminal under the control of the second node .
  • FIG. 1 is a schematic structural diagram of a scan driving control circuit according to at least one embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a scan driving control circuit according to at least one embodiment of the present disclosure
  • FIG. 3 is an equivalent circuit diagram of the first input subcircuit, the second input subcircuit, the first output control subcircuit and the first output subcircuit of the scan drive control circuit in at least one embodiment of the present disclosure
  • FIG. 4 is another equivalent circuit diagram of the first input subcircuit, the second input subcircuit, the first output control subcircuit and the first output subcircuit of the scan drive control circuit in at least one embodiment of the present disclosure
  • 5 is an equivalent circuit diagram of a second output control sub-circuit of the scan drive control circuit in at least one embodiment of the present disclosure
  • FIG. 6 is another equivalent circuit diagram of the second output control sub-circuit of the scan drive control circuit in at least one embodiment of the present disclosure
  • FIG. 7 is an equivalent circuit diagram of a third output control subcircuit and a second output subcircuit of the scan drive control circuit in at least one embodiment of the present disclosure
  • FIG. 8 is an equivalent circuit diagram of a scan driving control circuit in at least one embodiment of the present disclosure.
  • FIG. 9 is a working sequence diagram of the scanning drive control circuit shown in FIG. 8.
  • FIG. 10 is another working sequence diagram of the scanning drive control circuit shown in FIG. 8;
  • FIG. 11 is another equivalent circuit diagram of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • FIG. 12 is another equivalent circuit diagram of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • FIG. 13 is a flowchart of a method for driving a display substrate according to at least one embodiment of the present disclosure
  • FIG. 14 is a schematic diagram of a cascaded scan driving control circuit according to at least one embodiment of the present disclosure.
  • FIG. 15 is a schematic top view of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • Fig. 16 is a schematic partial cross-sectional view along the direction of P-P' in Fig. 15;
  • FIG. 17 is a top view of a scan driving control circuit after forming a first semiconductor layer according to at least one embodiment of the present disclosure
  • FIG. 18 is a top view of a scan driving control circuit after forming a first conductive layer according to at least one embodiment of the present disclosure
  • FIG. 19 is a top view of a scan driving control circuit after forming a second conductive layer according to at least one embodiment of the present disclosure
  • FIG. 20 is a top view of a scan driving control circuit after forming a third insulating layer according to at least one embodiment of the present disclosure
  • FIG. 21 is a top view of a scan driving control circuit after forming a third conductive layer according to at least one embodiment of the present disclosure
  • 22 is a top view of two cascaded scan drive control circuits according to at least one embodiment of the present disclosure.
  • FIG. 23 is a top view of the first conductive layer in FIG. 22;
  • FIG. 24 is another top view of the scan driving control circuit according to at least one embodiment of the present disclosure.
  • FIG. 25 is another top view of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • FIG. 26 is a schematic structural diagram of a display device according to at least one embodiment of the present disclosure.
  • FIG. 27 is another schematic structural diagram of a display device according to at least one embodiment of the present disclosure.
  • Embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. Embodiments may be embodied in many different forms. Those skilled in the art can easily understand the fact that the manner and contents can be changed into one or more forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the contents described in the following embodiments. In the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily.
  • connection should be interpreted in a broad sense unless otherwise specified and limited. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • electrically connected includes the situation that the constituent elements are connected together through an element having some kind of electrical function.
  • the “element having some kind of electrical function” is not particularly limited as long as it can transmit electrical signals between connected components. Examples of “elements having some kind of electrical function” include not only electrodes and wirings but also switching elements such as transistors, resistors, inductors, capacitors, other elements having one or more functions, and the like.
  • a transistor refers to an element including at least three terminals of a gate electrode (gate), a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • one of the electrodes is called the first pole, and the other electrode is called the second pole.
  • the first pole can be the source electrode or the drain electrode
  • the second pole can be A drain electrode or a source electrode
  • a gate electrode of a transistor is called a gate electrode.
  • parallel means a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus may include a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state in which the angle formed by two straight lines is 80° to 100°, and therefore, an angle of 85° to 95° may be included.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • the display substrate may include: a display area and a non-display area.
  • the non-display area may be located on the periphery of the display area.
  • the display area at least includes: a plurality of pixel circuits arranged regularly, a plurality of gate lines extending along the first direction (for example, including: scanning lines, reset lines, light emission control lines), a plurality of data lines extending along the second direction and power cable.
  • the first direction and the second direction are located in the same plane, and the first direction intersects the second direction, for example, the first direction is perpendicular to the second direction.
  • the non-display area is provided with a plurality of scanning driving control circuits, and the scanning driving control circuits can be configured to provide gate driving signals to the pixel circuits in the display area.
  • FIG. 1 is a schematic structural diagram of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • the scan driving control circuit provided in this embodiment includes: an input circuit, an output control circuit and an output circuit.
  • the input circuit is connected with the signal input terminal IN, the first clock signal terminal CK, the first voltage terminal V1 and the output control circuit, and is configured to transmit the signal of the signal input terminal IN to the output under the control of the first clock signal terminal CK control circuit, and transmit the signal of the first clock signal terminal CK or the first voltage terminal V1 to the output control circuit.
  • the output control circuit is connected to the first signal terminal SIG1, the second signal terminal SIG2, the second clock signal terminal CB, the second voltage terminal V2, the first node N1, the second node N2 and the input circuit, configured to be connected to the input circuit Under the control, store the signal of the first signal terminal SIG1, and transmit the signal of the second signal terminal SIG2 to the first node N1 under the control of the input circuit and the second clock signal terminal CB; or, under the control of the input circuit, store The signal of the second clock signal terminal CB, and under the control of the second node N2, transmits the signal of the second voltage terminal V2 to the first node N1.
  • the output circuit is connected to the first voltage terminal V1, the second voltage terminal V2, the signal output terminal OUT, the first node N1 and the second node N2, and is configured to output the first voltage to the signal output terminal OUT under the control of the second node N2.
  • the signal at the first voltage terminal V1, or, under the control of the first node N1, outputs the signal at the second voltage terminal V2 to the signal output terminal OUT.
  • the input signals of the signal input terminal IN, the first clock signal terminal CK and the second clock signal terminal CB may be pulse signals.
  • the first voltage terminal V1 can continuously provide a low-level signal
  • the second voltage terminal V2 can continuously provide a high-level signal.
  • this embodiment does not limit it.
  • the first signal terminal SIG1 may be connected to the second voltage terminal V2 or the first clock signal terminal CK.
  • the second signal terminal SIG2 may be connected to the first voltage terminal V1 or the second clock signal terminal CB.
  • this embodiment does not limit it.
  • the output signal of the scan driving control circuit provided in this embodiment may be provided as a gate driving signal (for example, a scan signal or a reset signal, or a light emission control signal) to the pixel circuit in the display area.
  • the scan driving control circuit of this embodiment can be applied to a low temperature polycrystalline oxide (LTPO, Low Temperature Polycrystalline Oxide) display substrate, and can provide gate driving signals to N-type transistors in the pixel circuits in the display area.
  • LTPO Low Temperature Polycrystalline Oxide
  • the scan driving control circuit provided in this embodiment can improve the stability of the first node N1 and the second node N2 through the output control circuit, thereby improving the output stability of the output circuit.
  • FIG. 2 is a schematic structural diagram of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • the input circuit includes: a first input subcircuit and a second input subcircuit;
  • the output control circuit includes: a first output control subcircuit, a second output control subcircuit, and a second output control subcircuit.
  • the output circuit includes: a first output subcircuit and a second output subcircuit.
  • the first input subcircuit is connected to the signal input terminal IN, the first clock signal terminal CK and the first output control subcircuit, and is configured to transmit the signal of the signal input terminal IN to the first output control subcircuit under the control of the first clock signal terminal CK.
  • the second input subcircuit is connected to the first voltage terminal V1, the first clock signal terminal CK, the first input subcircuit and the second output control subcircuit, and is configured to be connected to the first input subcircuit or the first clock signal terminal CK. Under control, the signal of the first clock signal terminal CK or the first voltage terminal V1 is transmitted to the second output control sub-circuit.
  • the first output control subcircuit is connected to the first signal terminal SIG1, the second clock signal terminal CB, the second node N2, the first input subcircuit and the second input subcircuit, and is configured to be connected to the first input subcircuit or the second Under the control of the input sub-circuit, the signal of the first signal terminal SIG1 or the second clock signal terminal CB is stored.
  • the second output control subcircuit is connected to the second signal terminal SIG2, the second clock signal terminal CB, the first node N1 and the second input subcircuit, and is configured to control the second input subcircuit and the second clock signal terminal CB Next, the signal of the second signal terminal SIG2 is transmitted to the first node N1.
  • the third output control subcircuit is connected to the second voltage terminal V2, the first node N1 and the second node N2, and is configured to transmit the signal of the second voltage terminal V2 to the first node N1 under the control of the second node N2.
  • the first output sub-circuit is connected to the first voltage terminal V1, the signal output terminal OUT and the second node N2, configured to output the signal of the first voltage terminal V1 to the signal output terminal OUT under the control of the second node N2.
  • the second output sub-circuit is connected to the second voltage terminal V2, the signal output terminal OUT and the first node N1, and is configured to output the signal of the second voltage terminal V2 to the signal output terminal OUT under the control of the first node N1.
  • both the first input subcircuit and the first output control subcircuit are connected to the second node N2.
  • the second input subcircuit, the first output control subcircuit and the second output control subcircuit are all connected to the third node.
  • this embodiment does not limit it.
  • FIG. 3 is an equivalent circuit diagram of the input circuit, the first output control sub-circuit and the first output sub-circuit of the scan driving control circuit according to at least one embodiment of the present disclosure.
  • the first input sub-circuit of the scan driving control circuit provided in this exemplary embodiment includes: a first transistor T1 .
  • the control pole of the first transistor T1 is connected to the first clock signal terminal CK, the first pole is connected to the signal input terminal IN, and the second pole is connected to the second node N2.
  • the second input sub-circuit includes: a second transistor T2 and a third transistor T3.
  • the control electrode of the second transistor T2 is connected to the second node N2, the first electrode is connected to the first clock signal terminal CK, and the second electrode is connected to the third node N3.
  • the control pole of the third transistor T3 is connected to the first clock signal terminal CK, the first pole is connected to the first voltage terminal V1, and the second pole is connected to the third node N3.
  • the first output sub-circuit includes: a tenth transistor T10.
  • the control pole of the tenth transistor T10 is connected to the second node N2, the first pole is connected to the first voltage terminal V1, and the second pole is connected to the signal output terminal OUT.
  • the first output control sub-circuit includes: a fourth transistor T4, a fifth transistor T5, a second capacitor C2 and a fourth capacitor C4.
  • the control electrode of the fourth transistor T4 is connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the second clock signal terminal CB, and the second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5.
  • the control electrode of the fifth transistor T5 is connected to the third node N3, and the first electrode of the fifth transistor T5 is connected to the first signal terminal SIG1.
  • a first pole of the second capacitor C2 is connected to the second node N2, and a second pole of the second capacitor C2 is connected to the signal output terminal OUT.
  • the first electrode of the fourth capacitor C4 is connected to the control electrode of the fourth transistor T4 and the control electrode of the tenth transistor T10 (that is, connected to the second node N2), and the second electrode of the fourth capacitor C4 is connected to the first electrode of the fifth transistor T5.
  • the diode is connected to the second pole of the fourth transistor T4.
  • the potential of the second node N2 can be kept stable when the tenth transistor T10 is turned on, so that the first output sub-circuit can provide a stable output .
  • FIG. 3 shows an exemplary structure of the input circuit, the first output control sub-circuit and the first output sub-circuit.
  • the implementation manners of the input circuit, the first output control subcircuit and the first output subcircuit are not limited thereto, as long as their functions can be realized.
  • the first input sub-circuit of the scan driving control circuit includes: a first transistor T1 .
  • the control pole of the first transistor T1 is connected to the first clock signal terminal CK, the first pole is connected to the signal input terminal IN, and the second pole is connected to the fourth node N4.
  • the second input sub-circuit includes: a second transistor T2 and a third transistor T3.
  • the control electrode of the second transistor T2 is connected to the fourth node N4, the first electrode is connected to the first clock signal terminal CK, and the second electrode is connected to the third node N3.
  • the control pole of the third transistor T3 is connected to the first clock signal terminal CK, the first pole is connected to the first voltage terminal V1, and the second pole is connected to the third node N3.
  • the first output sub-circuit includes: a tenth transistor T10.
  • the control pole of the tenth transistor T10 is connected to the second node N2, the first pole is connected to the first voltage terminal V1, and the second pole is connected to the signal output terminal OUT.
  • the first output control subcircuit includes: a fourth transistor T4 , a fifth transistor T5 , an eleventh transistor T11 , a second capacitor C2 and a fourth capacitor C4 .
  • the control electrode of the fourth transistor T4 is connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the second clock signal terminal CB, and the second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5.
  • the control electrode of the fifth transistor T5 is connected to the third node N3, and the first electrode is connected to the first signal terminal SIG1.
  • the control electrode of the eleventh transistor T11 is connected to the first voltage terminal V1, the first electrode is connected to the fourth node N4, and the second electrode is connected to the second node N2.
  • a first pole of the second capacitor C2 is connected to the second node N2, and a second pole of the second capacitor C2 is connected to the signal output terminal OUT.
  • the first electrode of the fourth capacitor C4 is connected to the control electrode of the fourth transistor T4 and the control electrode of the tenth transistor T10 (that is, connected to the second node N2), and the second electrode of the fourth capacitor C4 is connected to the first electrode of the fourth transistor T4.
  • the diode is connected to the second pole of the fifth transistor T5.
  • the potential of the second node N2 can be kept stable when the tenth transistor T10 is turned on, so that the first output sub-circuit provides stable output.
  • the eleventh transistor T11 By setting the eleventh transistor T11, the influence of the second node N2 on the fourth node N4 can be isolated.
  • FIG. 4 shows an exemplary structure of the input circuit, the first output control sub-circuit and the first output sub-circuit.
  • the implementation manners of the input circuit, the first output control subcircuit and the first output subcircuit are not limited thereto, as long as their functions can be realized.
  • FIG. 5 is an equivalent circuit diagram of a second output control subcircuit of the scan driving control circuit according to at least one embodiment of the present disclosure.
  • the second output control subcircuit of the scan driving control circuit provided in this exemplary embodiment includes: a sixth transistor T6 , a seventh transistor T7 and a first capacitor C1 .
  • the control electrode of the sixth transistor T6 is connected to the third node N3, the first electrode of the sixth transistor T6 is connected to the second signal terminal SIG2, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7.
  • the control electrode of the seventh transistor T7 is connected to the second clock signal terminal CB, and the first electrode is connected to the first node N1.
  • the first electrode of the first capacitor C1 is connected to the control electrode of the sixth transistor T6, and the second electrode is connected to the control electrode of the seventh transistor T7.
  • the second signal terminal SIG2 may provide a low-level signal, so that the potential of the first node N1 remains stable when the transistor of the second output sub-circuit is turned on, so that the second output sub-circuit provides a stable output.
  • FIG. 5 an exemplary structure of the second output control sub-circuit is shown in FIG. 5 .
  • the implementation of the second output control subcircuit is not limited thereto, as long as its function can be realized.
  • FIG. 6 is another equivalent circuit diagram of the second output control subcircuit of the scan driving control circuit according to at least one embodiment of the present disclosure.
  • the second output control subcircuit of the scan driving control circuit provided in this exemplary embodiment includes: a sixth transistor T6 , a seventh transistor T7 , a twelfth transistor T12 and a first capacitor C1 .
  • the control electrode of the sixth transistor T6 is connected to the third node N3, the first electrode of the sixth transistor T6 is connected to the second signal terminal SIG2, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7.
  • the control electrode of the seventh transistor T7 is connected to the second clock signal terminal CB, and the first electrode is connected to the first node N1.
  • the first electrode of the first capacitor C1 is connected to the control electrode of the sixth transistor T6, and the second electrode is connected to the control electrode of the seventh transistor T7.
  • the control electrode of the twelfth transistor T12 is connected to the first power supply terminal V1, the first electrode is connected to the fifth node N5, and the second electrode is connected to the third node N3.
  • the fifth node N5 is also connected to the first input subcircuit and the first output control subcircuit.
  • the second signal terminal SIG2 may provide a low-level signal, so that the potential of the first node N1 remains stable when the transistor of the second output sub-circuit is turned on, so that the second output sub-circuit provides a stable output.
  • the influence of the third node N3 on the fifth node N5 can be isolated.
  • FIG. 6 another exemplary structure of the second output control subcircuit is shown in FIG. 6 .
  • the implementation of the second output control subcircuit is not limited thereto, as long as its function can be realized.
  • the third output control subcircuit of the scan driving control circuit includes: an eighth transistor T8 and a third capacitor C3 .
  • the control electrode of the eighth transistor T8 is connected to the second node N2, the first electrode is connected to the second voltage terminal V2, and the second electrode is connected to the first node N1.
  • a first pole of the third capacitor C3 is connected to the first node N1, and a second pole is connected to the second voltage terminal V2.
  • the second output sub-circuit includes: a ninth transistor T9.
  • the control pole of the ninth transistor T9 is connected to the first node N1, the first pole is connected to the second voltage terminal V2, and the second pole is connected to the signal output terminal OUT.
  • FIG. 7 an exemplary structure of the third output control subcircuit and the second output subcircuit is shown in FIG. 7 .
  • the implementation manners of the third output control subcircuit and the second output subcircuit are not limited thereto, as long as their functions can be realized.
  • FIG. 8 is an equivalent circuit diagram of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • the scan drive control circuit provided by this exemplary embodiment includes: a first input subcircuit, a second input subcircuit, a first output control subcircuit, a second output control subcircuit, a third output control subcircuit circuit, a first output subcircuit and a second output subcircuit.
  • the first input subcircuit includes a first transistor T1.
  • the second input sub-circuit includes a second transistor T2 and a third transistor T3.
  • the first output control sub-circuit includes: a fourth transistor T4, a fifth transistor T5, a second capacitor C2 and a fourth capacitor C4.
  • the second output control sub-circuit includes: a sixth transistor T6, a seventh transistor T7 and a first capacitor C1.
  • the third output control sub-circuit includes: an eighth transistor T8 and a third capacitor C3.
  • the first output sub-circuit includes a tenth transistor T10.
  • the second output sub-circuit includes a ninth transistor T9.
  • the first signal terminal SIG1 is connected to the second voltage terminal V2
  • the second signal terminal SIG2 is connected to the first voltage terminal V1.
  • the control electrode of the first transistor T1 is connected to the first clock signal terminal CK, the first electrode is connected to the signal input terminal IN, and the second electrode is connected to the second node N2.
  • the control electrode of the second transistor T2 is connected to the second node N2, the first electrode is connected to the first clock signal terminal CK, and the second electrode is connected to the third node N3.
  • the control pole of the third transistor T3 is connected to the first clock signal terminal CK, the first pole is connected to the first voltage terminal V1, and the second pole is connected to the third node N3.
  • the control electrode of the fourth transistor T4 is connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the second clock signal terminal CB, and the second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5.
  • the control electrode of the fifth transistor T5 is connected to the third node N3, and the first electrode is connected to the second voltage terminal V2.
  • the control electrode of the sixth transistor T6 is connected to the third node N3, the first electrode of the sixth transistor T6 is connected to the first voltage terminal V1, and the second electrode of the sixth transistor T6 is connected to the first electrode of the seventh transistor T7.
  • the control electrode of the seventh transistor T7 is connected to the second clock signal terminal CB, and the second electrode is connected to the first node N1.
  • the control electrode of the eighth transistor T8 is connected to the second node N2, the first electrode is connected to the second voltage terminal V2, and the second electrode is connected to the first node N1.
  • the control pole of the ninth transistor T9 is connected to the first node N1, the first pole is connected to the second voltage terminal V2, and the second pole is connected to the signal output terminal OUT.
  • the control pole of the tenth transistor T10 is connected to the second node N2, the first pole is connected to the first voltage terminal V1, and the second pole is connected to the signal output terminal OUT.
  • a first electrode of the first capacitor C1 is connected to the third node N3, and a second electrode is connected to the control electrode of the seventh transistor T7.
  • the first electrode of the second capacitor C2 is connected to the second node N2, and the second electrode is connected to the signal output terminal OUT.
  • a first pole of the third capacitor C3 is connected to the first node N1, and a second pole is connected to the second voltage terminal V2.
  • the first pole of the fourth capacitor C4 is connected to the second node N2, and the second pole is connected to the second pole of the fifth transistor T5.
  • the first node N1, the second node N2, and the third node N3 are confluence points representing relevant electrical connections in the circuit diagram.
  • these nodes are nodes equivalent to the confluence of related electrical connections in the circuit diagram.
  • the first transistor T1 to the tenth transistor T10 in the scan driving control circuit may all be P-type thin film transistors, such as low temperature polysilicon (LTPS, Low Temperature Poly-silicon) thin film transistors.
  • LTPS low temperature polysilicon
  • the embodiment of the present disclosure may choose a thin film transistor with a bottom gate structure or a thin film transistor with a top gate structure, as long as the switching function can be realized. This embodiment does not limit it.
  • FIG. 9 is a working timing diagram of the scan driving control circuit shown in FIG. 8 .
  • the scan driving control circuit of this exemplary embodiment includes 10 transistor units (such as the first transistor T1 to the tenth transistor T10), 4 capacitor units (that is, the first capacitor C1 to the fourth Capacitor C4), 3 input terminals (i.e. signal input terminal IN, first clock signal terminal CK, second clock signal terminal CB), 1 output terminal (i.e.
  • first voltage terminal V1 continuously provides a low-level signal, for example, the voltage is VGL
  • second voltage terminal V2 continuously provides a high-level signal, for example, the voltage is VGH.
  • the working process of the scanning driving control circuit will be described below by taking the scanning signal or reset signal provided by the scanning driving control circuit of this embodiment to the N-type transistor of the pixel circuit as an example.
  • the working process of the scan driving control circuit provided by this exemplary embodiment includes the following stages.
  • a high-level signal is input to the first clock signal terminal CK
  • a low-level signal is input to the second clock signal terminal CB
  • a low-level signal is input to the signal input terminal IN.
  • the first clock signal terminal CK inputs a high-level signal, the first transistor T1 and the third transistor T3 are turned off, the second node N2 maintains the low potential of the previous stage, the second transistor T2, the fourth transistor T4, the eighth transistor T8 and The tenth transistor T10 is turned on.
  • the high-level signal input from the first clock signal terminal CK is transmitted to the third node N3 through the turned-on second transistor T2, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the low-level signal input by the second clock signal terminal CB is transmitted to the second pole of the fourth capacitor C4 through the turned-on fourth transistor T4.
  • the first pole of the fourth capacitor C4 (that is, the second node N2) maintains a lower potential.
  • the eighth transistor T8 is turned on, so that the potential of the first node N1 is a high potential (for example, VGH), and the ninth transistor T9 is turned off.
  • the tenth transistor T10 is turned on, so that the signal output terminal OUT outputs the low-level signal provided by the first voltage terminal V1.
  • a low-level signal is input to the first clock signal terminal CK
  • a high-level signal is input to the second clock signal terminal CB
  • a high-level signal is input to the signal input terminal IN.
  • the first clock signal terminal CK inputs a low-level signal
  • the first transistor T1 and the third transistor T3 are turned on
  • the turned-on first transistor T1 transmits the high-level signal provided by the signal input terminal IN to the second node N2, so that The potential of the second node N2 is pulled up to VGH.
  • the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off.
  • the turned-on third transistor T3 transmits the low-level signal input from the first voltage terminal V1 to the third node N3, and the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the high-level signal provided by the second voltage terminal V2 is transmitted to the second pole of the fourth capacitor C4 through the turned-on fifth transistor T5.
  • the first pole of the fourth capacitor (ie The second node N2) maintains a stable high potential.
  • the second clock signal terminal CB inputs a high-level signal, the seventh transistor T7 is turned off, the first node N1 maintains the high potential provided by the second voltage terminal V2 under the storage function of the third capacitor C3, and the ninth transistor T9 is turned off. Since both the ninth transistor T9 and the tenth transistor T10 are turned off, the signal output terminal OUT maintains the previous low level output.
  • a high-level signal is input to the first clock signal terminal CK
  • a low-level signal is input to the second clock signal terminal CB
  • a low-level signal is input to the signal input terminal IN.
  • the first clock signal terminal CK inputs a high level signal
  • the first transistor T1 and the third transistor T3 are turned off, and the second node N2 maintains the high potential of the previous stage.
  • the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off.
  • the second clock signal terminal CB inputs a low-level signal, and the potential of the first electrode of the first capacitor C1 (that is, the third node N3 ) jumps from the low potential VGL in the previous stage to a lower potential 2VGL-VGH.
  • the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the high-level signal provided by the second voltage terminal V2 is transmitted to the second electrode of the fourth capacitor C4 through the turned-on fifth transistor T5, so that the second node N2 maintains a stable high potential.
  • the second clock signal terminal CB inputs a low-level signal
  • the seventh transistor T7 is turned on
  • the low-level signal input from the first voltage terminal V1 is transmitted to the first node N1 through the turned-on sixth transistor T6 and seventh transistor T7
  • the ninth transistor T9 is turned on, and outputs the high-level signal provided by the second voltage terminal V2 to the signal output terminal OUT.
  • the first clock signal terminal CK inputs a low-level signal
  • the second clock signal terminal CB inputs a high-level signal
  • the signal input terminal IN inputs a low-level signal.
  • the first clock signal terminal CK inputs a low-level signal
  • the first transistor T1 and the third transistor T3 are turned on, and the turned-on first transistor T1 transmits the low-level signal input from the signal input terminal IN to the second node N2, so that The potential of the second node N2 is pulled down to VGL.
  • the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned on.
  • the turned-on eighth transistor T8 transmits the high-level signal provided by the second voltage terminal V2 to the first node N1, and the ninth transistor T9 is turned off.
  • the turned-on tenth transistor T10 transmits the low-level signal provided by the first voltage terminal V1 to the signal output terminal OUT.
  • the turned-on second transistor T2 transmits the low-level signal provided by the first clock signal terminal CK to the third node N3, and the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the second clock signal terminal CB inputs a high-level signal, and the seventh transistor T7 is turned off.
  • a high-level signal is input to the first clock signal terminal CK
  • a low-level signal is input to the second clock signal terminal CB
  • a low-level signal is input to the signal input terminal IN.
  • the first clock signal terminal CK inputs a high-level signal, and the first transistor T1 and the third transistor T3 are turned off.
  • the second node N2 maintains the low potential of the previous node, and the second transistor T2 , the fourth transistor T4 , the eighth transistor T8 and the tenth transistor T10 are turned on.
  • the turned-on fourth transistor T4 transmits the low-level signal input from the second clock signal terminal CB to the second pole of the fourth capacitor C4, so that the potential of the first pole of the fourth capacitor C4 (that is, the second node N2) changes. It is a lower potential than VGL.
  • the turned-on second transistor T2 transmits the high-level signal provided by the first clock signal terminal CK to the third node N3, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the turned-on eighth transistor T8 transmits the high-level signal provided by the second voltage terminal V2 to the first node N1, the potential of the first node N1 is VGH, and the ninth transistor T9 is turned off.
  • the tenth transistor T10 is turned on, and provides the low-level signal provided by the first voltage terminal V1 to the signal output terminal OUT.
  • the fourth stage t14 and the fifth stage t15 can be repeated until the signal input terminal IN inputs a high-level signal, and then restart from the second stage t12.
  • the signal output terminal OUT outputs a high-level signal, and in the remaining stages, the signal output terminal OUT outputs a low-level signal.
  • both the first clock signal input to the first clock signal terminal CK and the second clock signal input to the second clock signal terminal CB are pulse signals, and the pulse width of the first clock signal and the second clock signal
  • the pulse widths of the signals can be approximately the same.
  • the duty cycle of the first clock signal and the second clock signal may be greater than 1/2, for example, may be about 1/3.
  • the duty cycle refers to the proportion of the high-level duration in the entire pulse period within a pulse period (including the high-level duration and the low-level duration).
  • FIG. 10 is another working timing diagram of the scan driving control circuit shown in FIG. 8 .
  • the working process of the scan drive control circuit will be described by taking the scan drive control circuit of this embodiment to provide light emission control signals to the pixel circuits as an example.
  • the working process of the scan driving control circuit provided in this exemplary embodiment may include the following stages.
  • a high-level signal is input to the first clock signal terminal CK
  • a low-level signal is input to the second clock signal terminal CB
  • a low-level signal is input to the signal input terminal IN.
  • the first clock signal terminal CK inputs a high-level signal, the first transistor T1 and the third transistor T3 are turned off, the second node N2 maintains the low potential of the previous stage, the second transistor T2, the fourth transistor T4, the eighth transistor T8 and The tenth transistor T10 is turned on.
  • the high-level signal input from the first clock signal terminal CK is transmitted to the third node N3 through the turned-on second transistor T2, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the low-level signal input by the second clock signal terminal CB is transmitted to the second pole of the fourth capacitor C4 through the turned-on fourth transistor T4.
  • the first pole of the fourth capacitor C4 (that is, the second node N2) maintains a lower potential.
  • the eighth transistor T8 is turned on, so that the potential of the first node N1 is pulled up to VGH, and the ninth transistor T9 is turned off.
  • the tenth transistor T10 is turned on, so that the signal output terminal OUT outputs the low-level signal provided by the first voltage terminal V1.
  • a low-level signal is input to the first clock signal terminal CK
  • a high-level signal is input to the second clock signal terminal CB
  • a high-level signal is input to the signal input terminal IN.
  • the first clock signal terminal CK inputs a low-level signal, and the first transistor T1 and the third transistor T3 are turned on.
  • the turned-on first transistor T1 transmits the high-level signal provided by the signal input terminal IN to the second node N2, so that the potential of the second node N2 is pulled up to VGH.
  • the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off.
  • the turned-on third transistor T3 transmits the low-level signal input from the first voltage terminal V1 to the third node N3, and the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the high-level signal provided by the second voltage terminal V2 is transmitted to the second pole of the fourth capacitor C4 through the turned-on fifth transistor T5.
  • the first pole of the fourth capacitor (ie The second node N2) maintains a stable high level.
  • the second clock signal terminal CB inputs a high-level signal, the seventh transistor T7 is turned off, the first node N1 maintains the high potential VGH provided by the second voltage terminal V2 under the storage function of the third capacitor C3, and the ninth transistor T9 is turned off. Since both the ninth transistor T9 and the tenth transistor T10 are turned off, the signal output terminal OUT maintains the previous low level output.
  • the first clock signal terminal CK inputs a high-level signal
  • the second clock signal terminal CB inputs a low-level signal
  • the signal input terminal IN inputs a high-level signal.
  • the first clock signal terminal CK inputs a high level signal
  • the first transistor T1 and the third transistor T3 are turned off, and the second node N2 maintains the high potential of the previous stage.
  • the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off.
  • the second clock signal terminal CB inputs a low-level signal, and the potential of the first electrode of the first capacitor C1 (that is, the third node N3 ) jumps from the low potential VGL in the previous stage to a lower potential 2VGL-VGH.
  • the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the high-level signal provided by the second voltage terminal V2 is transmitted to the second electrode of the fourth capacitor C4 through the turned-on fifth transistor T5, so that the second node N2 maintains a stable high potential.
  • the second clock signal terminal CB inputs a low-level signal
  • the seventh transistor T7 is turned on
  • the low-level signal input from the first voltage terminal V1 is transmitted to the first node N1 through the turned-on sixth transistor T6 and seventh transistor T7
  • the ninth transistor T9 is turned on, and provides the high-level signal provided by the second voltage terminal V2 to the signal output terminal OUT.
  • the first clock signal terminal CK inputs a low-level signal
  • the second clock signal terminal CB inputs a high-level signal
  • the signal input terminal IN inputs a high-level signal.
  • the first clock signal terminal CK inputs a low-level signal, and the first transistor T1 and the third transistor T3 are turned on.
  • the turned-on first transistor T1 transmits the high-level signal input from the signal input terminal IN to the second node N2, and the potential of the second node N2 remains the high potential VGH of the previous stage.
  • the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off.
  • the turned-on third transistor T3 transmits the low-level signal provided by the first voltage terminal V1 to the third node N3, and the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the turned-on fifth transistor T5 transmits the high-level signal provided by the second voltage terminal V2 to the second pole of the fourth capacitor C4, and under the action of the jump of the fourth capacitor C4, the first pole of the fourth capacitor C4 ( That is, the second node N2) maintains a stable high potential.
  • the second clock signal terminal CB inputs a high-level signal
  • the seventh transistor T7 is turned off
  • the first node N1 is kept at the low potential of the previous stage under the storage effect of the third capacitor C3
  • the ninth transistor T9 is turned on
  • the signal output terminal OUT outputs a high-level signal provided by the second voltage terminal V2.
  • the first clock signal terminal CK inputs a high-level signal
  • the second clock signal terminal CB inputs a low-level signal
  • the signal input terminal IN inputs a low-level signal.
  • the first clock signal terminal CK inputs a high level signal
  • the first transistor T1 and the third transistor T3 are turned off, and the second node N2 maintains the high potential of the previous stage.
  • the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned off.
  • the second clock signal terminal CB inputs a low-level signal, and the potential of the second pole of the first capacitor C1 jumps from VGH in the previous stage to VGL. Due to the jump effect of the first capacitor C1, the first capacitor of the first capacitor C1
  • the potential of the pole (that is, the third node N3) jumps from VGL in the previous stage to a lower 2VGL-VGH, and the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the turned-on fifth transistor T5 transmits the high-level signal provided by the second voltage terminal V2 to the second pole of the fourth capacitor C4, so that the second node N2 maintains a stable high potential.
  • the second clock signal terminal CB inputs a low-level signal, and the seventh transistor T7 is turned on.
  • the turned-on sixth transistor T6 and seventh transistor T7 transmit the low-level signal provided by the first voltage terminal V1 to the first node N1, the ninth transistor T9 is turned on, and the signal output terminal OUT outputs the signal provided by the second voltage terminal V2. high level signal.
  • the first clock signal terminal CK inputs a low-level signal
  • the second clock signal terminal CB inputs a high-level signal
  • the signal input terminal IN inputs a low-level signal.
  • the first clock signal terminal CK inputs a low-level signal, and the first transistor T1 and the third transistor T3 are turned on.
  • the turned-on first transistor T1 transmits the low-level signal input from the signal input terminal IN to the second node N2, and the potential of the second node N2 is pulled down to VGL.
  • the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the tenth transistor T10 are turned on.
  • the turned-on eighth transistor T8 transmits the high-level signal provided by the second voltage terminal V2 to the first node N1, and the ninth transistor T9 is turned off.
  • the turned-on tenth transistor T10 transmits the low-level signal provided by the first voltage terminal V1 to the signal output terminal OUT.
  • the turned-on second transistor T2 transmits the low-level signal provided by the first clock signal terminal CK to the third node N3, and the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the second clock signal terminal CB inputs a high-level signal, and the seventh transistor T7 is turned off.
  • a high-level signal is input to the first clock signal terminal CK
  • a low-level signal is input to the second clock signal terminal CB
  • a low-level signal is input to the signal input terminal IN.
  • the first clock signal terminal CK inputs a high-level signal, and the first transistor T1 and the third transistor T3 are turned off.
  • the second node N2 maintains the low potential of the previous node, and the second transistor T2 , the fourth transistor T4 , the eighth transistor T8 and the tenth transistor T10 are turned on.
  • the turned-on fourth transistor T4 transmits the low-level signal input from the second clock signal terminal CB to the second pole of the fourth capacitor C4, so that the potential of the first pole of the fourth capacitor C4 (that is, the second node N2) changes. It is a lower potential than VGL.
  • the turned-on second transistor T2 transmits the high-level signal provided by the first clock signal terminal CK to the third node N3, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the turned-on eighth transistor T8 transmits the high-level signal provided by the second voltage terminal V2 to the first node N1, the potential of the first node N1 is VGH, and the ninth transistor T9 is turned off.
  • the tenth transistor T10 is turned on, and outputs the low-level signal provided by the first voltage terminal V1 to the signal output terminal OUT.
  • the sixth stage t26 and the seventh stage t27 can be repeated until the signal input terminal OUT inputs a high-level signal, and then restart from the second stage t22.
  • the signal output terminal OUT can output a high-level signal during the third stage t23 to the fifth stage t25, and the signal output terminal OUT can output a low-level signal in other stages.
  • the scanning drive control circuit provided in this exemplary embodiment can keep the potential of the second node N2 stable when the tenth transistor T10 is turned on through the first output control subcircuit, so as to improve the output stability of the tenth transistor T10, through the first output control subcircuit
  • the two-output control sub-circuit can keep the potential of the first node N1 stable when the ninth transistor T9 is turned on, so as to improve the output stability of the ninth transistor T9.
  • FIG. 11 is another equivalent circuit diagram of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • the scan drive control circuit provided by this exemplary embodiment includes: a first input subcircuit, a second input subcircuit, a first output control subcircuit, a second output control subcircuit, a third output control subcircuit circuit, a first output subcircuit and a second output subcircuit.
  • the first input subcircuit includes a first transistor T1.
  • the second input sub-circuit includes a second transistor T2 and a third transistor T3.
  • the first output control sub-circuit includes: a fourth transistor T4, a fifth transistor T5, an eleventh transistor T11, a second capacitor C2 and a fourth capacitor C4.
  • the second output control sub-circuit includes: a twelfth transistor T12, a sixth transistor T6, a seventh transistor T7 and a first capacitor C1.
  • the third output control sub-circuit includes: an eighth transistor T8 and a third capacitor C3.
  • the first output sub-circuit includes: a tenth transistor T10.
  • the second output sub-circuit includes a ninth transistor T9. In this exemplary embodiment, the first signal terminal is connected to the second voltage terminal V2, and the second signal terminal is connected to the first voltage terminal V1.
  • the control electrode of the first transistor T1 is connected to the first clock signal terminal CK, the first electrode is connected to the signal input terminal IN, and the second electrode is connected to the fourth node N4.
  • the control electrode of the second transistor T2 is connected to the fourth node N4, the first electrode is connected to the first clock signal terminal CK, and the second electrode is connected to the third node N3.
  • the control pole of the third transistor T3 is connected to the first clock signal terminal CK, the first pole is connected to the first voltage terminal V1, and the second pole is connected to the fifth node N5.
  • the control electrode of the fourth transistor T4 is connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the second clock signal terminal CB, and the second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5.
  • the control electrode of the fifth transistor T5 is connected to the fifth node N5, and the first electrode is connected to the second voltage terminal V2.
  • the control electrode of the sixth transistor T6 is connected to the third node N3, the first electrode of the sixth transistor T6 is connected to the first voltage terminal V1, and the second electrode of the sixth transistor T6 is connected to the first electrode of the seventh transistor T7.
  • the control electrode of the seventh transistor T7 is connected to the second clock signal terminal CB, and the second electrode is connected to the first node N1.
  • the control electrode of the eighth transistor T8 is connected to the second node N2, the first electrode is connected to the second voltage terminal V2, and the second electrode is connected to the first node N1.
  • the control pole of the ninth transistor T9 is connected to the first node N1, the first pole is connected to the second voltage terminal V2, and the second pole is connected to the signal output terminal OUT.
  • the control pole of the tenth transistor T10 is connected to the second node N2, the first pole is connected to the first voltage terminal V1, and the second pole is connected to the signal output terminal OUT.
  • the control electrode of the eleventh transistor T11 is connected to the first voltage terminal V1, the first electrode is connected to the fourth node N4, and the second electrode is connected to the second node N2.
  • the control electrode of the twelfth transistor T12 is connected to the first voltage terminal V1, the first electrode is connected to the fifth node N5, and the second electrode is connected to the third node N3.
  • a first electrode of the first capacitor C1 is connected to the third node N3, and a second electrode is connected to the control electrode of the seventh transistor T7.
  • the first electrode of the second capacitor C2 is connected to the second node N2, and the second electrode is connected to the signal output terminal OUT.
  • a first pole of the third capacitor C3 is connected to the first node N1, and a second pole is connected to the second voltage terminal V2.
  • the first pole of the fourth capacitor C4 is connected to the second node N2, and the second pole is connected to the second pole of the fifth transistor T5.
  • the first node N1, the second node N2, the third node N3, the fourth node N4, and the fifth node N5 represent confluence points of related electrical connections in the circuit diagram.
  • these nodes are nodes equivalent to the confluence of related electrical connections in the circuit diagram.
  • the first transistor T1 to the twelfth transistor T12 in the scan driving control circuit may all be P-type thin film transistors, such as low temperature polycrystalline silicon (LTPS, Low Temperature Poly-silicon) thin film transistors .
  • LTPS low temperature polycrystalline silicon
  • the embodiment of the present disclosure may choose a thin film transistor with a bottom gate structure or a thin film transistor with a top gate structure, as long as the switching function can be realized. This embodiment does not limit it.
  • the influence of the second node N2 on the fourth node N4 can be isolated through the eleventh transistor T11, and the third node N3 can be isolated from the fifth node N5 through the twelfth transistor T12. Impact.
  • FIG. 12 is another equivalent circuit diagram of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • the scan drive control circuit provided by this exemplary embodiment includes: a first input subcircuit, a second input subcircuit, a first output control subcircuit, a second output control subcircuit, a third output control subcircuit circuit, a first output subcircuit and a second output subcircuit.
  • the first input subcircuit includes a first transistor T1.
  • the second input sub-circuit includes a second transistor T2 and a third transistor T3.
  • the first output control sub-circuit includes: a fourth transistor T4, a fifth transistor T5, an eleventh transistor T11, a second capacitor C2 and a fourth capacitor C4.
  • the second output control sub-circuit includes: a twelfth transistor T12, a sixth transistor T6, a seventh transistor T7 and a first capacitor C1.
  • the third output control sub-circuit includes: an eighth transistor T8 and a third capacitor C3.
  • the first output sub-circuit includes: a tenth transistor T10.
  • the second output sub-circuit includes a ninth transistor T9.
  • the first signal terminal is connected to the first clock signal terminal CK
  • the second signal terminal is connected to the second clock signal terminal CB. That is, the second pole of the fifth transistor T5 is connected to the first clock signal terminal CK, and the first pole of the sixth transistor T6 is connected to the second clock signal terminal CB.
  • the first signal terminal SIG1 of the scan driving control circuit may be connected to the first clock signal terminal CK, and the second signal terminal SIG2 may be connected to the first voltage terminal V1 or the second clock signal terminal CB;
  • the first signal terminal SIG1 may be connected to the second voltage terminal V2, and the second signal terminal SIG2 may be connected to the first voltage terminal V1 or the second clock signal terminal CB.
  • this embodiment does not limit it.
  • FIG. 13 is a flowchart of a method for driving a display substrate according to an embodiment of the present disclosure. As shown in FIG. 13 , the method for driving a display substrate provided in this embodiment is applied to the display substrate provided in the foregoing embodiments.
  • the driving method provided in this embodiment may include the following steps.
  • Step S101 the input circuit transmits the signal of the signal input terminal to the output control circuit under the control of the first clock signal terminal, and transmits the signal of the first clock signal terminal or the first voltage terminal to the output control circuit;
  • Step S102 the output control circuit stores the signal of the first signal terminal under the control of the input circuit, and transmits the signal of the second signal terminal to the first node under the control of the input circuit and the second clock signal terminal, and the output circuit is at the first node Under control, output the signal of the second voltage terminal to the signal output terminal;
  • Step S103 the output control circuit stores the signal of the second clock signal terminal under the control of the input circuit, and transmits the signal of the second voltage terminal to the first node under the control of the second node, and the output circuit is under the control of the second node , to output the signal of the first voltage terminal to the signal output terminal.
  • FIG. 14 is a schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure.
  • the gate driving circuit provided by this exemplary embodiment includes a plurality of cascaded scan driving control circuits GOA.
  • the scanning driving control circuit can be implemented as described in the foregoing embodiments, and its implementation principles and types of effects are not repeated here.
  • the signal input terminal IN of the first-level scan drive control circuit is connected to the initial signal line STV, and the signal input terminal IN of the n+1-th scan drive control circuit is connected to the signal of the n-th scan drive control circuit.
  • the output terminal is connected, wherein, n is an integer.
  • the first clock signal terminals CK of the plurality of scan driving control circuits are connected to the first clock signal line CKL and configured to receive the first clock signal
  • the second clock signal terminal CB is connected to the second clock signal line CBL connection configured to receive a second clock signal.
  • the first voltage terminal V1 is connected to the power line continuously providing the low-level signal VGL
  • the second voltage terminal V2 is connected to the power line continuously providing the high-level signal VGH.
  • this embodiment does not limit it.
  • FIG. 15 is a top view of a scan driving control circuit according to at least one embodiment of the present disclosure.
  • Fig. 16 is a schematic partial cross-sectional view along the P-P' direction in Fig. 15 .
  • the equivalent circuit diagram of the scan driving control circuit shown in FIG. 15 may be shown in FIG. 8 .
  • the first signal terminal is connected to the second voltage terminal
  • the second signal terminal is connected to the first voltage terminal
  • the first clock signal terminal CK is connected to the first clock signal line CKL
  • the second clock signal terminal CB is connected to the second clock signal line CBL.
  • the second voltage terminal is connected to the first power line PL1 providing a high level signal.
  • the first voltage terminal connected to the first output sub-circuit is connected to the third power line PL3 providing a low level signal.
  • the first voltage end connected to the second input sub-circuit and the second output control sub-circuit is connected to the second power line PL2 providing a low level signal.
  • the first clock signal line CKL, the second clock signal line CBL, the initial signal line STV, the second power line PL2, the first The power line PL1 and the third power line PL3 are sequentially arranged along the first direction X.
  • the first clock signal line CKL, the second clock signal line CBL, the initial signal line STV, the second power line PL2 , the first power line PL1 and the third power line PL3 all extend along the second direction Y.
  • the first direction X crosses the second direction Y, for example, the first direction X is perpendicular to the second direction Y.
  • the signal output terminal OUT in a plane parallel to the display substrate, is located on the side of the tenth transistor T10 away from the ninth transistor T9 in the second direction Y.
  • the signal output terminal OUT may extend along the first direction X.
  • this embodiment does not limit it.
  • the second input sub-circuit (including the second transistor T2 and the third transistor T3 ) is located on the initial signal line in the first direction X between STV and the second power line PL2.
  • the first output sub-circuit (including the tenth transistor T10) and the second output sub-circuit (including the ninth transistor T9) are located between the first power line PL1 and the third power line PL3 in the first direction X.
  • the second transistor T2 and the third transistor T3 are adjacent in the second direction Y.
  • the ninth transistor T9 and the tenth transistor T10 are adjacent in the second direction Y.
  • the first transistor T1 , the fourth transistor T4 and the fifth transistor T5 are located on a side of the second power line PL2 away from the second clock signal line CBL.
  • the seventh transistor T7 is adjacent to the first capacitor C1, and the seventh transistor T7 is located between the first capacitor C1 and the first power line PL1.
  • the sixth transistor T6 is adjacent to the first power line PL1, and the sixth transistor T6 is located between the seventh transistor T7 and the first power line PL1.
  • the eighth transistor T8 is located between the first power line PL1 and the first transistor T1.
  • the first capacitor C1 is located between the first power line PL1 and the second power line PL2, and the orthographic projection of the first capacitor C1 on the base substrate is located at the projection of the first power line PL1 and the second power line PL2 on the base substrate Between, and the projection of the first capacitor C1 on the base substrate does not overlap with the projections of the first power line PL1 and the second power line PL2 on the base substrate.
  • "A and B are adjacent" means that there is no other transistor or capacitor between A and B.
  • the non-display area of the display substrate may include: a base substrate 30 , a first semiconductor layer sequentially disposed on the base substrate 30 , the first conductive layer, the second conductive layer and the third conductive layer.
  • the first insulating layer 31 is disposed between the first conductive layer and the first semiconductor layer.
  • the second insulating layer 32 is disposed between the first conductive layer and the second conductive layer.
  • the third insulating layer 33 is disposed between the second conductive layer and the third conductive layer.
  • the first insulating layer 31 to the third insulating layer 33 may all be inorganic insulating layers. However, this embodiment does not limit it.
  • FIG. 17 is a top view of the scan driving control circuit after forming the first semiconductor layer according to at least one embodiment of the present disclosure.
  • the first semiconductor layer in the non-display area at least includes: an active layer of a plurality of transistors of the scan driving control circuit.
  • the first semiconductor layer at least includes: the active layer 110 of the first transistor T1, the active layer 120 of the second transistor T2, the active layer 130 of the third transistor T3, the active layer 140 of the fourth transistor T4, the The active layer 150 of the fifth transistor T5, the active layer 160 of the sixth transistor T6, the active layer 170 of the seventh transistor T7, the active layer 180 of the eighth transistor T8, the active layer of the ninth transistor T9 and the tenth transistor Active layer of T10.
  • the active layer 130 of the third transistor T3, the active layer 110 of the first transistor T1, the active layer 150 of the fifth transistor T5, and the active layer 150 of the sixth transistor T6 may extend in the second direction Y.
  • the active layer 140 of the fourth transistor T4 may extend in the first direction X. Referring to FIG.
  • the included angle between the extending direction of the active layer 140 of the fourth transistor T4 and the extending direction of the active layer 110 of the first transistor T1 is greater than 85° and less than 95°.
  • the included angle between the extending direction of the active layer 140 of the fourth transistor T4 and the extending direction of the active layer 150 of the fifth transistor T5 is larger than 85° and smaller than 95°.
  • this embodiment does not limit it.
  • the active layer 130 of the third transistor T3 and the active layer 120 of the second transistor T2 are adjacent in the second direction Y.
  • the active layer 110 of the first transistor T1 is located between the active layer 130 of the third transistor T3 and the active layer 180 of the eighth transistor T8 in the first direction X.
  • the active layer 140 of the fourth transistor T4 is located between the active layer 110 of the first transistor T1 and the active layer 150 of the fifth transistor T5 in the second direction Y.
  • the active layer 160 of the sixth transistor T6 is located on a side of the active layer 170 of the seventh transistor T7 away from the active layer 150 of the fifth transistor T5 in the first direction X.
  • the active layer of the ninth transistor T9 and the active layer of the tenth transistor T10 are sequentially arranged in the second direction Y.
  • the active layer of the ninth transistor T9 is located on the side of the active layer 180 of the eighth transistor T8 away from the active layer 110 of the first transistor T1 in the first direction X, and the active layer of the tenth transistor T10 is in the first direction X.
  • X is located on a side where the active layer 160 of the sixth transistor T6 is away from the active layer 170 of the seventh transistor T7.
  • the active layer of the ninth transistor T9 includes the first subregion 190-1 and the second subregion 190-2; the active layer of the tenth transistor T10 includes the third subregion 200 -1 and the fourth division 200-2.
  • the first subregion 190-1 of the active layer of the ninth transistor T9 and the third subregion 200-1 of the active layer of the tenth transistor T10 may have an integrated structure, such as a rectangle.
  • the second subregion 190-2 of the active layer of the ninth transistor T9 and the fourth subregion 200-2 of the active layer of the tenth transistor T10 may have an integral structure, such as a rectangle.
  • this embodiment does not limit the number of divisions and the shape of at least one division of the active layer of the ninth transistor T9 and the tenth transistor T10 .
  • the orthographic projection of the active layer 120 of the second transistor T2 on the base substrate may be U-shaped.
  • the active layer 110 of the first transistor T1, the active layer 130 of the third transistor T3, the active layer 140 of the fourth transistor T4, the active layer 150 of the fifth transistor T5 and the active layer 160 of the sixth transistor T6 are in The orthographic projection on the substrate substrate can be dumbbell shaped.
  • the active layer 170 of the seventh transistor T7 and the active layer 180 of the eighth transistor T8 may have an integrated structure. However, this embodiment does not limit it.
  • the material of the first semiconductor layer may include polysilicon, for example.
  • the active layer may include at least one channel region and a plurality of doped regions.
  • the channel region may not be doped with impurities and has semiconductor characteristics.
  • a plurality of doped regions may be on both sides of the channel region, and be doped with impurities and thus have conductivity. Impurities can vary depending on the type of transistor.
  • the doped region of the active layer may be interpreted as a source electrode or a drain electrode of a transistor.
  • the source electrode of the first transistor T1 may correspond to the periphery of the channel region 110a of the active layer 110 and the first doped region 110b doped with impurities
  • the drain electrode of the first transistor T1 may correspond to the periphery of the active layer 110.
  • the periphery of the channel region 110a corresponds to the second doped region 110c doped with impurities.
  • the part of the active layer between the transistors can be interpreted as a wiring doped with impurities, which can be used to electrically connect the transistors.
  • the output capability of a transistor is related to the ratio of the width to the length of the channel region of the transistor, and the ratio of the width to the length of the channel region of a transistor with a strong output capability is large.
  • the width of the channel region 140a of the active layer 140 of the fourth transistor T4 (that is, the length of the channel region 140a along the second direction Y) is W T4
  • the width of the active layer 150 of the fifth transistor T5 is
  • the width of the channel region 150 a ie, the length of the channel region 150 a along the first direction X) is W T5 .
  • the width of the channel region 150a of the active layer 150 of the fifth transistor T5 and the width of the channel region 140a of the active layer 140 of the fourth transistor T4 satisfy: 2W T4 ⁇ W T5 .
  • the "width" of A indicates the characteristic dimension of A perpendicular to the extending direction.
  • FIG. 18 is a top view of the scan driving control circuit after forming the first conductive layer according to at least one embodiment of the present disclosure.
  • the first conductive layer in the non-display area at least includes: control electrodes of multiple transistors and first electrodes of multiple capacitors of the scan driving control circuit.
  • the first conductive layer may include: the control electrode 113 of the first transistor T1, the control electrode 123 of the second transistor T2, the control electrode 133 of the third transistor T3, the control electrode 143 of the fourth transistor T4, and the control electrode 143 of the fifth transistor T5.
  • the control electrode 133 of the third transistor T3 and the control electrode 113 of the first transistor T1 may have an integral structure.
  • the control electrode 123 of the second transistor T2, the control electrode 203 of the tenth transistor T10, and the first electrode C2-1 of the second capacitor C2 may have an integrated structure.
  • the control electrode 153 of the fifth transistor T5 , the control electrode 163 of the sixth transistor T6 and the first electrode C1 - 1 of the first capacitor C1 may have an integrated structure.
  • the control electrode 183 of the eighth transistor T8, the control electrode 143 of the fourth transistor T4, and the first electrode C4-1 of the fourth capacitor C4 may have an integrated structure.
  • the control electrodes 193a and 193b of the ninth transistor T9 and the first electrode C3-1 of the third capacitor C3 may be of an integral structure. However, this embodiment does not limit it.
  • the ninth transistor T9 may be a double-gate transistor to prevent and reduce leakage current.
  • this embodiment does not limit it.
  • FIG. 19 is a top view of the scan driving control circuit after forming the second conductive layer according to at least one embodiment of the present disclosure.
  • the second conductive layer in the non-display area at least includes: the second poles of multiple capacitors of the scan driving control circuit, a signal input terminal and a signal input terminal.
  • the second conductive layer may include: the second pole C1-2 of the first capacitor C1, the second pole C2-2 of the second capacitor C2, the second pole C3-2 of the third capacitor C3, and the second pole C3-2 of the fourth capacitor C4.
  • the second pole C2-2 of the second capacitor C2 and the signal output terminal OUT may be in an integral structure. However, this embodiment does not limit it.
  • the projection of the second pole C1 - 2 of the first capacitor C1 on the base substrate overlaps with the projection of the first pole C1 - 1 on the base substrate.
  • the projection of the second pole C2-2 of the second capacitor C2 on the substrate overlaps with the projection of the first pole C2-1 on the substrate.
  • the projection of the second pole C3 - 2 of the third capacitor C3 on the substrate overlaps with the projection of the first pole C3 - 1 on the substrate.
  • the projection of the second pole C4-2 of the fourth capacitor C4 on the substrate overlaps with the projection of the first pole C4-1 on the substrate.
  • FIG. 20 is a top view of a scan driving control circuit after forming a third insulating layer according to at least one embodiment of the present disclosure.
  • a plurality of via holes are formed on the third insulating layer 33 in the non-display area.
  • the plurality of vias may include: a plurality of first vias F1 to F25 , a plurality of second vias K1 to K10 , and a plurality of third vias D1 to D5 .
  • the third insulating layer 33, the second insulating layer 32 and the first insulating layer 31 in the plurality of first via holes F1 to F25 are etched away, exposing the surface of the first semiconductor layer.
  • the third insulating layer 33 and the second insulating layer 32 in the plurality of second via holes K1 to K10 are etched away, exposing the surface of the first conductive layer.
  • the third insulating layer 33 in the plurality of third via holes D1 to D5 is etched away, exposing the surface of the second conductive layer.
  • FIG. 21 is a top view of the scan driving control circuit after forming the third conductive layer according to at least one embodiment of the present disclosure.
  • the third conductive layer in the non-display area at least includes: first poles and second poles of a plurality of transistors of the scan driving control circuit, a plurality of clock signal lines and a plurality of power supply lines.
  • the third conductive layer may include: the first pole and the second pole of the first transistor T1 to the tenth transistor T10, the first clock signal line CKL, the second clock signal line CBL, the initial signal line STV, the first power supply line PL1 , the second power line PL2 , the third power line PL3 , the first connection electrode 211 and the second connection electrode 212 .
  • the first pole 131 of the third transistor T3, the first pole 161 of the sixth transistor T6 and the second power line PL2 may have an integrated structure.
  • the second pole 121 of the second transistor T2 and the second pole 132 of the third transistor T3 may have an integral structure.
  • the second pole 142 of the fourth transistor T4 and the second pole 152 of the fifth transistor T5 may have an integrated structure.
  • the first pole 151 of the fifth transistor T5 , the first pole 181 of the eighth transistor T8 , the first pole 191 of the ninth transistor T9 and the first power line PL1 may have an integrated structure.
  • the second pole 162 of the sixth transistor T6 and the second pole 172 of the seventh transistor T7 may have an integral structure.
  • the second pole 192 of the ninth transistor T9 and the second pole 202 of the tenth transistor T10 may have an integrated structure.
  • the first pole 201 of the tenth transistor T10 and the third power line PL3 may have an integral structure.
  • the first connection electrode 211 is connected to the first pole C2-1 of the second capacitor C2 through the second via hole K9, and connected to the fourth capacitor C4 through the second via hole K7.
  • the first pole C4-1 of the first transistor T1 is connected to the second doped region 110c of the active layer 110 of the first transistor T1 through the first via hole F6, and is also connected to the control electrode 143 of the fourth transistor T4 through the second via hole K6 connect.
  • the projection of the first connection electrode 211 on the base substrate is located between the projections of the first power line PL1 and the second power line PL2 on the base substrate.
  • the second connection electrode 212 is connected to the second electrode C1-2 of the first capacitor C1 through the third via hole D3, and is also connected to the control electrode 173 of the seventh transistor T7 through the second via hole K5.
  • the first power line PL1 is connected to the second pole C3 - 2 of the third capacitor C3 through a plurality of (for example, three) third via holes D4 arranged vertically.
  • this embodiment does not limit it.
  • the first transistor T1 includes: an active layer 110 , a control electrode 113 , a first electrode 111 and a second electrode 112 .
  • the active layer 110 of the first transistor T1 includes: a channel region 110a, a first doped region 110b and a second doped region 110c.
  • the active layer 110 of the first transistor T1 is adjacent to the second power line PL2.
  • the distance L2 between the channel region 110a of the active layer 110 of the first transistor T1 close to the side of the second power line PL2 and the side of the second power line PL2 away from the first transistor T1 satisfies: 0 ⁇ L2 ⁇ 4W PL2 ;
  • W PL2 is the width of the second power line PL2 (that is, the length X3 of the second power line PL2 along the first direction X).
  • the first electrode 111 of the first transistor T1 is connected to the first doped region 110b of the active layer 110 of the first transistor T1 through the first via hole F5, and is also connected to the signal input terminal IN through the third via hole D1.
  • the control electrode 113 of the first transistor T1 and the control electrode 133 of the third transistor T3 have an integrated structure, and the first clock signal line CKL is connected to the control electrode 113 of the first transistor T1 through two second via holes K1 arranged vertically. In order to realize that the control electrode 113 of the first transistor T1 receives the first clock signal.
  • arranged side by side may mean arranged in sequence along the first direction X
  • “arranged vertically” may mean arranged in sequence along the second direction Y.
  • the second transistor T2 includes: an active layer 120 , a control electrode 123 , a first electrode 121 and a second electrode 122 .
  • the active layer 120 of the second transistor T2 includes: a channel region 120a, a first doped region 120b and a second doped region 120c.
  • the control electrode 123 of the second transistor T2, the first electrode C2-1 of the second capacitor C2, and the control electrode 203 of the tenth transistor T10 are integrated.
  • the first electrode 121 of the second transistor T2 is connected to the first doped region 120b of the active layer 120 of the second transistor T2 through the first via hole F4, and is also connected to the control electrode 113 of the first transistor T1 through the second via hole K2.
  • the second pole 122 of the second transistor T2 is integrated with the second pole 132 of the third transistor T3.
  • the second electrode 122 of the second transistor T2 is connected to the second doped region 120c of the active layer 120 of the second transistor T2 through the first via hole F3, and is also connected to the control electrode 153 of the fifth transistor T5 through the second via hole K8. connect.
  • the second power line PL2 is located on a side of the second transistor T2 away from the first clock signal line CKL.
  • the active layer 120 of the second transistor T2 is adjacent to the second power line PL2.
  • the distance L4 between the channel region 120a of the active layer 120 of the second transistor T2 close to the second power line PL2 and the side of the second power line PL2 away from the second transistor T2 satisfies: 0 ⁇ L4 ⁇ 3W PL2 ;
  • W PL2 is the width of the second power line PL2.
  • the third transistor T3 includes: an active layer 130 , a control electrode 133 , a first electrode 131 and a second electrode 132 .
  • the active layer 130 of the third transistor T3 includes: a channel region 130a, a first doped region 130b and a second doped region 130c.
  • the first pole 131 of the third transistor T3 is integrated with the second power line PL2.
  • the first electrode 131 of the third transistor T3 is connected to the first doped region 130b of the active layer 130 of the third transistor T3 through the first via hole F1.
  • the second pole 132 of the third transistor T3 is connected to the second doped region 130c of the active layer 130 of the third transistor T3 through the first via hole F2.
  • the second power line PL2 is located on a side of the third transistor T3 away from the initial signal line STV.
  • the distance L3 between the channel region 130a of the active layer 130 of the third transistor T3 close to the side of the second power line PL2 and the side of the second power line PL2 away from the third transistor T3 satisfies: 0 ⁇ L3 ⁇ 4W PL2 ;
  • W PL2 is the width of the second power line PL2.
  • the fourth transistor T4 includes: an active layer 140 , a control electrode 143 , a first electrode 141 and a second electrode 142 .
  • the active layer 140 of the fourth transistor T4 includes: a channel region 140a, a first doped region 140b and a second doped region 140c.
  • the control electrode 143 of the fourth transistor T4 and the first electrode C4-1 of the fourth capacitor C4 are integrally formed.
  • the first electrode 141 of the fourth transistor T4 is connected to the first doped region 140b of the active layer 140 of the fourth transistor T4 through the first via hole F7, and is also connected to the control electrode 173 of the seventh transistor T7 through the second via hole K4. connect.
  • the second pole 142 of the fourth transistor T4 is integrated with the second pole 152 of the fifth transistor T5.
  • the second pole 142 of the fourth transistor T4 is connected to the second doped region 140c of the active layer 140 of the fourth transistor T4 through the first via hole F8, and is also connected to the second pole of the fourth capacitor C4 through the third via hole D2. C4-2 connection.
  • the fifth transistor T5 includes: an active layer 150 , a control electrode 153 , a first electrode 151 and a second electrode 152 .
  • the active layer 150 of the fifth transistor T5 includes: a channel region 150a, a first doped region 150b and a second doped region 150c.
  • the control electrode 153 of the fifth transistor T5 and the control electrode 163 of the sixth transistor T6 are integrated.
  • the first pole 151 of the fifth transistor T5 is integrated with the first power line PL1.
  • the first pole 151 of the fifth transistor T5 is connected to the first doped region 150b of the active layer 150 of the fifth transistor T5 through the first via hole F10.
  • the second pole 152 of the fifth transistor T5 is connected to the second doped region 150c of the active layer 150 of the fifth transistor T5 through the first via hole F9.
  • the sixth transistor T6 includes: an active layer 160 , a control electrode 163 , a first electrode 161 and a second electrode 162 .
  • the active layer 160 of the sixth transistor T6 includes: a channel region 160a, a first doped region 160b and a second doped region 160c.
  • the first pole 161 of the sixth transistor T6 is integrated with the second power line PL2.
  • the first pole 161 of the sixth transistor T6 is connected to the first doped region 160b of the active layer 160 of the sixth transistor T6 through the first via hole F14.
  • the second pole 162 of the sixth transistor T6 and the second pole 172 of the seventh transistor T7 are integrally formed.
  • the second pole 162 of the sixth transistor T6 is connected to the second doped region 160c of the active layer 160 of the sixth transistor T6 through the first via hole F15.
  • the seventh transistor T7 includes: an active layer 170 , a control electrode 173 , a first electrode 171 and a second electrode 172 .
  • the active layer 170 of the seventh transistor T7 and the active layer 180 of the eighth transistor T8 are integrally structured.
  • the active layer 170 of the seventh transistor T7 includes: a channel region 170a, a first doped region 170b and a second doped region 170c.
  • the first doped region 170b of the active layer 170 of the seventh transistor T7 is connected to the second doped region 180c of the active layer 180 of the eighth transistor T8.
  • the first electrode 171 of the seventh transistor T7 is connected to the first doped region 170b of the active layer 170 of the seventh transistor T7 through the first via hole F12, and is also connected to the first electrode of the third capacitor C3 through the second via hole K10. C3-1 connection.
  • the second pole 172 of the seventh transistor T7 is connected to the second doped region 170c of the active layer 170 of the seventh transistor T7 through the first via hole F13.
  • the second clock signal line CBL is connected to the control electrode 173 of the seventh transistor T7 through two second via holes K3 arranged vertically.
  • the eighth transistor T8 includes: an active layer 180 , a control electrode 183 and a first electrode 181 .
  • the active layer 180 of the eighth transistor T8 includes: a channel region 180a, a first doped region 180b and a second doped region 180c.
  • the control electrode 183 of the eighth transistor T8 and the first electrode C4-1 of the fourth capacitor C4 are integrated.
  • the first pole 181 of the eighth transistor T8 is integrated with the first power line PL1.
  • the first electrode 181 of the eighth transistor T8 is connected to the first doped region 180b of the active layer 180 of the eighth transistor T8 through the first via hole F11.
  • the ninth transistor T9 includes: an active layer, control electrodes 193 a and 193 b , a first electrode 191 and a second electrode 192 .
  • the active layer of the ninth transistor T9 includes a first partition 190-1 and a second partition 190-2.
  • the first subregion 190-1 of the ninth transistor T9 includes: channel regions 190-1a1 and 190-1a2, a first doped region 190-1b, a second doped region 190-1c, and a third doped region 190-1d .
  • the second subregion 190-2 of the ninth transistor T9 includes: channel regions 190-2a1 and 190-2a2, a first doped region 190-2b, a second doped region 190-2c, and a third doped region 190-2d .
  • the first pole 191 of the ninth transistor T9 is integrated with the first power line PL1.
  • the first electrode 191 of the ninth transistor T9 is connected to the first doped region 190-1b of the first subregion 190-1 of the ninth transistor T9 through a plurality of (for example, three) first vias F18 arranged side by side.
  • the second pole 192 of the ninth transistor T9 and the second pole 202 of the tenth transistor T10 are integrally formed.
  • the second pole 192 of the ninth transistor T9 is connected to the second doped region 190-1c of the first subregion 190-1 of the ninth transistor T9 through a plurality of (for example, three) first vias F16 arranged side by side.
  • the second doped region 190-2c of the second subregion 190-2 of the ninth transistor T9 is connected through a plurality of (for example, three) first via holes F17 arranged side by side, and also through a plurality of (for example, three) Three) first vias F20 are connected to the third doped region 190-1d of the first subregion 190-1 of the ninth transistor T9, and are connected to The third doped region 190-2d of the second subregion 190-2 of the ninth transistor T9 is connected.
  • the tenth transistor T10 includes: an active layer, a control electrode 203 , a first electrode 201 and a second electrode 202 .
  • the active layer of the tenth transistor T10 includes: a third partition 200-1 and a fourth partition 200-2.
  • the third subregion 200-1 of the tenth transistor T10 includes: channel regions 200-1a1 and 200-1a2, a first doped region 200-1b, a second doped region 200-1c, and a third doped region 200-1d .
  • the fourth subregion 200-2 of the tenth transistor T10 includes: a channel region 200-2a, a first doped region 200-2b and a second doped region 200-2c.
  • the third subregion 200-1 of the tenth transistor T10 and the first subregion 190-1 of the ninth transistor T9 have an integral structure, and the second doped region 200-1c of the third subregion 200-1 and the first subregion 190-1 of the ninth transistor The third doped region 190-1d of 190-1 is connected.
  • the fourth subregion 200-2 of the tenth transistor T10 and the second subregion 190-2 of the ninth transistor T9 have an integrated structure, and the second doped region 200-2c of the fourth subregion 200-2 and the second doped region 200-2c of the ninth transistor T9
  • the third doped region 190-2d of the partition 190-2 is connected.
  • the first pole 201 of the tenth transistor T10 is integrated with the third power line PL3.
  • the first electrode 201 of the tenth transistor T10 is connected to the first doped region 200-1b of the third subregion 200-1 of the tenth transistor T10 through a plurality of (for example, three) first vias F22 arranged side by side, and It is connected to the first doped region 200-2b of the fourth subregion 200-2 of the tenth transistor T10 through a plurality of (for example, three) first vias F23 arranged side by side.
  • the second pole 202 of the tenth transistor T10 is connected to the third doped region 200-1d of the third subregion 200-1 of the tenth transistor T10 through a plurality of (for example, three) first vias F24 arranged side by side.
  • the second pole 202 of the tenth transistor T10 is also connected to the signal output terminal OUT through two third via holes D5 arranged side by side.
  • the output control circuit of the scan driving control circuit includes: a first node control capacitor and a second node control capacitor.
  • the first node control capacitor may be configured to control the potential of the first node N1
  • the second node control capacitor may be configured to control the potential of the second node N2.
  • the first node control capacitor includes a first capacitor C1 and a third capacitor C3.
  • the second node control capacitor includes a second capacitor C2 and a fourth capacitor C4.
  • the potential of the second node N2 can be made more stable, so that the tenth transistor T10 can realize a stable output.
  • the general function of the capacitor is to stabilize the potential of the node, and the area of the capacitor is related to the range in which the potential of the node controlled by the capacitor needs to be maintained.
  • capacitors need to be properly arranged in a smaller space to realize their functions.
  • the ratio of the width of the capacitor for example, the length along the first direction
  • the width of the scan drive control circuit it is possible to ensure or even optimize the scan rate under the premise of efficient use of space. performance of the drive control circuit.
  • the lengths of the first node control capacitor, the second node control capacitor and the scan driving control circuit in the first direction satisfy:
  • L C1k is the length of the first node control capacitor in the first direction
  • L C2k is the length of the second node control capacitor in the first direction
  • LY is the length of the scan driving control circuit in the first direction.
  • the length LY of the scan driving control circuit in the first direction is the distance between the side of the clock signal line or the start signal line away from the display area and the side of the power line close to the display area.
  • the wiring on the side away from the display area shall prevail.
  • the side close to the display area has a power supply line and other lines (for example, the line extending from the signal output end to the display area)
  • the line close to the display area shall prevail.
  • the length LY of the scan driving control circuit in the first direction X is the side of the first clock signal line CKL away from the display area and the side of the third power line PL3 close to the display area. the distance between.
  • the length L C1k of the first node control capacitor in the first direction may be the shorter of the length of the first capacitor C1 in the first direction and the length of the third capacitor C3 in the first direction. the big one.
  • the length L C2k of the second node control capacitor in the first direction may be the larger of the length of the second capacitor C2 in the first direction and the length of the fourth capacitor C4 in the first direction.
  • the length of the capacitor in the first direction may be the maximum value of the length of the capacitor in the first direction.
  • the lengths of the first capacitor, the third capacitor, the second node control capacitor and the scan driving control circuit in the first direction satisfy:
  • L C1 is the length of the first capacitor in the first direction
  • L C3 is the length of the third capacitor in the first direction
  • L C2k is the length of the second node control capacitor in the first direction
  • LY is the scan The length of the drive control circuit in the first direction.
  • the length of the first capacitor and the scan driving control circuit in the first direction satisfies:
  • the length of the second node control capacitor and the scan drive control circuit in the first direction satisfies:
  • the length of the third capacitor and the scan drive control circuit in the first direction satisfies:
  • the capacitor may overlap with the projection of the power line or the clock signal line on the base substrate.
  • the projection of the third capacitor and the first power line on the base substrate overlaps, and the overlapping area satisfies:
  • S C3 is the projected area of the third capacitor on the base substrate
  • S C3-1 is the overlapping area of the projection of the third capacitor and the first power line on the base substrate
  • S C2 is the projection area of the second capacitor on the substrate. The projected area on the base substrate.
  • the second node control capacitor overlaps with the projection of the first power line on the base substrate, and the overlapping area satisfies:
  • S C2k-1 is the overlapping area of the second node control capacitor and the projection of the first power line on the substrate
  • X2 is the length of the first power line in the first direction
  • L5 is the second node control capacitor The length in the second direction of the overlapping area of one of the capacitors and the projection of the first power line on the base substrate.
  • the projected area of the second node control capacitor may be the sum of the projected area of the second capacitor and the projected area of the fourth capacitor.
  • L5' is the length in the second direction Y of the overlapping area of the projection of the second capacitor C2 and the first power line PL1 on the base substrate.
  • L5" is the length in the second direction Y of the overlapping area of the projection of the fourth capacitor C4 and the first power line PL1 on the substrate substrate.
  • One of the capacitors of the second node control capacitor and the first power line are on the substrate
  • the length L5 of the projected overlapping area on the substrate in the second direction may be L5' or L5".
  • the second node control capacitor overlaps with the projection of the second power line on the base substrate, and the overlapping area satisfies:
  • S C2k-2 is the overlapping area of the second node control capacitor and the projection of the second power line on the substrate
  • X3 is the length of the second power line in the first direction
  • L6 is the second node control capacitor The length in the second direction of the overlapping area of one of the capacitors and the projection of the second power line on the base substrate.
  • L6' is the length in the second direction Y of the overlapping area of the projection of the second capacitor C2 and the second power line PL2 on the base substrate.
  • L6" is the length in the second direction Y of the overlapping area of the fourth capacitor C4 and the projection of the second power line PL2 on the substrate.
  • One of the capacitors of the second node control capacitor and the second power line are on the substrate
  • the length L6 of the projected overlapping area on the substrate in the second direction may be L6' or L6".
  • the distance between the center of the first capacitor C1 in the first direction X and the side of the first power line PL1 away from the first capacitor C1 in the first direction X L7 is greater than the distance L8 between the center of the first capacitor C1 in the first direction X and the side of the second power line PL2 close to the first capacitor C1 in the first direction X, and L7 ⁇ 2*L8.
  • the distance L9 between the side of the active layer 180 of the eighth transistor T8 close to the third capacitor C3 and the side of the third capacitor C3 close to the eighth transistor T8 satisfies : W CLK ⁇ L9 ⁇ W PL1 ; wherein, W CLK is the width of the clock signal line, and W PL1 is the width of the first power line.
  • W CLK may be the width of the first clock signal line CKL or may be the width of the second clock signal line CBL.
  • the width W PL1 of the first power line PL1 is the length X2 of the first power line PL1 in the first direction X.
  • the side of the capacitor is the outermost side.
  • L9 may be the distance between the side of the active layer 180 of the eighth transistor T8 close to the third capacitor C3 and the side of the third capacitor C3 closest to the eighth transistor T8.
  • the capacitance values of the first capacitor, the third capacitor and the second node control capacitor satisfy:
  • C 1 is the capacitance value of the first capacitor
  • C 3 is the capacitance value of the third capacitor
  • C 2k is the capacitance value of the second node control capacitor.
  • the capacitance of the second node control capacitor may be the sum of the capacitances of the second capacitor C2 and the fourth capacitor C4.
  • FIG. 22 is a top view of a cascaded scan driving control circuit according to at least one embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram of the first conductive layer shown in FIG. 22 .
  • the first pole C2-1 of the second capacitor C2 of the nth-level scan drive control circuit and the fourth capacitor of the n+1-th scan drive control circuit may have an integral structure.
  • the stability of the second node can be improved while simplifying the process.
  • the signal output terminal OUT of the nth level scan driving control circuit and the input terminal IN of the n+1th level scan driving control circuit may have an integrated structure.
  • FIG. 24 is another top view of the scan driving control circuit according to at least one embodiment of the present disclosure.
  • the signal output terminal OUT is located on a side of the ninth transistor T9 and the tenth transistor T10 away from the first power line PL1 .
  • the signal output terminal OUT and the second pole of the second capacitor C2 may have an integral structure.
  • the signal output terminal OUT may have three protrusions protruding toward a side close to the first power line PL1 along the first direction X.
  • the second pole 192 of the ninth transistor T9 can be connected to the first protruding part of the signal output terminal OUT through the third via hole D6, and can also be connected to the second protruding part of the signal output terminal OUT through the third via hole D7.
  • the second pole 202 of the tenth transistor T10 can be connected to the third protrusion of the signal output terminal OUT through the third via hole D8.
  • this embodiment does not limit it.
  • the length LY of the scan driving control circuit in the first direction X may be the extension distance of the first clock signal line CKL away from the side of the display area and the signal output terminal OUT. The distance between the sides of the line close to the display area.
  • FIG. 25 is another top view of the scan driving control circuit according to at least one embodiment of the present disclosure.
  • the boundary of the first conductive layer of the scan driving control circuit is closer to the display area than the side of the third power line PL3 .
  • the length LY of the scan driving control circuit in the first direction X may be the side of the first clock signal line CKL away from the display area and the side of the first conductive layer of the scan driving control circuit close to the display area (
  • the control electrode 203 of the tenth transistor T10 is close to the distance between the sides of the display area).
  • the structure of the display substrate will be described below through an example of the manufacturing process of the display substrate with reference to FIGS. 15 to 21 .
  • the “patterning process” mentioned in this disclosure includes deposition of film layer, coating of photoresist, mask exposure, development, etching and stripping of photoresist. Any one or more of sputtering, evaporation and chemical vapor deposition can be used for deposition, any one or more of spray coating and spin coating can be used for coating, and any of dry etching and wet etching can be used for etching. one or more.
  • “Film” refers to a layer of film produced by depositing or coating a certain material on a substrate.
  • the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • a and B are arranged in the same layer in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the projection of A includes the projection of B means that the boundary of the projection of B falls within the boundary range of the projection of A, or the boundary of the projection of A overlaps with the boundary of the projection of B.
  • the manufacturing process of the display substrate of this exemplary embodiment includes the following steps.
  • the substrate substrate 30 may be a rigid substrate or a flexible substrate.
  • the rigid substrate may comprise one or more of glass, metal foil.
  • Flexible substrates may include polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide One or more of amine, polyvinyl chloride, polyethylene, textile fiber.
  • a first semiconductor thin film is deposited on the base substrate 30, and the first semiconductor thin film is patterned through a patterning process to form a first semiconductor layer pattern, as shown in FIG. 17 .
  • the first semiconductor layer pattern includes at least: an active layer of a plurality of transistors (for example, transistors T1 to T10 ) in the scan driving control circuit.
  • the active layer may include at least one channel region and a plurality of doped regions.
  • the channel region may not be doped with impurities and has semiconductor characteristics.
  • the doped region is doped with impurities and thus has conductivity. Impurities may vary depending on the type of transistor (eg, N-type or P-type).
  • the material of the first semiconductor thin film may be polysilicon.
  • a first insulating film and a first conductive film are sequentially deposited on the base substrate 30 with the aforementioned pattern, and the first conductive film is patterned by a patterning process to form a first semiconductor layer covering the pattern.
  • the first conductive layer pattern may include: control electrodes of multiple transistors (eg, transistors T1 to T10 ) of the scan driving control circuit, multiple capacitors (eg, first capacitors C1 to The first pole of four capacitors C4).
  • a second insulating film and a second conductive film are sequentially deposited on the base substrate 30 formed with the aforementioned pattern, and the second conductive film is patterned by a patterning process to form a second insulating film covering the first conductive layer.
  • the insulating layer 32 and the second conductive layer pattern disposed on the second insulating layer 32 are shown in FIG. 19 .
  • the second conductive layer pattern may include: second poles of a plurality of capacitors (eg, first capacitors C1 to fourth capacitors C4 ) of the scan driving control circuit, a signal input terminal IN and a signal output terminal OUT.
  • a third insulating film is deposited on the base substrate 30 with the aforementioned pattern, and the third insulating film is patterned by a patterning process to form a pattern of the third insulating layer 33 covering the second conductive layer, such as Figure 20 shows.
  • a plurality of via holes are opened on the third insulating layer 33 .
  • the plurality of vias at least include: a plurality of first vias F1 to F25 , a plurality of second vias K1 to K10 , and a plurality of third vias D1 to D5 .
  • the third insulating layer 33 , the second insulating layer 32 and the first insulating layer 31 in the plurality of first via holes F1 to F25 are etched away, exposing the surface of the first semiconductor layer.
  • the third insulating layer 33 and the second insulating layer 32 in the plurality of second via holes K1 to K10 are etched away, exposing the surface of the first conductive layer.
  • the third insulating layer 33 in the plurality of third via holes D1 to D5 is etched away, exposing the surface of the second conductive layer.
  • a third conductive film is deposited on the base substrate 30 with the aforementioned pattern formed, and the third conductive film is patterned by a patterning process to form a third conductive layer pattern on the third insulating layer 33, such as Figure 21.
  • the third conductive layer pattern may include: first and second electrodes of a plurality of transistors (eg, transistors T1 to T10 ) of the scan driving control circuit, a first connection electrode 211 and a second connection electrode 212 .
  • the pixel circuit may be formed in the display area.
  • the first semiconductor layer of the display area may include the active layer of the transistor of the pixel circuit
  • the first conductive layer of the display area may include the control electrode of the transistor of the pixel circuit and the first electrode of the storage capacitor
  • the second conductive layer of the display area may include The layer may include at least the second electrode of the storage capacitor of the pixel circuit
  • the third conductive layer of the display area may include at least the first electrode and the second electrode of the transistor of the pixel circuit.
  • a second semiconductor layer may be formed in the display area, and an insulating layer is disposed between the second semiconductor layer and the first conductive layer.
  • the material of the second semiconductor thin film can be metal oxide, for example, IGZO.
  • the present embodiment does not limit the position of the second semiconductor layer.
  • a fourth insulating layer, an anode layer, a pixel definition layer, an organic light emitting layer, a cathode layer, and an encapsulation layer pattern may be sequentially formed in the display region.
  • a fourth insulating film is coated on the base substrate formed with the aforementioned pattern, and a fourth insulating layer pattern is formed by masking, exposing and developing the fourth insulating film.
  • an anode film is deposited on the substrate of the display area with the aforementioned pattern formed, and the anode film is patterned by a patterning process to form an anode pattern on the fourth insulating layer.
  • a pixel definition film is coated on the base substrate with the aforementioned pattern, and a pixel definition layer (PDL, Pixel Define Layer) pattern is formed through masking, exposure and development processes, and the pixel definition layer is formed on each sub-pixel in the display area , the pixel definition layer in each sub-pixel is formed with a pixel opening exposing the anode.
  • PDL Pixel Define Layer
  • an organic light-emitting layer is formed in the aforementioned pixel opening, and the organic light-emitting layer is connected to the anode.
  • a cathode thin film is deposited, and the cathode thin film is patterned through a patterning process to form a cathode pattern.
  • an encapsulation layer is formed on the cathode, and the encapsulation layer may include a stacked structure of inorganic material/organic material/inorganic material.
  • the first conductive layer, the second conductive layer, and the third conductive layer can use metal materials, such as any of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • metal materials such as any of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • metal materials such as any of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • metal materials such as any of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • metal materials such as any of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo).
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the first insulating layer 31, the second insulating layer 32 and the third insulating layer 33 can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can Is single layer, multilayer or composite layer. Organic materials such as polyimide, acrylic or polyethylene terephthalate can be used for the fourth insulating layer.
  • the first insulating layer 31 and the second insulating layer 32 are called a gate insulating (GI) layer
  • the third insulating layer 33 is called an interlayer insulating (ILD) layer
  • the fourth insulating layer is called a planarization layer.
  • the pixel definition layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate.
  • the anode can use transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the cathode can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or any one or more of the above metals alloy. However, this embodiment does not limit it.
  • reflective materials such as metal can be used for the anode
  • transparent conductive materials can be used for the cathode.
  • the structure shown in this exemplary embodiment and its preparation process are only exemplary illustrations. In some exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the preparation process of this exemplary embodiment can be realized by using currently mature preparation equipment, and is well compatible with the existing preparation process. The process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield.
  • an embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate.
  • the display substrate may be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.
  • the display device can be any product or component with a display function, such as an OLED display device, a watch, a mobile phone, a tablet computer, a television set, a monitor, a notebook computer, a digital photo frame, a navigator, and the like. However, this embodiment does not limit it.
  • FIG. 25 is a schematic structural diagram of a display device according to at least one embodiment of the present disclosure.
  • the display device may include: a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, and the pixel array may include a plurality of scan lines (such as GL1 to GLn), A plurality of data signal lines (eg, DL1 to DLn), a plurality of light emission control lines (eg, EL1 to ELn), and a plurality of sub-pixels 10 .
  • Each sub-pixel 10 may be connected to a corresponding data signal line, a corresponding scan line, and a corresponding light emission control line.
  • the timing controller may provide grayscale values and control signals suitable for the specification of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the
  • the scan driver can supply a clock signal, an emission stop signal, and the like suitable for the specifications of the light-emitting driver to the light-emitting driver.
  • the data driver may generate data voltages to be supplied to the data signal lines DL1, DL2, DL3, . . . and DLm using gray values and control signals received from the timing controller, and m may be an integer.
  • the data driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data signal lines DL1 to DLm in units of pixel rows.
  • the scan driver may generate scan signals to be supplied to the scan lines GL1, GL2, GL3, . . . and GLn by receiving a clock signal, a scan start signal, etc. from the timing controller, and n may be an integer.
  • the scan driver may sequentially supply scan signals having turn-on level pulses to the scan lines GL1 to GLn.
  • the scan driver can be configured in the form of a shift register, and can generate scan signals in such a manner as to sequentially transmit scan start signals supplied in the form of on-level pulses to the next-stage circuit under the control of a clock signal .
  • the light emission driver may generate emission signals to be supplied to the light emission control lines EL1, EL2, EL3, . . . , and ELn by receiving a clock signal, an emission stop signal, etc. from the timing controller.
  • the light emission driver may sequentially supply emission signals having off-level pulses to the light emission control lines EL1 to ELn.
  • the light emitting driver may be configured in the form of a shift register, and may generate light emitting signals in such a manner as to sequentially transmit light emitting stop signals provided in the form of off-level pulses to the next-stage circuit under the control of a clock signal.
  • the light emitting driver may include multiple cascaded scan driving control circuits as provided in the above embodiments. In this example, the working sequence of the scan driving control circuit can be shown in FIG. 10 .
  • the shape of the sub-pixel 10 may be a rectangle, a rhombus, a pentagon, or a hexagon.
  • the three sub-pixels can be arranged horizontally, vertically or squarely; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically or squarely .
  • this embodiment does not limit it.
  • one pixel unit in the display area may include three sub-pixels, and the three sub-pixels may be red sub-pixels, green sub-pixels and blue sub-pixels respectively.
  • this embodiment does not limit it.
  • one pixel unit may include four sub-pixels, and the four sub-pixels are respectively a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel.
  • a timing controller, a data driver, a scan driver, and a light emitting driver may be disposed in the non-display area.
  • the scan driver and the light-emitting driver can be arranged on opposite sides of the display area, for example, the left side and the right side of the display area; the timing controller and the data driver can be arranged on one side of the display area, for example, the lower side of the display area .
  • this embodiment is not limited to this.
  • a subpixel includes pixel circuitry.
  • the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • a pixel circuit may include N-type transistors and P-type transistors.
  • the N-type transistor can be, for example, an oxide thin film transistor
  • the P-type transistor can be, for example, a low temperature polysilicon thin film transistor.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current.
  • the low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (LTPO) , Low Temperature Polycrystalline Oxide) display substrate, can take advantage of the advantages of both, can achieve low-frequency drive, can reduce power consumption, and can improve display quality.
  • LTPO low-temperature polycrystalline oxide
  • Low Temperature Polycrystalline Oxide Low Temperature Polycrystalline Oxide
  • FIG. 27 is another schematic structural diagram of a display device according to at least one embodiment of the present disclosure.
  • the scan driver can provide driving signals to the P-type transistors of the pixel circuit through the first group of scan lines GL1 to GLn, and can also provide driving signals to the pixel circuits through the second group of scan lines SL1 to SLn.
  • the N-type transistor of the circuit provides the drive signal.
  • the light emitting driver may provide light emitting signals to the pixel circuits through the light emitting control lines EL1 to ELn.
  • the scan driver may include a plurality of cascaded scan drive control circuits as described in the above embodiments to provide drive signals to the N-type transistors of the pixel circuit through the second set of scan lines SL1 to SLn.
  • the working sequence of the scan driving control circuit can be shown in FIG. 9 .

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

L'invention concerne un substrat d'affichage comprenant un substrat de base (30) et un circuit de contrôle de commande de balayage qui est disposé dans une zone non d'affichage du substrat de base (30). Le circuit de contrôle de commande de balayage comprend un circuit d'entrée, un circuit de contrôle de sortie et un circuit de sortie. Le circuit de contrôle de sortie est connecté au circuit d'entrée et au circuit de sortie. Le circuit de contrôle de sortie comprend un premier condensateur de contrôle de nœud et un second condensateur de contrôle de nœud. La longueur du premier condensateur de contrôle de nœud dans une première direction L C1k, la longueur du second condensateur de contrôle de nœud dans la première direction L C2k et la longueur du circuit de contrôle de commande de balayage dans la première direction L Y satisfont (aa).
PCT/CN2022/104688 2021-07-09 2022-07-08 Substrat d'affichage et dispositif d'affichage WO2023280314A1 (fr)

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EP22837059.9A EP4280202A1 (fr) 2021-07-09 2022-07-08 Substrat d'affichage et dispositif d'affichage
KR1020237028712A KR20240032702A (ko) 2021-07-09 2022-07-08 디스플레이 기판 및 디스플레이 장치

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