WO2023276107A1 - Procédé de formation de couche semi-conductrice - Google Patents

Procédé de formation de couche semi-conductrice Download PDF

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Publication number
WO2023276107A1
WO2023276107A1 PCT/JP2021/024937 JP2021024937W WO2023276107A1 WO 2023276107 A1 WO2023276107 A1 WO 2023276107A1 JP 2021024937 W JP2021024937 W JP 2021024937W WO 2023276107 A1 WO2023276107 A1 WO 2023276107A1
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Prior art keywords
semiconductor layer
forming
insulating layer
substrate
semiconductor
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PCT/JP2021/024937
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English (en)
Japanese (ja)
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弘樹 杉山
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日本電信電話株式会社
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Priority to JP2023531290A priority Critical patent/JPWO2023276107A1/ja
Priority to PCT/JP2021/024937 priority patent/WO2023276107A1/fr
Publication of WO2023276107A1 publication Critical patent/WO2023276107A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy

Definitions

  • the present invention relates to a method for forming a semiconductor layer having a heterointerface perpendicular to a substrate.
  • Group III-V semiconductors can create functions by forming heterojunctions, and are used in various devices such as transistors, light-emitting/light-receiving elements. Heterojunctions are usually formed by growing crystals in a direction perpendicular to the III-V semiconductor substrate to form a heterointerface parallel to the substrate. Devices made of III-V compounds, which are widely put into practical use, utilize such heterojunctions and heterointerfaces. Formation of such heterojunction devices made of III-V group semiconductors on Si substrates is expected from the viewpoint of multifunctionality through integration with Si devices, and various fabrication techniques have been practiced. rice field.
  • TFET tunnel field effect transistor
  • Non-Patent Document 2 With conventional technology, it is necessary to form a nanowire structure as described in Non-Patent Document 2 and a mesa structure with a very high aspect ratio as described in Non-Patent Document 3, making it difficult to mass-produce practical devices. it is conceivable that.
  • Non-Patent Document 4 As a technique for overcoming this, for example, as described in Non-Patent Document 4, a ⁇ 111 ⁇ facet formed on a Si (100) substrate by anisotropic etching and a selective growth technique are used to apply A technique has been reported in which crystal growth is performed in the horizontal direction to form a heterojunction perpendicular to the growth direction. However, in this case, stacking faults are likely to occur due to growth in the ⁇ 111 ⁇ direction, making it difficult to form high-quality crystals with high uniformity.
  • Fujimatsu et al. "71mV/dec of Sub-threshold Slope in Vertical Tunnel Field-effect Transistors with GaAsSb/InGaAs Heterostructure", 2012 International Conference on Indium Phosphide and Related Materials, 13235642, pp. 25-28, 2013. Y. Han et al., "Micrometer-scale InP selectively grown on SOI for fully integrated Si-photonics", Applied Physics Letters, vol. 117, 052102, 2020.
  • the present invention has been made to solve the above-described problems, and makes it possible to easily form a heterojunction on a Si substrate by means of a heterointerface perpendicular to a substrate made of a Group III-V compound semiconductor. for the purpose.
  • a crystal substrate made of a group III-V compound semiconductor crystal having a (110) plane as a main surface is attached onto a Si substrate, and the attached crystal substrate is formed into a thin layer.
  • a crystal substrate made of a group III-V compound semiconductor crystal having a (110) plane as a main surface is adhered onto a Si substrate, whereby a second crystal substrate is formed on the Si substrate. Since one semiconductor layer is formed, a heterojunction can be easily formed on the Si substrate by a heterointerface perpendicular to the substrate made of a Group III-V compound semiconductor.
  • FIG. 1A is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining a method of forming a semiconductor layer according to an embodiment of the present invention.
  • FIG. 1B is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention.
  • FIG. 1C is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention.
  • FIG. 1D is a cross-sectional view showing the state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention.
  • FIG. 1A is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining a method of forming a semiconductor layer according to an embodiment of the present invention.
  • FIG. 1B is a cross-sectional view showing a state of
  • FIG. 1E is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention.
  • FIG. 1F is a plan view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention.
  • FIG. 1G is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention.
  • FIG. 1H is a plan view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention.
  • FIG. 1I is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention.
  • FIG. 1J is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention.
  • FIG. 1K is a cross-sectional view showing the state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention.
  • FIG. 1L is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention.
  • FIG. 1M is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention.
  • FIG. 1N is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention.
  • FIG. 1O is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention.
  • FIG. 1P is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention.
  • FIGS. 1A to 1P A method for forming a semiconductor layer according to an embodiment of the present invention will be described below with reference to FIGS. 1A to 1P.
  • a Si substrate 101 having a main surface formed with a Si oxide layer 102 made of SiO 2 is prepared.
  • the main surface of the Si substrate 101 is the (001) plane.
  • Si oxide layer 102 can be formed by depositing SiO 2 by well-known deposition techniques.
  • a crystal substrate 103 is attached onto the Si substrate 101. Then, as shown in FIG. 1B, the surface of the Si oxide layer 102 and the surface of the crystal substrate 103 are bonded by a known bonding technique.
  • the crystal substrate 103 is composed of a III-V group compound semiconductor crystal having a (110) plane as the main surface. This III-V compound semiconductor can be, for example, InP.
  • a first semiconductor layer 104 is formed on the Si substrate 101 as shown in FIG. 1C (first step).
  • the thinning of the crystal substrate 103 can be implemented by chemical etching, a CMP (chemical-mechanical-polishing) method, or the like.
  • the first semiconductor layer 104 is formed on the Si substrate 101 with the Si oxide layer 102 interposed therebetween.
  • the main surface of the first semiconductor layer 104 can be formed in a state inclined from the (110) plane toward the ⁇ 111 ⁇ B plane by 3 to 6°.
  • the above state can be obtained by using a crystal substrate 103 whose main surface is inclined from the (110) plane toward the ⁇ 111 ⁇ B plane by 3 to 6 degrees.
  • the thinning of the crystal substrate 103 is carried out, for example, by adjusting the polishing angle so that the main surface is inclined 3 to 6° from the (110) plane toward the ⁇ 111 ⁇ B plane. can be done.
  • the main surface of the first semiconductor layer 104 is tilted from the (110) plane toward the ⁇ 111 ⁇ B plane by 3 to 6 degrees, so that the first semiconductor layer 104, which will be described later, undergoes crystal re-growth. , it is possible to suppress the formation of ⁇ 112 ⁇ or ⁇ 111 ⁇ facets and obtain a flat growth surface (Refs. 1 and 2).
  • the first insulating layer 105 can have a laminated structure of an Al oxide layer 105a made of Al 2 O 3 and a Si oxide layer 105b (Reference 3).
  • the first insulating layer 105 can be configured with a laminated structure of an Al oxide layer 105a with a thickness of 3 nm and a Si oxide layer 105b with a thickness of 30 nm.
  • the [001] direction of the first semiconductor layer 104 is the long side, and [ A rectangular planar first opening 125b having a short side in the ⁇ 110] direction is formed (second step).
  • the first opening 125b can be formed by using a resist pattern formed by a known photolithography technique or electron beam lithography technique as a mask and performing an etching process such as well-known ICP etching.
  • the first opening 125b can have a long side length of 1 ⁇ m and a short side length of 100 nm in plan view. The size of this aperture can be appropriately set according to the size of the desired heterostructure.
  • a sacrificial pattern 106 made of amorphous Si is formed on the first insulating layer 105 (third step).
  • the sacrificial pattern 106 is formed in a rectangular planar shape with long sides in the [ ⁇ 110] direction of the first semiconductor layer 104 and short sides in the [001] direction.
  • the sacrificial pattern 106 has an area larger than that of the first opening 125b when viewed from above, and is formed so as to be centered on the first opening 125b.
  • the sacrificial pattern 106 fills (fills) the first opening 125b to form a flat surface.
  • the sacrificial pattern 106 can be formed by depositing Si by a chemical vapor deposition method or the like to form a Si film, and patterning the formed silicon film by a known lithography technique or etching technique.
  • the dimensions such as the long side, short side and thickness of the sacrificial pattern 106 can be appropriately set according to the size of the semiconductor device having the desired heterojunction structure.
  • sacrificial pattern 106 may be 50 nm thick.
  • a second insulating layer 107 is formed on the first insulating layer 105 to cover the sacrificial pattern 106 (fourth step).
  • the second insulating layer 107 is used as a selective growth mask for III-V compound semiconductors, and can be made of SiO 2 , for example.
  • the second insulating layer 107 can be formed, for example, to have a thickness of about 100 nm.
  • a through-hole 127 reaching the sacrificial pattern 106 is formed at a location that does not overlap the first opening 125b of the second insulating layer 107 (fifth step).
  • the through holes 127 are formed, for example, at the edges of the two short sides of the sacrificial pattern 106, which is rectangular in plan view.
  • the sacrificial pattern 106 is removed through the two formed through holes 127 to form a hollow structure 126 between the first insulating layer 105 and the second insulating layer 107, as shown in FIG. 1K. . Further, a first lower opening 125a is formed in the Al oxide layer 105a below the first opening 125b to expose the first semiconductor layer 104 in this region (sixth step).
  • the hollow structure 126 is formed in a rectangular planar shape with long sides in the [ ⁇ 110] direction of the first semiconductor layer 104 and short sides in the [001] direction.
  • the sacrificial pattern 106 can be selectively removed by dry etching using XeF2 .
  • the first lower opening 125a can be formed in the Al oxide layer 105a by selective etching using TMAH (Methyl Ammonium Hydroxide).
  • the first insulating layer 105 is used as a selective growth mask to crystallize (epitaxially) grow a group III-V compound semiconductor, As shown in FIG. 1L, a second semiconductor layer 108 is formed (seventh step). The second semiconductor layer 108 is grown between the first insulating layer 105 and the second insulating layer 107 (hollow structure 126) from the surface of the first semiconductor layer 104 exposed in the first opening 125b.
  • the hollow structure 126 moves left and right around the first opening 125b and has at least two side surfaces 138a and 138b. These side surfaces 138a and 138b are facets of crystal-grown group III-V compound semiconductors.
  • the second semiconductor layer 108 is formed in a range in which the side surfaces 138 a and 138 b are arranged between the first insulating layer 105 and the second insulating layer 107 .
  • the first semiconductor layer 104 can be formed by epitaxially growing InP from the exposed surface (110) of the first semiconductor layer 104 made of InP by metal organic chemical vapor deposition (MOCVD). (Reference 3).
  • MOCVD metal organic chemical vapor deposition
  • the side surfaces 138a and 138b of the second semiconductor layer 108 are grown perpendicular to the surface of the Si substrate 101.
  • a [ ⁇ 110] facet can be obtained, and the crystal grows in the [ ⁇ 110] direction while maintaining this state.
  • the second semiconductor layer 108 is, for example, epitaxially grown until the side surfaces 138a and 138b reach a location several nm apart from the region of the first opening 125b in plan view. Alternatively, the second semiconductor layer 108 may be grown until it reaches the lower surface of the second insulating layer 107 that serves as the ceiling of the hollow structure 126 after it reaches the hollow structure 126 by filling the first opening 125b. can. Further, as illustrated in FIG. 1L, a second semiconductor layer 108 made of n + -InP into which n-type impurities are introduced at a high concentration is grown to reach the lower surface of the second insulating layer 107 that serves as the ceiling of the hollow structure 126. From this point, the growth of non-doped InP can be switched to continue the formation of the second semiconductor layers 108a and 108b.
  • the second semiconductor layer 108 (second semiconductor layer 108a, second semiconductor layer 108b) between the first insulating layer 105 and the second insulating layer 107 is formed.
  • a group III-V compound semiconductor having a composition different from that of the second semiconductor layer 108 is epitaxially grown from the side surfaces 138a and 138b of the second semiconductor layer 108a and the second semiconductor layer 108b).
  • the third semiconductor layer 109a and the third semiconductor layer 109a form heterojunctions with the side surfaces 138a and 138b of the second semiconductor layer 108 (the second semiconductor layers 108a and 108b).
  • a semiconductor layer 109b is formed (eighth step).
  • the interface where the heterojunction is formed is a plane perpendicular to the plane of the Si substrate 101 .
  • epitaxial growth of the third semiconductor layers 109a and 109b can be carried out by changing the material supplied at a predetermined time. For example, by epitaxially growing non-doped InGaAs, the third semiconductor layers 109a and 109b can be formed.
  • InGaAs doped with p-type impurities is epitaxially grown to form fourth semiconductor layers 110a and 110b, and InP doped with p-type impurities at a high concentration is grown to form a fifth semiconductor layer.
  • a semiconductor layer 111a and a fifth semiconductor layer 111b are formed.
  • the interface between the fourth semiconductor layer 110a and the fifth semiconductor layer 111a is a heterojunction interface, and the interface between the fourth semiconductor layer 110b and the fifth semiconductor layer 111b is also a heterojunction interface.
  • Each interface is a plane perpendicular to the plane of the Si substrate 101 .
  • the fourth semiconductor layer 110 a , the fourth semiconductor layer 110 b , the fifth semiconductor layer 111 a , and the fifth semiconductor layer 111 b are exposed on the first insulating layer 105 .
  • gate electrodes 114a and 114b are formed on the third semiconductor layers 109a and 109b via the gate insulating layers 113a and 113b. Also, source electrodes 115a and 115b are formed to be ohmically connected to the fifth semiconductor layers 111a and 111b. Also, a drain electrode 116 that is ohmically connected to the second semiconductor layer 108 is formed.
  • the n-type second semiconductor layer 108 is used as the drain
  • the p-type fourth semiconductor layers 110a and 110b are used as the sources
  • the hetero interface perpendicular to the plane of the Si substrate 101 forms a barrier.
  • a tunneling field effect transistor can be formed in which quantum tunneling is modulated by the gate voltage applied to the gate electrodes 114a and 114b.
  • the thickness, crystal composition, and doping concentration of each semiconductor layer can be applied by appropriately designing the transistor structure so as to obtain desired characteristics, and applying the designed values.
  • the crystal substrate 103 (the first semiconductor layer 104) is made of InP in the above description, it is not limited to this.
  • the crystal substrate 103 (first semiconductor layer 104) can be made of GaAs, for example.
  • Quantum well structures using materials such as InGaAs, InP, and InGaAsP can be formed by the method of forming a semiconductor layer according to the embodiment, and the methods can be applied to fabricate light-emitting devices such as lasers using minute quantum well structures. Needless to say.
  • a crystal substrate made of a group III-V compound semiconductor crystal having a (110) plane as a main surface is adhered onto a Si substrate, thereby forming a crystal substrate on the Si substrate. Since the first semiconductor layer is formed, it becomes possible to easily form a heterojunction on the Si substrate by a heterointerface perpendicular to the substrate made of a group III-V compound semiconductor. According to the present invention, it is possible to form a group III-V semiconductor thin film crystal having a heterointerface perpendicular to the substrate on a Si substrate, and the functions of a group III-V semiconductor device and a Si device are integrated. It becomes possible to fabricate a device that is not available in

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

La présente invention consiste à préparer un substrat de Si (101) ayant une couche d'oxyde de Si (102) composée de SiO2 formé sur une surface principale, à fixer un substrat de cristal sur le substrat de Si (101), à fabriquer le substrat de cristal fixé dans une couche mince, ce qui permet de former une première couche semi-conductrice (104) sur le substrat de Si (101), puis à former une première couche d'isolation (105), et utiliser la première couche d'isolation (105) en tant que masque de croissance sélectif pour faire croître de manière épitaxiale un semi-conducteur composé du groupe III-V à partir de la surface de la première couche semi-conductrice (104) exposée dans une région prévue à partir d'une première ouverture (125b), formant ainsi une seconde couche semi-conductrice (108).
PCT/JP2021/024937 2021-07-01 2021-07-01 Procédé de formation de couche semi-conductrice WO2023276107A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0210825A (ja) * 1988-04-05 1990-01-16 Thomson Csf 単結晶半導体材料層及び絶縁材料層の交互層製造方法
JPH02130917A (ja) * 1988-11-11 1990-05-18 Nec Corp 半導体膜の製造方法
JPH02188912A (ja) * 1989-01-17 1990-07-25 Nec Corp ３‐５族化合物半導体の選択成長方法
JPH06140346A (ja) * 1992-04-02 1994-05-20 Thomson Csf ヘテロエピタキシアルの薄い層と電子デバイスの製造法
JP2013098559A (ja) * 2011-10-31 2013-05-20 Samsung Electronics Co Ltd Ｉｉｉ−ｖ族化合物半導体層を含む半導体素子及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0210825A (ja) * 1988-04-05 1990-01-16 Thomson Csf 単結晶半導体材料層及び絶縁材料層の交互層製造方法
JPH02130917A (ja) * 1988-11-11 1990-05-18 Nec Corp 半導体膜の製造方法
JPH02188912A (ja) * 1989-01-17 1990-07-25 Nec Corp ３‐５族化合物半導体の選択成長方法
JPH06140346A (ja) * 1992-04-02 1994-05-20 Thomson Csf ヘテロエピタキシアルの薄い層と電子デバイスの製造法
JP2013098559A (ja) * 2011-10-31 2013-05-20 Samsung Electronics Co Ltd Ｉｉｉ−ｖ族化合物半導体層を含む半導体素子及びその製造方法

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