WO2023276107A1

WO2023276107A1 - Method for forming semiconductor layer

Info

Publication number: WO2023276107A1
Application number: PCT/JP2021/024937
Authority: WO
Inventors: 弘樹杉山
Original assignee: 日本電信電話株式会社
Priority date: 2021-07-01
Filing date: 2021-07-01
Publication date: 2023-01-05
Also published as: JPWO2023276107A1

Abstract

The present invention includes preparing a Si substrate (101) having a Si oxide layer (102) composed of SiO2 formed on a main surface, affixing a crystal substrate on the Si substrate (101), making the affixed crystal substrate into a thin layer, thereby forming a first semiconductor layer (104) on the Si substrate (101), and then forming a first insulation layer (105), and using the first insulation layer (105) as a selective growth mask to epitaxially grow a group III-V compound semiconductor from the surface of the first semiconductor layer (104) exposed in an anticipated region from a first opening (125b), thereby forming a second semiconductor layer (108).

Description

Method for forming semiconductor layer

The present invention relates to a method for forming a semiconductor layer having a heterointerface perpendicular to a substrate.

Group III-V semiconductors can create functions by forming heterojunctions, and are used in various devices such as transistors, light-emitting/light-receiving elements. Heterojunctions are usually formed by growing crystals in a direction perpendicular to the III-V semiconductor substrate to form a heterointerface parallel to the substrate. Devices made of III-V compounds, which are widely put into practical use, utilize such heterojunctions and heterointerfaces. Formation of such heterojunction devices made of III-V group semiconductors on Si substrates is expected from the viewpoint of multifunctionality through integration with Si devices, and various fabrication techniques have been practiced. rice field.

On the other hand, the technology for forming high-quality heterointerfaces perpendicular to the substrate and the horizontal heterojunctions on Si substrates, and the technology for fabricating devices on Si substrates using such heterointerfaces have been reported. is not established as a technology. If such a technique for forming a heterojunction surface perpendicular to the substrate plane is realized, various applications can be considered. For example, a tunnel field effect transistor (TFET) composed of a heterojunction as described in Non-Patent Document 1 can be formed on a Si substrate. As described in Non-Patent Document 1, this device requires the formation of a heterojunction perpendicular to the gate electrode and gate insulating layer.

With conventional technology, it is necessary to form a nanowire structure as described in Non-Patent Document 2 and a mesa structure with a very high aspect ratio as described in Non-Patent Document 3, making it difficult to mass-produce practical devices. it is conceivable that.

As a technique for overcoming this, for example, as described in Non-Patent Document 4, a {111} facet formed on a Si (100) substrate by anisotropic etching and a selective growth technique are used to apply A technique has been reported in which crystal growth is performed in the horizontal direction to form a heterojunction perpendicular to the growth direction. However, in this case, stacking faults are likely to occur due to growth in the {111} direction, making it difficult to form high-quality crystals with high uniformity.

As described above, conventionally, there has been the problem that it is not easy to form a heterojunction on a Si substrate by means of a heterointerface perpendicular to a substrate made of a Group III-V compound semiconductor.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and makes it possible to easily form a heterojunction on a Si substrate by means of a heterointerface perpendicular to a substrate made of a Group III-V compound semiconductor. for the purpose.

In the method of forming a semiconductor layer according to the present invention, a crystal substrate made of a group III-V compound semiconductor crystal having a (110) plane as a main surface is attached onto a Si substrate, and the attached crystal substrate is formed into a thin layer. a first step of forming a first semiconductor layer on a Si substrate by converting the first semiconductor layer on the first semiconductor layer; a second step of forming a first insulating layer having a first opening having a rectangular planar shape to form a rectangular planar shape; A third step of forming a sacrificial pattern made of amorphous Si and having a rectangular planar shape with a short side of a fifth step of forming a through hole reaching the sacrificial pattern in a portion of the second insulating layer that does not overlap with the first opening; a sixth step in which the surface of the layer is exposed; and using the first insulating layer having the first opening as a selective growth mask, the III-V group compound semiconductor is crystallized from the surface of the first semiconductor layer exposed in the first opening. between the first insulating layer and the second insulating layer, with the side faces consisting of the facets of the grown III-V compound semiconductor being crystallized between the first insulating layer and the second insulating layer. A seventh step of forming a second semiconductor layer; and an eighth step of crystal-growing the group III-V compound semiconductor to form a third semiconductor layer forming a heterojunction with the side surface of the second semiconductor layer.

As described above, according to the present invention, a crystal substrate made of a group III-V compound semiconductor crystal having a (110) plane as a main surface is adhered onto a Si substrate, whereby a second crystal substrate is formed on the Si substrate. Since one semiconductor layer is formed, a heterojunction can be easily formed on the Si substrate by a heterointerface perpendicular to the substrate made of a Group III-V compound semiconductor.

FIG. 1A is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining a method of forming a semiconductor layer according to an embodiment of the present invention. FIG. 1B is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention. FIG. 1C is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention. FIG. 1D is a cross-sectional view showing the state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention. FIG. 1E is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention. FIG. 1F is a plan view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention. FIG. 1G is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention. FIG. 1H is a plan view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention. FIG. 1I is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention. FIG. 1J is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention. FIG. 1K is a cross-sectional view showing the state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention. FIG. 1L is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention. FIG. 1M is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention. FIG. 1N is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention. FIG. 1O is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention. FIG. 1P is a cross-sectional view showing a state of a semiconductor layer in an intermediate step for explaining the method of forming a semiconductor layer according to the embodiment of the present invention.

A method for forming a semiconductor layer according to an embodiment of the present invention will be described below with reference to FIGS. 1A to 1P.

First, as shown in FIG. 1A, a Si substrate 101 having a main surface formed with a Si oxide layer 102 made of SiO ₂ is prepared. The main surface of the Si substrate 101 is the (001) plane. For example, Si oxide layer 102 can be formed by depositing SiO ₂ by well-known deposition techniques.

Next, as shown in FIG. 1B, a crystal substrate 103 is attached onto the Si substrate 101. Then, as shown in FIG. In this example, the surface of the Si oxide layer 102 and the surface of the crystal substrate 103 are bonded by a known bonding technique. The crystal substrate 103 is composed of a III-V group compound semiconductor crystal having a (110) plane as the main surface. This III-V compound semiconductor can be, for example, InP.

Next, by thinning the attached crystal substrate 103, a first semiconductor layer 104 is formed on the Si substrate 101 as shown in FIG. 1C (first step). For example, the thinning of the crystal substrate 103 can be implemented by chemical etching, a CMP (chemical-mechanical-polishing) method, or the like. In this example, the first semiconductor layer 104 is formed on the Si substrate 101 with the Si oxide layer 102 interposed therebetween.

Here, the main surface of the first semiconductor layer 104 can be formed in a state inclined from the (110) plane toward the {111}B plane by 3 to 6°. For example, the above state can be obtained by using a crystal substrate 103 whose main surface is inclined from the (110) plane toward the {111}B plane by 3 to 6 degrees. Further, the thinning of the crystal substrate 103 is carried out, for example, by adjusting the polishing angle so that the main surface is inclined 3 to 6° from the (110) plane toward the {111}B plane. can be done.

As described above, the main surface of the first semiconductor layer 104 is tilted from the (110) plane toward the {111}B plane by 3 to 6 degrees, so that the first semiconductor layer 104, which will be described later, undergoes crystal re-growth. , it is possible to suppress the formation of {112} or {111} facets and obtain a flat growth surface (Refs. 1 and 2).

Next, as shown in FIG. 1D, a first insulating layer 105 is formed. The first insulating layer 105 can have a laminated structure of an Al oxide layer 105a made of Al ₂ O ₃ and a Si oxide layer 105b (Reference 3). For example, the first insulating layer 105 can be configured with a laminated structure of an Al oxide layer 105a with a thickness of 3 nm and a Si oxide layer 105b with a thickness of 30 nm.

Next, as shown in FIGS. 1E and 1F, on the Si oxide layer 105b of the first insulating layer 105, on the first semiconductor layer 104, the [001] direction of the first semiconductor layer 104 is the long side, and [ A rectangular planar first opening 125b having a short side in the −110] direction is formed (second step). For example, the first opening 125b can be formed by using a resist pattern formed by a known photolithography technique or electron beam lithography technique as a mask and performing an etching process such as well-known ICP etching. The first opening 125b can have a long side length of 1 μm and a short side length of 100 nm in plan view. The size of this aperture can be appropriately set according to the size of the desired heterostructure.

Next, as shown in FIGS. 1G and 1H, a sacrificial pattern 106 made of amorphous Si is formed on the first insulating layer 105 (third step). The sacrificial pattern 106 is formed in a rectangular planar shape with long sides in the [−110] direction of the first semiconductor layer 104 and short sides in the [001] direction. The sacrificial pattern 106 has an area larger than that of the first opening 125b when viewed from above, and is formed so as to be centered on the first opening 125b. In addition, the sacrificial pattern 106 fills (fills) the first opening 125b to form a flat surface.

For example, the sacrificial pattern 106 can be formed by depositing Si by a chemical vapor deposition method or the like to form a Si film, and patterning the formed silicon film by a known lithography technique or etching technique. The dimensions such as the long side, short side and thickness of the sacrificial pattern 106 can be appropriately set according to the size of the semiconductor device having the desired heterojunction structure. For example, sacrificial pattern 106 may be 50 nm thick.

Next, as shown in FIG. 1I, a second insulating layer 107 is formed on the first insulating layer 105 to cover the sacrificial pattern 106 (fourth step). The second insulating layer 107 is used as a selective growth mask for III-V compound semiconductors, and can be made of SiO ₂ , for example. The second insulating layer 107 can be formed, for example, to have a thickness of about 100 nm.

Next, as shown in FIG. 1J, a through-hole 127 reaching the sacrificial pattern 106 is formed at a location that does not overlap the first opening 125b of the second insulating layer 107 (fifth step). The through holes 127 are formed, for example, at the edges of the two short sides of the sacrificial pattern 106, which is rectangular in plan view.

Next, the sacrificial pattern 106 is removed through the two formed through holes 127 to form a hollow structure 126 between the first insulating layer 105 and the second insulating layer 107, as shown in FIG. 1K. . Further, a first lower opening 125a is formed in the Al oxide layer 105a below the first opening 125b to expose the first semiconductor layer 104 in this region (sixth step). The hollow structure 126 is formed in a rectangular planar shape with long sides in the [−110] direction of the first semiconductor layer 104 and short sides in the [001] direction.

For example, the sacrificial pattern 106 can be selectively removed by dry etching using _XeF2 . Also, the first lower opening 125a can be formed in the Al oxide layer 105a by selective etching using TMAH (Methyl Ammonium Hydroxide).

Next, from the surface of the first semiconductor layer 104 exposed in the region seen from the first opening 125b, the first insulating layer 105 is used as a selective growth mask to crystallize (epitaxially) grow a group III-V compound semiconductor, As shown in FIG. 1L, a second semiconductor layer 108 is formed (seventh step). The second semiconductor layer 108 is grown between the first insulating layer 105 and the second insulating layer 107 (hollow structure 126) from the surface of the first semiconductor layer 104 exposed in the first opening 125b.

When this growth reaches the hollow structure 126 by filling the first

lower openings

125a and 125b, it progresses in the [-110] direction of the first semiconductor layer 104 centering on the first openings 125b. The hollow structure 126 moves left and right around the first opening 125b and has at least two

side surfaces

138a and 138b. These side surfaces 138a and 138b are facets of crystal-grown group III-V compound semiconductors. The second semiconductor layer 108 is formed in a range in which the side surfaces 138 a and 138 b are arranged between the first insulating layer 105 and the second insulating layer 107 .

For example, the first semiconductor layer 104 can be formed by epitaxially growing InP from the exposed surface (110) of the first semiconductor layer 104 made of InP by metal organic chemical vapor deposition (MOCVD). (Reference 3). In this growth, by appropriately adjusting the growth temperature and the supply ratio of the group V source material and the group III source material, the

side surfaces

138a and 138b of the second semiconductor layer 108 are grown perpendicular to the surface of the Si substrate 101. A [−110] facet can be obtained, and the crystal grows in the [−110] direction while maintaining this state.

The second semiconductor layer 108 is, for example, epitaxially grown until the

side surfaces

138a and 138b reach a location several nm apart from the region of the first opening 125b in plan view. Alternatively, the second semiconductor layer 108 may be grown until it reaches the lower surface of the second insulating layer 107 that serves as the ceiling of the hollow structure 126 after it reaches the hollow structure 126 by filling the first opening 125b. can. Further, as illustrated in FIG. 1L, a second semiconductor layer 108 made of n ⁺ -InP into which n-type impurities are introduced at a high concentration is grown to reach the lower surface of the second insulating layer 107 that serves as the ceiling of the hollow structure 126. From this point, the growth of non-doped InP can be switched to continue the formation of the

second semiconductor layers

108a and 108b.

Next, following the formation of the second semiconductor layer 108 (second semiconductor layer 108a, second semiconductor layer 108b) described above, the second semiconductor layer 108 (second semiconductor layer 108) between the first insulating layer 105 and the second insulating layer 107 is formed. A group III-V compound semiconductor having a composition different from that of the second semiconductor layer 108 is epitaxially grown from the

side surfaces

138a and 138b of the second semiconductor layer 108a and the second semiconductor layer 108b). As a result, as shown in FIG. 1M, the third semiconductor layer 109a and the third semiconductor layer 109a form heterojunctions with the

side surfaces

138a and 138b of the second semiconductor layer 108 (the

second semiconductor layers

108a and 108b). 3 A semiconductor layer 109b is formed (eighth step). The interface where the heterojunction is formed is a plane perpendicular to the plane of the Si substrate 101 .

For example, in the growth of the second semiconductor layer 108 by the MOCVD method, epitaxial growth of the

third semiconductor layers

109a and 109b can be carried out by changing the material supplied at a predetermined time. For example, by epitaxially growing non-doped InGaAs, the

third semiconductor layers

109a and 109b can be formed.

Subsequently, InGaAs doped with p-type impurities is epitaxially grown to form

fourth semiconductor layers

110a and 110b, and InP doped with p-type impurities at a high concentration is grown to form a fifth semiconductor layer. A semiconductor layer 111a and a fifth semiconductor layer 111b are formed. The interface between the fourth semiconductor layer 110a and the fifth semiconductor layer 111a is a heterojunction interface, and the interface between the fourth semiconductor layer 110b and the fifth semiconductor layer 111b is also a heterojunction interface. Each interface is a plane perpendicular to the plane of the Si substrate 101 .

After that, by removing the second insulating layer 107, as shown in FIG. , the fourth semiconductor layer 110 a , the fourth semiconductor layer 110 b , the fifth semiconductor layer 111 a , and the fifth semiconductor layer 111 b are exposed on the first insulating layer 105 .

After that, as shown in FIG. 1P,

gate electrodes

114a and 114b are formed on the

third semiconductor layers

109a and 109b via the

gate insulating layers

113a and 113b. Also,

source electrodes

115a and 115b are formed to be ohmically connected to the

fifth semiconductor layers

111a and 111b. Also, a drain electrode 116 that is ohmically connected to the second semiconductor layer 108 is formed.

As described above, the n-type second semiconductor layer 108 is used as the drain, the p-type

fourth semiconductor layers

110a and 110b are used as the sources, and the hetero interface perpendicular to the plane of the Si substrate 101 forms a barrier. Through this, a tunneling field effect transistor can be formed in which quantum tunneling is modulated by the gate voltage applied to the

gate electrodes

114a and 114b. The thickness, crystal composition, and doping concentration of each semiconductor layer can be applied by appropriately designing the transistor structure so as to obtain desired characteristics, and applying the designed values.

In addition, although the crystal substrate 103 (the first semiconductor layer 104) is made of InP in the above description, it is not limited to this. The crystal substrate 103 (first semiconductor layer 104) can be made of GaAs, for example. Also, in the above description, an example of manufacturing a field effect transistor by the method of forming a semiconductor layer according to the embodiment has been described, but the present invention is not limited to this. Quantum well structures using materials such as InGaAs, InP, and InGaAsP can be formed by the method of forming a semiconductor layer according to the embodiment, and the methods can be applied to fabricate light-emitting devices such as lasers using minute quantum well structures. Needless to say.

As described above, according to the present invention, a crystal substrate made of a group III-V compound semiconductor crystal having a (110) plane as a main surface is adhered onto a Si substrate, thereby forming a crystal substrate on the Si substrate. Since the first semiconductor layer is formed, it becomes possible to easily form a heterojunction on the Si substrate by a heterointerface perpendicular to the substrate made of a group III-V compound semiconductor. According to the present invention, it is possible to form a group III-V semiconductor thin film crystal having a heterointerface perpendicular to the substrate on a Si substrate, and the functions of a group III-V semiconductor device and a Si device are integrated. It becomes possible to fabricate a device that is not available in

It should be noted that the present invention is not limited to the embodiments described above, and many modifications and combinations can be implemented by those skilled in the art within the technical concept of the present invention. It is clear.

[Reference 1] M. Mitsuhara et al., "InP and related compounds grown on (110) InP substrates by metalorganic molecular beam epitaxy (chemical beam epitaxy)", Journal of Crystal Growth, vol. 136, pp. 195-199 , 1994.
[Reference 2] Y. Ogiso et al., "Static properties of planar Mach-Zehnder optical modulator on (110) InP substrate", Electronics Letters, vol. 49, no. 14, 2013.
[Reference 3] A. Goswami et al., "Controlling facets and defects of InP nanostructures in confined epitaxial lateral overgrowth", PHYSICAL REVIEW MATERIALS, vol. 4, no. 12, 123403, 2020.

Reference Signs List 101 Si substrate 102 Si oxide layer 103 Crystal substrate 104 First semiconductor layer 105 First insulating layer 105a Al oxide layer 105b Si oxide layer 106 Sacrificial pattern 107 Third 2 insulating

layers

108, 108a, 108b...

second semiconductor layer

109a, 109b...

third semiconductor layer

110a, 110b...

fourth semiconductor layer

111a, 111b...

fifth semiconductor layer

113a, 113b... gate insulating layer,

Reference numerals

114a, 114b: gate electrode, 115a, 115b: source electrode, 116: drain electrode, 125a: first lower opening, 125b: first opening, 126: hollow structure, 127: through hole, 138a, 138b: side surface.

Claims

A crystal substrate made of a group III-V compound semiconductor crystal having a main surface of (110) plane is adhered onto a Si substrate, and the adhered crystal substrate is thinned to form a first substrate on the Si substrate. a first step of forming a semiconductor layer;
On the first semiconductor layer, a first insulating layer is formed having a rectangular planar first opening whose long sides are in the [001] direction of the first semiconductor layer and whose short sides are in the [−110] direction. a second step of
On the first insulating layer, a sacrificial pattern made of amorphous Si having a rectangular planar shape with long sides in the [−110] direction of the first semiconductor layer and short sides in the [001] direction of the first semiconductor layer is provided. a third step of forming;
a fourth step of forming a second insulating layer on the first insulating layer to cover the sacrificial pattern;
a fifth step of forming a through hole reaching the sacrificial pattern in a portion of the second insulating layer that does not overlap with the first opening;
a sixth step of removing the sacrificial pattern through the through hole to expose the surface of the first semiconductor layer in the first opening;
Using the first insulating layer having the first opening as a selective growth mask, a group III-V compound semiconductor is crystal-grown from the surface of the first semiconductor layer exposed in the first opening, and the first insulating layer and the A second semiconductor layer is formed between the first insulating layer and the second insulating layer in a state in which a side surface composed of facets of a group III-V compound semiconductor crystal-grown is arranged between the second insulating layer and the second insulating layer. a seventh step to
Subsequent to the formation of the second semiconductor layer, from the side surface of the second semiconductor layer between the first insulating layer and the second insulating layer, a Group III-V compound having a composition different from that of the second semiconductor layer and an eighth step of crystal-growing a semiconductor to form a third semiconductor layer forming a heterojunction with the side surface of the second semiconductor layer.
In the method of forming a semiconductor layer according to claim 1,
A method of forming a semiconductor layer, wherein the main surface of the first semiconductor layer is formed in a state inclined from the (110) plane toward the {111}B plane by 3 to 6 degrees.
In the method for forming a semiconductor layer according to claim 1 or 2,
A method of forming a semiconductor layer, wherein the crystal substrate is made of InP or GaAs.